# Pin definitions Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html) This topic explains the pin assignments of the QCS6490 and QCS5430 chipsets. The figure and table within this topic provide details on pinouts, pad attributes, and their corresponding definitions. ## I/O parameter definitions Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html) The following table lists pad attributes and their descriptions, pad pull details, and the pad voltage groupings used throughout this topic. | Symbol | Description | | --- | --- | | ***Pad attribute*** | ***Pad attribute*** | | AI | Analog input (does not include pad circuitry) | | AO | Analog output (does not include pad circuitry) | | B | Bidirectional digital with CMOS input | | DI | Digital input (CMOS) | | DO | Digital output (CMOS) | | H | High-voltage tolerant | | S | Schmitt trigger input | | Z | High impedance (Hi-Z) output | | ***Pad pull details for digital I/Os*** | ***Pad pull details for digital I/Os*** | | nppdpukp | Programmable pull resistor. The default pull direction is indicated using capital letters and is a prefix to other programmable options:


NP: pdpukp = default no-pull with programmable options following the colon (:)


PD: nppukp = default pull-down with programmable options following the colon (:)


PU: nppdkp = default pull-up with programmable options following the colon (:)


KP: nppdpu = default keeper with programmable options following the colon (:) | | KP | Internal weak keeper device (keepers cannot drive external buses) | | NP | Internal pull | | PU | Internal pull-up device | | PD | Internal pull-down device | | ***Pad voltage groupings for baseband circuits*** | ***Pad voltage groupings for baseband circuits*** | | EBI | Pad group for EBI pads | | PX0 | Power for pad group 0 | | PX1 | Power for pad group 1 | | PX2 | Pad group 2 (SDC2); 1.8 V or 2.95 V | | PX3 | Pad group 3 (most peripherals); 1.8 V | | PX5 | Pad group 5 (UIM1); 1.8 V or 2.95 V | | PX6 | Pad group 6 (UIM2); 1.8 V or 2.95 V | | PX7 | Pad group 7 (eMMC); tied to VDD\_P7 pins (1.8 V only) | | PX10 | Pad group 10 (UFS\_REF\_CLK and UFS\_RESET); 1.2 V | | PX11 | Pad group 11 (CXO); 1.2 V | | CSI | Supply voltage for MIPI-CSI circuits and I/Os; tied to VDD\_A\_CSI\_X\_1P2 (1.2 V) | | DSI | Supply voltage for MIPI-DSI circuits and I/Os; tied to VDD\_A\_DSI\_1P2 (1.2 V) | ## Pin map Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html) The QCS6490 and QCS5430 chipsets are available in the pico scale package (1287 PSP). A high-level view of the pin assignments is shown in the following figure. For more information on package details and to create printed circuit board (PCB) footprint, see [Mechanical information](https://docs.qualcomm.com/doc/80-23889-1/topic/mechanical-information.html). QCS6490 and QCS5430 [Pin Assignment and GPIO Configuration Spreadsheet (80-23889-1A)](https://docs.qualcomm.com/bundle/80-23889-1A/resource/80-23889-1A.xlsm) lists all QCS6490 and QCS5430 pad numbers (in alphanumeric order), pad names, pad voltages, pad types, and functional descriptions. Figure : QCS6490 and QCS5430 pin assignments Page-1 Sheet.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 A GND EBI01_CAL GND GND GND EBI0_LP4_C A2_LP5_CA3 EBI0_LP4_C A1_LP5_CA1 EBI0_LP4_D Q14_LP5_DQ 6 EBI0_LP4_D MI1_LP5_DM I0 EBI0_LP4_D Q9_LP5_DQ1 GND GND GND GND EBI1_LP4_D Q9_LP5_DQ9 EBI1_LP4_D MI1_LP5_DM I1 EBI1_LP4_D Q14_LP5_DQ 14 EBI1_LP4_C A1_LP5_CA5 EBI1_LP4_CS 1_LP5_CA3 GND GND GND GND GND A B REFGEN_RE XT0 GND GND GND GND EBI0_LP4_C S0_LP5_CA2 EBI0_LP4_D Q15_LP5_DQ 7 EBI0_LP4_D Q13_LP5_DQ 5 EBI0_LP4_D Q8_LP5_DQ0 EBI0_LP4_D Q10_LP5_DQ 2 UFS0_RX1_P UFS0_RX0_ P UFS0_REFC LK EBI1_LP4_D Q10_LP5_DQ 10 EBI1_LP4_D Q8_LP5_DQ8 EBI1_LP4_D Q13_LP5_DQ 13 EBI1_LP4_D Q15_LP5_DQ1 5 EBI1_LP4_CS 0_LP5_CA4 GND GND GND GND SLEEP_CLK B C GND SDC1_DATA _3 EBI0_LP4_D Q1_LP5_DQ9 EBI0_LP4_D Q4_LP5_DQ1 2 EBI0_LP4_D Q5_LP5_DQ1 3 GND EBI0_LP4_C KE0_LP5_CS 1 GND GND GND GND UFS0_RX1_ M UFS0_RX0_ M GND GND GND GND EBI1_LP4_CK E0_LP5_CS0 GND EBI1_LP4_D Q5_LP5_DQ5 EBI1_LP4_D Q4_LP5_DQ4 EBI1_LP4_D Q1_LP5_DQ1 GPIO_171 PS_HOLD C D SDC1_DATA _0 GND EBI0_LP4_D Q2_LP5_DQ1 0 EBI0_LP4_D Q6_LP5_DQ1 4 EBI0_LP4_D Q7_LP5_DQ1 5 EBI0_LP4_C A3_LP5_CA4 EBI0_LP4_C A0_LP5_CA0 GND EBI0_LP4_D Q11_LP5_DQ 3 EBI0_LP4_D Q12_LP5_DQ 4 UFS0_TX1_ M UFS0_TX0_ M UFS0_RESE T_N EBI1_LP4_D Q12_LP5_DQ 12 EBI1_LP4_D Q11_LP5_DQ1 1 GND EBI1_LP4_C A0_LP5_CA6 EBI1_LP4_C A3_LP5_CA2 EBI1_LP4_D Q7_LP5_DQ7 EBI1_LP4_D Q6_LP5_DQ6 EBI1_LP4_D Q2_LP5_DQ2 GND GPIO_172 D E SDC1_DATA _5 SDC1_DATA _2 GND GND GND EBI0_LP4_C A4_LP5_CA5 GND EBI0_LP4_C K_C_LP5_CK _C GND GND GND UFS0_TX1_P UFS0_TX0_ P GND GND GND EBI1_LP4_CK _C_LP5_CK_ C GND EBI1_LP4_C A5_LP5_CA0 GND GND GND GPIO_174 GPIO_173 E F SDC1_DATA _4 DNC EBI0_LP4_D Q0_LP5_DQ8 EBI0_LP4_D Q3_LP5_DQ1 1 GND EBI0_LP4_C S1_LP5_NC EBI0_LP4_C KE1_LP5_CS 0 EBI0_LP4_C K_T_LP5_CK _T GND EBI0_LP4_D QS1_C_LP5_ DQS0_C GND GND DDR_RESET _N EBI1_LP4_D QS1_C_LP5_ DQS1_C EBI1_LP4_CK _T_LP5_CK_ T EBI1_LP4_CK E1_LP5_CS1 EBI1_LP4_C A2_LP5_NC GND EBI1_LP4_D Q3_LP5_DQ3 EBI1_LP4_D Q0_LP5_DQ0 GND GPIO_159 F Legend G SDC1_RCLK SDC1_CLK GND GND EBI0_LP4_D MI0_LP5_D MI1 EBI0_LP4_C A5_LP5_CA6 GND GND EBI0_LP4_N C_LP5_WCK 0_T EBI0_LP4_D QS1_T_LP5_ DQS0_T GND GND GND EBI1_LP4_D QS1_T_LP5_ DQS1_T EBI1_LP4_N C_LP5_WCK1 _T GND GND EBI1_LP4_C A4_LP5_CA1 EBI1_LP4_D MI0_LP5_D MI0 GND GND GPIO_161 GPIO_160 G Color Net Group H SDC1_DATA _1 SDC1_CMD GND GND GND GND GND GND EBI0_LP4_N C_LP5_WCK 0_C GND GND GND GND GND EBI1_LP4_N C_LP5_WCK1 _C GND GND GND GND GND GND GND GPIO_162 H GPIO J SDC1_DATA _6 SDC1_DATA _7 GND EBI0_LP4_D QS0_C_LP5_ DQS1_C GND EBI0_LP4_N C_LP5_WCK1 _C GND GND GND GND GND GND GND GND GND GND GND GND EBI1_LP4_N C_LP5_WCK 0_C GND EBI1_LP4_D QS0_C_LP5_ DQS0_C GND GPIO_164 GPIO_163 J Power K GPIO_83 GPIO_91 GND EBI0_LP4_D QS0_T_LP5_ DQS1_T EBI0_LP4_N C_LP5_WCK1 _T GND GND GND GND GND GND GND GND GND GND GND GND GND EBI1_LP4_N C_LP5_WCK 0_T EBI1_LP4_D QS0_T_LP5_ DQS0_T GND GND GPIO_165 K GND L GPIO_15 GPIO_14 GPIO_93 GND GND GND GND GND VDD_A_PLL _EBI0 GND GND VDD_PX_10 VDD_PX_1 GND VDD_A_PLL _EBI1 GND GND GND GND GND GND GND GPIO_148 GPIO_166 L PCIE M GPIO_12 GPIO_13 VDD_PX_7 VDD_CX VDD_CX GND GND GND GND GND GND DNC GND GND VDD_APC0 VDD_APC1 GND VDD_APC1 GND GPIO_149 M USB N GPIO_18 GPIO_19 GPIO_17 GND VDD_CX VDD_CX VDD_CX VDD_A_EBI 0 VDD_A_EBI 0 VDD_A_EBI 0 VDD_A_EBI 0 GND GND VDD_A_EBI1 VDD_A_EBI1 VDD_A_EBI1 VDD_A_EBI1 VDD_APC0 GND VDD_APC1 VDD_APC1 VDD_APC1 GPIO_144 GPIO_147 N QLink P GPIO_68 GPIO_16 VDD_PX_3 GND VDD_MX VDD_MX VDD_IO_EBI 0 VDD_IO_EBI 0 VDD_IO_EBI 0 VDD_IO_EBI 0 VDD_A_UFS _0_1P2 VDD_A_UFS _0_CORE VDD_IO_EBI 1 VDD_IO_EBI 1 VDD_IO_EBI 1 VDD_IO_EBI 1 GND VDD_APC0 GND VDD_APC1 GPIO_150 GPIO_146 GPIO_145 P CSI R GND PCIE0_REFC LK_P GND GND GND GND GND GND VDD_D_EBI 0 GND GND GND GND GND VDD_D_EBI1 GND GND VDD_APC0 GND VDD_APC1 GND GPIO_151 GPIO_158 GND R DSI T PCIE0_REFC LK_M GND VDD_CX VDD_CX GND VDD_CX GND GND GND GND GND VDD_A_QRE FS_0P875_4 _5 VDD_CX GND GND GND GND VDD_APC0 GND VDD_APC1 VDD_A_QRE FS_0P875_3 GPIO_152 GPIO_154 T SDC U PCIE0_RX_P PCIE0_RX_ M VDD_CX VDD_CX VDD_CX VDD_CX VDD_CX VDD_CX VDD_CX VDD_CX VDD_CX VDD_CX GND VDD_CX VDD_APC0 VDD_APC0 VDD_APC0 VDD_APC0 GND VDD_APC1 GND GPIO_153 GPIO_156 GPIO_155 U Display Port V PCIE0_TX_ M PCIE0_TX_P GND GND GND GND GND GND GND GND VDD_CX GND VDD_CX VDD_MX VDD_APC0 VDD_APC0 VDD_APC0 VDD_APC0 GND VDD_APC1 RESIN_N PMIC_SPMI_ CLK GPIO_157 V eDP W GPIO_67 GND CSI4_B2_LN 3_P CSI4_C2_LN 3_M GND GND VDD_A_TUR ING_Q6_CS_ 1P8 GND GND GND GND VDD_CX GND VDD_MX GND GND GND GND GND VDD_APC1 GND PMIC_SPMI_ DATA GPIO_94 RESOUT_N W Y GPIO_65 CSI4_A2_LN 2_M CSI4_C1_LN 2_P VDD_A_PCI E_0_1P2 VDD_A_QRE FS_0P875_9 VDD_CX VDD_CX VDD_CX VDD_CX VDD_CX VDD_CX VDD_MX GND VDD_APC1 VDD_APC1 VDD_APC1 VDD_APC1 VDD_A_APC _CS_1P8 VDD_APC1 VDD_APC1 VDD_APC1 GND GPIO_95 Y AA GPIO_64 GPIO_66 CSI4_B1_LN1 _M CSI4_A1_LN1 _P VDD_A_PCI E_0_CORE VDD_CX VDD_CX VDD_CX VDD_CX VDD_CX VDD_CX VDD_CX GND VDD_MX VDD_APC1 VDD_APC1 VDD_APC1 VDD_APC1 VDD_APC1 VDD_APC1 VDD_APC1 VDD_APC1 GPIO_96 GPIO_97 AA AB CSI3_NC_CL K_P GND CSI4_C0_LN 0_M CSI4_B0_LN 0_P GND GND GND GND GND GND GND VDD_MX VDD_WPSS_ CX GND GND GND GND GND GND GND GND GPIO_98 GPIO_99 AB AC CSI3_B0_LN 0_P CSI3_A0_CL K_M CSI4_A0_CL K_M CSI4_NC_CL K_P VDD_A_CSI _4_0P9 GND GND GND GND GND GND VDD_CX GND VDD_MX GND GND GND GND GND GND VDD_PX_3 DSI0_B1_CL K_P DSI0_C1_CL K_M GND AC AD CSI3_C0_LN 0_M GND GND VDD_A_CSI _4_1P2 GND VDD_CX VDD_CX VDD_CX VDD_CX VDD_CX VDD_CX VDD_MX VDD_CX GND VDD_APC1 VDD_APC1 VDD_APC1 VDD_APC1 VDD_APC1 GND GND DSI0_A1_LN1 _M DSI0_NC_LN 3_M AD AE CSI3_A1_LN1 _P CSI3_B1_LN1 _M GPIO_2 GPIO_3 DNC VDD_CX VDD_CX VDD_CX VDD_CX VDD_CX VDD_CX VDD_CX GND VDD_CX VDD_APC1 VDD_APC1 VDD_APC1 VDD_APC1 VDD_APC1 VDD_LPI_CX VDD_PX_0 DSI0_C0_LN 1_P DSI0_C2_LN 3_P GND AE AF CSI3_C1_LN 2_P CSI3_A2_LN 2_M GPIO_1 VDD_PX_3 GND GND GND GND GND GND GND VDD_MX VDD_CX GND GND GND GND GND GND GND GND DSI0_A2_LN 2_P DSI0_B2_LN 2_M AF AG GND CSI3_B2_LN 3_P CSI3_C2_LN 3_M GPIO_0 DNC VDD_MX VDD_MX VDD_MX VDD_MX VDD_MX VDD_MX VDD_MX GND VDD_CX VDD_CX VDD_LPI_M X VDD_LPI_CX VDD_LPI_CX VDD_LPI_CX VDD_LPI_CX VDD_A_DSI _0_1P2 DSI0_A0_LN 0_P DSI0_B0_LN 0_M GPIO_80 AG AH GND GND GND VDD_A_CSI _23_1P2 GND GND VDD_MODE M VDD_MX GND VDD_CX VDD_CX VDD_MX VDD_CX GND VDD_LPI_M X VDD_LPI_M X VDD_LPI_M X VDD_LPI_M X VDD_LPI_CX VDD_A_DSI _0_PLL_0P9 GND GND GPIO_100 AH AJ CSI2_A1_LN1 _P CSI2_B1_LN1 _M CSI2_A0_CL K_M CSI2_NC_CL K_P VDD_A_CSI _23_0P9 VDD_MODE M VDD_MODE M GND VDD_CX VDD_CX VDD_CX VDD_CX GND VDD_CX GND GND GND GND GND GND VDD_A_DSI _0_0P9 EDP0_TX3_ P EDP0_TX3_ M GND AJ AK GND CSI2_C0_LN 0_M CSI2_B0_LN 0_P GND GND VDD_MODE M VDD_MX GND GND GND VDD_MX VDD_CX GND VDD_GFX_C X_ISENSE GND GND GND GND GND GND EDP0_TX2_ P EDP0_TX2_ M AK AL CSI2_C1_LN 2_P CSI2_A2_LN 2_M CSI2_B2_LN 3_P CSI2_C2_LN 3_M VDD_A_CSI _01_0P9 GND VDD_MODE M GND GND GND GND GND VDD_MX VDD_CX VDD_CX VDD_CX VDD_CX VDD_CX VDD_CX VDD_CX VDD_A_QRE FS_0P875_2 GND EDP0_TX1_P EDP0_TX1_ M AL AM GND GND GND VDD_A_CSI _01_1P2 GND GND VDD_MODE M VDD_MX VDD_CX GND VDD_CX VDD_MX GND VDD_CX VDD_A_GFX _CS_1P8 GND GND GND GND VDD_VREF_ 0P9 GND EDP0_TX0_ P EDP0_TX0_ M AM AN CSI1_A1_LN1 _P CSI1_B1_LN1 _M CSI1_A0_CL K_M CSI1_NC_CL K_P VDD_A_QRE FS_0P875_8 GND VDD_MODE M GND VDD_MODE M VDD_MODE M VDD_CX VDD_CX GND VDD_CX VDD_MX GND VDD_MX VDD_MX VDD_GFX VDD_GFX VDD_VREF_ 1P2 EDP0_AUX_ P EDP0_AUX_ M GND AN AP GND CSI1_C0_LN 0_M CSI1_B0_LN 0_P GND VDD_MODE M GND VDD_MODE M GND VDD_MODE M GND GND VDD_MX GND VDD_GFX GND VDD_GFX GND VDD_GFX GND GND GND GND GND AP AR CSI1_C1_LN2 _P CSI1_A2_LN 2_M CSI1_B2_LN 3_P CSI1_C2_LN 3_M VDD_MODE M GND VDD_MODE M GND VDD_MODE M GND VDD_MODE M GND VDD_CX VDD_CX VDD_GFX GND VDD_GFX GND VDD_GFX GND SDC2_CMD SDC2_DATA _0 SDC2_DATA _1 GPIO_81 AR AT GND GND GND GND VDD_MODE M GND VDD_MODE M GND VDD_MODE M GND VDD_MODE M VDD_MX VDD_MX VDD_GFX GND VDD_GFX GND VDD_GFX GND VDD_PX_2 SDC2_DATA _3 SDC2_CLK SDC2_DATA _2 AT AU CSI0_A1_LN1 _P CSI0_B1_LN1 _M CSI0_A0_CL K_M CSI0_NC_CL K_P VDD_MX GND VDD_MODE M GND VDD_MODE M GND VDD_MODE M GND VDD_CX GND VDD_GFX GND VDD_GFX GND VDD_GFX GND GPIO_107 GPIO_106 GPIO_101 GND AU AV GND CSI0_C0_LN 0_M CSI0_B0_LN 0_P GND VDD_MODE M GND VDD_MODE M GND VDD_MODE M GND VDD_MODE M GND VDD_MX VDD_GFX GND VDD_GFX GND VDD_GFX GND VDD_PXVBI AS_SDC GPIO_108 GPIO_103 GPIO_102 AV AW CSI0_C1_LN 2_P CSI0_A2_LN 2_M CSI0_B2_LN 3_P CSI0_C2_LN 3_M VDD_MX GND VDD_MODE M GND VDD_MODE M GND VDD_MODE M GND VDD_PX_3 GND VDD_GFX GND VDD_GFX GND VDD_GFX GND GPIO_33 GPIO_32 GPIO_105 GPIO_104 AW AY GND GND GND GND VDD_MODE M GND VDD_MODE M GND VDD_MODE M GND VDD_MODE M VDD_QFPRO M VDD_CX VDD_GFX GND VDD_GFX GND VDD_GFX GND VDD_GFX GPIO_34 GPIO_41 GPIO_40 AY BA GPIO_73 GPIO_74 GPIO_75 GPIO_76 VDD_MX GND VDD_MODE M GND VDD_MODE M GND VDD_MODE M GND GND GND VDD_GFX GND VDD_GFX GND VDD_GFX GND GPIO_44 GPIO_35 GPIO_42 GND BA BB GPIO_70 GPIO_71 GPIO_72 GND VDD_MODE M GND VDD_MODE M GND VDD_MODE M GND VDD_MODE M VDD_A_GNS S_0P9 GND GND GND VDD_MX VDD_MX VDD_MX VDD_MX VDD_GFX GPIO_45 GPIO_48 GPIO_43 BB BC GND GPIO_69 GPIO_31 GND VDD_MODE M GND VDD_A_QLI NK_0_1P2 VDD_A_QLI NK_0_0P9 VDD_MODE M VDD_A_QLI NK_1_1P2 VDD_A_QLI NK_1_0P9_C K VDD_A_QRE FS_0P875_6 VDD_NAV_L PI_MX GND VDD_A_USB SSDP_0_1P2 VDD_VREF_ 1P2 VDD_VREF_ 0P9 GND GND VDD_GFX GPIO_46 GPIO_47 GPIO_50 GPIO_49 BC BD GPIO_27 GPIO_30 GPIO_29 GND GND GND VDD_A_QLI NK_0_0P9_ CK GND VDD_MODE M VDD_A_QLI NK_1_0P9 GND VDD_A_USB HS_CORE GND VDD_A_USB SSDP_0_CO RE GND GND VDD_A_QRE FS_0P875_0 GND GND GND GPIO_54 GPIO_52 GPIO_51 BD BE GPIO_25 GPIO_26 GPIO_28 GND GND GND VDD_A_QRE FS_0P875_7 GND VDD_MODE M GND GND GND VDD_A_USB HS_1P8 GND GND GND GND VDD_PX_11 VDD_PX_5 VDD_PX_6 VDD_A_QRE FS_0P875_1 GPIO_55 GPIO_53 GND BE BF GPIO_24 GPIO_23 GPIO_22 GND GND GND GND GND VDD_MODE M GND GND GND VDD_A_USB HS_3P1 GND GND GND GND GND GND GND GPIO_36 GPIO_57 GPIO_56 BF BG GND GPIO_21 GPIO_20 VDD_PX_3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GPIO_37 GPIO_59 GPIO_58 BG BH GPIO_78 GPIO_77 GPIO_79 GND GND GND QLINK0_L2_ M QLINK0_L1_ M GND GND GND GND USB1_HS_P USB0_HS_D P GND GND VDD_A_QRE FS_1P25 VDD_PXVBI AS_UIM VDD_A_CX O_1P8 VDD_PX_3 GPIO_60 GPIO_39 GPIO_38 BH BJ GPIO_11 GPIO_10 GPIO_131 GPIO_126 GPIO_89 QLINK0_L4_ P QLINK0_L0_ M QLINK0_L3_ P GND GND GND GND USB1_HS_M USB0_HS_D M GND USB0_SS_R X1_P GND DNC VDD_A_QRE FS_1P8 DNC GPIO_139 GPIO_61 GPIO_62 GND BJ BK GPIO_9 GPIO_8 GPIO_119 GPIO_128 GND QLINK0_CLK _M QLINK0_L2_ P QLINK0_L1_P DNC GND GND GND GND GND USB0_DP_A UX_P USB0_SS_T X1_M USB0_SS_R X0_M GND GND GND GPIO_140 GPIO_82 GPIO_63 BK BL GND GPIO_124 GPIO_120 GPIO_125 GPIO_88 QLINK0_L4_ M QLINK0_L0_ P QLINK0_L3_ M GND DNC DNC GND DNC GND GND USB0_SS_R X1_M USB0_SS_T X0_M GND PCIE1_RX1_P GND GND GPIO_142 GPIO_141 GPIO_109 BL BM GPIO_7 GPIO_123 GPIO_118 GPIO_127 GND QLINK0_CLK _P GND GND DNC DNC DNC DNC GND JTAG_TMS USB0_DP_A UX_M USB0_SS_T X1_P USB0_SS_R X0_P PCIE1_REFC LK_P PCIE1_TX1_ M PCIE1_RX0_ M GPIO_115 GPIO_116 GPIO_110 BM BN GPIO_6 GPIO_5 GPIO_132 GPIO_138 GPIO_87 GND GND GPIO_134 GND DNC DNC DNC DNC JTAG_TDI JTAG_TDO GND USB0_SS_T X0_P GND PCIE1_RX1_ M PCIE1_TX0_ M GND GPIO_114 GPIO_112 GND BN BP GPIO_4 GPIO_122 GPIO_117 GPIO_90 GPIO_85 GPIO_133 GPIO_129 GPIO_136 GND DNC DNC DNC GND JTAG_TRST _N MODE_1 GND GND PCIE1_REFC LK_M PCIE1_TX1_P PCIE1_RX0_ P QREFS_CXO _REXT GND GPIO_111 BP BR GND GND GPIO_121 GND GPIO_86 GPIO_84 GPIO_130 GPIO_135 GPIO_137 GND GND DNC GND JTAG_SRST _N JTAG_TCK MODE_0 GND REFGEN_RE XT1 GND PCIE1_TX0_ P GND CXO GPIO_113 GND BR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 ## Pin descriptions Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html) The following table describes the pin functions, pin pull types, and pin voltages. It also provides a mapping of pin numbers and pin names for all the pins on the device. These include general pins, GPIO pins, and power pins. | Pad number | Pad name and/or function | Pad characteristics[^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_w2v_dfb_w1c) | Pad characteristics[^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_w2v_dfb_w1c) | Functional description | | --- | --- | --- | --- | --- | | Pad number | Pad name and/or function | Voltage | Type | Functional description | | AU5 | CSI0\_A0\_CLK\_M | CSI | AI



AI, AO | MIPI-CSI 0 (D-PHY), differential clock – negative



MIPI-CSI 0 (C-PHY), trio lane 0 – A | | AU1 | CSI0\_A1\_LN1\_P | CSI | AI



AI, AO | MIPI-CSI 0 (D-PHY), differential lane 1 – positive



MIPI-CSI 0 (C-PHY), trio lane 1 – A | | AW3 | CSI0\_A2\_LN2\_M | CSI | AI



AI, AO | MIPI-CSI 0 (D-PHY), differential lane 2 – negative



MIPI-CSI 0 (C-PHY), trio lane 2 – A | | AV6 | CSI0\_B0\_LN0\_P | CSI | AI



AI, AO | MIPI-CSI 0 (D-PHY), differential lane 0 – positive



MIPI-CSI 0 (C-PHY), trio lane 0 – B | | AU3 | CSI0\_B1\_LN1\_M | CSI | AI



AI, AO | MIPI-CSI 0 (D-PHY), differential lane 1 – negative



MIPI-CSI 0 (C-PHY), trio lane 1 – B | | AW5 | CSI0\_B2\_LN3\_P | CSI | AI



AI, AO | MIPI-CSI 0 (D-PHY), differential lane 3 – positive



MIPI-CSI 0 (C-PHY), trio lane 2 – B | | AV4 | CSI0\_C0\_LN0\_M | CSI | AI



AI, AO | MIPI-CSI 0 (D-PHY), differential lane 0 – negative



MIPI-CSI 0 (C-PHY), trio lane 0 – C | | AW1 | CSI0\_C1\_LN2\_P | CSI | AI



AI, AO | MIPI-CSI 0 (D-PHY), differential lane 2 – positive



MIPI-CSI 0 (C-PHY), trio lane 1 – C | | AW7 | CSI0\_C2\_LN3\_M | CSI | AI



AI, AO | MIPI-CSI 0 (D-PHY), differential lane 3 – negative



MIPI-CSI 0 (C-PHY), trio lane 2 – C | | AU7 | CSI0\_NC\_CLK\_P | CSI | AI



AI, AO | MIPI-CSI 0 (D-PHY), differential clock – positive



MIPI-CSI 0 (C-PHY), no connect | | AN5 | CSI1\_A0\_CLK\_M | CSI | AI



AI, AO | MIPI-CSI 1 (D-PHY), differential clock – negative



MIPI-CSI 1 (C-PHY), trio lane 0 – A | | AN1 | CSI1\_A1\_LN1\_P | CSI | AI



AI, AO | MIPI-CSI 1 (D-PHY), differential lane 1 – positive



MIPI-CSI 1 (C-PHY), trio lane 1 – A | | AR3 | CSI1\_A2\_LN2\_M | CSI | AI



AI, AO | MIPI-CSI 1 (D-PHY), differential lane 2 – negative



MIPI-CSI 1 (C-PHY), trio lane 2 – A | | AP6 | CSI1\_B0\_LN0\_P | CSI | AI



AI, AO | MIPI-CSI 1 (D-PHY), differential lane 0 – positive



MIPI-CSI 1 (C-PHY), trio lane 0 – B | | AN3 | CSI1\_B1\_LN1\_M | CSI | AI



AI, AO | MIPI-CSI 1 (D-PHY), differential lane 1 – negative



MIPI-CSI 1 (C-PHY), trio lane 1 – B | | AR5 | CSI1\_B2\_LN3\_P | CSI | AI



AI, AO | MIPI-CSI 1 (D-PHY), differential lane 3 – positive



MIPI-CSI 1 (C-PHY), trio lane 2 – B | | AP4 | CSI1\_C0\_LN0\_M | CSI | AI



AI, AO | MIPI-CSI 1 (D-PHY), differential lane 0 – negative



MIPI-CSI 1 (C-PHY), trio lane 0 – C | | AR1 | CSI1\_C1\_LN2\_P | CSI | AI



AI, AO | MIPI-CSI 1 (D-PHY), differential lane 2 – positive



MIPI-CSI 1 (C-PHY), trio lane 1 – C | | AR7 | CSI1\_C2\_LN3\_M | CSI | AI



AI, AO | MIPI-CSI 1 (D-PHY), differential lane 3 – negative



MIPI-CSI 1 (C-PHY), trio lane 2 – C | | AN7 | CSI1\_NC\_CLK\_P | CSI | AI



AI, AO | MIPI-CSI 1 (D-PHY), differential clock – positive
MIPI-CSI 1 (C-PHY), no
connect | | AJ5 | CSI2\_A0\_CLK\_M | CSI | AI



AI, AO | MIPI-CSI 2 (D-PHY), differential clock – negative



MIPI-CSI 2 (C-PHY), trio lane 0 – A | | AJ1 | CSI2\_A1\_LN1\_P | CSI | AI



AI, AO | MIPI-CSI 2 (D-PHY), differential lane 1 – positive



MIPI-CSI 2 (C-PHY), trio lane 1 – A | | AL3 | CSI2\_A2\_LN2\_M | CSI | AI



AI, AO | MIPI-CSI 2 (D-PHY), differential lane 2 – negative



MIPI-CSI 2 (C-PHY), trio lane 2 – A | | AK6 | CSI2\_B0\_LN0\_P | CSI | AI



AI, AO | MIPI-CSI 2 (D-PHY), differential lane 0 – positive



MIPI-CSI 2 (C-PHY), trio lane 0 – B | | AJ3 | CSI2\_B1\_LN1\_M | CSI | AI



AI, AO | MIPI-CSI 2 (D-PHY), differential lane 1 – negative



MIPI-CSI 2 (C-PHY), trio lane 1 – B | | AL5 | CSI2\_B2\_LN3\_P | CSI | AI



AI, AO | MIPI-CSI 2 (D-PHY), differential lane 3 – positive



MIPI-CSI 2 (C-PHY), trio lane 2 – B | | AK4 | CSI2\_C0\_LN0\_M | CSI | AI



AI, AO | MIPI-CSI 2 (D-PHY), differential lane 0 – negative



MIPI-CSI 2 (C-PHY), trio lane 0 – C | | AL1 | CSI2\_C1\_LN2\_P | CSI | AI



AI, AO | MIPI-CSI 2 (D-PHY), differential lane 2 – positive



MIPI-CSI 2 (C-PHY), trio lane 1 – C | | AL7 | CSI2\_C2\_LN3\_M | CSI | AI



AI, AO | MIPI-CSI 2 (D-PHY), differential lane 3 – negative
MIPI-CSI 2 (C-PHY), trio
lane 2 – C | | AJ7 | CSI2\_NC\_CLK\_P | CSI | AI



AI, AO | MIPI-CSI 2 (C-PHY), no connect



MIPI-CSI 2 (D-PHY), differential clock – positive | | AC3 | CSI3\_A0\_CLK\_M | CSI | AI



AI, AO | MIPI-CSI 3 (D-PHY), differential clock – negative



MIPI-CSI 3 (C-PHY), trio lane 0 – A | | AE1 | CSI3\_A1\_LN1\_P | CSI | AI



AI, AO | MIPI-CSI 3 (D-PHY), differential lane 1 – positive
MIPI-CSI 3 (C-PHY), trio
lane 1 – A | | AF4 | CSI3\_A2\_LN2\_M | CSI | AI



AI, AO | MIPI-CSI 3 (D-PHY), differential lane 2 – negative
MIPI-CSI 3 (C-PHY), trio
lane 2 – A | | AC1 | CSI3\_B0\_LN0\_P | CSI | AI



AI, AO | MIPI-CSI 3 (D-PHY), differential lane 0 – positive
MIPI-CSI 3 (C-PHY), trio
lane 0 – B | | AE3 | CSI3\_B1\_LN1\_M | CSI | AI



AI, AO | MIPI-CSI 3 (D-PHY), differential lane 1 – negative
MIPI-CSI 3 (C-PHY), trio
lane 1 – B | | AG3 | CSI3\_B2\_LN3\_P | CSI | AI



AI, AO | MIPI-CSI 3 (D-PHY), differential lane 3 – positive
MIPI-CSI 3 (C-PHY), trio
lane 2 – B | | AD2 | CSI3\_C0\_LN0\_M | CSI | AI



AI, AO | MIPI-CSI 3 (D-PHY), differential lane 0 – negative
MIPI-CSI 3 (C-PHY), trio
lane 0 – C | | AF2 | CSI3\_C1\_LN2\_P | CSI | AI



AI, AO | MIPI-CSI 3 (D-PHY), differential lane 2 – positive
MIPI-CSI 3 (C-PHY), trio
lane 1 – C | | AG5 | CSI3\_C2\_LN3\_M | CSI | AI



AI, AO | MIPI-CSI 3 (D-PHY), differential lane 3 – negative
MIPI-CSI 3 (C-PHY), trio
lane 2 – C | | AB2 | CSI3\_NC\_CLK\_P | CSI | AI



AI, AO | MIPI-CSI 3 (D-PHY), differential clock – positive
MIPI-CSI 3 (C-PHY), no
connect | | AC5 | CSI4\_A0\_CLK\_M | CSI | AI



AI, AO | MIPI-CSI 4 (D-PHY), differential clock – negative
MIPI-CSI 4 (C-PHY), trio
lane 0 – A | | AA7 | CSI4\_A1\_LN1\_P | CSI | AI



AI, AO | MIPI-CSI 4 (D-PHY), differential lane 1 – positive
MIPI-CSI 4 (C-PHY), trio
lane 1 – A | | Y4 | CSI4\_A2\_LN2\_M | CSI | AI



AI, AO | MIPI-CSI 4 (D-PHY), differential lane 2 – negative
MIPI-CSI 4 (C-PHY), trio
lane 2 – A | | AB8 | CSI4\_B0\_LN0\_P | CSI | AI



AI, AO | MIPI-CSI 4 (D-PHY), differential lane 0 – positive
MIPI-CSI 4 (C-PHY), trio
lane 0 – B | | AA5 | CSI4\_B1\_LN1\_M | CSI | AI



AI, AO | MIPI-CSI 4 (D-PHY), differential lane 1 – negative
MIPI-CSI 4 (C-PHY), trio
lane 1 – B | | W5 | CSI4\_B2\_LN3\_P | CSI | AI



AI, AO | MIPI-CSI 4 (D-PHY), differential lane 3 – positive
MIPI-CSI 4 (C-PHY), trio
lane 2 – B | | AB6 | CSI4\_C0\_LN0\_M | CSI | AI



AI, AO | MIPI-CSI 4 (D-PHY), differential lane 0 – negative
MIPI-CSI 4 (C-PHY), trio
lane 0 – C | | Y6 | CSI4\_C1\_LN2\_P | CSI | AI



AI, AO | MIPI-CSI 4 (D-PHY), differential lane 2 – positive
MIPI-CSI 4 (C-PHY), trio
lane 1 – C | | W7 | CSI4\_C2\_LN3\_M | CSI | AI



AI, AO | MIPI-CSI 4 (D-PHY), differential lane 3 – negative
MIPI-CSI 4 (C-PHY), trio
lane 2 – C | | AC7 | CSI4\_NC\_CLK\_P | CSI | AI



AI, AO | MIPI-CSI 4 (D-PHY), differential clock – positive
MIPI-CSI 4 (C-PHY), no
connect | | BR43 | CXO | PX\_11 | DI | Core crystal oscillator (digital 19.2 MHz system clock) | | F26 | DDR\_RESET\_N | PX\_1 | DO | LPDDRx reset (shared by EBIs) | | BM30 | USB0\_DP\_AUX\_M | – | AI, AO | DisplayPort auxiliary channel – negative | | BK30 | USB0\_DP\_AUX\_P | – | AI, AO | DisplayPort auxiliary channel – positive | | AG43 | DSI0\_A0\_LN0\_P | DSI | AI, AO | MIPI-DSI 0 (D-PHY), differential lane 0 – positive
MIPI-DSI 0 (C-PHY), trio
lane 0 – A | | AD44 | DSI0\_A1\_LN1\_M | DSI | AI, AO | MIPI-DSI 0 (D-PHY), differential lane 1 – negative
MIPI-DSI 0 (C-PHY), trio
lane 1 – A | | AF44 | DSI0\_A2\_LN2\_P | DSI | AI, AO | MIPI-DSI 0 (D-PHY), differential lane 2 – positive
MIPI-DSI 0 (C-PHY), trio
lane 2 – A | | AG45 | DSI0\_B0\_LN0\_M | DSI | AI, AO | MIPI-DSI 0 (D-PHY), differential lane 0 – negative
MIPI-DSI 0 (C-PHY), trio
lane 0 – B | | AC43 | DSI0\_B1\_CLK\_P | DSI | AI, AO | MIPI-DSI 0 (D-PHY), differential clock – positive
MIPI-DSI 0 (C-PHY), trio
lane 1 – B | | AF46 | DSI0\_B2\_LN2\_M | DSI | AI, AO | MIPI-DSI 0 (D-PHY), differential lane 2 – negative
MIPI-DSI 0 (C-PHY), trio
lane 2 – B | | AE43 | DSI0\_C0\_LN1\_P | DSI | AI, AO | MIPI-DSI 0 (D-PHY), differential lane 1 – positive
MIPI-DSI 0 (C-PHY), trio
lane 0– C | | AC45 | DSI0\_C1\_CLK\_M | DSI | AI, AO | MIPI-DSI 0 (D-PHY), differential clock – negative
MIPI-DSI 0 (C-PHY), trio
lane 1 – C | | AE45 | DSI0\_C2\_LN3\_P | DSI | AI, AO | MIPI-DSI 0 (D-PHY), differential lane 3 – positive
MIPI-DSI 0 (C-PHY), trio
lane 2 – C | | AD46 | DSI0\_NC\_LN3\_M | DSI | AI, AO | MIPI-DSI 0 (D-PHY), differential lane 3 – negative
MIPI-DSI 0 (C-PHY), no
connect | | A3 | EBI01\_CAL | EBI | AI | EBI 0/1 LPDDRx calibration resistor | | D14 | EBI0\_LP4\_CA0\_LP5\_CA0 | EBI | DO | EBI0 LPDDR4X command/address bit 0

EBI0 LPDDR5 command/address bit 0 | | A13 | EBI0\_LP4\_CA1\_LP5\_CA1 | EBI | DO | EBI0 LPDDR4X command/address bit 1

EBI0 LPDDR5 command/address bit 1 | | B12 | EBI0\_LP4\_CS0\_LP5\_CA2 | EBI | DO | EBI0 LPDDR4X chip-select 0
EBI0 LPDDR5 command/address bit 2 | | A11 | EBI0\_LP4\_CA2\_LP5\_CA3 | EBI | DO | EBI0 LPDDR4X command/address bit 2

EBI0 LPDDR5 command/address bit 3 | | D12 | EBI0\_LP4\_CA3\_LP5\_CA4 | EBI | DO | EBI0 LPDDR4X command/address bit 3

EBI0 LPDDR5 command/address bit 4 | | E11 | EBI0\_LP4\_CA4\_LP5\_CA5 | EBI | DO | EBI0 LPDDR4X command/address bit 4

EBI0 LPDDR5 command/address bit 5 | | G11 | EBI0\_LP4\_CA5\_LP5\_CA6 | EBI | DO | EBI0 LPDDR4X command/address bit 5

EBI0 LPDDR5 command/address bit 6 | | F14 | EBI0\_LP4\_CKE1\_LP5\_CS0 | EBI | DO | EBI0 LPDDR4X clock enable 1
EBI0 LPDDR5 chip-select 0 | | C13 | EBI0\_LP4\_CKE0\_LP5\_CS1 | EBI | DO | EBI0 LPDDR4X clock enable 0
EBI0 LPDDR5 chip-select 1 | | F12 | EBI0\_LP4\_CS1\_LP5\_NC | EBI | DO | EBI0 LPDDR4 chip-select 1 | | E15 | EBI0\_LP4\_CK\_C\_LP5\_CK\_C | EBI | DO | EBI0 LPDDR4X differential clock – negative

EBI0 LPDDR5 differential clock – negative | | F16 | EBI0\_LP4\_CK\_T\_LP5\_CK\_T | EBI | DO | EBI0 LPDDR4X differential clock – positive

EBI0 LPDDR5 differential clock – positive | | A17 | EBI0\_LP4\_DMI1\_LP5\_DMI0 | EBI | DO | EBI0 LPDDR4X data mask inversion 1

EBI0 LPDDR5 data mask inversion 0 | | G9 | EBI0\_LP4\_DMI0\_LP5\_DMI1 | EBI | DO | EBI0 LPDDR4X data mask inversion 0

EBI0 LPDDR5 data mask inversion 1 | | F20 | EBI0\_LP4\_DQS1\_C\_LP5\_DQS0\_C | EBI | B | EBI0 LPDDR4X differential data strobe for byte 1 negative

EBI0 LPDDR5 differential data strobe for byte 0 negative | | J7 | EBI0\_LP4\_DQS0\_C\_LP5\_DQS1\_C | EBI | B | EBI0 LPDDR4X differential data strobe for byte 0 negative

EBI0 LPDDR5 differential data strobe for byte 1 negative | | G21 | EBI0\_LP4\_DQS1\_T\_LP5\_DQS0\_T | EBI | B | EBI0 LPDDR4X differential data strobe for byte 1 positive

EBI0 LPDDR5 differential data strobe for byte 0 positive | | K8 | EBI0\_LP4\_DQS0\_T\_LP5\_DQS1\_T | EBI | B | EBI0 LPDDR4X differential data strobe for byte 0 positive

EBI0 LPDDR5 differential data strobe for byte 1 positive | | B18 | EBI0\_LP4\_DQ8\_LP5\_DQ0 | EBI | B | EBI0 LPDDR4X data bit 8

EBI0 LPDDR5 data bit 0 | | A19 | EBI0\_LP4\_DQ9\_LP5\_DQ1 | EBI | B | EBI0 LPDDR4X data bit 9

EBI0 LPDDR5 data bit 1 | | B20 | EBI0\_LP4\_DQ10\_LP5\_DQ2 | EBI | B | EBI0 LPDDR4X data bit 10

EBI0 LPDDR5 data bit 2 | | D18 | EBI0\_LP4\_DQ11\_LP5\_DQ3 | EBI | B | EBI0 LPDDR4X data bit 11

EBI0 LPDDR5 data bit 3 | | D20 | EBI0\_LP4\_DQ12\_LP5\_DQ4 | EBI | B | EBI0 LPDDR4X data bit 12

EBI0 LPDDR5 data bit 4 | | B16 | EBI0\_LP4\_DQ13\_LP5\_DQ5 | EBI | B | EBI0 LPDDR4X data bit 13

EBI0 LPDDR5 data bit 5 | | A15 | EBI0\_LP4\_DQ14\_LP5\_DQ6 | EBI | B | EBI0 LPDDR4X data bit 14

EBI0 LPDDR5 data bit 6 | | B14 | EBI0\_LP4\_DQ15\_LP5\_DQ7 | EBI | B | EBI0 LPDDR4X data bit 15

EBI0 LPDDR5 data bit 7 | | F6 | EBI0\_LP4\_DQ0\_LP5\_DQ8 | EBI | B | EBI0 LPDDR4X data bit 0

EBI0 LPDDR5 data bit 8 | | C5 | EBI0\_LP4\_DQ1\_LP5\_DQ9 | EBI | B | EBI0 LPDDR4X data bit 1

EBI0 LPDDR5 data bit 9 | | D6 | EBI0\_LP4\_DQ2\_LP5\_DQ10 | EBI | B | EBI0 LPDDR4X data bit 2

EBI0 LPDDR5 data bit 10 | | F8 | EBI0\_LP4\_DQ3\_LP5\_DQ11 | EBI | B | EBI0 LPDDR4X data bit 3

EBI0 LPDDR5 data bit 11 | | C7 | EBI0\_LP4\_DQ4\_LP5\_DQ12 | EBI | B | EBI0 LPDDR4X data bit 4

EBI0 LPDDR5 data bit 12 | | C9 | EBI0\_LP4\_DQ5\_LP5\_DQ13 | EBI | B | EBI0 LPDDR4X data bit 5

EBI0 LPDDR5 data bit 13 | | D8 | EBI0\_LP4\_DQ6\_LP5\_DQ14 | EBI | B | EBI0 LPDDR4X data bit 6

EBI0 LPDDR5 data bit 14 | | D10 | EBI0\_LP4\_DQ7\_LP5\_DQ15 | EBI | B | EBI0 LPDDR4X data bit 7

EBI0 LPDDR5 data bit 15 | | H18 | EBI0\_LP4\_NC\_LP5\_WCK0\_C | EBI | DO | EBI0 LPDDR5 differential data clock for byte 0 negative | | J11 | EBI0\_LP4\_NC\_LP5\_WCK1\_C | EBI | DO | EBI0 LPDDR5 differential data clock for byte 1 negative | | G17 | EBI0\_LP4\_NC\_LP5\_WCK0\_T | EBI | DO | EBI0 LPDDR5 differential data clock for byte 0 positive | | K10 | EBI0\_LP4\_NC\_LP5\_WCK1\_T | EBI | DO | EBI0 LPDDR5 differential data clock for byte 1 positive | | E37 | EBI1\_LP4\_CA5\_LP5\_CA0 | EBI | DO | EBI1 LPDDR4X command/address bit 5

EBI1 LPDDR5 command/address bit 0 | | G37 | EBI1\_LP4\_CA4\_LP5\_CA1 | EBI | DO | EBI1 LPDDR4X command/address bit 4

EBI1 LPDDR5 command/address bit 1 | | D36 | EBI1\_LP4\_CA3\_LP5\_CA2 | EBI | DO | EBI1 LPDDR4X command/address bit 3

EBI1 LPDDR5 command/address bit 2 | | A37 | EBI1\_LP4\_CS1\_LP5\_CA3 | EBI | DO | EBI1 LPDDR4X chip-select 1
EBI1 LPDDR5 command/address bit 3 | | B36 | EBI1\_LP4\_CS0\_LP5\_CA4 | EBI | DO | EBI1 LPDDR4X chip-select 0
EBI1 LPDDR5 command/address bit 4 | | A35 | EBI1\_LP4\_CA1\_LP5\_CA5 | EBI | DO | EBI1 LPDDR4X command/address bit 1

EBI1 LPDDR5 command/address bit 5 | | D34 | EBI1\_LP4\_CA0\_LP5\_CA6 | EBI | DO | EBI1 LPDDR4X command/address bit 0

EBI1 LPDDR5 command/address bit 6 | | C35 | EBI1\_LP4\_CKE0\_LP5\_CS0 | EBI | DO | EBI1 LPDDR4X clock enable 0
EBI1 LPDDR5 chip-select 0 | | F34 | EBI1\_LP4\_CKE1\_LP5\_CS1 | EBI | DO | EBI1 LPDDR4X clock enable 1
EBI1 LPDDR5 chip-select 1 | | F36 | EBI1\_LP4\_CA2\_LP5\_NC | EBI | DO | EBI1 LPDDR4X command/address bit 2 | | E33 | EBI1\_LP4\_CK\_C\_LP5\_CK\_C | EBI | DO | EBI1 LPDDR4X differential clock – negative

EBI1 LPDDR5 differential clock – negative | | F32 | EBI1\_LP4\_CK\_T\_LP5\_CK\_T | EBI | DO | EBI1 LPDDR4X differential clock – positive

EBI1 LPDDR5 differential clock – positive | | G39 | EBI1\_LP4\_DMI0\_LP5\_DMI0 | EBI | DO | EBI1 LPDDR4X data mask 0
EBI1 LPDDR5 data mask 0 | | A31 | EBI1\_LP4\_DMI1\_LP5\_DMI1 | EBI | DO | EBI1 LPDDR4X data mask 1

EBI1 LPDDR5 data mask 1 | | J41 | EBI1\_LP4\_DQS0\_C\_LP5\_DQS0\_C | EBI | B | EBI1 LPDDR4X differential data strobe for byte 0 negative

EBI1 LPDDR5 differential data strobe for byte 0 negative | | F28 | EBI1\_LP4\_DQS1\_C\_LP5\_DQS1\_C | EBI | B | EBI1 LPDDR4X differential data strobe for byte 1 negative

EBI1 LPDDR5 differential data strobe for byte 1 negative | | K40 | EBI1\_LP4\_DQS0\_T\_LP5\_DQS0\_T | EBI | B | EBI1 LPDDR4X differential data strobe for byte 0 positive

EBI1 LPDDR5 differential data strobe for byte 0 positive | | G29 | EBI1\_LP4\_DQS1\_T\_LP5\_DQS1\_T | EBI | B | EBI1 LPDDR4X differential data strobe for byte 1 positive



EBI1 LPDDR5 differential data strobe for byte 1 positive | | F42 | EBI1\_LP4\_DQ0\_LP5\_DQ0 | EBI | B | EBI1 LPDDR4X data bit 0



EBI1 LPDDR5 data bit 0 | | C43 | EBI1\_LP4\_DQ1\_LP5\_DQ1 | EBI | B | EBI1 LPDDR4X data bit 1



EBI1 LPDDR5 data bit 1 | | D42 | EBI1\_LP4\_DQ2\_LP5\_DQ2 | EBI | B | EBI1 LPDDR4X data bit 2



EBI1 LPDDR5 data bit 2 | | F40 | EBI1\_LP4\_DQ3\_LP5\_DQ3 | EBI | B | EBI1 LPDDR4X data bit 3



EBI1 LPDDR5 data bit 3 | | C41 | EBI1\_LP4\_DQ4\_LP5\_DQ4 | EBI | B | EBI1 LPDDR4X data bit 4



EBI1 LPDDR5 data bit 4 | | C39 | EBI1\_LP4\_DQ5\_LP5\_DQ5 | EBI | B | EBI1 LPDDR4X data bit 5



EBI1 LPDDR5 data bit 5 | | D40 | EBI1\_LP4\_DQ6\_LP5\_DQ6 | EBI | B | EBI1 LPDDR4X data bit 6



EBI1 LPDDR5 data bit 6 | | D38 | EBI1\_LP4\_DQ7\_LP5\_DQ7 | EBI | B | EBI1 LPDDR4X data bit 7



EBI1 LPDDR5 data bit 7 | | B30 | EBI1\_LP4\_DQ8\_LP5\_DQ8 | EBI | B | EBI1 LPDDR4X data bit 8



EBI1 LPDDR5 data bit 8 | | A29 | EBI1\_LP4\_DQ9\_LP5\_DQ9 | EBI | B | EBI1 LPDDR4X data bit 9



EBI1 LPDDR5 data bit 9 | | B28 | EBI1\_LP4\_DQ10\_LP5\_DQ10 | EBI | B | EBI1 LPDDR4X data bit 10



EBI1 LPDDR5 data bit 10 | | D30 | EBI1\_LP4\_DQ11\_LP5\_DQ11 | EBI | B | EBI1 LPDDR4X data bit 11



EBI1 LPDDR5 data bit 11 | | D28 | EBI1\_LP4\_DQ12\_LP5\_DQ12 | EBI | B | EBI1 LPDDR4X data bit 12



EBI1 LPDDR5 data bit 12 | | B32 | EBI1\_LP4\_DQ13\_LP5\_DQ13 | EBI | B | EBI1 LPDDR4X data bit 13



EBI1 LPDDR5 data bit 13 | | A33 | EBI1\_LP4\_DQ14\_LP5\_DQ14 | EBI | B | EBI1 LPDDR4X data bit 14



EBI1 LPDDR5 data bit 14 | | B34 | EBI1\_LP4\_DQ15\_LP5\_DQ15 | EBI | B | EBI1 LPDDR4X data bit 15



EBI1 LPDDR5 data bit 15 | | J37 | EBI1\_LP4\_NC\_LP5\_WCK0\_C | EBI | DO | EBI1 LPDDR5 differential data clock for byte 0 negative | | H30 | EBI1\_LP4\_NC\_LP5\_WCK1\_C | EBI | DO | EBI1 LPDDR5 differential data clock for byte 1 negative | | K38 | EBI1\_LP4\_NC\_LP5\_WCK0\_T | EBI | DO | EBI1 LPDDR5 differential data clock for byte 0 positive | | G31 | EBI1\_LP4\_NC\_LP5\_WCK1\_T | EBI | DO | EBI1 LPDDR5 differential data clock for byte 1 positive | | AN45 | EDP0\_AUX\_M | – | B | eDP 1.4 auxiliary channel – negative | | AN43 | EDP0\_AUX\_P | – | B | eDP 1.4 auxiliary channel – positive | | AM46 | EDP0\_TX0\_M | – | AO | eDP 1.4 transmit channel 0 – negative | | AM44 | EDP0\_TX0\_P | – | AO | eDP 1.4 transmit channel 0 – positive | | AL47 | EDP0\_TX1\_M | – | AO | eDP 1.4 transmit channel 1 – negative | | AL45 | EDP0\_TX1\_P | – | AO | eDP 1.4 transmit channel 1 – positive | | AK46 | EDP0\_TX2\_M | – | AO | eDP 1.4 transmit channel 2 – negative | | AK44 | EDP0\_TX2\_P | – | AO | eDP 1.4 transmit channel 2 – positive | | AJ45 | EDP0\_TX3\_M | – | AO | eDP 1.4 transmit channel 3 – negative | | AJ43 | EDP0\_TX3\_P | – | AO | eDP 1.4 transmit channel 3 – positive | | BJ25 | USB1\_HS\_M | – | B | USB1\_HS – negative | | BH26 | USB1\_HS\_P | – | B | USB1\_HS – positive | | BR31 | MODE\_0 | PX\_3 | DI | Mode control bit 0 – unconnected for native mode | | BP30 | MODE\_1 | PX\_3 | DI | Mode control bit 1 – unconnected for native mode | | T2 | PCIE0\_REFCLK\_M | – | AI, AO | PCIe 0 Gen 3 reference clock – negative | | R3 | PCIE0\_REFCLK\_P | – | AI, AO | PCIe 0 Gen 3 reference clock – positive | | U3 | PCIE0\_RX\_M | – | AI | PCIe 0 Gen 3 receive – negative | | U1 | PCIE0\_RX\_P | – | AI | PCIe 0 Gen 3 receive – positive | | V2 | PCIE0\_TX\_M | – | AO | PCIe 0 Gen 3 transmit – negative | | V4 | PCIE0\_TX\_P | – | AO | PCIe 0 Gen 3 transmit – positive | | BP36 | PCIE1\_REFCLK\_M | – | AI, AO | PCIe 1 Gen 3 reference clock – negative | | BM36 | PCIE1\_REFCLK\_P | – | AI, AO | PCIe 1 Gen 3 reference clock – positive | | BM40 | PCIE1\_RX0\_M | – | AI | PCIe 1 Gen 3 receive lane 0 – negative | | BP40 | PCIE1\_RX0\_P | – | AI | PCIe 1 Gen 3 receive lane 0 – positive | | BN37 | PCIE1\_RX1\_M | – | AI | PCIe 1 Gen 3 receive lane 1 – negative | | BL37 | PCIE1\_RX1\_P | – | AI | PCIe 1 Gen 3 receive lane 1 – positive | | BN39 | PCIE1\_TX0\_M | – | AO | PCIe 1 Gen 3 transmit lane 0 – negative | | BR39 | PCIE1\_TX0\_P | – | AO | PCIe 1 Gen 3 transmit lane 0 – positive | | BM38 | PCIE1\_TX1\_M | – | AO | PCIe 1 Gen 3 transmit lane 1 – negative | | BP38 | PCIE1\_TX1\_P | – | AO | PCIe 1 Gen 3 transmit lane 1 – positive | | V44 | PMIC\_SPMI\_CLK | PX\_0 | DO | Slave and PBUS interface for PMICs – clock | | W43 | PMIC\_SPMI\_DATA | PX\_0 | BH-PD:nppukp | Slave and PBUS interface for PMICs – data | | C47 | PS\_HOLD | PX\_3 | DO | Power-supply hold signal to PMIC | | BK12 | QLINK0\_CLK\_M | – | AI, AO | QLink0 clock – negative | | BM12 | QLINK0\_CLK\_P | – | AI, AO | QLink0 clock – positive | | BH14 | QLINK0\_L2\_M | – | AI, AO | QLink0 lane 2 – negative | | BK14 | QLINK0\_L2\_P | – | AI, AO | QLink0 lane 2 – positive | | BL11 | QLINK0\_L4\_M | – | AI, AO | QLink0 lane 4 – negative | | BJ11 | QLINK0\_L4\_P | – | AI, AO | QLink0 lane 4 – positive | | BL15 | QLINK0\_L3\_M | – | AI, AO | QLink0 lane 3 – negative | | BJ15 | QLINK0\_L3\_P | – | AI, AO | QLink0 lane 3 – positive | | BJ13 | QLINK0\_L0\_M | – | AI, AO | QLink0 lane 0 – negative | | BL13 | QLINK0\_L0\_P | – | AI, AO | QLink0 lane 0 – positive | | BH16 | QLINK0\_L1\_M | – | AI, AO | QLink0 lane 1 – negative | | BK16 | QLINK0\_L1\_P | – | AI, AO | QLink0 lane 1 – positive | | BP42 | QREFS\_CXO\_REXT | PX\_11 | AI, AO | External resistor for on-chip clocking | | B2 | REFGEN\_REXT0 | PX\_3 | AI, AO | East-side high-speed interface – external resistor | | BR35 | REFGEN\_REXT1 | PX\_3 | AI, AO | West-side high-speed interface – external resistor | | V42 | RESIN\_N | PX\_0 | DI | Reset input | | W47 | RESOUT\_N | PX\_3 | DO | Reset output | | G3 | SDC1\_CLK | PX\_7 | DO-NP:pdpukp | Secure digital controller 1 clock | | H4 | SDC1\_CMD | PX\_7 | B-NP:pdpukp | Secure digital controller 1 command | | D2 | SDC1\_DATA0 | PX\_7 | B-NP:pdpukp | Secure digital controller 1 data bit 0 | | H2 | SDC1\_DATA1 | PX\_7 | B-NP:pdpukp | Secure digital controller 1 data bit 1 | | E3 | SDC1\_DATA2 | PX\_7 | B-NP:pdpukp | Secure digital controller 1 data bit 2 | | C3 | SDC1\_DATA3 | PX\_7 | B-NP:pdpukp | Secure digital controller 1 data bit 3 | | F2 | SDC1\_DATA4 | PX\_7 | B-NP:pdpukp | Secure digital controller 1 data bit 4 | | E1 | SDC1\_DATA5 | PX\_7 | B-NP:pdpukp | Secure digital controller 1 data bit 5 | | J1 | SDC1\_DATA6 | PX\_7 | B-NP:pdpukp | Secure digital controller 1 data bit 6 | | J3 | SDC1\_DATA7 | PX\_7 | B-NP:pdpukp | Secure digital controller 1 data bit 7 | | G1 | SDC1\_RCLK | PX\_7 | DI-PD:pdpukp | Secure digital controller 1 return clock | | AT44 | SDC2\_CLK | PX\_2 | DO-NP:pdpukp | Secure digital controller 2 clock | | AR41 | SDC2\_CMD | PX\_2 | BH-NP:pdpukp | Secure digital controller 2 command | | AR43 | SDC2\_DATA0 | PX\_2 | BH-NP:pdpukp | Secure digital controller 2 data bit 0 | | AR45 | SDC2\_DATA1 | PX\_2 | BH-NP:pdpukp | Secure digital controller 2 data bit 1 | | AT46 | SDC2\_DATA2 | PX\_2 | BH-NP:pdpukp | Secure digital controller 2 data bit 2 | | AT42 | SDC2\_DATA3 | PX\_2 | BH-NP:pdpukp | Secure digital controller 2 data bit 3 | | B46 | SLEEP\_CLK | PX\_3 | DI | Sleep clock | | BR27 | JTAG\_SRST\_N | PX\_3 | DI-PU:nppdkp | JTAG reset for debug | | BR29 | JTAG\_TCK | PX\_3 | DI-PU:nppdkp | JTAG clock input | | BN27 | JTAG\_TDI | PX\_3 | DI-PU:nppdkp | JTAG data input | | BN29 | JTAG\_TDO | PX\_3 | DO-Z | JTAG data output | | BM28 | JTAG\_TMS | PX\_3 | DI-PU:nppdkp | JTAG mode select input | | BP28 | JTAG\_TRST\_N | PX\_3 | DI-PU:nppdkp | JTAG reset | | C25 | UFS\_RX0\_M | – | AI | UFS lane 0 receiver – negative | | B24 | UFS\_RX0\_P | – | AI | UFS lane 0 receiver – positive | | D24 | UFS\_TX0\_M | – | AO | UFS lane 0 transmit – negative | | E25 | UFS\_TX0\_P | – | AO | UFS lane 0 transmit – positive | | C23 | UFS\_RX1\_M | – | AI | UFS lane 1 receiver – negative | | B22 | UFS\_RX1\_P | – | AI | UFS lane 1 receiver – positive | | D22 | UFS\_TX1\_M | – | AO | UFS lane 1 transmit – negative | | E23 | UFS\_TX1\_P | – | AO | UFS lane 1 transmit – positive | | B26 | UFS0\_REFCLK | PX\_10 | DO-Z:PD:nppukp | UFS reference clock | | D26 | UFS0\_RESET\_N | PX\_10 | DO-Z:PD:nppukp | UFS reset | | BJ27 | USB0\_HS\_DM | – | AI, AO | USB 2.0 high-speed data – negative | | BH28 | USB0\_HS\_DP | – | AI, AO | USB 2.0 high-speed data – positive | | BK34 | USB0\_SS\_RX0\_M | – | AI | USB 3.0 Type-C PHY receiver 0 – negative | | BM34 | USB0\_SS\_RX0\_P | – | AI | USB 3.0 Type-C PHY receiver 0 – positive | | BL31 | USB0\_SS\_RX1\_M | – | AI | USB 3.0 Type-C PHY receiver 1 – negative | | BJ31 | USB0\_SS\_RX1\_P | – | AI | USB 3.0 Type-C PHY receiver 1 – positive | | BL33 | USB0\_SS\_TX0\_M | – | AO | USB 3.0 Type-C PHY transmit 0 – negative | | BN33 | USB0\_SS\_TX0\_P | – | AO | USB 3.0 Type-C PHY transmit 0 – positive | | BK32 | USB0\_SS\_TX1\_M | – | AO | USB 3.0 Type-C PHY transmit 1 – negative | | BM32 | USB0\_SS\_TX1\_P | – | AO | USB 3.0 Type-C PHY transmit 1 – positive | | | | | | | ^1^ For parameter and acronym definitions, see [Table : I/O description (pad type) parameters](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#lwx1605206318030__table_qrk_mnk_b3b). Note: - GPIO pins can support multiple functions. To assign GPIOs to particular functions as in [Table : Pin descriptions – general pins](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__table_bkv_zjf_rnb), identify all application requirements and map each GPIO to its function. Ensure to avoid GPIO assignment conflicts. See the following table for a list of all supported functions for each GPIO. - Some GPIOs can wake up the SoC from sleep. For more information, see [Table : Pin descriptions – general-purpose input/output ports](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__table_u1k_vdn_tnb). To avoid excessive current leakage, examine each GPIO external connection and programmed configuration. Ensure control of the following factors: - GPIO configuration - Input vs. output - Pull-up or pull-down - External connections - Unused inputs - Connections to high impedance (tri-state) outputs - Unattached connections to external devices For GPIO assignments, see QCS6490 and QCS5430 [Pin Assignment and GPIO Configuration Spreadsheet (80-23889-1A)](https://docs.qualcomm.com/bundle/80-23889-1A/resource/80-23889-1A.xlsm). It lists all pad name and/or function for QCS6490 and QCS5430 GPIOs (in numeric order), pad numbers, pad voltages, pull states, and available configurations. | Pad number | Pad name | Configurable function | Pad

characteristics [^2^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_o3b_dfb_w1c) | Pad

characteristics [^2^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_o3b_dfb_w1c) | Functional description | Wake-up function | | --- | --- | --- | --- | --- | --- | --- | | Pad number | Pad name | Configurable function | Voltage | Type | Functional description | Wake-up function | | AG7 | GPIO\_0 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AG7 | GPIO\_0 | UART\_CTS | PX\_3 | DI | QUP 0 SE0, lane 0: UART\_CTS | Y | | AG7 | GPIO\_0 | I2C\_SDA | PX\_3 | B | QUP 0 SE0, lane 0: I2C\_SDA | Y | | AG7 | GPIO\_0 | SPI\_MISO | PX\_3 | DI | QUP 0 SE0, lane 0: SPI\_MISO | Y | | AG7 | GPIO\_0 | I3C\_SDA | PX\_3 | B | QUP 0 SE0, lane 0: I3C\_SDA | Y | | AF6 | GPIO\_1 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AF6 | GPIO\_1 | UART\_RFR | PX\_3 | DO | QUP 0 SE0, lane 1: UART\_RFR | N | | AF6 | GPIO\_1 | I2C\_SCL | PX\_3 | DO | QUP 0 SE0, lane 1: I2C\_SCL | N | | AF6 | GPIO\_1 | SPI\_MOSI | PX\_3 | DO | QUP 0 SE0, lane 1: SPI\_MOSI | N | | AF6 | GPIO\_1 | I3C\_SCL | PX\_3 | DO | QUP 0 SE0, lane 1: I3C\_SCL | N | | AE5 | GPIO\_2 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AE5 | GPIO\_2 | UART\_TX | PX\_3 | DO | QUP 0 SE0, lane 2: UART\_TX | N | | AE5 | GPIO\_2 | SPI\_SCLK | PX\_3 | DO | QUP 0 SE0, lane 2: SPI\_SCLK | N | | AE5 | GPIO\_2 | SPI\_CS\_1 | PX\_3 | DO | QUP 0 SE7, lane 4: SPI\_CS\_1 | N | | AE5 | GPIO\_2 | QDSS\_GPIO\_TRACEDATA\_LOCA[0] | PX\_3 | DO | QDSS trace data bit 0 A | N | | AE7 | GPIO\_3 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AE7 | GPIO\_3 | UART\_RX | PX\_3 | DI | QUP0 SE0, lane 3: UART\_RX | Y | | AE7 | GPIO\_3 | SPI\_CS\_0 | PX\_3 | DO | QUP0 SE0, lane 3: SPI\_CS\_0 | Y | | AE7 | GPIO\_3 | SPI\_CS\_2 | PX\_3 | DO | QUP0 SE7, lane 5: SPI\_CS\_2 | Y | | AE7 | GPIO\_3 | QDSS\_GPIO\_TRACEDATA\_LOCA[1] | PX\_3 | DO | QDSS trace data bit 1 A | Y | | BP2 | GPIO\_4 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BP2 | GPIO\_4 | UART\_CTS | PX\_3 | DI | QUP0 SE1, lane 0 UART\_CTS | Y | | BP2 | GPIO\_4 | I2C\_SDA | PX\_3 | B | QUP0 SE1, lane 0 I2C\_SDA | Y | | BP2 | GPIO\_4 | SPI\_MISO | PX\_3 | DI | QUP0 SE1, lane 0 SPI\_MISO | Y | | BP2 | GPIO\_4 | I3C\_SDA | PX\_3 | B | QUP 0 SE1, lane 0: I3C\_SDA | Y | | BN3 | GPIO\_5 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BN3 | GPIO\_5 | UART\_RFR | PX\_3 | DO | QUP0 SE1, lane 1: UART\_RFR | N | | BN3 | GPIO\_5 | I2C\_SCL | PX\_3 | DO | QUP0 SE1, lane 1: I2C\_SCL | N | | BN3 | GPIO\_5 | SPI\_MOSI | PX\_3 | DO | QUP0 SE1, lane 1: SPI\_MOSI | N | | BN3 | GPIO\_5 | I3C\_SCL | PX\_3 | DO | QUP 0 SE1, lane 1: I3C\_SCL | N | | BN1 | GPIO\_6 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BN1 | GPIO\_6 | UART\_TX | PX\_3 | DO | QUP0 SE1, lane 2: UART\_TX | N | | BN1 | GPIO\_6 | SPI\_SCLK | PX\_3 | DO | QUP0 SE1, lane 2: SPI\_SCLK | N | | BN1 | GPIO\_6 | SPI\_CS\_3 | PX\_3 | DO | QUP0 SE7, lane 6: SPI\_CS\_3 | N | | BM2 | GPIO\_7 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BM2 | GPIO\_7 | UART\_RX | PX\_3 | DI | QUP0 SE1, lane 3: UART\_RX | Y | | BM2 | GPIO\_7 | SPI\_CS\_0 | PX\_3 | DO | QUP0 SE1, lane 3: SPI\_CS\_0 | Y | | BK4 | GPIO\_8 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BK4 | GPIO\_8 | UART\_CTS | PX\_3 | DI | QUP0 SE2, lane 0: UART\_CTS | Y | | BK4 | GPIO\_8 | I2C\_SDA | PX\_3 | B | QUP0 SE2, lane 0: I2C\_SDA | Y | | BK4 | GPIO\_8 | SPI\_MISO | PX\_3 | DI | QUP0 SE2, lane 0: SPI\_MISO | Y | | BK4 | GPIO\_8 | QDSS\_GPIO\_TRACEDATA\_LOCA[2] | PX\_3 | DO | QDSS trace data bit 2 A | Y | | BK2 | GPIO\_9 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BK2 | GPIO\_9 | UART\_RFR | PX\_3 | DO | QUP0 SE2, lane 1: UART\_RFR | N | | BK2 | GPIO\_9 | I2C\_SCL | PX\_3 | DO | QUP0 SE2, lane 1: I2C\_SCL | N | | BK2 | GPIO\_9 | SPI\_MOSI | PX\_3 | DO | QUP0 SE2, lane 1: SPI\_MOSI | N | | BK2 | GPIO\_9 | QDSS\_GPIO\_TRACEDATA\_LOCA[3] | PX\_3 | DO | QDSS trace data bit 3 A | N | | BJ3 | GPIO\_10 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BJ3 | GPIO\_10 | GNSS\_L1\_ELNA\_EN | PX\_3 | DO | eLNA enable for L1 | N | | BJ3 | GPIO\_10 | UART\_TX | PX\_3 | DO | QUP0 SE2, lane 2: UART\_TX | N | | BJ3 | GPIO\_10 | SPI\_SCLK | PX\_3 | DO | QUP0 SE2, lane 2: SPI\_SCLK | N | | BJ3 | GPIO\_10 | QDSS\_GPIO\_TRACEDATA\_LOCA[4] | PX\_3 | DO | QDSS trace data bit 4 A | N | | BJ1 | GPIO\_11 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BJ1 | GPIO\_11 | GNSS\_L2\_L5\_ELNA\_EN | PX\_3 | DO | eLNA enable for L2\_L5 | Y | | BJ1 | GPIO\_11 | UART\_RX | PX\_3 | DI | QUP0 SE2, lane 3: UART\_RX | Y | | BJ1 | GPIO\_11 | SPI\_CS\_0 | PX\_3 | DO | QUP0 SE2, lane 3: SPI\_CS\_0 | Y | | BJ1 | GPIO\_11 | QDSS\_GPIO\_TRACEDATA\_LOCA[5] | PX\_3 | DO | QDSS trace data bit 5 A | Y | | M2 | GPIO\_12 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | M2 | GPIO\_12 | UART\_CTS | PX\_3 | DI | QUP0 SE3, lane 0: UART\_CTS | Y | | M2 | GPIO\_12 | I2C\_SDA | PX\_3 | B | QUP0 SE3, lane 0: I2C\_SDA | Y | | M2 | GPIO\_12 | SPI\_MISO | PX\_3 | DI | QUP0 SE3, lane 0: SPI\_MISO | Y | | M2 | GPIO\_12 | QDSS\_GPIO\_TRACECTL\_LOCA | PX\_3 | DO | QDSS trace control A | Y | | M4 | GPIO\_13 | | PX\_3 | PD:nppukp | Configurable I/O | N | | M4 | GPIO\_13 | UART\_RFR | PX\_3 | DO | QUP0 SE3, lane 1: UART\_RFR | N | | M4 | GPIO\_13 | I2C\_SCL | PX\_3 | DO | QUP0 SE3, lane 1: I2C\_SCL | N | | M4 | GPIO\_13 | SPI\_MOSI | PX\_3 | DO | QUP0 SE3, lane 1: SPI\_MOSI | N | | M4 | GPIO\_13 | QDSS\_GPIO\_TRACECLK\_LOCA | PX\_3 | DO | QDSS trace clock A | N | | L3 | GPIO\_14 | | PX\_3 | PD:nppukp | Configurable I/O | N | | L3 | GPIO\_14 | UART\_TX | PX\_3 | DO | QUP0 SE3, lane 2: UART\_TX | N | | L3 | GPIO\_14 | SPI\_SCLK | PX\_3 | DO | QUP0 SE3, lane 2: SPI\_SCLK | N | | L3 | GPIO\_14 | BOOT\_CONFIG[12] | PX\_3 | DI | Boot configuration control bit 12 | N | | L1 | GPIO\_15 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | L1 | GPIO\_15 | UART\_RX | PX\_3 | DI | QUP0 SE3, lane 3: UART\_RX | Y | | L1 | GPIO\_15 | SPI\_CS\_0 | PX\_3 | DO | QUP0 SE3, lane 3: SPI\_CS\_0 | Y | | L1 | GPIO\_15 | QDSS\_CTI\_TRIG0\_OUT\_MIRA | PX\_3 | DO | QDSS trigger output 0 A | Y | | L1 | GPIO\_15 | BOOT\_CONFIG[9] | PX\_3 | DI | Boot configuration control bit 9 | Y | | P4 | GPIO\_16 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | P4 | GPIO\_16 | UART\_CTS | PX\_3 | DI | QUP0 SE4, lane 0: UART\_CTS | Y | | P4 | GPIO\_16 | I2C\_SDA | PX\_3 | B | QUP0 SE4, lane 0: I2C\_SDA | Y | | P4 | GPIO\_16 | SPI\_MISO | PX\_3 | DI | QUP0 SE4, lane 0: SPI\_MISO | Y | | P4 | GPIO\_16 | QDSS\_CTI\_TRIG1\_OUT\_MIRA | PX\_3 | DO | QDSS trigger output 1 A | Y | | N5 | GPIO\_17 | | PX\_3 | PD:nppukp | Configurable I/O | N | | N5 | GPIO\_17 | UART\_RFR | PX\_3 | DO | QUP0 SE4, lane 1: UART\_RFR | N | | N5 | GPIO\_17 | I2C\_SCL | PX\_3 | DO | QUP0 SE4, lane 1: I2C\_SCL | N | | N5 | GPIO\_17 | SPI\_MOSI | PX\_3 | DO | QUP0 SE4, lane 1: SPI\_MOSI | N | | N1 | GPIO\_18 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | N1 | GPIO\_18 | UART\_TX | PX\_3 | DO | QUP0 SE4, lane 2: UART\_TX | Y | | N1 | GPIO\_18 | SPI\_SCLK | PX\_3 | DO | QUP0 SE4, lane 2: SPI\_SCLK | Y | | N1 | GPIO\_18 | QDSS\_CTI\_TRIG1\_IN\_MIRA | PX\_3 | DI | QDSS trigger input 1 A | Y | | N3 | GPIO\_19 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | N3 | GPIO\_19 | UART\_RX | PX\_3 | DI | QUP0 SE4, lane 3: UART\_RX | Y | | N3 | GPIO\_19 | SPI\_CS\_0 | PX\_3 | DO | QUP0 SE4, lane 3: SPI\_CS\_0 | Y | | BG5 | GPIO\_20 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BG5 | GPIO\_20 | UART\_CTS | PX\_3 | DI | QUP0 SE5, lane 0: UART\_CTS | Y | | BG5 | GPIO\_20 | I2C\_SDA | PX\_3 | B | QUP0 SE5, lane 0: I2C\_SDA | Y | | BG5 | GPIO\_20 | SPI\_MISO | PX\_3 | DI | QUP0 SE5, lane 0: SPI\_MISO | Y | | BG5 | GPIO\_20 | CCI\_TIMER0 | PX\_3 | DO | Camera control interface timer | Y | | BG5 | GPIO\_20 | QDSS\_GPIO\_TRACEDATA\_LOCA[6] | PX\_3 | DO | QDSS trace data 6 | Y | | BG3 | GPIO\_21 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BG3 | GPIO\_21 | UART\_RFR | PX\_3 | DO | QUP0 SE5, lane 1: UART\_RFR | Y | | BG3 | GPIO\_21 | I2C\_SCL | PX\_3 | DO | QUP0 SE5, lane 1: I2C\_SCL | Y | | BG3 | GPIO\_21 | SPI\_MOSI | PX\_3 | DO | QUP 0 SE5, lane 1: SPI\_MOSI | Y | | BG3 | GPIO\_21 | CCI\_TIMER1 | PX\_3 | DO | Camera control interface timer 1 | Y | | BG3 | GPIO\_21 | QDSS\_GPIO\_TRACEDATA\_LOCA[7] | PX\_3 | DO | QDSS trace data 7 | Y | | BF6 | GPIO\_22 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BF6 | GPIO\_22 | UART\_TX | PX\_3 | DO | QUP0 SE5, lane 2: UART\_TX | N | | BF6 | GPIO\_22 | SPI\_SCLK | PX\_3 | DO | QUP0 SE5, lane 2: SPI\_SCLK | N | | BF6 | GPIO\_22 | QDSS\_GPIO\_TRACEDATA\_LOCA[8] | PX\_3 | DO | QDSS trace data 8 | N | | BF4 | GPIO\_23 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BF4 | GPIO\_23 | UART\_RX | PX\_3 | DI | QUP0 SE5, lane 3: UART\_RX | Y | | BF4 | GPIO\_23 | SPI\_CS\_0 | PX\_3 | DO | QUP0 SE5, lane 3: SPI\_CS\_0 | Y | | BF4 | GPIO\_23 | QDSS\_GPIO\_TRACEDATA\_LOCA[9] | PX\_3 | DO | QDSS trace data 9 | Y | | BF2 | GPIO\_24 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BF2 | GPIO\_24 | UART\_CTS | PX\_3 | DI | QUP0 SE6, lane 0: UART\_CTS | Y | | BF2 | GPIO\_24 | I2C\_SDA | PX\_3 | B | QUP0 SE6, lane 0: I2C\_SDA | Y | | BF2 | GPIO\_24 | SPI\_MISO | PX\_3 | DI | QUP0 SE6, lane 0: SPI\_MISO | Y | | BF2 | GPIO\_24 | QDSS\_GPIO\_TRACEDATA\_LOCA[10] | PX\_3 | DO | QDSS trace data bit 10 A | Y | | BE1 | GPIO\_25 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BE1 | GPIO\_25 | UART\_RFR | PX\_3 | DO | QUP0 SE6, lane 1: UART\_RFR | Y | | BE1 | GPIO\_25 | I2C\_SCL | PX\_3 | DO | QUP0 SE6, lane 1: I2C\_SCL | Y | | BE1 | GPIO\_25 | SPI\_MOSI | PX\_3 | DO | QUP0 SE6, lane 1: SPI\_MOSI | Y | | BE1 | GPIO\_25 | QDSS\_GPIO\_TRACEDATA\_LOCA[11] | PX\_3 | DO | QDSS trace data bit 11 A | Y | | BE3 | GPIO\_26 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BE3 | GPIO\_26 | UART\_TX | PX\_3 | DO | QUP0 SE6, lane 2: UART\_TX | N | | BE3 | GPIO\_26 | SPI\_SCLK | PX\_3 | DO | QUP0 SE6, lane 2: SPI\_SCLK | N | | BE3 | GPIO\_26 | QDSS\_GPIO\_TRACEDATA\_LOCA[12] | PX\_3 | DO | QDSS trace data bit 12 A | N | | BD2 | GPIO\_27 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BD2 | GPIO\_27 | UART\_RX | PX\_3 | DI | QUP0 SE6, lane 3: UART\_RX | Y | | BD2 | GPIO\_27 | SPI\_CS\_0 | PX\_3 | DO | QUP0 SE6, lane 3: SPI\_CS\_0 | Y | | BD2 | GPIO\_27 | QDSS\_GPIO\_TRACEDATA\_LOCA[13] | PX\_3 | DO | QDSS trace data 13 | Y | | BE5 | GPIO\_28 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BE5 | GPIO\_28 | UART\_CTS | PX\_3 | DI | QUP0 SE7, lane 0: UART\_CTS | Y | | BE5 | GPIO\_28 | I2C\_SDA | PX\_3 | B | QUP0 SE7, lane 0: I2C\_SDA | Y | | BE5 | GPIO\_28 | SPI\_MISO | PX\_3 | DI | QUP0 SE7, lane 0: SPI\_MISO | Y | | BE5 | GPIO\_28 | QDSS\_GPIO\_TRACEDATA\_LOCA[14] | PX\_3 | DO | QDSS trace data 14 | Y | | BD6 | GPIO\_29 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BD6 | GPIO\_29 | UART\_RFR | PX\_3 | DO | QUP0 SE7, lane 1: UART\_RFR | N | | BD6 | GPIO\_29 | I2C\_SCL | PX\_3 | DO | QUP0 SE7, lane 1: I2C\_SCL | N | | BD6 | GPIO\_29 | SPI\_MOSI | PX\_3 | DO | QUP0 SE7, lane 1: SPI\_MOSI | N | | BD6 | GPIO\_29 | QDSS\_GPIO\_TRACEDATA\_LOCA[15] | PX\_3 | DO | QDSS trace data bit 15 A | N | | BD4 | GPIO\_30 | | PX\_3 | PU:nppdkp | Configurable I/O | N | | BD4 | GPIO\_30 | UART\_TX | PX\_3 | DO | QUP0 SE7, lane 2: UART\_TX | N | | BD4 | GPIO\_30 | SPI\_SCLK | PX\_3 | DO | QUP0 SE7, lane 2: SPI\_SCLK | N | | BC5 | GPIO\_31 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BC5 | GPIO\_31 | UART\_RX | PX\_3 | DI | QUP0 SE7, lane 3: UART\_RX | Y | | BC5 | GPIO\_31 | SPI\_CS\_0 | PX\_3 | DO | QUP0 SE7, lane 3: SPI\_CS\_0 | Y | | AW43 | GPIO\_32 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AW43 | GPIO\_32 | UART\_CTS | PX\_3 | DI | QUP1 SE0, lane 0: UART\_CTS | Y | | AW43 | GPIO\_32 | I2C\_SDA | PX\_3 | B | QUP1 SE0, lane 0: I2C\_SDA | Y | | AW43 | GPIO\_32 | SPI\_MISO | PX\_3 | DI | QUP1 SE0, lane 0: SPI\_MISO | Y | | AW43 | GPIO\_32 | QUP\_SPMI\_DATA | PX\_3 | B | | Y | | AW41 | GPIO\_33 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AW41 | GPIO\_33 | UART\_RFR | PX\_3 | DO | QUP1 SE0, lane 1: UART\_RFR | N | | AW41 | GPIO\_33 | I2C\_SCL | PX\_3 | DO | QUP1 SE0, lane 1: I2C\_SCL | N | | AW41 | GPIO\_33 | SPI\_MOSI | PX\_3 | DO | QUP1 SE0, lane 1: SPI\_MOSI | N | | AW41 | GPIO\_33 | QUP\_SPMI\_CLK | PX\_3 | DO | | N | | AY42 | GPIO\_34 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AY42 | GPIO\_34 | UART\_TX | PX\_3 | DO | QUP1 SE0, lane 2: UART\_TX | Y | | AY42 | GPIO\_34 | SPI\_SCLK | PX\_3 | DO | QUP1 SE0, lane 2: SPI\_SCLK | Y | | BA43 | GPIO\_35 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BA43 | GPIO\_35 | UART\_RX | PX\_3 | DI | QUP1 SE0, lane 3: UART\_RX | Y | | BA43 | GPIO\_35 | SPI\_CS\_0 | PX\_3 | DO | QUP1 SE0, lane 3: SPI\_CS\_0 | Y | | BF42 | GPIO\_36 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BF42 | GPIO\_36 | UART\_CTS | PX\_3 | DI | QUP1 SE1, lane 0: UART\_CTS | Y | | BF42 | GPIO\_36 | I2C\_SDA | PX\_3 | B | QUP1 SE1, lane 0: I2C\_SDA | Y | | BF42 | GPIO\_36 | SPI\_MISO | PX\_3 | DI | QUP1 SE1, lane 0: SPI\_MISO | Y | | BF42 | GPIO\_36 | I3C\_SDA | PX\_3 | B | QUP 1SE1, lane 0: I3C\_SDA | Y | | BG43 | GPIO\_37 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BG43 | GPIO\_37 | UART\_RFR | PX\_3 | DO | QUP1 SE1, lane 1: UART\_RFR | N | | BG43 | GPIO\_37 | I2C\_SCL | PX\_3 | DO | QUP1 SE1, lane 1: I2C\_SCL | N | | BG43 | GPIO\_37 | SPI\_MOSI | PX\_3 | DO | QUP1 SE1, lane 1: SPI\_MOSI | N | | BG43 | GPIO\_37 | I3C\_SCL | PX\_3 | DO | QUP 1SE1, lane 1: I3C\_SCL | N | | BH46 | GPIO\_38 | | PX\_3 | PU:nppdkp | Configurable I/O | N | | BH46 | GPIO\_38 | UART\_TX | PX\_3 | DO | QUP1 SE1, lane 2: UART\_TX | N | | BH46 | GPIO\_38 | SPI\_SCLK | PX\_3 | DO | QUP1 SE1, lane 2: SPI\_SCLK | N | | BH46 | GPIO\_38 | SPI\_CS\_3 | PX\_3 | DO | QUP1 SE4, lane 6: SPI\_CS\_3 | N | | BH44 | GPIO\_39 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BH44 | GPIO\_39 | UART\_RX | PX\_3 | DI | QUP1 SE1, lane 3: UART\_RX | Y | | BH44 | GPIO\_39 | SPI\_CS\_0 | PX\_3 | DO | QUP1 SE1, lane 3: SPI\_CS\_0 | Y | | AY46 | GPIO\_40 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AY46 | GPIO\_40 | UART\_CTS | PX\_3 | DI | QUP1 SE2, lane 0: UART\_CTS | Y | | AY46 | GPIO\_40 | I2C\_SDA | PX\_3 | B | QUP1 SE2, lane 0: I2C\_SDA | Y | | AY46 | GPIO\_40 | SPI\_MISO | PX\_3 | DI | QUP1 SE2, lane 0: SPI\_MISO | Y | | AY44 | GPIO\_41 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AY44 | GPIO\_41 | UART\_RFR | PX\_3 | DO | QUP1 SE2, lane 1: UART\_RFR | Y | | AY44 | GPIO\_41 | I2C\_SCL | PX\_3 | DO | QUP1 SE2, lane 1: I2C\_SCL | Y | | AY44 | GPIO\_41 | SPI\_MOSI | PX\_3 | DO | QUP1 SE2, lane 1: SPI\_MOSI | Y | | BA45 | GPIO\_42 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BA45 | GPIO\_42 | UART\_TX | PX\_3 | DO | QUP1 SE2, lane 2: UART\_TX | N | | BA45 | GPIO\_42 | SPI\_SCLK | PX\_3 | DO | QUP1 SE2, lane 2: SPI\_SCLK | N | | BB46 | GPIO\_43 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BB46 | GPIO\_43 | UART\_RX | PX\_3 | DI | QUP1 SE2, lane 3: UART\_RX | Y | | BB46 | GPIO\_43 | SPI\_CS\_0 | PX\_3 | DO | QUP1 SE2, lane 3: SPI\_CS\_0 | Y | | BA41 | GPIO\_44 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BA41 | GPIO\_44 | UART\_CTS | PX\_3 | DI | QUP1 SE3, lane 0: UART\_CTS | Y | | BA41 | GPIO\_44 | I2C\_SDA | PX\_3 | B | QUP1 SE3, lane 0: I2C\_SDA | Y | | BA41 | GPIO\_44 | SPI\_MISO | PX\_3 | DI | QUP1 SE3, lane 0: SPI\_MISO | Y | | BB42 | GPIO\_45 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BB42 | GPIO\_45 | UART\_RFR | PX\_3 | DO | QUP1 SE3, lane 1: UART\_RFR | Y | | BB42 | GPIO\_45 | I2C\_SCL | PX\_3 | DO | QUP1 SE3, lane 1: I2C\_SCL | Y | | BB42 | GPIO\_45 | SPI\_MOSI | PX\_3 | DO | QUP1 SE3, lane 1: SPI\_MOSI | Y | | BC41 | GPIO\_46 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BC41 | GPIO\_46 | UART\_TX | PX\_3 | DO | QUP1 SE3, lane 2: UART\_TX | N | | BC41 | GPIO\_46 | SPI\_SCLK | PX\_3 | DO | QUP1 SE3, lane 2: SPI\_SCLK | N | | BC43 | GPIO\_47 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BC43 | GPIO\_47 | UART\_RX | PX\_3 | DI | QUP1 SE3, lane 3: UART\_RX | Y | | BC43 | GPIO\_47 | SPI\_CS\_0 | PX\_3 | DO | QUP1 SE3, lane 3: SPI\_CS\_0 | Y | | BC43 | GPIO\_47 | DP\_HOT\_PLUG\_DETECT | PX\_3 | DI | DisplayPort hot plug detect | Y | | BB44 | GPIO\_48 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BB44 | GPIO\_48 | UART\_CTS | PX\_3 | DI | QUP1 SE4, lane 0: UART\_CTS | Y | | BB44 | GPIO\_48 | I2C\_SDA | PX\_3 | B | QUP1 SE4, lane 0: I2C\_SDA | Y | | BB44 | GPIO\_48 | SPI\_MISO | PX\_3 | DI | QUP1 SE4, lane 0: SPI\_MISO | Y | | BC47 | GPIO\_49 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BC47 | GPIO\_49 | UART\_RFR | PX\_3 | DO | QUP1 SE4, lane 1: UART\_RFR | N | | BC47 | GPIO\_49 | I2C\_SCL | PX\_3 | DO | QUP1 SE4, lane 1: I2C\_SCL | N | | BC47 | GPIO\_49 | SPI\_MOSI | PX\_3 | DO | QUP1 SE4, lane 1: SPI\_MOSI | N | | BC45 | GPIO\_50 | | PX\_3 | PD-nppukp | Configurable I/O | N | | BC45 | GPIO\_50 | UART\_TX | PX\_3 | DO | QUP1 SE4, lane 2: UART\_TX | N | | BC45 | GPIO\_50 | SPI\_SCLK | PX\_3 | DO | QUP1 SE4, lane 2: SPI\_SCLK | N | | BC45 | GPIO\_50 | SPI\_CS\_3 | PX\_3 | DO | QUP1 SE6, lane 6: SPI\_CS\_3 | N | | BD46 | GPIO\_51 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BD46 | GPIO\_51 | UART\_RX | PX\_3 | DI | QUP1 SE4, lane 3: UART\_RX | Y | | BD46 | GPIO\_51 | SPI\_CS\_0 | PX\_3 | DO | QUP1 SE4, lane 3: SPI\_CS\_0 | Y | | BD44 | GPIO\_52 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BD44 | GPIO\_52 | UART\_CTS | PX\_3 | DI | QUP1 SE5, lane 0: UART\_CTS | Y | | BD44 | GPIO\_52 | I2C\_SDA | PX\_3 | B | QUP1 SE5, lane 0: I2C\_SDA | Y | | BD44 | GPIO\_52 | SPI\_MISO | PX\_3 | DI | QUP1 SE5, lane 0: SPI\_MISO | Y | | BE45 | GPIO\_53 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BE45 | GPIO\_53 | UART\_RFR | PX\_3 | DO | QUP1 SE5, lane 1: UART\_RFR | N | | BE45 | GPIO\_53 | I2C\_SCL | PX\_3 | DO | QUP1 SE5, lane 1: I2C\_SCL | N | | BE45 | GPIO\_53 | SPI\_MOSI | PX\_3 | DO | QUP1 SE5, lane 1: SPI\_MOSI | N | | BD42 | GPIO\_54 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BD42 | GPIO\_54 | UART\_TX | PX\_3 | DO | QUP1 SE5, lane 2: UART\_TX | Y | | BD42 | GPIO\_54 | SPI\_SCLK | PX\_3 | DO | QUP1 SE5, lane 2: SPI\_SCLK | Y | | BD42 | GPIO\_54 | SPI\_CS\_2 | PX\_3 | DO | QUP1 SE4, lane 5: SPI\_CS\_2 | Y | | BE43 | GPIO\_55 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BE43 | GPIO\_55 | UART\_RX | PX\_3 | DI | QUP1 SE5, lane 3: UART\_RX | Y | | BE43 | GPIO\_55 | SPI\_CS\_0 | PX\_3 | DO | QUP1 SE5, lane 3: SPI\_CS\_0 | Y | | BE43 | GPIO\_55 | SPI\_CS\_1 | PX\_3 | DO | QUP1 SE4, lane 4: SPI\_CS\_1 | Y | | BF46 | GPIO\_56 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BF46 | GPIO\_56 | UART\_CTS | PX\_3 | DI | QUP1 SE6, lane 0: UART\_CTS | Y | | BF46 | GPIO\_56 | I2C\_SDA | PX\_3 | B | QUP1 SE6, lane 0: I2C\_SDA | Y | | BF46 | GPIO\_56 | SPI\_MISO | PX\_3 | DI | QUP1 SE6, lane 0: SPI\_MISO | Y | | BF44 | GPIO\_57 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BF44 | GPIO\_57 | UART\_RFR | PX\_3 | DO | QUP1 SE6, lane 1: UART\_RFR | N | | BF44 | GPIO\_57 | I2C\_SCL | PX\_3 | DO | QUP1 SE6, lane 1: I2C\_SCL | N | | BF44 | GPIO\_57 | SPI\_MOSI | PX\_3 | DO | QUP1 SE6, lane 1: SPI\_MOSI | N | | BG47 | GPIO\_58 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BG47 | GPIO\_58 | UART\_TX | PX\_3 | DO | QUP1 SE6, lane 2: UART\_TX | N | | BG47 | GPIO\_58 | SPI\_SCLK | PX\_3 | DO | QUP1 SE6, lane 2: SPI\_SCLK | N | | BG47 | GPIO\_58 | QDSS\_GPIO\_TRACECTL\_LOCB | PX\_3 | DO | QDSS trace control B | N | | BG45 | GPIO\_59 | | PX\_3 | PU:nppdkp | Configurable I/O | Y | | BG45 | GPIO\_59 | UART\_RX | PX\_3 | DI | QUP1 SE6, lane 3: UART\_RX | Y | | BG45 | GPIO\_59 | SPI\_CS\_0 | PX\_3 | DO | QUP1 SE6, lane 3: SPI\_CS\_0 | Y | | BG45 | GPIO\_59 | QDSS\_GPIO\_TRACECLK\_LOCB | PX\_3 | DO | QDSS trace clock B | Y | | BH42 | GPIO\_60 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BH42 | GPIO\_60 | UART\_CTS | PX\_3 | DI | QUP1 SE7, lane 0: UART\_CTS | Y | | BH42 | GPIO\_60 | I2C\_SDA | PX\_3 | B | QUP1 SE7, lane 0: I2C\_SDA | Y | | BH42 | GPIO\_60 | SPI\_MISO | PX\_3 | DI | QUP1 SE7, lane 0: SPI\_MISO | Y | | BH42 | GPIO\_60 | EDP\_HOT\_PLUG\_DETECT | PX\_3 | DI | eDP hot plug detect | Y | | BJ43 | GPIO\_61 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BJ43 | GPIO\_61 | UART\_RFR | PX\_3 | DO | QUP1 SE7, lane 1: UART\_RFR | Y | | BJ43 | GPIO\_61 | I2C\_SCL | PX\_3 | DO | QUP1 SE7, lane 1: I2C\_SCL | Y | | BJ43 | GPIO\_61 | SPI\_MOSI | PX\_3 | DO | QUP1 SE7, lane 1: SPI\_MOSI | Y | | BJ43 | GPIO\_61 | SD\_WRITE\_PROTECT | PX\_3 | DO | Secure digital card write protection | Y | | BJ45 | GPIO\_62 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BJ45 | GPIO\_62 | UART\_TX | PX\_3 | DO | QUP1 SE7, lane 2: UART\_TX | N | | BJ45 | GPIO\_62 | SPI\_SCLK | PX\_3 | DO | QUP1 SE7, lane 2: SPI\_SCLK | N | | BJ45 | GPIO\_62 | SPI\_CS\_1 | PX\_3 | DO | QUP1 SE6, lane 4: SPI\_CS\_1 | N | | BK46 | GPIO\_63 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BK46 | GPIO\_63 | UART\_RX | PX\_3 | DI | QUP1 SE6, lane 3: UART\_RX | Y | | BK46 | GPIO\_63 | SPI\_CS\_0 | PX\_3 | DO | QUP1 SE6, lane 3: SPI\_CS\_0 | Y | | BK46 | GPIO\_63 | SPI\_CS\_2 | PX\_3 | DO | QUP1 SE6, lane 5: SPI\_CS\_2 | Y | | BK46 | GPIO\_63 | BOOT\_CONFIG[11] | PX\_3 | DI | Boot configuration control bit 11 | Y | | AA1 | GPIO\_64 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AA1 | GPIO\_64 | CAM\_MCLK0 | PX\_3 | DO | Camera master clock 0 | N | | Y2 | GPIO\_65 | | PX\_3 | PD:nppukp | Configurable I/O | N | | Y2 | GPIO\_65 | CAM\_MCLK1 | PX\_3 | DO | Camera master clock 1 | N | | AA3 | GPIO\_66 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AA3 | GPIO\_66 | CAM\_MCLK2 | PX\_3 | DO | Camera master clock 2 | N | | W1 | GPIO\_67 | | PX\_3 | PD:nppukp | Configurable I/O | N | | W1 | GPIO\_67 | CAM\_MCLK3 | PX\_3 | DO | Camera master clock 3 | N | | P2 | GPIO\_68 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | P2 | GPIO\_68 | CAM\_MCLK4 | | DO | Camera master clock 4 | Y | | BC3 | GPIO\_69 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BC3 | GPIO\_69 | CCI\_I2C\_SDA0 | PX\_3 | B | Dedicated camera control interface I²C serial data | N | | BB2 | GPIO\_70 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BB2 | GPIO\_70 | CCI\_I2C\_SCL0 | PX\_3 | DO | Dedicated camera control interface I²C clock | N | | BB4 | GPIO\_71 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BB4 | GPIO\_71 | CCI\_I2C\_SDA1 | PX\_3 | B | Dedicated camera control interface I²C 1 serial data | N | | BB6 | GPIO\_72 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BB6 | GPIO\_72 | CCI\_I2C\_SCL1 | PX\_3 | DO | Dedicated camera control interface I²C 1 clock | Y | | BA1 | GPIO\_73 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BA1 | GPIO\_73 | CCI\_I2C\_SDA2 | PX\_3 | B | Dedicated camera control interface I²C 2 serial data | N | | BA3 | GPIO\_74 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BA3 | GPIO\_74 | CCI\_I2C\_SCL2 | PX\_3 | DO | Dedicated camera control interface I²C 2 clock | N | | BA5 | GPIO\_75 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BA5 | GPIO\_75 | CCI\_I2C\_SDA3 | PX\_3 | B | Dedicated camera control interface I²C 3 serial data | Y | | BA7 | GPIO\_76 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | | PX\_3 | PD:nppukp | Configurable I/O | N | | BA7 | GPIO\_76 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | CCI\_I2C\_SCL3 | PX\_3 | DO | Dedicated camera control interface I²C 3 clock | N | | BA7 | GPIO\_76 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | GCC\_GP1\_CLK\_MIRB | PX\_3 | DO | Global general-purpose clock 1 B | N | | BH4 | GPIO\_77 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BH4 | GPIO\_77 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | CCI\_TIMER2 | PX\_3 | DO | Camera control interface timer 2 | Y | | BH4 | GPIO\_77 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | GCC\_GP2\_CLK\_MIRB | PX\_3 | DO | General-purpose clock | Y | | BH2 | GPIO\_78 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BH2 | GPIO\_78 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | CCI\_TIMER3 | PX\_3 | DO | Camera control interface timer 3 | Y | | BH2 | GPIO\_78 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | CCI\_ASYNC\_IN1 | PX\_3 | DI | Camera control interface async 1 | Y | | BH2 | GPIO\_78 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | GCC\_GP3\_CLK\_MIRB | PX\_3 | DO | General-purpose clock | Y | | BH6 | GPIO\_79 | | PX\_3 | PU:nppdkp | Configurable I/O | Y | | BH6 | GPIO\_79 | CCI\_TIMER4 | PX\_3 | DO | Camera control interface timer 4 | Y | | BH6 | GPIO\_79 | CCI\_ASYNC\_IN2 | PX\_3 | DI | Camera control interface async 2 | Y | | BH6 | GPIO\_79 | PCIE1\_CLKREQN | PX\_3 | DI | PCIe1 clock request signal | Y | | BH6 | GPIO\_79 | MDP\_VSYNC\_E | PX\_3 | DI | MDP vertical sync – external | Y | | AG47 | GPIO\_80 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AG47 | GPIO\_80 | MDP\_VSYNC\_P\_MIRA | PX\_3 | DI | MDP vertical sync – primary | Y | | AG47 | GPIO\_80 | MDP\_VSYNC0\_OUT | PX\_3 | DO | MDP vertical sync 0 output | Y | | AG47 | GPIO\_80 | MDP\_VSYNC1\_OUT | PX\_3 | DO | MDP vertical sync 1 output | Y | | AG47 | GPIO\_80 | MDP\_VSYNC4\_OUT | PX\_3 | DO | MDP vertical sync 4 output | Y | | AR47 | GPIO\_81 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AR47 | GPIO\_81 | MDP\_VSYNC\_S\_MIRA | PX\_3 | DI | MDP vertical sync – secondary | Y | | AR47 | GPIO\_81 | MDP\_VSYNC2\_OUT | PX\_3 | DO | MDP vertical sync 2 output | Y | | AR47 | GPIO\_81 | MDP\_VSYNC3\_OUT | PX\_3 | DO | MDP vertical sync 3 output | Y | | AR47 | GPIO\_81 | MDP\_VSYNC5\_OUT | PX\_3 | DO | MDP vertical sync 5 output | Y | | BK44 | GPIO\_82 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BK44 | GPIO\_82 | FORCED\_USB\_BOOT | PX\_3 | DI | Forced USB boot | Y | | K2 | GPIO\_83 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | K2 | GPIO\_83 | BOOT\_CONFIG[8] | PX\_3 | DI | Boot configuration control bit 8 | Y | | BR11 | GPIO\_84 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BR11 | GPIO\_84 | USB2PHY\_AC\_EN0 | PX\_3 | DO | USB AC coupling 0 control | N | | BP10 | GPIO\_85 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BP10 | GPIO\_85 | USB2PHY\_AC\_EN1 | PX\_3 | DO | USB AC coupling 1 control | N | | BR9 | GPIO\_86 | – | PX\_3 | PD:nppukp | Configurable I/O | Y | | BN9 | GPIO\_87 | – | PX\_3 | PD:nppukp | Configurable I/O | N | | BL9 | GPIO\_88 | | PX\_3 | PU:nppdkp | Configurable I/O | Y | | BL9 | GPIO\_88 | PCIE0\_CLKREQN | PX\_3 | DI | PCIe clock request | Y | | BJ9 | GPIO\_89 | – | PX\_3 | PD:nppukp | Configurable I/O | Y | | BP8 | GPIO\_90 | – | PX\_3 | PD:nppukp | Configurable I/O | Y | | K4 | GPIO\_91 | – | PX\_3 | PD:nppukp | Configurable I/O | Y | | L5 | GPIO\_93 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | L5 | GPIO\_93 | CAM\_MCLK5 | PX\_3 | DO | Camera master clock 5 | Y | | L5 | GPIO\_93 | CCI\_ASYNC\_IN0 | PX\_3 | DI | Camera control interface async | Y | | L5 | GPIO\_93 | BOOT\_CONFIG[13] | PX\_3 | DI | Boot configuration control bit 13 | Y | | W45 | GPIO\_94 | | PX\_3 | PD:nppukp | Configurable I/O | N | | W45 | GPIO\_94 | LPASS\_SLIMBUS\_CLK | PX\_3 | B | Low-power audio SLIMbus clock | N | | Y46 | GPIO\_95 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | Y46 | GPIO\_95 | LPASS\_SLIMBUS\_DATA0 | PX\_3 | B | Low-power audio SLIMbus data 0 | Y | | AA45 | GPIO\_96 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AA45 | GPIO\_96 | PRI\_MI2S\_MCLK | PX\_3 | DO | Primary MI2S master clock | N | | AA47 | GPIO\_97 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AA47 | GPIO\_97 | MI2S0\_SCK | PX\_3 | DO | MI2S 0 clock | N | | AB44 | GPIO\_98 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AB44 | GPIO\_98 | MI2S0\_DATA0 | PX\_3 | B | MI2S 0 serial data channel 0 | N | | AB46 | GPIO\_99 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AB46 | GPIO\_99 | MI2S0\_DATA1 | PX\_3 | B | MI2S 0 serial data channel 1 | N | | AH46 | GPIO\_100 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AH46 | GPIO\_100 | MI2S0\_WS | PX\_3 | B | MI2S 0 serial data word select | N | | AU45 | GPIO\_101 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AU45 | GPIO\_101 | MI2S2\_SCK | PX\_3 | B | MI2S 2 clock | Y | | AU45 | GPIO\_101 | QDSS\_GPIO\_TRACEDATA\_LOCB[0] | PX\_3 | DO | QDSS trace data bit 0 B | Y | | AV46 | GPIO\_102 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AV46 | GPIO\_102 | MI2S2\_DATA0 | PX\_3 | B | MI2S 2 serial data channel 0 | Y | | AV46 | GPIO\_102 | GP\_PDM\_MIRA[0] | PX\_3 | DO | General-purpose PDM output 0 A | Y | | AV46 | GPIO\_102 | QDSS\_GPIO\_TRACEDATA\_LOCB[1] | PX\_3 | DO | QDSS trace data bit 1 B | Y | | AV44 | GPIO\_103 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AV44 | GPIO\_103 | MI2S2\_WS | PX\_3 | B | MI2S 2 serial data word select | Y | | AV44 | GPIO\_103 | GP\_PDM\_MIRA[1] | PX\_3 | DO | General-purpose PDM output 1 A | Y | | AV44 | GPIO\_103 | QDSS\_GPIO\_TRACEDATA\_LOCB[2] | PX\_3 | DO | QDSS trace data bit 2 B | Y | | AW47 | GPIO\_104 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AW47 | GPIO\_104 | MI2S2\_DATA1 | PX\_3 | B | MI2S 2 serial data channel 1 | Y | | AW47 | GPIO\_104 | GP\_PDM\_MIRA[2] | PX\_3 | DO | General-purpose PDM output 2 A | Y | | AW47 | GPIO\_104 | QDSS\_GPIO\_TRACEDATA\_LOCB[3] | PX\_3 | DO | QDSS trace data bit 3 | Y | | AW45 | GPIO\_105 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | | PX\_3 | PD:nppukp | Configurable I/O | N | | AW45 | GPIO\_105 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | SEC\_MI2S\_MCLK | PX\_3 | DO | Secondary MI2S master clock | N | | AW45 | GPIO\_105 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | MI2S1\_DATA1 | PX\_3 | B | MI2S 1 serial data channel 1 | N | | AW45 | GPIO\_105 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | AUDIO\_REF\_CLK | PX\_3 | DI | Audio reference clock | N | | AW45 | GPIO\_105 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | GCC\_GP1\_CLK\_MIRA | PX\_3 | A | General-purpose clock 1 A | N | | AW45 | GPIO\_105 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | QDSS\_GPIO\_TRACEDATA\_LOCB[4] | PX\_3 | DO | QDSS trace data bit 4 B | N | | AU43 | GPIO\_106 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | | PX\_3 | PD:nppukp | Configurable I/O | N | | AU43 | GPIO\_106 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | MI2S1\_SCK | PX\_3 | B | MI2S 1 clock | N | | AU43 | GPIO\_106 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | GCC\_GP2\_CLK\_MIRA | PX\_3 | DO | General-purpose clock 2 A | N | | AU43 | GPIO\_106 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | QDSS\_GPIO\_TRACEDATA\_LOCB[5] | PX\_3 | DO | QDSS trace data bit 5 B | N | | AU41 | GPIO\_107 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | | PX\_3 | PD:nppukp | Configurable I/O | N | | AU41 | GPIO\_107 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | MI2S1\_DATA0 | PX\_3 | B | MI2S 1 serial data channel 0 | N | | AU41 | GPIO\_107 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | GCC\_GP3\_CLK\_MIRA | PX\_3 | DO | General-purpose clock 3 A | N | | AU41 | GPIO\_107 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_1) | QDSS\_GPIO\_TRACEDATA\_LOCB[6] | PX\_3 | DO | QDSS trace data bit 6 B | N | | AV42 | GPIO\_108 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AV42 | GPIO\_108 | MI2S1\_WS | PX\_3 | B | MI2S 1 serial word select | N | | AV42 | GPIO\_108 | QDSS\_GPIO\_TRACEDATA\_LOCB[7] | PX\_3 | DO | QDSS trace data bit 7 B | N | | BL47 | GPIO\_109 | | PX\_6 | PD:nppukp | Configurable I/O | N | | BL47 | GPIO\_109 | UIM1\_DATA | PX\_6 | B | UIM1 data (dual voltage) | N | | BM46 | GPIO\_110 | | PX\_6 | PD:nppukp | Configurable I/O | N | | BM46 | GPIO\_110 | UIM1\_CLK | PX\_6 | DO | UIM1 clock (dual voltage) | N | | BP46 | GPIO\_111 | | PX\_6 | PD:nppukp | Configurable I/O | N | | BP46 | GPIO\_111 | UIM1\_RESET | PX\_6 | DO | UIM1 reset (dual voltage) | N | | BN45 | GPIO\_112 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BN45 | GPIO\_112 | UIM1\_PRESENT | PX\_3 | DI | UIM1 presence detection | Y | | BR45 | GPIO\_113 | | PX\_5 | PD:nppukp | Configurable I/O | N | | BR45 | GPIO\_113 | UIM0\_DATA | PX\_5 | B | UIM0 data (dual voltage) | N | | BN43 | GPIO\_114 | | PX\_5 | PD:nppukp | Configurable I/O | N | | BN43 | GPIO\_114 | UIM0\_CLK | PX\_5 | DO | UIM0 clock (dual voltage) | N | | BM42 | GPIO\_115 | | PX\_5 | PD:nppukp | Configurable I/O | N | | BM42 | GPIO\_115 | UIM0\_RESET | PX\_5 | DO | UIM0\_RESET | N | | BM44 | GPIO\_116 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BM44 | GPIO\_116 | UIM0\_PRESENT | PX\_3 | DI | UIM0 presence detection | Y | | BP6 | GPIO\_117 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BP6 | GPIO\_117 | RFFE0\_CLK | PX\_3 | DO | RF front-end interface clock | Y | | BM6 | GPIO\_118 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BM6 | GPIO\_118 | RFFE0\_DATA | PX\_3 | B | RF front-end 0 interface data | N | | BM6 | GPIO\_118 | BOOT\_CONFIG[0] | PX\_3 | DI | Boot configuration control bit 0 | N | | BK6 | GPIO\_119 | – | PX\_3 | PD:nppukp | Configurable I/O | Y | | BL5 | GPIO\_120 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BL5 | GPIO\_120 | BOOT\_CONFIG[1] | PX\_3 | DI | Boot configuration control bit 1 | N | | BR5 | GPIO\_121 | – | PX\_3 | PD:nppukp | Configurable I/O | Y | | BP4 | GPIO\_122 | | PX\_3 | >PD:nppukp | Configurable I/O | N | | BP4 | GPIO\_122 | BOOT\_CONFIG[2] | PX\_3 | DI | Boot configuration control bit 2 | N | | BM4 | GPIO\_123 | – | PX\_3 | PD:nppukp | Configurable I/O | Y | | BL3 | GPIO\_124 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BL3 | | BOOT\_CONFIG[3] | PX\_3 | DI | Boot configuration control bit 3 | N | | BL7 | GPIO\_125 | – | PX\_3 | PD:nppukp | Configurable I/O | Y | | BJ7 | GPIO\_126 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BJ7 | GPIO\_126 | BOOT\_CONFIG[4] | PX\_3 | DI | Boot configuration control bit 4 | N | | BM8 | GPIO\_127 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BM8 | GPIO\_127 | WLAN\_COEX\_UART1\_RX | PX\_3 | DI | Interface between WCN and QCS6490 | Y | | BK8 | GPIO\_128 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BK8 | GPIO\_128 | WLAN\_COEX\_UART1\_TX | PX\_3 | DO | Interface between WCN and QCS6490 | Y | | BK8 | GPIO\_128 | BOOT\_CONFIG[10] | PX\_3 | DI | Boot configuration control bit 10 | Y | | BP14 | GPIO\_129 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BP14 | GPIO\_129 | NAV\_GPIO\_0 | PX\_3 | B | Generic input/output 0 for GNSS | Y | | BR13 | GPIO\_130 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BR13 | GPIO\_130 | NAV\_GPIO\_1 | PX\_3 | B | Generic input/output 1 for GNSS | Y | | BR13 | GPIO\_130 | BOOT\_CONFIG[7] | PX\_3 | DI | Boot configuration control bit 7 | Y | | BJ5 | GPIO\_131 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BJ5 | GPIO\_131 | PA\_INDICATOR\_1\_OR\_2 | PX\_3 | DO | PA transmit indicator | Y | | BJ5 | GPIO\_131 | NAV\_GPIO\_2 | PX\_3 | B | Generic input/output 2 for GNSS | Y | | BJ5 | GPIO\_131 | BOOT\_CONFIG[5] | PX\_3 | DI | Boot configuration control bit 5 | Y | | BN5 | GPIO\_132 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BN5 | GPIO\_132 | GRFC0\_MIRA | PX\_3 | DO | Generic RF controller bit 0 A | N | | BN5 | GPIO\_132 | BOOT\_CONFIG[6] | PX\_3 | DI | Boot configuration control bit 6 | N | | BP12 | GPIO\_133 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BP12 | GPIO\_133 | QLINK0\_REQUEST | PX\_3 | DI | QLink0 request | Y | | BN15 | GPIO\_134 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BN15 | GPIO\_134 | QLINK0\_ENABLE | PX\_3 | DO | QLink0 enable | N | | BR15 | GPIO\_135 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BR15 | GPIO\_135 | QLINK0\_WMSS\_RESET\_N | PX\_3 | DO | QLINK0 SDR subsystem
reset output | N | | BR15 | GPIO\_135 | BOOT\_CONFIG[14] | PX\_3 | DI | Boot configuration control bit 14 | N | | BP16 | GPIO\_136 | – | PX\_3 | PD:nppukp | Configurable I/O | Y | | BR17 | GPIO\_137 | – | PX\_3 | PD:nppukp | Configurable I/O | N | | BN7 | GPIO\_138 | | PX\_3 | | Configurable I/O | N | | BN7 | GPIO\_138 | BOOT\_CONFIG[15] | PX\_3 | DI | Boot configuration control bit 15 | N | | BJ41 | GPIO\_139 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BJ41 | GPIO\_139 | FORCED\_USB\_BOOT\_POLARITY\_ SEL | PX\_3 | DI | Forced USB boot parity select | N | | BK42 | GPIO\_140 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BK42 | GPIO\_140 | USB\_PHY\_PS | PX\_3 | DI | USB PHY port select | Y | | BL45 | GPIO\_141 | – | PX\_3 | PD:nppukp | Configurable I/O | Y | | BL43 | GPIO\_142 | – | PX\_3 | PD:nppukp | Configurable I/O | Y | | N45 | GPIO\_144 | | PX\_3 | PD:nppukp | Configurable I/O | N | | N45 | GPIO\_144 | LPI\_GPIO\_0 [^4^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_a4n_nhb_w1c) | PX\_3 | B | LPI GPIO 0 | N | | N45 | GPIO\_144 | SWR\_TX\_CLK | PX\_3 | DO | SoundWire transmit clock | N | | N45 | GPIO\_144 | LPI\_QUA\_MI2S\_SCK | PX\_3 | B | LPI quaternary MI2S clock | N | | P46 | GPIO\_145 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | P46 | GPIO\_145 | LPI\_GPIO\_1 | PX\_3 | B | LPI GPIO 1 | Y | | P46 | GPIO\_145 | SWR\_TX\_DATA0 | PX\_3 | DO | SoundWire transmit data 0 | Y | | P46 | GPIO\_145 | LPI\_QUA\_MI2S\_WS | PX\_3 | B | LPI quaternary MI2S word select | Y | | P44 | GPIO\_146 | | PX\_3 | PD:nppukp | Configurable I/O | N | | P44 | GPIO\_146 | LPI\_GPIO\_2 | PX\_3 | B | LPI GPIO 2 | N | | P44 | GPIO\_146 | SWR\_TX\_DATA1 | PX\_3 | DO | SoundWire transmit data 1 | N | | P44 | GPIO\_146 | LPI\_QUA\_MI2S\_DATA0 | PX\_3 | B | LPI quaternary MI2S data 0 | N | | N47 | GPIO\_147 | | PX\_3 | PD:nppukp | Configurable I/O | N | | N47 | GPIO\_147 | LPI\_GPIO\_3 | PX\_3 | B | LPI GPIO 3 | N | | N47 | GPIO\_147 | SWR\_RX\_CLK | PX\_3 | DI | SoundWire receive clock | N | | N47 | GPIO\_147 | LPI\_QUA\_MI2S\_DATA1 | PX\_3 | B | LPI quaternary MI2S data 1 | N | | L45 | GPIO\_148 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | L45 | GPIO\_148 | LPI\_GPIO\_4 | PX\_3 | B | LPI GPIO 4 | Y | | L45 | GPIO\_148 | SWR\_RX\_DATA0 | PX\_3 | DI | SoundWire receive data 0 | Y | | L45 | GPIO\_148 | LPI\_QUA\_MI2S\_DATA2 | PX\_3 | B | LPI quaternary MI2S data 2 | Y | | M46 | GPIO\_149 | | PX\_3 | PD:nppuk | Configurable I/O | N | | M46 | GPIO\_149 | LPI\_GPIO\_5 | PX\_3 | B | LPI GPIO 5 | N | | M46 | GPIO\_149 | SWR\_RX\_DATA1 | PX\_3 | DI | SoundWire receive data 1 | N | | M46 | GPIO\_149 | EXT\_MCLK1\_C | PX\_3 | DO | External master clock 1 C | N | | M46 | GPIO\_149 | LPI\_QUA\_MI2S\_DATA3 | PX\_3 | B | LPI quaternary MI2S data 3 | N | | P42 | GPIO\_150 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | P42 | GPIO\_150 | QDSS\_GPIO\_TRACEDATA\_LOCA[8] | PX\_3 | DO | QDSS trace data bit 8 A | Y | | P42 | GPIO\_150 | LPI\_GPIO\_6 | PX\_3 | B | LPI GPIO 6 | Y | | P42 | GPIO\_150 | LPI\_DMIC1\_CLK | PX\_3 | DO | LPI DMIC 1 Clock | Y | | P42 | GPIO\_150 | LPI\_I2S1\_CLK | PX\_3 | B | LPI I2S 1 clock | Y | | R43 | GPIO\_151 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | R43 | GPIO\_151 | QDSS\_GPIO\_TRACEDATA\_LOCA[9] | PX\_3 | DO | QDSS trace data bit 9 A | Y | | R43 | GPIO\_151 | LPI\_GPIO\_7 | PX\_3 | B | LPI GPIO 7 | Y | | R43 | GPIO\_151 | LPI\_DMIC1\_DATA | PX\_3 | DI | LPI DMIC 1 data | Y | | R43 | GPIO\_151 | LPI\_I2S1\_WS | PX\_3 | B | LPI I2S 1 word select | Y | | T44 | GPIO\_152 | | PX\_3 | PD:nppukp | Configurable I/O | N | | T44 | GPIO\_152 | QDSS\_GPIO\_TRACEdata\_LOCA[10] | PX\_3 | DO | QDSS trace data bit 10 A | N | | T44 | GPIO\_152 | LPI\_GPIO\_8 | PX\_3 | B | LPI GPIO 8 | N | | T44 | GPIO\_152 | LPI\_DMIC2\_CLK | PX\_3 | DO | LPI DMIC 2 clock | N | | T44 | GPIO\_152 | LPI\_I2S1\_data0 | PX\_3 | B | LPI I2S 1 data 0 | N | | U43 | GPIO\_153 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | U43 | GPIO\_153 | QDSS\_GPIO\_TRACEdata\_LOCA[11] | PX\_3 | DO | QDSS trace data bit 11 A | Y | | U43 | GPIO\_153 | LPI\_GPIO\_9 | PX\_3 | B | LPI GPIO 9 | Y | | U43 | GPIO\_153 | LPI\_DMIC2\_DATA | PX\_3 | DI | LPI DMIC 2 data | Y | | U43 | GPIO\_153 | LPI\_I2S1\_DATA1 | PX\_3 | B | LPI I2S 1 data 1 | Y | | U43 | GPIO\_153 | EXT\_MCLK1\_B | PX\_3 | DO | External master clock 1 B | Y | | T46 | GPIO\_154 | | PX\_3 | PD:nppukp | Configurable I/O | N | | T46 | GPIO\_154 | LPI\_GPIO\_10 | PX\_3 | B | LPI GPIO 10 | N | | T46 | GPIO\_154 | LPI\_I2S2\_CLK | PX\_3 | B | LPI MI2S 2 clock | N | | T46 | GPIO\_154 | WSA\_SWR\_CLK | PX\_3 | DO | SoundWire clock for WSA | N | | U47 | GPIO\_155 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | U47 | GPIO\_155 | LPI\_GPIO\_11 | PX\_3 | B | LPI GPIO 11 | Y | | U47 | GPIO\_155 | LPI\_I2S2\_WS | PX\_3 | B | LPI I2S 2 Word select | Y | | U47 | GPIO\_155 | WSA\_SWR\_DATA | PX\_3 | B | SoundWire data for WSA | Y | | U45 | GPIO\_156 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | U45 | GPIO\_156 | QDSS\_CTI\_TRIG0\_IN\_MIRB | PX\_3 | DI | QDSS trigger input 0 B | Y | | U45 | GPIO\_156 | LPI\_GPIO\_12 | PX\_3 | B | LPI GPIO 12 | Y | | U45 | GPIO\_156 | LPI\_DMIC3\_CLK | PX\_3 | DO | LPI DMIC 3 clock | Y | | U45 | GPIO\_156 | LPI\_I2S2\_DATA0 | PX\_3 | B | LPI I2S 2 data 0 | Y | | V46 | GPIO\_157 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | V46 | GPIO\_157 | QDSS\_CTI\_TRIG1\_IN\_MIRB | PX\_3 | DI | QDSS trigger input 1 B | Y | | V46 | GPIO\_157 | LPI\_GPIO\_13 | PX\_3 | B | LPI GPIO 13 | Y | | V46 | GPIO\_157 | LPI\_DMIC3\_DATA | PX\_3 | DO | LPI DMIC 3 data | Y | | V46 | GPIO\_157 | LPI\_I2S2\_DATA1 | PX\_3 | B | LPI I2S 2 data 1 | Y | | V46 | GPIO\_157 | EXT\_MCLK1\_A | PX\_3 | DO | External master clock 1 A | Y | | R45 | GPIO\_158 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | R45 | GPIO\_158 | LPI\_GPIO\_14 | PX\_3 | B | LPI GPIO 14 | Y | | R45 | GPIO\_158 | SWR\_TX\_DATA2 | PX\_3 | DO | SoundWire transmit data 2 | Y | | F46 | GPIO\_159 | | PX\_3 | PD:nppuk | Configurable I/O | N | | F46 | GPIO\_159 | LPI\_GPIO\_15 [^5^](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#kxg1605206453609__fn_pv4_qhb_w1c) | PX\_3 | B | LPI GPIO 15 | N | | F46 | GPIO\_159 | LPI\_I2C\_SDA | PX\_3 | B | LPI\_QUP0 SE0, lane 0: I2C\_SDA | N | | F46 | GPIO\_159 | LPI\_I3C\_SDA | PX\_3 | B | LPI\_QUP0 SE0, lane 0: I3C\_SDA | N | | F46 | GPIO\_159 | SYNC\_OUT\_GPIO\_0 | PX\_3 | DO | Sync out GPIO\_0 | N | | G47 | GPIO\_160 | | PX\_3 | PD:nppukp | Configurable I/O | N | | G47 | GPIO\_160 | LPI\_GPIO\_16 | PX\_3 | B | LPI GPIO 16 | N | | G47 | GPIO\_160 | LPI\_I2C\_SCL | PX\_3 | DO | LPI\_QUP0 SE0, lane 1: I2C\_SCL | N | | G47 | GPIO\_160 | LPI\_I3C\_SCL | PX\_3 | DO | LPI\_QUP0 SE0, lane 1: I3C\_SCL | N | | G47 | GPIO\_160 | SYNC\_OUT\_GPIO\_1 | PX\_3 | DO | Sync out GPIO\_1 | N | | G45 | GPIO\_161 | | PX\_3 | PD:nppukp | Configurable I/O | N | | G45 | GPIO\_161 | LPI\_GPIO\_17 | PX\_3 | B | LPI GPIO 17 | N | | G45 | GPIO\_161 | LPI\_I2C\_SDA | PX\_3 | B | LPI\_QUP0 SE1, lane 0: I2C\_SDA | N | | G45 | GPIO\_161 | LPI\_I3C\_SDA | PX\_3 | B | LPI\_QUP0 SE1, lane 0: I3C\_SDA | N | | G45 | GPIO\_161 | SPI\_CS\_1 | PX\_3 | DO | LPI\_QUP0 SE2, lane 4: SPI\_CS\_1 | N | | G45 | GPIO\_161 | SYNC\_OUT\_GPIO\_2 | PX\_3 | DO | Sync out GPIO\_2 | N | | H46 | GPIO\_162 | | PX\_3 | PD:nppukp | Configurable I/O | N | | H46 | GPIO\_162 | LPI\_GPIO\_18 | PX\_3 | B | LPI GPIO 18 | N | | H46 | GPIO\_162 | LPI\_I2C\_SCL | PX\_3 | DO | LPI\_QUP0 SE1, lane 1: I2C\_SCL | N | | H46 | GPIO\_162 | LPI\_I3C\_SCL | PX\_3 | DO | LPI\_QUP0 SE1, lane 1: I3C\_SCL | N | | H46 | GPIO\_162 | SYNC\_OUT\_GPIO\_3 | PX\_3 | DO | Sync out GPIO\_3 | N | | J47 | GPIO\_163 | | PX\_3 | PD:nppukp | Configurable I/O | N | | J47 | GPIO\_163 | LPI\_GPIO\_19 | PX\_3 | B | LPI GPIO 19 | N | | J47 | GPIO\_163 | LPI\_UART\_CTS | PX\_3 | DI | LPI\_QUP0 SE2, lane 0: UART\_CTS | N | | J47 | GPIO\_163 | LPI\_I2C\_SDA | PX\_3 | B | LPI\_QUP0 SE2, lane 0: I2C\_SDA | N | | J47 | GPIO\_163 | LPI\_SPI\_MISO | PX\_3 | DI | LPI\_QUP0 SE2, lane 0: SPI\_MISO | N | | J47 | GPIO\_163 | SYNC\_OUT\_GPIO\_4 | PX\_3 | DO | Sync out GPIO\_4 | N | | J45 | GPIO\_164 | | PX\_3 | PD:nppukp | Configurable I/O | N | | J45 | GPIO\_164 | LPI\_GPIO\_20 | PX\_3 | B | LPI GPIO 20 | N | | J45 | GPIO\_164 | LPI\_UART\_RFR | PX\_3 | DO | LPI\_QUP0 SE2, lane 1: UART\_RFR | N | | J45 | GPIO\_164 | LPI\_I2C\_SCL | PX\_3 | DO | LPI\_QUP0 SE2, lane 1: I2C\_SCL | N | | J45 | GPIO\_164 | LPI\_SPI\_MOSI | PX\_3 | DO | LPI\_QUP0 SE2, lane 1: SPI\_MOSI | N | | J45 | GPIO\_164 | SYNC\_OUT\_GPIO\_5 | PX\_3 | DO | Sync out GPIO\_5 | N | | K46 | GPIO\_165 | | PX\_3 | PD:nppukp | Configurable I/O | N | | K46 | GPIO\_165 | QDSS\_CTI\_TRIG0\_OUT\_MIRB | PX\_3 | DO | QDSS trigger output 0 B | N | | K46 | GPIO\_165 | LPI\_GPIO\_21 | PX\_3 | B | LPI GPIO 21 | N | | K46 | GPIO\_165 | LPI\_UART\_TX | PX\_3 | DO | LPI\_QUP0 SE2, lane 2: UART\_TX | N | | K46 | GPIO\_165 | LPI\_SPI\_SCLK | PX\_3 | DO | LPI\_QUP0 SE2, lane 2: SPI\_SCLK | N | | K46 | GPIO\_165 | SYNC\_OUT\_GPIO\_6 | PX\_3 | DO | Sync out GPIO\_6 | N | | L47 | GPIO\_166 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | L47 | GPIO\_166 | QDSS\_CTI\_TRIG1\_OUT\_MIRB | PX\_3 | DO | QDSS trigger output 1 B | Y | | L47 | GPIO\_166 | LPI\_GPIO\_22 | PX\_3 | B | LPI GPIO 22 | Y | | L47 | GPIO\_166 | LPI\_UART\_RX | PX\_3 | DI | LPI\_QUP0 SE2, lane 3: UART\_RX | Y | | L47 | GPIO\_166 | LPI\_SPI\_CS\_0 | PX\_3 | DO | LPI\_QUP0 SE2, lane 3: SPI\_CS\_0 | Y | | L47 | GPIO\_166 | SYNC\_OUT\_GPIO\_7 | PX\_3 | DO | Sync out GPIO\_7 | Y | | C45 | GPIO\_171 | | PX\_3 | PD:nppukp | Configurable I/O | N | | C45 | GPIO\_171 | QDSS\_GPIO\_TRACEDATA\_LOCB[12] | PX\_3 | DO | QDSS trace data bit 12 B | N | | C45 | GPIO\_171 | LPI\_GPIO\_23 | PX\_3 | B | LPI GPIO 23 | N | | C45 | GPIO\_171 | LPI\_I2C\_SDA | PX\_3 | B | LPI\_QUP0 SE5, lane 0: I2C\_SDA | N | | C45 | GPIO\_171 | LPI\_UART\_TX | PX\_3 | DO | LPI\_QUP0 SE5, lane 2: UART\_TX | N | | C45 | GPIO\_171 | SYNC\_OUT\_GPIO\_12 | PX\_3 | DO | Sync out GPIO\_12 | N | | D46 | GPIO\_172 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | D46 | GPIO\_172 | QDSS\_GPIO\_TRACEDATA\_LOCB[13] | PX\_3 | DO | QDSS trace data bit 13 B | Y | | D46 | GPIO\_172 | LPI\_GPIO\_24 | PX\_3 | B | LPI GPIO 24 | Y | | D46 | GPIO\_172 | LPI\_I2C\_SCL | PX\_3 | DO | LPI\_QUP0 SE5, lane 1: I2C\_SCL | Y | | D46 | GPIO\_172 | LPI\_UART\_RX | PX\_3 | DI | LPI\_QUP0 SE5, lane 3: UART\_RX | Y | | D46 | GPIO\_172 | SYNC\_OUT\_GPIO\_13 | PX\_3 | DO | Sync out GPIO\_13 | Y | | E47 | GPIO\_173 | | PX\_3 | PD:nppukp | Configurable I/O | N | | E47 | GPIO\_173 | QDSS\_GPIO\_TRACEDATA\_LOCB[14] | PX\_3 | DO | QDSS trace data bit 14 B | N | | E47 | GPIO\_173 | LPI\_GPIO\_25 | PX\_3 | B | LPI GPIO 25 | N | | E47 | GPIO\_173 | LPI\_UART\_TX | PX\_3 | DO | LPI\_QUP0 SE6, lane 2: UART\_TX | N | | E47 | GPIO\_173 | SYNC\_OUT\_GPIO\_14 | PX\_3 | DO | Sync out GPIO\_14 | N | | E45 | GPIO\_174 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | E45 | GPIO\_174 | QDSS\_GPIO\_TRACEDATA\_LOCB[15] | PX\_3 | DO | QDSS trace data bit 15 B | Y | | E45 | GPIO\_174 | LPI\_GPIO\_26 | PX\_3 | B | LPI GPIO 26 | Y | | E45 | GPIO\_174 | LPI\_UART\_RX | PX\_3 | DI | LPI\_QUP0 SE6, lane 3: UART\_RX | Y | | E45 | GPIO\_174 | SYNC\_OUT\_GPIO\_15 | PX\_3 | DO | Sync out GPIO\_15 | Y | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ^2^ For parameter and acronym definitions, see [Table : I/O description (pad type) parameters](https://docs.qualcomm.com/doc/80-23889-1/topic/pin-definitions.html#lwx1605206318030__table_qrk_mnk_b3b). ^3^ GP\_CLK GPIO function can be configured to output clock/PWM. ^4^ LPI\_GPIO\_144 to LPI\_GPIO\_158 supports LPASS application (15 LPI GPIOs). ^5^ LPI\_GPIO\_159 to LPI\_GPIO\_174 supports SSC application (12 LPI GPIOs). | Pad number | Pad name | Functional description | | --- | --- | --- | | AG9, AE9, M30, BJ39, F4, BJ35, BM20, BP20, BP22, BM22, BL19, BN19, BK18, BM18, BN23, BR23, BN21, BL21, BP24, BM24, BL25, BN25 | DNC | Do not connect.



Note: Pad internally connected, do not connect
externally. | | A1, A5, A7, A9, A21, A23, A25, A27, A39, A41, A43, A45, A47, AA25, AB4, AB10, AB12, AB14, AB16, AB18, AB20, AB22, AB28, AB30, AB32, AB34, AB36, AB38, AB40, AB42, AC11, AC13, AC15, AC17, AC19, AC21, AC25, AC29, AC31, AC33, AC35, AC37, AC39, AC47, AD4, AD6, AD10, AD28, AD40, AD42, AE25, AE47, AF10, AF12, AF14, AF16, AF18, AF20, AF22, AF28, AF30,AF32, AF34, AF36, AF38, AF40, AF42, AG1, AG25, AH2, AH4, AH6, AH10, AH12, AH18, AH28, AH42, AH44, AJ15, AJ25, AJ29, AJ31, AJ33, AJ35, AJ37, AJ39, AJ47, AK2, AK10, AK12, AK18, AK20, AK22, AK28, AK32, AK34, AK36, AK38, AK40, AK42, AL11, AL15, AL17, AL19, AL21, AL23, AL43, AM2, AM4, AM6, AM10, AM12, AM20, AM26, AM32, AM34, AM36, AM38, AM42, AN11, AN15, AN25, AN31, AN47, AP2, AP8, AP12, AP16, AP20, AP22, AP26, AP30, AP34, AP38, AP40, AP42, AP44, AP46, AR11, AR15, AR19, AR23, AR31, AR35, AR39, AT2, AT4, AT6, AT8, AT12, AT16, AT20, AT30, AT34, AT38, AU11, AU15, AU19, AU23, AU27, AU31, AU35, AU39, AU47, AV2, AV8, AV12, AV16, AV20, AV24, AV30, AV34, AV38, AW11, AW15, AW19, AW23, AW27, AW31, AW35, AW39, AY2, AY4, AY6, AY8, AY12, AY16, AY20, AY30, AY34, AY38, B4, B6, B8, B10, B38, B40, B42, B44, BA11, BA15, BA19, BA23, BA25, BA27, BA31, BA35, BA39, BA47, BB8, BB12, BB16, BB20, BB26, BB28, BB30, BC1, BC7, BC11, BC27, BC35, BC37, BD8, BD10, BD12, BD16, BD22, BD26, BD30, BD32, BD36, BD38, BD40, BE7, BE9, BE11, BE15, BE19, BE21, BE23, BE27, BE29, BE31, BE33, BE47, BF8, BF10, BF12, BF14, BF16, BF20, BF22, BF24, BF28, BF30, BF32, BF34, BF36, BF38, BF40, BG1, BG9, BG11, BG13, BG15, BG17, BG19, BG21, BG23, BG25, BG27, BG29, BG31, BG33, BG35, BG37, BG39, BG41, BH8, BH10, BH12, BH18, BH20, BH22, BH24, BH30, BH32, BJ17, BJ19, BJ21, BJ23, BJ29, BJ33, BJ47, BK10, BK20, BK22, BK24, BK26, BK28, BK36, BK38, BK40, BL1, BL17, BL23, BL27, BL29, BL35, BL39, BL41, BM10, BM14, BM16, BM26, BN11, BN13, BN17, BN31, BN35, BN41, BN47, BP18, BP26, BP32, BP34, BP44, BR1, BR3, BR7, BR19, BR21, BR25, BR33, BR37, BR41, BR47, C1, C11, C15, C17, C19, C21, C27, C29, C31, C33, C37, D4, D16, D32, D44, E5, E7, E9, E13, E17, E19, E21, E27, E29, E31, E35, E39, E41, E43, F10, F18, F22, | GND | Ground | | F24, F38, F44, G5, G7, G13, G15, G23, G25, G27, G33, G35, G41, G43, H6, H8, H10, H12, H14, H16, H20, H22, H24, H26, H28, H32, H34, H36, H38, H40, H42, H44, J5, J9, J13, J15, J17, J19, J21, J23, J25, J27, J29, J31, J33, J35, J39, J43, K6, K12, K14, K16, K18, K20, K22, K24, K26, K28, K30, K32, K34, K36, K42, K44, L7, L9, L11, L13, L15, L19, L21, L27, L31, L33, L35, L37, L39, L41, L43, M12, M14, M18, M20, M22, M26, M32, M34, M40, M44, N7, N23, N25, N37, P8, P34, P38, R1, R5, R7, R9, R11, R13, R15, R19, R21, R23, R25, R27, R31, R33, R37, R41, R47, T4, T10, T14, T16, T18, T20, T22, T28, T30, T32, T34, T38, U25, U37, U41, V6, V8, V10, V12, V14, V16, V18, V20, V24, V38, W3, W9, W11, W15, W17, W19, W21, W25, W29, W31, W33, W35, W37, W41, Y26, Y44 | GND | Ground | | Y36 | VDD\_A\_APC\_CS\_1P8 | Power for application processor current sensor; 1.8 V circuits | | AL9 | VDD\_A\_CSI\_01\_0P9 | Power for CSI 0, 1: 0.9 V circuits | | AM8 | VDD\_A\_CSI\_01\_1P2 | Power for CSI 0, 1: 1.2 V circuits | | AJ9 | VDD\_A\_CSI\_23\_0P9 | Power for CSI 2, 3: 0.9 V circuits | | AH8 | VDD\_A\_CSI\_23\_1P2 | Power for CSI 2, 3: 1.2 V circuits | | AC9 | VDD\_A\_CSI\_4\_0P9 | Power for CSI 4: 0.9 V circuits | | AD8 | VDD\_A\_CSI\_4\_1P2 | Power for CSI 4: 1.2 V circuits | | BH38 | VDD\_A\_CXO\_1P8 | Power for 1.8 V clock circuits | | N15, N17, N19, N21 | VDD\_A\_EBI0 | Power for EBI PHY circuits | | N27, N29, N31, N33 | VDD\_A\_EBI1 | Power for EBI PHY circuits | | AM30 | VDD\_A\_GFX\_CS\_1P8 | Power for graphics current sensor circuits | | L17 | VDD\_A\_PLL\_EBI0 | Power for EBI0 PLL circuits | | L29 | VDD\_A\_PLL\_EBI1 | Power for EBI1 PLL circuits | | W13 | VDD\_A\_TURING\_Q6\_CS\_1P8 | Power for Q6 current sensor1.8 V circuits | | W23, Y14, Y16, V26, V22, Y18, Y20, Y22, Y12, AA11, AA13, AA15, AA17, AA19, AA21, AA23, AC23, AD12, AD14, AD16, AD18, AD20, AD22, AD26, AE11, AE13, AE15, AE17, AE19, AE21, AE23, AE27, AF26, AG27, AG29, AH20, AH22, AH26, AJ17, AJ19, AJ21, AJ23, AJ27, AK26, AL27, AL29, AL31, AL33, AL35, AL37, AL39, AM18, AM22, AM28, AN21, AN23, AN27, AR25, AR27, AU25, AY26, M8, M10, N9, N11, N13, T6, T8, T12, T26, U5, U7, U9, U11, U13, U15, U17, U19, U21, U23, U27 | VDD\_CX | Power for digital core circuits | | R17 | VDD\_D\_EBI0 | Power for EBI0 digital circuits | | R29 | VDD\_D\_EBI1 | Power for EBI1 digital circuits | | P14, P16, P18, P20 | VDD\_IO\_EBI0 | Power for EBI0 I/O circuits | | P26, P28, P30, P32 | VDD\_IO\_EBI1 | Power for EBI1 I/O circuits | | AA27, AB24, AC27, AD24, AF24, AG11, AG13, AG15, AG17, AG19, AG21, AG23, AH16, AH24, AK16, AK24, AL25, AM16, AM24, AN29, AN33, AN35, AP24, AT24, AT26, AU9, AV26, AW9, BA9, BB32, BB34, BB36, BB38, P10, P12, V28, Y24, W27 | VDD\_MX | Power for on-chip memory | | AE41 | VDD\_PX0 | Power for pad group 0 – control signals | | L25 | VDD\_PX1 | Power for pad group 1 | | L23 | VDD\_PX10 | Power for pad group 10 – UFS | | BE35 | VDD\_PX11 | Power for pad group 11 – CXO pad | | AT40 | VDD\_PX2 | Power for pad group 2 – SDC2 pads | | AC41, AF8, AW25, BG7, BH40, P6 | VDD\_PX3 | Power for pad group 3 – most I/O pads | | BE37 | VDD\_PX5 | Power for pad group 5 – UIM1 pads | | BE39 | VDD\_PX6 | Power for pad group 6 – UIM2 pads | | M6 | VDD\_PX7 | Power for pad group 7 | | AV40 | VDDPX\_VBIAS\_SDC | Reference voltage for SDC | | BH36 | VDDPX\_VBIAS\_UIM | Reference voltage for UIM | | M36, N35, P36, R35, T36, U29, U31, U33, U35, V30, V32, V34, V36 | VDD\_APC0 | Power for the Kryo Silver application processor | | Y40, Y32, Y34, Y38, Y30, Y28, Y42, W39, V40, U39, AA29, AA31, AA33, AA35, AA37, AA39, AA41, AA43, AD30, AD32, AD34, AD36, AD38, AE29, AE31, AE33, AE35, AE37, M38, M42, N39, N41, N43, P40, R39, T40 | VDD\_APC1 | Power for the Kryo Gold application processor | | AJ41 | VDD\_A\_DSI\_0\_0P9 | Power for the DSI0 0.9 V circuits | | AG41 | VDD\_A\_DSI\_0\_1P2 | Power for the DSI0 1.2 V circuits | | AH40 | VDD\_A\_DSI\_0\_PLL\_0P9 | Power for the DSI0 0.9 V PLL circuits | | AM40 | VDD\_VREF\_0P9 | Power for eDP 0.9 V circuits | | AN41 | VDD\_VREF\_1P2 | Power for eDP 1.2 V circuits | | BB24 | VDD\_A\_GNSS\_0P9 | Power for 0.9 V GNSS circuits | | Y8 | VDD\_A\_PCIE\_0\_1P2 | Power for the PCIe0 PLL | | AA9 | VDD\_A\_PCIE\_0\_CORE | Power for PCIe0 core circuits | | BC31 | VDD\_A\_PCIE\_1\_1P2 | Power for the PCIe1 PLL | | BC33 | VDD\_A\_PCIE\_1\_CORE | Power for PCIe1 core circuits | | BC15 | VDD\_A\_QLINK\_0\_0P9 | Power for the QLink0 0.9 V circuits | | BD14 | VDD\_A\_QLINK\_0\_0P9\_CK | Power for the QLink0 0.9 V clock circuits | | BC13 | VDD\_A\_QLINK\_0\_1P2\_CK | Power for the QLink0 1.2 V clock circuits | | BD20 | VDD\_A\_QLINK\_1\_0P9 | Power for the QLink1 0.9 V circuits | | BC21 | VDD\_A\_QLINK\_1\_0P9\_CK | Power for the QLink1 0.9 V clock circuits | | BC19 | VDD\_A\_QLINK\_1\_1P2 | Power for the QLink1 1.2 V clock circuits | | AL41, AN9, BD34, BE41, BC23, BE13, T42, T24, Y10 | VDD\_A\_QREFS\_0P875 | Reference voltage for the QREFS 0.875 V circuits | | BH34 | VDD\_A\_QREFS\_1P25 | Reference voltage for the QREFS 1.25 V circuits | | BJ37 | VDD\_A\_QREFS\_1P8 | Reference voltage for the QREFS 1.8 V circuits | | P22 | VDD\_A\_UFS\_0\_1P2 | Power for the UFS 1.2 V circuits | | P24 | VDD\_A\_UFS\_0\_CORE | Power for the UFS core circuits | | BE25 | VDD\_A\_USBHS\_1P8 | Power for the USB high speed1.8 V circuits | | BF26 | VDD\_A\_USBHS\_3P1 | Power for the USB high speed3.1 V circuits | | BD24 | VDD\_A\_USBHS\_CORE | Power for the USB HS core | | BC29 | VDD\_A\_USBSSDP\_0\_1P2 | Power for USB SS and DisplayPort 1.2 V circuits | | BD28 | VDD\_A\_USBSSDP\_0\_CORE | Power for the USB SS and DisplayPort core circuits | | AN37, AN39, AP28, AP32, AP36, AR29, AR33, AR37, AT28, AT32, AT36, AU29, AU33, AU37, AV28, AV32, AV36, AW29, AW33, AW37, AY28, AY32, AY36, AY40, BA29, BA33, BA37, BB40, BC39 | VDD\_GFX | Power for graphics | | AK30 | VDD\_GFX\_CX\_ISENSE | Power for the GFX current sensor circuits | | AE39, AG33, AG35, AG37, AG39, AH38 | VDD\_LPI\_CX | Power for LPI digital core circuits | | AG31, AH30, AH32, AH34, AH36 | VDD\_LPI\_MX | Power for low-power island memory circuits | | AH14, AJ11, AJ13, AK14, AL13, AM14, AN13, AN17, AN19, AP10, AP14, AP18, AR9, AR13, AR17, AR21, AT10, AT14, AT18, AT22, AU13, AU17, AU21, AV10, AV14, AV18, AV22, AW13, AW17, AW21, AY10, AY14, AY18, AY22, BA13, BA17, BA21, BB10, BB14, BB18, BB22, BC9, BC17, BD18, BE17, BF18 | VDD\_Modem | Power for modem circuits | | BC25 | VDD\_LPI\_NAV\_MX | Power for LPI on chip memory– NAV | | AY24 | VDD\_QFPROM | Power for programming the QFPROM | | AB26 | VDD\_WPSS\_CX | Power for WLAN digital core circuits | | | | | Last Published: Sep 23, 2025 [Previous Topic Overview](https://docs.qualcomm.com/bundle/publicresource/80-23889-1/topics/Introduction.md) [Next Topic Electrical specifications](https://docs.qualcomm.com/bundle/publicresource/80-23889-1/topics/electrical-specifications.md)