# Overview
Source: [https://docs.qualcomm.com/doc/80-27134-10/topic/overview.html](https://docs.qualcomm.com/doc/80-27134-10/topic/overview.html)
## Device description
Source: [https://docs.qualcomm.com/doc/80-27134-10/topic/overview.html](https://docs.qualcomm.com/doc/80-27134-10/topic/overview.html)
The QPS615 chip is an Ethernet audio-video bridging (AVB)/time-sensitive networking (TSN)
bridge IC that allows high-speed interface between the host System-on-Chip (SoC) and
Ethernet devices on the network. When connected to an application processor or other SoC
host, the QPS615 chip enables the host device to transmit audio, video, and data
information over a 10 Gbps Ethernet network. The QPS615 chip connects to the host via
PCIe running at Gen 3.0. Additionally, it also has a PCIe switch feature that allows
connection of up to two endpoint devices. The Ethernet media access control (MAC)
interface connects to the Ethernet switch supporting both AVB and legacy traffic. The
on-chip Arm® Cortex®-M3 processor, when running, can perform system control and
management.
For the complete features and system specifications, see [QPS615 Data Sheet
(80-27134-1)](https://docs.qualcomm.com/bundle/80-27134-1/resource/80-27134-1.pdf).
## Key features
Source: [https://docs.qualcomm.com/doc/80-27134-10/topic/overview.html](https://docs.qualcomm.com/doc/80-27134-10/topic/overview.html)
- Arm Cortex-M3 250 MHz
- Realizes improved code efficiency by using the thumb-2 instruction set
- PCIe Gen 3.0/3.1 compliant
- Supports PCIe Gen 3.0, 2.0, and 1.0
- Supports power management: L0s, L1, and L1 PM substate
- Supports single root I/O virtualization (SR-IOV)
- Supports two PCIe physical function (PF) and three PCIe virtual function (VF)
for each PF
- Two ports:
- Port A supports: USXGMII and SGMII
- Port B supports: USXGMII/SGMII and RGMII
- Supports 10 M/100 M/1000 M/2.5 G/5 Gbps and 10 Gbps
- Eight channel DMA controller per port to transfer data over PCIe/SRAM
- Interface: MDIO
- On-chip memory: 128 kB SRAM
- Peripherals: I²C, SPI, and UART
### Package
- 263-pin nanoscale package (NSP)
- Package size: 7.0 mm × 7.0 mm × 0.802 mm with 0.44 mm pitch
## High-level block diagram and package outline
Source: [https://docs.qualcomm.com/doc/80-27134-10/topic/overview.html](https://docs.qualcomm.com/doc/80-27134-10/topic/overview.html)
Last Published: Feb 12, 2025