# Metrics and capabilities

## Performance metrics

Subsections of this chapter provide summaries of performance metrics. For more information on performance metrics, refer to the ICD HTML file:

- For Windows (x86): `C:\PROGRA~2\Qualcomm\Shared\Prof_Ext\`
- For Linux: `/opt/qcom/Shared/Prof_Ext/`
- For Windows on Snapdragon: `C:\Program Files (Arm)\Qualcomm\Shared\Prof_Ext\`

### DSP performance metrics

| ID | Name | Unit | Description |
| --- | --- | --- | --- |
| 0x1000/4096 | MPPS | MPackets/se c | Total packets executed per second |
| 0x1001/4097 | QDSP6 load | MCPS | QDSP6 load in millions of clock cycles per second |
| 0x1002/4098 | QDSP6 utilization | Percentage | QDSP6 core clock utilization |
| 0x1003/4099 | pCPP | cycles | Processor cycle per packet (pCPP) |
| 0x1004/4100 | MIPS | MIPS | Total instructions are executed per second; each packet can have more than one instruction |
| 0x1005/4101 | 1 thread packets | MPackets/sec | Packets are executed per second when only one hardware thread is active |
| 0x1006/4102 | 2 thread packets | MPackets/sec | Packets are executed per second when two hardware threads are active |
| 0x1007/4103 | 3 thread packets | MPackets/sec | Packets are executed per second when three hardware threads are active |
| 0x1008/4104 | 4 thread packets | MPackets/sec | Packets are executed per second when four hardware threads are active |
| 0x1009/4105 | 5 thread packets | MPackets/sec | Packets executed per second when five hardware threads are active |
| 0x100A/4106 | 6 thread packets | MPackets/sec | Packets executed per second when six hardware threads are active |
| 0x100B/4107 | 7 thread packets | MPackets/sec | Packets executed per second when seven hardware threads are active |
| 0x100C/4108 | 8 thread packets | MPackets/sec | Packets executed per second when all eight hardware threads are active |
| 0x100D/4109 | 1 thread cycles | MCPS | Total cycles per second when only one hardware thread is active |
| 0x100E/4110 | 2 thread cycles | MCPS | Total cycles per second when two hardware threads are active |
| 0x100F/4111 | 3 thread cycles | MCPS | Total cycles per second when three hardware threads are active |
| 0x1010/4112 | 4 thread cycles | MCPS | Total cycles per second when four hardware threads are active |
| 0x1011/4113 | 5 thread cycles | MCPS | Total cycles per second when five hardware threads are active |
| 0x1012/4114 | 6 thread cycles | MCPS | Total cycles per second when six hardware threads are active |
| 0x1013/4115 | 7 thread cycles | MCPS | Total cycles per second when seven hardware threads are active |
| 0x1014/4116 | 8 thread cycles | MCPS | Total cycles per second when eight hardware threads are active |
| 0x1015/4117 | 1 threadCPP | Cycles/Packet | Cycles per packets executed only when one hardware thread is active |
| 0x1016/4118 | 2 threadCPP | Cycles/Packet | Cycles per packets executed only when two hardware threads are active |
| 0x1017/4119 | 3 threadCPP | Cycles/Packet | Cycles per packets executed only when three hardware threads are active |
| 0x1018/4120 | 4 threadCPP | Cycles/Packet | Cycles per packets executed only when four hardware threads are active |
| 0x1019/4121 | 5 threadCPP | Cycles/Packet | Cycles per packets executed only when five hardware threads are active |
| 0x101A/4122 | 6 threadCPP | Cycles/Packet | Cycles per packets executed only when six hardware threads are active |
| 0x101B/4123 | 7 threadCPP | Cycles/Packet | Cycles per packets executed only when seven hardware threads are active |
| 0x101C/4124 | 8 threadCPP | Cycles/Packet | Cycles per packets executed only when eight hardware threads are active |
| 0x101D/4125 | 1 thread%load | % | % of packets executed per second when only one hardware thread is active |
| 0x101E/4126 | 2 thread%load | % | % of packets executed per second when two hardware threads are active |
| 0x101F/4127 | 3 thread%load | % | % of packets executed per second when three hardware threads are active |
| 0x1020/4128 | 4 thread%load | % | % of packets are executed per second when four hardware threads are active |
| 0x1021/4129 | 5 thread%load | % | % of packets executed per second when five hardware threads are active |
| 0x1022/4130 | 6 thread%load | % | % of packets executed per second when six hardware threads are active |
| 0x1023/4131 | 7 thread%load | % | % of packets are executed per second when seven hardware threads are active |
| 0x1024/4132 | 8 thread%load | % | % of packets executed per second when all eight hardware threads are active |
| 0x1025/4133 | Committed tc1/vx | MIPS | Committed tc1class instructions. Doesn’t include nops |
| 0x1026/4134 | Committed loads | MIPS | Committed load instructions. Includes cached and uncached |
| 0x1027/4135 | Committed stores | MIPS | Committed store instructions. Includes cached and uncached |
| 0x1028/4136 | All branches | MIPS | Committed packets contains program flow inst. Includes cr jumps, endloop, j, jr, dealloc\_return, system/trap |
| 0x1029/4137 | Branches taken | MIPS | Committed packets resulted in change-of- flow. Any taken jump. Includes endloop and dealloc\_return |
| 0x102A/4138 | End loops | MIPS | Committed packets contain an endloop that was taken |
| 0x102B/4139 | Conditional branches | MIPS | Committed packets contain conditional branches |
| 0x102C/4140 | Unconditional branches | MIPS | Committed packets contain unconditional branches |
| 0x1031/4145 | AXI read request | MBps | 64‑byte line read requests issued by the primary AXI master |
| 0x1032/4146 | AXI write request | MBps | 64‑byte line write requests issued by the primary AXI master |
| 0x1033/4147 | AHB read request | MBps | Read requests issued by AHB master, all devices accessed are AHB requests |
| 0x1034/4148 | AHB write request | MBps | Write requests issued by AHB master, all devices accessed are AHB requests |
| 0x1035/4149 | L1icache miss ratio | % | L1 instruction caches miss ratio, high value indicates lot of code,calls, jumps or not optimized code |
| 0x1036/4150 | L1icache misses per packet | % | L1 instruction cache misses per packet executed, how much % of code misses L1I cache |
| 0x1037/4151 | L1DCache miss per packet | % | L1 instruction caches miss ratio, high value indicates lot of code,calls, jumps or not optimized code |
| 0x1038/4152 | IU cache read from L2 | MBps | Instruction reads from L2 cache |
| 0x1039/4153 | IU cache read from DDR | MBps | Instruction reads from DDR due to miss in L2 cache |
| 0x103A/4154 | IU cache read from TCM | MBps | Instruction reads from TCM (tightly coupled memory) |
| 0x103B/4155 | IU cacheL2 miss ratio | % | L2 instruction cache miss ratio,high value indicates lot of code, calls, jumps, or not optimized code |
| 0x103C/4156 | IU cache prefetch from L2 | MBps | Hardware instruction prefetch from L2 |
| 0x103D/4157 | IU cache prefetch from DDR | MBps | Hardware instruction reads from DDR due to prefetch miss in the L2 cache |
| 0x103E/4158 | IU cache prefetch miss ratio | % | L2 instruction prefetch cache miss ratio, high value indicates calls or jumps |
| 0x103F/4159 | DU cache read from L2 | MBps | Data reads from L2 cache |
| 0x1040/4160 | DU cache read from TCM | MBps | Data reads from TCM |
| 0x1041/4161 | DU cache read from DDR | MBps | Data reads from DDR due to miss in L2 cache |
| 0x1042/4162 | DU cacheL2 miss ratio | % | L2 data reads cache miss ratio |
| 0x1043/4163 | DU cache prefetch from DDR | MBps | Data prefetch (software or hardware) reads from the L2 cache |
| 0x1044/4164 | DU cache prefetch from L2 | MBps | Data prefetch (software or hardware) reads from DDR due to miss in the L2 cache |
| 0x1045/4165 | DU cache prefetch miss ratio | % | L2 cachedata prefetch miss ratio |
| 0x1046/4166 | DU cache write to L2 | MBps | Data writes to L2 cache |
| 0x1047/4167 | DU cache write to TCM | MBps | Data writes to TCM |
| 0x1048/4168 | DU cache write to DDR | MBps | Data writes to DDR due to miss in L2 |
| 0x1049/4169 | DU cache write miss ratio | % | L2 cache write-miss ratio |
| 0x104A/4170 | L2 FETCHengine access | MBps | Data reads from DDR viaL2FETCH engine |
| 0x104B/4171 | L2 FETCHengine miss | MBps | Data reads from DDR viaL2FETCH engine |
| 0x104C/4172 | ARCH LOCKStalls | MCPS | Cycles cluster could not commit due to kernel lock or TLB lock |
| 0x104D/4173 | Flow change stalls | MCPS | Cluster stalls due to redirects such as branch mispredict |
| 0x104E/4174 | IU stalls | MCPS | Cluster stalls due to I/Q being empty |
| 0x104F/4175 | DU miss stalls | MCPS | Cluster stalls due to D-cache miss |
| 0x1050/4176 | DU busy stalls | MCPS | Cluster stalls due to D-cache is busy |
| 0x1051/4177 | Reg interlock stalls | MCPS | Cluster stalls due to register interlock, register port conflict, and so on. |
| 0x1052/4178 | DU uncached stalls | MCPS | Cluster stalls due to uncached DU accesses |
| 0x1053/4179 | BLC\_Latency\_per\_read\_request | ns | Bus latency counter (BLC) per read request |
| 0x1054/4180 | BLC\_average\_overlap\_reads | count | BLC average overlap reads |
| 0x1055/4181 | BLC\_Latency\_per\_txn | ns | BLC latency per transaction |
| 0x1056/4182 | QDSP Clock | MHz | Final Q6 Core clock frequency |
| 0x1057/4183 | MemNoc ClockVote | MHz | Final MemNOC bus clock vote from DSP subsystem |
| 0x1058/4184 | MemNoc Clock Projected | MHz | Projected MemNOC clock frequency for the Final MemNOC clock Vote (Actual clock frequency may differ basedon other subsystem votes |
| 0x1059/4185 | SNoC clock vote | MHz | Final SNoC bus clock vote from DSP subsystem |
| 0x105A/4186 | SNOC Clock Projected | MHz | Projected SNOC clock frequency for the Final SNOC clock vote (Actual clock frequency may differ based on other subsystem votes |
| 0x105B/4187 | DCVS coreclock Vote | MHz | DCVS Q6 core clock frequency |
| 0x105C/4188 | DCVS MemNoc clock vote | MHz | Dynamic MemNOCbus clock vote from DSP subsystem |
| 0x105D/4189 | DCVS SNOC clock vote | MHz | Dynamic SNOC bus clock vote from DSP subsystem |
| 0x105E/4190 | Clients core clock vote | MHz | Static Q6 core clock frequency |
| 0x105F/4191 | Clients MemNoc clock vote | MHz | Static MemNOCbus clock vote from DSP subsystem |
| 0x1060/4192 | Clients MemNoc clock Projected | MHz | Projected MemNOCclock frequency for the static MemNOC clock Vote |
| 0x1061/4193 | Clients SNOC clock vote | MHz | Static SNOC bus clock vote from DSP subsystem |
| 0x1062/4194 | Clients SNOC clock Projected | MHz | Projected SNOC clock frequency for the static SNOC clock Vote |
| 0x1063/4195 | rootPD available heap | MB | Total Available AMSS Heap |
| 0x1064/4196 | AUDIOPD available heap | MB | Total Available Heap AudioPD |
| 0x1065/4197 | SENSORPD Heap available | MB | Total Available Heap SensorPD |
| 0x1066/4198 | Committed packet B2B | MPPS | Packets executed after two cycles in the same thread |
| 0x1067/4199 | Committed packet BSB | MPPS | Packets executed back-to-back |
| 0x1068/4200 | Committed packet SMT | MPPS | Packets executed in the same cycle |
| 0x1069/4201 | Data TLB Miss | count | Data TLB misses |
| 0x106A/4202 | Instruction TLB Miss | count | Instruction TLB misses |
| 0x106B/4203 | Joint TLB Miss | count | Joint TLB misses |
| 0x106D/4205 | IPC | Instructions/cycle | Total instructions executed per cycle |
| 0x1700/5888 | DSP Core Clock | NA | QDSP Core clock from NPA query |
| 0x1701/5889 | Bandwidth Vote | NA | SNOC and BIMC clocks from NPA query |
| 0x1702/5890 | Root PD Heap | NA | Allocated, available, and maximum continuous chunk available in Root PD Heap |
| 0x1703/5891 | Audio Heap | NA | Allocated, available, and maximum continuous chunk available in Audio PD Heap |
| 0x1704/5892 | Sensors Heap | NA | Allocated, available, and maximum continuous chunk available in Sensors PD Heap |
| 0x1705/5893 | Measured BusClock | NA | Measured MemNOC, BIMC (clk/bimc) and CPU L3 clock |
| 0x1706/5894 | DCVS Clients | NA | DCVS clients information |
| 0x1708/5896 | QDSP6 revision and subversion | NA | QDSP6 revision and subversion information |
| 0x1709/5897 | Hardware Threads | NA | Maximum hardware threads |
| 0x170C/5900 | L2 CacheSize | NA | L2 and L2TCM CacheSize information |
| 0x170F/5903 | Core ClockList | NA | Core clock plan information |
| 0x1710/5904 | Power Stats | NA | Power stats information |
| 0x1711/5905 | FastRPC Process | NA | FastRPC process information |
| 0x1712/5906 | FastRPC Process Heap | NA | FastRPC process heap information |
| 0x1713/5907 | FastRPC Skeleton Process | NA | FastRPC skeleton process information |
| 0x1714/5908 | FastRPC Thread | NA | FastRPC thread information |
| 0x106E/4206 | TLP Name | NA | Thread Name |
| 0x106F/4207 | TLP ProcessID | NA | TLP ProcessID |
| 0x1070/4208 | TLP\_Priority | NA | Thread priority |
| 0x1071/4209 | TLP MPPS | MPackets/se c | Total packets executed per second |
| 0x1072/4210 | TLP\_MCPS | MCycles/sec | Millions of clock cycles per second |
| 0x1703/4211 | TLP CPP | Cycles/Packet | TLP Cycles per packet |
| 0x1704/4212 | TLP Time | us | Thread execution time |

### NSP performance metrics

| ID | Name | Unit | Description |
| --- | --- | --- | --- |
| 0x102D/4141 | AXI 128 Byte read request | MBps | 128‑byte line read requests issued by primary AXI master |
| 0x102E/4142 | AXI 128Byte write request | MBps | 128‑byte line write requests issued by primary AXI master |
| 0x102F/4143 | AXI 256Byte read request | MBps | 256-byte line read requests issued by the primary AXI master |
| 0x1030/4144 | AXI 256Byte write request | MBps | 256-byte line read requests issued by primary AXI master |
| 0x1100/4352 | Qualcomm® Hexagon™ Vector eXtensions (HVX) Utilization | Percentage | HVX utilization |
| 0x1104/4356 | HVX REG interlock | MCPS | Stall cycles due to interlocks |
| 0x1106/4358 | HVX L2 load stalls | MCycles/sec | Stall cycles due to load pending |
| 0x1108/4360 | HVX L2 store stalls | MCycles/sec | Stall cycles due to store not yet allocated in L2 |
| 0x1109/4361 | HVX SCATGATH OUTSTANDING | MCycles/sec | HVX Scatter/gather: Network scoreboard not updated |
| 0x110A/4362 | HVX SCATGATH full | MCycles/sec | HVX scatter/gather input buffer full |
| 0x110E/4366 | HVX power over | MCycles/sec | Sustained power exceeds budget |
| 0x110F/4367 | HVX MPPS | MPPS | HVX Packets executed, packet should have at least one HVX instruction |
| 0x1110/4368 | HVX XE MPPS | MPPS | HVX and Scalar Packets executed by a thread with XE bit set(HVX unit allocated), ideally it has to be close to HVX MPPS if not then it is not using the HVX unit to the full extent |
| 0x1111/4369 | HVX L2 stores | MBps | HVX L2 store bandwidth |
| 0x1112/4370 | HVX L2 stor miss | MBps | HVX store misses in the L2 cache and write to DDR |
| 0x1113/4371 | HVX L2 loads | MIPS | HVX L2 cacheload bandwidth |
| 0x1114/4372 | HVX L2 load miss | MBps | HVX load misses in L2 cache and reads from DDR |
| 0x1115/4373 | HVX L2 load miss ratio | % | HVX L2 cache load to miss ratio, lower value indicates better L2 utilization, which is possible with prefetch or uDMA |
| 0x1116/4374 | HVX L2 store miss ratio | % | HVX L2 cachestore to miss ratio |
| 0x1119/4377 | HVX active | MCPS | HVX active cycles |
| 0x111A/4378 | HVX VTCM stalls | MCPS | HVX stalls due to L2 cache loading |
| 0x111B/4379 | HVX store buffer full | MCPS | HVX stalls due to L2 cache stores |
| 0x111C/4380 | HVX voltage exceed | MCPS | HVX stall cycles due to VTCM (vector tightly coupled memory) transaction pending |
| 0x111D/4381 | HVX ALU Instructions | MIPS | HVX Scatter/gather: Network scoreboard not updated |
| 0x111E/4382 | HVX MPY instructions | MIPS | HVX scatter/gather input buffer full |
| 0x111F/4383 | HVX SHIFT instructions | MIPS | HVX store buffer full cycles |
| 0x1120/4384 | HVX permute instructions | MIPS | HVX Throttling: Voltage model would exceed the undershoot threshold |
| 0x1121/4385 | HVX SCATGATH Active | MCPS | HVX L2 cacheload bandwidth |
| 0x1180/4480 | HMX utilization | Percentage | HMX Utilization |
| 0x1181/4481 | HMX Active | MCPS | HMX active cycles |
| 0x1190/4496 | UDMA Active | MCPS | Cycles user DMA is not idle |
| 0x1191/4497 | UDMA descriptor fetch stalls | MCPS | Cycles user DMA is stalled on descriptor fetch |
| 0x1192/4498 | UDMA stalls | MCPS | Cycles use DMA is stalled in monitor or guest mode |
| 0x1193/4499 | UDMA poll cycles | MCPS | User DMA DMPolling (Direct Memory Polling) command cycles |
| 0x1194/4500 | UDMA syncT cycles | MCPS | User DMA DMSynchT (Direct Memory Synchronization Time) command cycles |
| 0x1195/4501 | UDMA DLBC wait | MCPS | Cycles user DMA stalls due to waiting for a DLBC (deep learning-based compression) fetch to return |
| 0x1196/4502 | UDMA TLB misses | Count/sec | User DMA TLB miss count |
| 0x1197/4503 | UDMA cmds | MIPS | User DMA descriptor done |
| 0x1198/4504 | UDMA L2 Coherent WR | MBPS | Coherent user DMA store access through the cache hierarchy. This event includes stores to the descriptor |
| 0x1199/4505 | UDMA L2 coherent WR miss | MBPS | Coherent userDMA store access through the cache hierarchy that was a cache miss. This event includes stores to the descriptor |
| 0x119A/4506 | UDMA L2 coherent RD | MBPS | Coherent userDMA read access through the cache hierarchy |
| 0x119B/4507 | UDMA L2 coherent RD miss | MBPS | Coherent userDMA read access through the cache hierarchy that was a cache miss |
| 0x119C/4508 | UDMA L2 non-coherent WR | MBPS | Noncoherent user DMA store access. Access bypassed the cache hierarchy. DLBC fetch excluded from this store access |
| 0x119D/4509 | UDMA L2 non-coherent RD | MBPS | Noncoherent user DMA read access. Access bypasses the cache hierarchy |
| 0x119E/4510 | UDMA VTCM store | MBPS | User DMA storeaccess to the VTCM memory |
| 0x119F/4511 | UDMA VTCM reads | MBPS | User DMA read accessfrom the VTCM memory |
| 0x11A0/4512 | UDMA DLBC fetch | MIPS | User DMA DLBC fetch |
| 0x11A1/4513 | UDMA unaligned read | MIPS | The numberof unaligned reads.alignment: 128 B for L2/VTCM, 256 B for bypass |
| 0x11A2/4514 | UDMA unaligned write | MIPS | The numberof unaligned writes. alignment: 128 B for L2/VTCM, 256 B for bypass |
| 0x11A3/4515 | UBWC coherent RD cycles | MCPS | Cycles user DMA stalled by L2 read |
| 0x11A4/4516 | UBWC coherent WR cycles | MCPS | Cycles user DMA stalled by L2 write |
| 0x11A5/4517 | UBWC non-coherent RD cycles | MCPS | Cycles user DMA stalled by noncoherent read |
| 0x11A6/4518 | UBWC non-coherent WR cycles | MCPS | Cycles user DMA stalled by noncoherent write |
| 0x11A7/4519 | UBWC VTCM RD cycles | MCPS | Cycles user DMA stalled by L2 read |
| 0x11A8/4520 | UBWC VTCM RD cycles | MCPS | Cycles user DMA stalled by L2 write |
| 0x11A9/4521 | HMX Clock | MHz | HMX Clock frequency |
| 0x11AA/4522 | Q6-CENG Bus Clock | MHz | Q6 processor to CENG bus clock frequency |
| 0x11AB/4523 | Thermal Q6 throttle frequency | MHz | Thermal Q6 throttle frequency |
| 0x11AC/4524 | User Q6 ClockLimit | MHz | User Q6 ClockLimit |
| 0x170A/5898 | HVX Threads | NA | HVX Threads information |
| 0x170B/5899 | VTCM Cache Size | NA | VTCM cache sizeinformation |
| 0x170D/5901 | HMX Hardware Info | NA | HMX hardware information |
| 0x170E/5902 | Chipset Info | NA | Chipset information |

### HLOS (Android and QNX) performance metrics

| ID | Name | Unit | Description |
| --- | --- | --- | --- |
| 0x1200/4608 | CPU 0 Load | % | CPU Core0 % utilization |
| 0x1201/4609 | CPU 1 Load | % | CPU Core1 % utilization |
| 0x1202/4610 | CPU 2 Load | % | CPU Core2 % utilization |
| 0x1203/4611 | CPU 3 Load | % | CPU Core3 % utilization |
| 0x1204/4612 | CPU 4 Load | % | CPU Core4 % utilization |
| 0x1205/4613 | CPU 5 Load | % | CPU Core5 % utilization |
| 0x1206/4614 | CPU 6 Load | % | CPU Core6 % utilization |
| 0x1207/4615 | CPU 7 Load | % | CPU Core7 % utilization |
| 0x1208/4616 | CPU Total Load | % | Total CPU Utilization % (weighted avg of individual core %) |
| 0x1209/4617 | CPU CLK0 Frequency | MHz | CPU CLK0 Frequency |
| 0x120A/4618 | CPU CLK1 Frequency | MHz | CPU CLK1 Frequency |
| 0x120B/4619 | CPU CLK2 Frequency | MHz | CPU CLK2 Frequency |
| 0x120C/4620 | CPU CLK3 Frequency | MHz | CPU CLK3 Frequency |
| 0x120D/4621 | CPU CLK4 Frequency | MHz | CPU CLK4 Frequency |
| 0x120E/4622 | CPU CLK5 Frequency | MHz | CPU CLK5 Frequency |
| 0x120F/4623 | CPU CLK6 Frequency | MHz | CPU CLK6 Frequency |
| 0x1210/4624 | CPU CLK7 Frequency | MHz | CPU CLK7 Frequency |
| 0x1222/4642 | CPU Process Stats | % | Process CPU Utilization % |
| 0x1300/4864 | GPU Clocks Cycle Executed | MHz | Number of GPU clocks per second. |
| 0x1301/4865 | GPU Utilization % | % | Percentage utilization of the GPU |
| 0x1302/4866 | GPU Memory Bus Busy % | % | Approximate percentage of time the GPU’s bus to system memory is busy |
| 0x1303/4867 | GPU Memory Read Total | bytes/sec | Total number of bytes readby the GPU from memory per second |
| 0x1304/4868 | GPU Memory Write Total | bytes/sec | Total number of bytes writtenby the GPU to memory per second. |
| 0x121F/4639 | Free Memory | KB | Process memory stats,free bytes |
| 0x1220/4640 | Used Memory | KB | Process memory stats,used bytes |
| 0x1221/4641 | Total Memory | KB | Process memory stats,total bytes |
| 0x1223/4643 | Free Swap Memory | KB | Process swap memory stats, free bytes |
| 0x1224/4644 | Used Swap Memory | KB | Process swap memory stats, used bytes |
| 0x1225/4645 | Total Swap Memory | KB | Process swap memory stats, total bytes |
| 0x1228/4648 | Memory Usage% | % | Percentage Memory Utilization |
| 0x1229/4649 | Swap Memory Usage % | % | Percentage Swap Memory Utilization |
| 0x121A/4634 | Disk IO Physical Read Bytes | MBps | Disk IO Physical Read Bytes |
| 0x121B/4635 | Disk IO Physical Write Bytes | MBps | Disk IO Physical Write Bytes |
| 0x121C/4636 | IO Cache Read Bytes | MBps | IO Cache Read Bytes |
| 0x121D/4637 | IO Cache Write Bytes | MBps | IO Cache Write Bytes |
| 0x1226/4646 | IO KB\_read/s | KBPS | Disk Read Speed |
| 0x1227/4647 | IO KB\_write/s | KBPS | Disk Write Speed |
| 0x1211/4625 | DDR Controller Total Bandwidth | MBps | DDR Controller Total Bandwidth |
| 0x1212/4626 | DDR Controller read bandwidth | MBps | DDR Controller read bandwidth |
| 0x1213/4627 | DDR Controller write bandwidth | MBps | DDR Controller write bandwidth |
| 0x1214/4628 | DDR Total Bandwidth | MBps | DDR Total Bandwidth |
| 0x1215/4629 | DDR Total Read Bandwidth | MBps | DDR Total Read Bandwidth DDR physical |
| 0x1216/4630 | DDR Total Write Bandwidth | MBps | DDR Total Write Bandwidth DDR physical |
| 0x1235/4661 | NOC DDR APPS0 Bandwidth | MBps | NOC DDR APPS0 Bandwidth |
| 0x1236/4662 | NOC DDR APPS1 Bandwidth | MBps | NOC DDR APPS1 Bandwidth |
| 0x1237/4663 | NOC DDR GPU Bandwidth | MBps | NOC DDR GPU Bandwidth |
| 0x1238/4664 | NOC DDR NSP Bandwidth | MBps | NOC DDR NSP Bandwidth |
| 0x1900/6400 | CPU Frequency | % | Per Core CPU Frequency |
| 0x1901/6401 | CPU Utilization | % | Per Core CPU Utilization |
| 0x1902/6402 | CPU Total Utilization | % | Total CPU Utilization % (weighted avg of individual core)<br>%] |
| 0x1903/6403 | CPU Total Frequency | % | Total CPU Frequency % (Weighted avgof individual core %) |
| 0x1940/6464 | Thermal Zone Temperature | deg C | Temperature of thermal zones |

### DDR bandwith performance metrics

| ID | Name | Unit | Description |
| --- | --- | --- | --- |
| 0x1600/5632 | GPU BW at DDR | MBps | GPU initiated bandwidth |
| 0x1601/5633 | CPU BW at DDR | MBps | CPU initiated bandwidth |
| 0x1602/5634 | Total DDR BW | MBps | Total Bandwidth |
| 0x1603/5635 | GPU BW Utilization | % | Utilization % of GPU initiated BW w.r.t theoretical Max at the DDR operating level |
| 0x1604/5636 | CPU BW Utilization | % | Utilization % of CPU initiated BW w.r.t theoretical Max at the DDR operating level |
| 0x1605/5637 | Total DDR Utilization | % | Utilization % of TotalBW w.r.t theoretical Max at the DDR operating level |
| 0x1606/5638 | NSP BW at DDR | MBps | NSP Initiated Bandwidth |
| 0x1607/5639 | NSP BW Utilization | % | Utilization % of NSP initiated BW w.r.t theoretical Max at the DDR operating level |

## Profiling capabilities

Profiling capabilities are device dependent.

| Command | Description | Android | QNX | WoS | LE | HGY |
| --- | --- | --- | --- | --- | --- | --- |
| `adsp-dsp-metrics` | aDSP processor metrics | Yes | Yes | Yes | Yes | Yes |
| `ndsp-dsp-metrics` | cDSP processor metrics | Yes | Yes | Yes | Yes | Yes |
| `sdsp-dsp-metrics` | sDSP processor metrics | Yes | Yes | Yes | Yes | Yes |
| `nsp1-dsp-metrics` | CSDP1 processor metrics | Yes | Yes | Yes | Yes | Yes |
| `gdsp0-dsp-metrics` | GDSP0 processor metrics | Yes | Yes | Yes | Yes | Yes |
| `gdsp1-dsp-metrics` | GDSP1 processor metrics | Yes | Yes | Yes | Yes | Yes |
| `apps-proc-cpu-metrics` | CPU process metrics | Yes | Yes | Yes | Yes | Yes |
| `proc-gpu-specific-metrics` | GPU processor metrics | Yes | Yes | Yes | Yes | No |
| `apps-proc-process-metrics` | Process profiling metrics | Yes | Yes | Yes | Yes | Yes |
| `bw-profiler-ddr-metrics` | DDR profiling metrics | Yes | No | Yes | No | No |
| `apps-proc-ddr-metrics` | DDR profiling metrics | No | Yes | No | No | Yes |
| `adsp-dsp-stats` | aDSP processor stats | Yes | Yes | Yes | Yes | Yes |
| `cdsp-dsp-stats` | cDSP processor stats | Yes | Yes | Yes | Yes | Yes |
| `sdsp-dsp-stats` | sDSP processor stats | Yes | Yes | Yes | Yes | Yes |
| `cdsp1-dsp-stats` | cDSP1 processor stats | Yes | Yes | Yes | Yes | Yes |
| `gdsp0-dsp-stats` | gDSP0 processor stats | Yes | Yes | Yes | Yes | Yes |
| `gdsp1-dsp-stats` | gDSP1 processor stats | Yes | Yes | Yes | Yes | Yes |
| `apps-proc-cpu-ddr-bw-metrics` | CPU DDR BW metrics | No | Yes | No | No | No |
| `apps-proc-io-metrics` | IO metrics | Yes | Yes | No | Yes | Yes |
| `apps-proc-mem-metrics` | Memory metrics | Yes | Yes | No | Yes | Yes |
| `wos-apps-proc-cpu-metric` | CPU process metrics | No | No | Yes | No | No |
| `wos-apps-proc-thermal-metrics` | Thermal Metrics | No | No | Yes | No | No |

Last Published: Aug 25, 2025

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