# I2C
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
**Parent Topic:** [Framework and programming model](https://docs.qualcomm.com/doc/80-58740-1/topic/framework_and_programming_model.html)
## Overview
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
Inter-integrated Circuit (I2C) is a serial communication bus, which uses a multi-slave
and multi-master architecture and is connected to low-speed peripherals. Each device has a
unique address identifier and can be used as a transmitter or receiver. The address of each
device connected to the bus can be set by software through a unique address and the existing
master or slave relation. The master can work as a master transmitter or a master receiver. If
two or more masters are initialized at the same time, data can be prevented from being damaged
through conflict detection and arbitration during transmission.
QCC74x has two I2C controller masters, whose slaveAddr, subAddr, and data to be
transferred can be flexibly configured, to facilitate communication with slaves. With the FIFO
of 2-word depth and interrupt function, it can be used with DMA to improve efficiency and
supports flexible adjustment of clock frequency.
## Features
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
- Master mode
- Multimaster mode and arbitration function
- Flexible control of the level duration of the start, end and
data transmission phases in segments
- Supports 7‑bit address mode and 10‑bit address mode
- Supports DMA transfer mode
- Supports multiple interrupt mechanisms
## Functional
description
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
Table : I2C pin list
| Name | Type | Description |
| --- | --- | --- |
| I2Cx\_SCL | Input/output I2C | I2C serial clock signal |
| I2Cx\_SDA | Input/output I2C | I2C serial data signal |
### Start and stop
conditions
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
All transmissions start with a START condition and end with a STOP condition. The
START and STOP conditions are generally generated by the master. The bus is considered to be
busy after the START condition and to be idle for a certain period after the STOP
condition.
START condition: SDA produces a high-to-low level transition when SCL is high;
STOP condition: SDA produces a low-to-high level transition when SCL is high.
Waveform diagram:
Figure : Start and stop conditions of I2C
### Data transfer format
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
#### 7‑bit address mode
The first 8 bits
transferred are addressing bytes, including a 7‑bit slave address and a 1‑bit direction bit.
Sending or receiving data by the master is controlled by the 8th bit in the first byte sent
by the master. If it is 0, it means that the data is sent by the master, while "1" indicates
that data is received by the master. After the direction bit is the answer bit (ACK), which
is sent by the slave to answer (pull the signal low) and the host starts transmitting the
specified length of data after receiving the answer. Upon data transfer is completed, the
master sends out a STOP signal, with the waveform shown below:
Figure : Master transmit and slave receive data formats
Figure : Master receive and slave transmit data formats
**Master transmit and Slave receive timing**
Figure : Timing of master transmitter and slave receiver
**Master receive and Slave transmit timing**
Figure : Timing of master receiver and slave transmitter
#### 10‑bit address mode
The cr\_i2c\_10b\_addr\_en in the register i2c\_config must be set to 1 before use.
The 10‑bit slave address consists of the two bytes after the START condition (S) or the
repeated START condition (Sr). The first 7 bits of the first byte are 1111 0XX, where XX are
the first two bits of MSB of the 10‑bit address. The 8th bit of the first byte is the
read/write bit that determines the transfer direction. The second byte is the remaining low
8 bits of the 10‑bit address. The data transfer format is as follows.
Figure : Master transmit and slave receive data format (10‑bit slave address)
When receiving the 10‑bit address following the START condition, the slave compares the
first byte (1111 0XX) of the slave address with its own address, and checks whether the
eighth bit (read/write bit) is 0. If the value of XX in the first byte is the same as the
top two bits of the slave's 10‑bit address, the first byte match passes and the slave will
give answer A. If there are multiple slave devices connected to the bus, more than one
device may match and generate answer A. Next, all slaves start to match the second byte
(XXXX XXXX), where only one slave has the same lower eight bits of the 10‑bit address as the
second byte, and that slave will give answer A. The slave that is addressed by the master
remains addressed until it receives a termination condition or a repeat start condition.
Figure : Master receive and slave transmit data format (10‑bit slave address)
Before the second acknowledgment A, the process is the same as that of the
master-transmitter addressing the slave-receiver. After the repeated START condition (Sr),
the matched slave will remain in the addressed state. This slave will check whether the
first 7 bits of the first byte after Sr are 1111 0XX, and then test whether the 8th bit is 1
(read). If this also matches, the slave considers that it is addressed as a transmitter and
generates an acknowledgment (A). The slave-transmitter remains in the addressed state until
it receives the STOP condition (P) or the repeated START condition (Sr) followed by a
different slave address. Then, under Sr, all the slaves will compare their addresses with
11110XX and test the eighth bit (read/write bit). However, they will not be addressed,
because for 10‑bit devices, the read/write bit is 1, or for 7‑bit devices, the slave
addresses of 1111 0XX do not match.
### Arbitration
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
When there are multiple masters on an I2C bus, it may happen that multiple masters
start data transfer at the same time. At this time, the arbitration mechanism decides which
master has the right to transfer data, while other masters have to give up the control of the
bus and wait until the bus is idle before transferring data again.
During data transfer, all masters must check whether the SDA is consistent with the
data they want to send when SCL stays high. When the SDA level is different from the expected
one, it means that other masters are transferring data at the same time. The masters with
different SDA levels lose the arbitration and the other masters complete the data
transfer.
The waveform of two masters transferring data and initiating the
arbitration mechanism at the same time is as follows:
Figure : Waveform of simultaneous data transfer
## I2C clock setting
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
I2C clock can be derived from bclk (bus clock) and xclk, and frequency division can be
done on this basis. The duration of the start condition, each bit of data and the end
condition are set by registers i2c\_prd\_start, i2c\_prd\_data and i2c\_prd\_stop respectively. Each
of these durations can be subdivided into 4 phases, and the number of samples in each phase is
controlled by a separate byte in the register (the actual value is the register value plus 1).
The 4 phase settings in the data section together determine the frequency division factor of
the I2C clock. As shown in the figure below, suppose that the I2C clock source is selected as
80 M bclk and the register i2c\_prd\_data is set to 0x09070b09, then the second 0 in the figure
is 0x09+1=0x0a, the second 1 is 0x07+1=0x08, the second 2 is 0x0b+1=0x0c, and the second 3 is
0x09+1=0x0a. Then the clock frequency of I2C is 80 MHz/(0x0a+0x08+0x0c+0x0a) = 2 MHz.
Similarly, the first 0, 1, 2 and 3 are set by register i2c\_prd\_start, which determines the
duration of the start condition, and the third 0, 1, 2 and 3 are set by register i2c\_prd\_stop,
which determines the duration of the end condition.
Figure : I2C clock setting
## I2C configuration flow
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
### Configuration items
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
- Read/write flag bit
- Slave address
- Slave register address
- Slave register address length
- Data (Tx: configure the sent data; Rx: store the received data)
- Data length
- Enable signal
### Read/Write flag bit
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
I2C supports Tx and Rx working statuses. The cr\_i2c\_pkt\_dir in the register
i2c\_config represents the Tx/Rx status, '0' for Tx status and '1' for Rx status.
### Slave address
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
Each slave connected to I2C has a unique device address, which is usually 7 bits
long. This address is written into the cr\_i2c\_slv\_addr in the register i2c\_config. I2C will
automatically shift to the left by 1 bit before sending the address, and the Tx/Rx direction
bit will be added to the LSB.
### Slave register address
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
The slave register address represents the register address where I2C must read and
write a slave register. The slave register address is written to the register i2c\_sub\_addr,
and the cr\_i2c\_sub\_addr\_en in the register i2c\_config must be set to 1. If cr\_i2c\_sub\_addr\_en
in the register i2c\_config is set to 0, the I2C master skips the slave register address field
when sending.
### Slave register
address length
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
The slave register address length is subtracted by 1 and then
written to cr\_i2c\_sub\_addr\_bc in the register i2c\_config.
### Data
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
It refers to the data that must be sent to or received from the slave. When sending
data, I2C must write the data (in word) into the register i2c\_fifo\_wdata. When receiving data,
I2C must read out the data (in word) from the register i2c\_fifo\_rdata.
### Data length
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
The cr\_i2c\_pkt\_len in the i2c\_config register sets the send data length (the value
written to the register + 1 is the send data length), and the maximum send length is
256 bytes.
### Enable signal
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
After the above items are configured, when cr\_i2c\_m\_en in the
enable signal register i2c\_config is set to 1, the I2C sending
process will be started automatically.
When the read/write flag bit is configured as 0, I2C sends data. Take sending 2 bytes
as an example, the master's transmission flow is as follows:
1. Start bit
2. (The slave address shifts to the left by 1 bit + 0) + ACK
3. Slave register address + ACK
4. 1-byte data + ACK
5. 1-byte data + ACK
6. Stop bit
When the read/write flag bit is configured as 1, I2C receives data. Take receiving
2 bytes as an example, the master's transmission flow is as follows:
1. Start bit
2. (The slave address shifts to the left by 1 bit + 0) + ACK
3. Slave register address + ACK
4. Start bit
5. (The slave address shifts to the left by 1 bit + 1) + ACK
6. 1-byte data + ACK
7. 1-byte data + ACK
8. Stop bit
## FIFO management
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
I2C FIFO has a 2-word depth, and I2C includes RxFIFO and TxFIFO. The rx\_fifo\_cnt in the
register i2c\_fifo\_config\_1 represents how much data (in word) in RxFIFO must be read.
The tx\_fifo\_cnt in the register i2c\_fifo\_config\_1 represents how much free space (in
word) in TxFIFO for writing.
I2C FIFO status:
- RxFIFO underflow: When the data in RxFIFO is completely read out or empty, if I2C
continues to read data from RxFIFO, the rx\_fifo\_underflow in the register i2c\_fifo\_config\_0
will be set to 1;
- RxFIFO overflow: When I2C receives data until the two words of RxFIFO are filled,
without reading RxFIFO, if I2C receives data again, the rx\_fifo\_overflow in the register
i2c\_fifo\_config\_0 will be set to 1;
- TxFIFO underflow: When the data size filled into TxFIFO does not meet the configured
I2C data length: cr\_i2c\_pkt\_len in i2c\_config, and no new data is filled into TxFIFO, the
tx\_fifo\_underflow in the register i2c\_fifo\_config\_0 will be set to 1;
- TxFIFO overflow: After the two words of TxFIFO are filled, before the data in TxFIFO
is sent out, if data is filled into TxFIFO again, the tx\_fifo\_overflow in the
register i2c\_fifo\_config\_0 will be set to 1.
## Use with DMA
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
I2C can send and receive data through DMA. Setting i2c\_dma\_tx\_en in the register
i2c\_fifo\_config\_0 to 1 will enable the DMA Tx mode. After the channel for I2C is allocated,
DMA will transfer data from memory to the i2c\_fifo\_wdata register. Setting i2c\_dma\_rx\_en in
the register i2c\_fifo\_config\_0 to 1 will enable the DMA Rx mode. After the channel for I2C is
allocated, DMA will transfer the data in the register i2c\_fifo\_rdata to memory. When I2C is
used with DMA, DMA will automatically transfer data, so it is unnecessary for the CPU to write
data into I2C TxFIFO or read data from I2C RxFIFO.
### DMA sending flow
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
1. Set the read/write flag bit to 0
2. Set slave address
3. Set slave register address
4. Set slave register address length
5. Data Length
6. Set enable signal register to 1
7. Configure DMA transfer size
8. Configure the transfer width of the DMA source address
9. Configure the transfer width of DMA destination address (when I2C is used with
DMA, the transfer width of destination address must be set to 32 bits, which is
word-aligned)
10. Configure the DMA source address as the memory address for
storing sent data
11. Configure the DMA destination address to I2C TxFIFO address, i2c\_fifo\_wdata
12. Enable DMA
### DMA receiving flow
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
1. Set the read/write flag bit to 1
2. Set slave address
3. Set slave register address
4. Set slave register address length
5. Data Length
6. Set enable signal register to 1
7. Configure DMA transfer size
8. Configure the transfer width of DMA source address (when I2C is used with DMA, the
transfer width of source address must be set to 32 bits, which is word-aligned)
9. Configure the transfer width of the DMA destination address
10. Configure the DMA source address to I2C RxFIFO address, i2c\_fifo\_rdata
11. Configure the DMA destination address as the memory address for
storing received data
12. Enable DMA
## Interrupt
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
I2C includes the following interrupts:
- I2C\_TRANS\_END\_INT
I2C transfer end interrupt, which is generated when I2C
completes a transfer
- I2C\_TX\_FIFO\_READY\_INT
When tx\_fifo\_cnt in i2c\_fifo\_config\_1 is greater than
tx\_fifo\_th, a TxFIFO request interrupt is generated, and the interrupt flag will be
automatically cleared when the condition is not satisfied
- I2C\_RX\_FIFO\_READY\_INT
When rx\_fifo\_cnt in i2c\_fifo\_config\_1 is greater than
rx\_fifo\_th, a RxFIFO request interrupt is generated, and the interrupt flag will be
automatically cleared when the condition is not satisfied
- I2C\_NACK\_RECV\_INT
When the I2C module detects a NACK state, a NACK interrupt is
generated
- I2C\_ARB\_LOST\_INT
I2C arbitration lost interrupt
- I2C\_FIFO\_ERR\_INT
FIFO ERROR interrupt is generated when Tx/RxFIFO overflows or
underflows
## Register description
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
| Name | Description |
| --- | --- |
| [i2c_config](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html#i2c-i2c-config) | Master configure |
| [i2c_int_sts](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html#i2c-i2c-int-sts) | Interrupt configure and status |
| [i2c_sub_addr](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html#i2c-i2c-sub-addr) | Subaddress setting |
| [i2c_bus_busy](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html#i2c-i2c-bus-busy) | Bus busy status |
| [i2c_prd_start](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html#i2c-i2c-prd-start) | Start period setting |
| [i2c_prd_stop](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html#i2c-i2c-prd-stop) | Stop period setting |
| [i2c_prd_data](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html#i2c-i2c-prd-data) | Data period setting |
| [i2c_fifo_config_0](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html#i2c-i2c-fifo-config-0) | FIFO status and DMA mode |
| [i2c_fifo_config_1](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html#i2c-i2c-fifo-config-1) | FIFO threshold and available count |
| [i2c_fifo_wdata](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html#i2c-i2c-fifo-wdata) | TxFIFO |
| [i2c_fifo_rdata](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html#i2c-i2c-fifo-rdata) | RxFIFO |
### i2c\_config
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
Address: 0x40018000
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:28 | cr\_i2c\_deg\_cnt | RW | 0 | Deglitch function cycle count |
| 27:20 | cr\_i2c\_pkt\_len | RW | 0 | Packet length (unit: byte) |
| 19:18 | RSVD | | | |
| 17:8 | cr\_i2c\_slv\_addr | RW | 0 | Slave address for I2C transaction (target address) |
| 7 | cr\_i2c\_10b\_addr\_en | RW | 0 | Slave address 10‑bit mode enable |
| 6:5 | cr\_i2c\_sub\_addr\_bc | RW | 0 | Subaddress field byte count
- 0: 1‑byte
- 1: 2‑byte
- 2: 3‑byte
- 3: 4‑byte
|
| 4 | cr\_i2c\_sub\_addr\_en | RW | 0 | Enable signal of I2C subaddress field |
| 3 | cr\_i2c\_scl\_sync\_en | RW | 1 | Enable signal of I2C SCL synchronization, should be enabled to
support Multi-Master and Clock-Stretching
(Normally should not be turned-off) |
| 2 | cr\_i2c\_deg\_en | RW | 0 | Enable signal of I2C input deglitch function (for all input pins) |
| 1 | cr\_i2c\_pkt\_dir | RW | 1 | Transfer direction of the packet
|
| 0 | cr\_i2c\_m\_en | RW | 0 | Enable signal of I2C Master function
Asserting this bit will trigger the transaction, and should be deasserted
after finish |
### i2c\_int\_sts
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
Address: 0x40018004
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:30 | RSVD | | | |
| 29 | cr\_i2c\_fer\_en | RW | 1 | Interrupt enable of i2c\_fer\_int |
| 28 | cr\_i2c\_arb\_en | RW | 1 | Interrupt enable of i2c\_arb\_int |
| 27 | cr\_i2c\_nak\_en | RW | 1 | Interrupt enable of i2c\_nak\_int |
| 26 | cr\_i2c\_rxf\_en | RW | 1 | Interrupt enable of i2c\_rxf\_int |
| 25 | cr\_i2c\_txf\_en | RW | 1 | Interrupt enable of i2c\_txf\_int |
| 24 | cr\_i2c\_end\_en | RW | 1 | Interrupt enable of i2c\_end\_int |
| 23:22 | RSVD | | | |
| 21 | rsvd | rsvd | 0 | |
| 20 | cr\_i2c\_arb\_clr | W1C | 0 | Interrupt clear of i2c\_arb\_int |
| 19 | cr\_i2c\_nak\_clr | W1C | 0 | Interrupt clear of i2c\_nak\_int |
| 18 | rsvd | rsvd | 0 | |
| 17 | rsvd | rsvd | 0 | |
| 16 | cr\_i2c\_end\_clr | W1C | 0 | Interrupt clear of i2c\_end\_int |
| 15:14 | RSVD | | | |
| 13 | cr\_i2c\_fer\_mask | RW | 1 | Interrupt mask of i2c\_fer\_int |
| 12 | cr\_i2c\_arb\_mask | RW | 1 | Interrupt mask of i2c\_arb\_int |
| 11 | cr\_i2c\_nak\_mask | RW | 1 | Interrupt mask of i2c\_nak\_int |
| 10 | cr\_i2c\_rxf\_mask | RW | 1 | Interrupt mask of i2c\_rxf\_int |
| 9 | cr\_i2c\_txf\_mask | RW | 1 | Interrupt mask of i2c\_txf\_int |
| 8 | cr\_i2c\_end\_mask | RW | 1 | Interrupt mask of i2c\_end\_int |
| 7:6 | RSVD | | | |
| 5 | i2c\_fer\_int | R | 0 | I2C Tx/RxFIFO error interrupt, autocleared when FIFO overflow/underflow
error flag is cleared |
| 4 | i2c\_arb\_int | R | 0 | I2C arbitration lost interrupt |
| 3 | i2c\_nak\_int | R | 0 | I2C NACK-received interrupt |
| 2 | i2c\_rxf\_int | R | 0 | I2C RxFIFO ready (rx\_fifo\_cnt > rx\_fifo\_th) interrupt, autocleared
when data is popped |
| 1 | i2c\_txf\_int | R | 1 | I2C TxFIFO ready (tx\_fifo\_cnt > tx\_fifo\_th) interrupt, autocleared
when data is pushed |
| 0 | i2c\_end\_int | R | 0 | I2C transfer end interrupt |
### i2c\_sub\_addr
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
Address: 0x40018008
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:24 | cr\_i2c\_sub\_addr\_b3 | RW | 0 | I2C subaddress field - byte[3] |
| 23:16 | cr\_i2c\_sub\_addr\_b2 | RW | 0 | I2C subaddress field - byte[2] |
| 15:8 | cr\_i2c\_sub\_addr\_b1 | RW | 0 | I2C subaddress field - byte[1] |
| 7:0 | cr\_i2c\_sub\_addr\_b0 | RW | 0 | I2C subaddress field - byte[0] (subaddress starts from this byte) |
### i2c\_bus\_busy
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
Address: 0x4001800c
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:2 | RSVD | | | |
| 1 | cr\_i2c\_bus\_busy\_clr | W1C | 0 | Clear signal of bus\_busy status, not for normal usage (in case
I2C bus hangs) |
| 0 | sts\_i2c\_bus\_busy | R | 0 | Indicator of I2C bus busy
|
### i2c\_prd\_start
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
Address: 0x40018010
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:24 | cr\_i2c\_prd\_s\_ph\_3 | RW | 0xF | Length of START condition phase 3 (unit: I2C source clock
period) |
| 23:16 | cr\_i2c\_prd\_s\_ph\_2 | RW | 0xF | Length of START condition phase 2 (unit: I2C source clock
period) |
| 15:8 | cr\_i2c\_prd\_s\_ph\_1 | RW | 0xF | Length of START condition phase 1 (unit: I2C source clock
period) |
| 7:0 | cr\_i2c\_prd\_s\_ph\_0 | RW | 0xF | Length of START condition phase 0 (unit: I2C source clock
period) |
### i2c\_prd\_stop
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
Address: 0x40018014
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:24 | cr\_i2c\_prd\_p\_ph\_3 | RW | 0xF | Length of STOP condition phase 3 (unit: I2C source clock
period) |
| 23:16 | cr\_i2c\_prd\_p\_ph\_2 | RW | 0xF | Length of STOP condition phase 2 (unit: I2C source clock
period) |
| 15:8 | cr\_i2c\_prd\_p\_ph\_1 | RW | 0xF | Length of STOP condition phase 1 (unit: I2C source clock
period) |
| 7:0 | cr\_i2c\_prd\_p\_ph\_0 | RW | 0xF | Length of STOP condition phase 0 (unit: I2C source clock
period) |
### i2c\_prd\_data
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
Address: 0x40018018
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:24 | cr\_i2c\_prd\_d\_ph\_3 | RW | 0xF | Length of DATA phase 3 (unit: I2C source clock period) |
| 23:16 | cr\_i2c\_prd\_d\_ph\_2 | RW | 0xF | Length of DATA phase 2 (unit: I2C source clock period) |
| 15:8 | cr\_i2c\_prd\_d\_ph\_1 | RW | 0xF | Length of DATA phase 1 (unit: I2C source clock period)
Note: This value should not be set to 8'd0, adjust source clock rate
instead if a higher I2C clock rate is required |
| 7:0 | cr\_i2c\_prd\_d\_ph\_0 | RW | 0xF | Length of DATA phase 0 (unit: I2C source clock period) |
### i2c\_fifo\_config\_0
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
Address: 0x40018080
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:8 | RSVD | | | |
| 7 | rx\_fifo\_underflow | R | 0 | Underflow flag of RxFIFO, can be cleared by rx\_fifo\_clr |
| 6 | rx\_fifo\_overflow | R | 0 | Overflow flag of RxFIFO, can be cleared by rx\_fifo\_clr |
| 5 | tx\_fifo\_underflow | R | 0 | Underflow flag of TxFIFO, can be cleared by tx\_fifo\_clr |
| 4 | tx\_fifo\_overflow | R | 0 | Overflow flag of TxFIFO, can be cleared by tx\_fifo\_clr |
| 3 | rx\_fifo\_clr | W1C | 0 | Clear signal of RxFIFO, RxFIFO is empty when write 1 to this bit |
| 2 | tx\_fifo\_clr | W1C | 0 | Clear signal of TxFIFO, TxFIFO is empty when write 1 to this bit |
| 1 | i2c\_dma\_rx\_en | RW | 0 | Enable signal of dma\_rx\_req/ack interface |
| 0 | i2c\_dma\_tx\_en | RW | 0 | Enable signal of dma\_tx\_req/ack interface |
### i2c\_fifo\_config\_1
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
Address: 0x40018084
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:25 | RSVD | | | |
| 24 | rx\_fifo\_th | RW | 0 | RxFIFO threshold, dma\_rx\_req will not be asserted if rx\_fifo\_cnt is less
than this value |
| 23:17 | RSVD | | | |
| 16 | tx\_fifo\_th | RW | 0 | TxFIFO threshold, dma\_tx\_req will not be asserted if tx\_fifo\_cnt is less
than this value |
| 15:10 | RSVD | | | |
| 9:8 | rx\_fifo\_cnt | R | 0 | RxFIFO available count, means count of data received in RxFIFO |
| 7:2 | RSVD | | | |
| 1:0 | tx\_fifo\_cnt | R | 0x2 | TxFIFO available count, means empty space remained in TxFIFO |
### i2c\_fifo\_wdata
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
Address: 0x40018088
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:0 | i2c\_fifo\_wdata | W | X | TxFIFO, size is 4\*2 = 8-byte |
### i2c\_fifo\_rdata
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html](https://docs.qualcomm.com/doc/80-58740-1/topic/i2c.html)
Address: 0x4001808c
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:0 | i2c\_fifo\_rdata | R | 0 | RxFIFO, size is 4\*2 = 8-byte |
Last Published: Feb 11, 2026