# MJPEG
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
**Parent Topic:** [Framework and programming model](https://docs.qualcomm.com/doc/80-58740-1/topic/framework_and_programming_model.html)
## Overview
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
MJPEG (Motion Joint Photographic Experts Group) is a video coding format that can be
accurate to frame editing and multi-layer image processing. It handles motion video sequences
as continuous still images. This compression method compresses each frame individually and
completely. By compressing the original data in YCbCr format, the memory space occupied by one
frame of image can be greatly reduced.
## Features
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
- Configurable input formats including:
- YCbCr4:2:2 plane or packed mode
- YCbCr4:2:0 plane mode
- YCbCr4:0:0
- Configurable input data Y, Cb, Cr sort order
- The quantization coefficient table can be freely configured
- Support software mode and linkage mode
- Support swap mode
- Support kick mode
- Reserve jpg head space and automatically add jpg tail
- Continuously cache up to 4 sets of picture information
- Various application interruptions are conducive to flexible use and error prompts
## Function description
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
### Input configuration
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
The YCbCr format of the input data can be selected by bit <REG\_YUV\_MODE> of
register MJPEG\_CONTROL\_1, including YCbCr4:2:2 plane or packed mode, YCbCr4:2:0 plane mode and
YCbCr4:0:0 grayscale image. When the YCbCr4:2:2 packing mode is selected, the arrangement
order of Y, Cb and Cr can be configured through the upper 8 bits of the register
MJPEG\_HEADER\_BYTE. When other modes are selected, the order of Cb and Cr can be set by bit
<REG\_ORDER\_U\_EVEN> of register MJPEG\_CONTROL\_1. The detailed configuration is shown in
the figure below.
Figure : MJPEG YUYV interleave order configuration
### Quantization
coefficient table
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
The quantization coefficient table can be freely configured by the user,
<reg\_q\_0\_00> to <reg\_q\_0\_3F> represent the quantization tables of the Y component
of grayscale information, and <reg\_q\_1\_00> to <reg\_q\_1\_3F> represent the
quantization tables of the chrominance information Cb and Cr. The quantization table is
arranged in the order from the upper-left corner to the bottom, the first column is followed
by the second column, that is, reg\_q\_0\_00 represents the quantization value of the first row
and the first column of the Y component, and reg\_q\_0\_01 represents the quantization of the
second row and the first column of the Y component. Value, reg\_q\_0\_07 represents the quantized
value of the Y component in the eighth row and first column, reg\_q\_0\_08 represents the
quantized value in the first row and second column of the Y component, and so on.
### Software mode and link
mode
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
When the bit <REG\_MJPEG\_SW\_MODE> of the MJPEG\_CONTROL\_2 register is set to 1,
the software mode is enabled. In this mode, MJPEG reads the original image data of the
specified number of frames from the memory for compression. In this mode, the image data must
be prepared in advance.
When the bit <REG\_MJPEG\_SW\_MODE> of the MJPEG\_CONTROL\_2 register is cleared to
0, the linkage mode is enabled. In this mode, MJPEG processes the output of the CAM module as
its input. MJPEG is processed with 8\*8 data blocks as a unit. When the CAM finishes writing 8
lines of data to the memory, MJPEG starts to work, and the memory space processed by MJPEG
will be released to the CAM for reuse, so that the CAM can complete the linkage with MJPEG
without the memory space of a whole picture.
### Swap mode
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
When using swap mode, the MJPEG storage space is evenly divided into two blocks, when
MJPEG finishes writing one block, an interrupt is generated to notify the software to read the
data, and it writes the data to the other block. Alternate use back and forth, to use less
than one frame of picture storage space for data processing.
### Kick mode
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
The kick mode is enabled when bit <REG\_SW\_KICK\_MODE> of
the MJPEG\_CONTROL\_2 register is set to 1. In this mode, each time a
1 is written to the bit <REG\_SW\_KICK> of the MJPEG\_CONTROL\_2
register, a compression is started. The number of compressed lines
is determined by the bit <REG\_SW\_KICK\_HBLK> of the
MJPEG\_YUV\_MEM\_SW register. It should be noted that the kick mode
can only be used in software mode, not in linkage mode.
### Jpg function
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
The jpg function will automatically reserve some bytes of space at the beginning of
each frame of data and fill it with the specified data. The size of this space is set by the
lower 12 bits of the register MJPEG\_HEADER\_BYTE. There are 768 bytes of memory at offset 0x800
for storing the data that must be filled at the beginning of each frame. The user only must
write the jpg header information into it, and this information will be included at the
beginning of each frame of data generated. In addition, if the autofill jpg end is enabled,
two bytes of data will be added at the end of each frame of data, and the value of these two
bytes is 0xFFD9.
### Cache image
information
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
The module contains 4 groups of FIFO to record the picture address, picture size and
picture ID. Whenever this module completely writes a frame to the memory, it will record the
start address, image size and image ID of the frame image in this FIFO, but it should be noted
that when the memory is insufficient, or there are 4 sets of FIFO when the storage is full,
the module will automatically discard the information of the next picture. In the part where
the picture information is taken out, the pop action can be performed through the APB
interface to empty the oldest picture information. At this time, the FIFO is automatically
advanced to ensure the FIFO. Timing of internal picture information.
### Support various interrupt information (can be configured independently of the
switch)
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
- Normal interrupt: can be set to interrupt after writing several pictures
- Camera interrupt: When the speed of MJPEG processing cannot keep up with the speed of CAM
module writing, and the CAM overflows, an interrupt is issued
- Memory interrupt: When the memory is overwritten, an interrupt is issued
- Frame interrupt: When there are more than 4 groups of unprocessed pictures, an interrupt
is issued
- Swap interrupt: When a memory block is full in swap mode, an interrupt is issued
## Register description
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
| Name | Description |
| --- | --- |
| [mjpeg_control_1](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-control-1) | MJPEG configure |
| [mjpeg_control_2](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-control-2) | MJPEG software mode |
| [mjpeg_yy_frame_addr](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-yy-frame-addr) | Memory start address of Y |
| [mjpeg_uv_frame_addr](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-uv-frame-addr) | Memory start address of UV |
| [mjpeg_yuv_mem](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-yuv-mem) | Number of Y/UV block line |
| [jpeg_frame_addr](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-jpeg-frame-addr) | Memory start address of JPEG |
| [jpeg_store_memory](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-jpeg-store-memory) | Burst count of memory |
| [mjpeg_control_3](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-control-3) | Interrupt and bus status |
| [mjpeg_frame_fifo_pop](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-frame-fifo-pop) | Interrupt clear and pop |
| [mjpeg_frame_size](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-frame-size) | Total block count |
| [mjpeg_header_byte](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-header-byte) | YUV order and auto fill |
| [mjpeg_swap_mode](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-swap-mode) | Swap mode |
| [mjpeg_swap_bit_cnt](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-swap-bit-cnt) | Remain bit count |
| [mjpeg_yuv_mem_sw](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-yuv-mem-sw) | Number of kick block line |
| [mjpeg_Y_frame_read_status_1](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-Y-frame-read-status-1) | Y read status1 |
| [mjpeg_Y_frame_read_status_2](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-Y-frame-read-status-2) | Y read status2 |
| [mjpeg_Y_frame_write_status](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-Y-frame-write-status) | Y write status |
| [mjpeg_UV_frame_read_status_1](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-UV-frame-read-status-1) | UV read status1 |
| [mjpeg_UV_frame_read_status_2](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-UV-frame-read-status-2) | UV read status2 |
| [mjpeg_UV_frame_write_status](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-UV-frame-write-status) | UV write status |
| [mjpeg_frame_w_hblk_status](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-frame-w-hblk-status) | Vertical block write status |
| [mjpeg_start_addr0](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-start-addr0) | Start address of frame0 |
| [mjpeg_bit_cnt0](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-bit-cnt0) | Bit count of frame0 |
| [mjpeg_start_addr1](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-start-addr1) | Start address of frame1 |
| [mjpeg_bit_cnt1](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-bit-cnt1) | Bit count of frame1 |
| [mjpeg_start_addr2](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-start-addr2) | Start address of frame2 |
| [mjpeg_bit_cnt2](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-bit-cnt2) | Bit count of frame2 |
| [mjpeg_start_addr3](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-start-addr3) | Start address of frame3 |
| [mjpeg_bit_cnt3](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-bit-cnt3) | Bit count of frame3 |
| [mjpeg_q_enc](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-q-enc) | Quantize SRAM setting |
| [mjpeg_frame_id_10](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-frame-id-10) | ID of frame 0/1 |
| [mjpeg_frame_id_32](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-frame-id-32) | ID of frame 2/3 |
| [mjpeg_debug](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html#mjenc-mjpeg-debug) | ID latch timing |
### mjpeg\_control\_1
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021000
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:30 | RSVD | | | |
| 29:24 | reg\_mjpeg\_hw\_frame | RW | 0 | Non-SW mode frame cnt
0 - Nonauto stop |
| 23:14 | RSVD | | | |
| 13:12 | reg\_yuv\_mode | RW | 0 | YUV format setting
- 0: YUV420 planar
- 1: YUV400 gray scale
- 2: YUV422 planar
- 3: INTV422
|
| 11 | RSVD | | | |
| 10:8 | reg\_w\_xlen | RW | 0x3 | AXI burst length setting
- 0: Single
- 1: INCR4
- 2: INCR8
- 3: INCR16
- Others: RSVD
|
| 7 | reg\_read\_fwrap | RW | 1 | Only effect in non-software mode
This bit determine whether YUV frame read start at the start address |
| 6 | reg\_reflect\_dmy | RW | 0 | UV dummy with reflect |
| 5 | reg\_last\_hf\_hblk\_dmy | RW | 0 | MJPEG last half vertical block with dummy data 8'h80 |
| 4 | reg\_last\_hf\_wblk\_dmy | RW | 0 | MJPEG last half horizontal block with dummy data 8'h80 |
| 3 | reg\_hw\_mode\_swen | RW | 0 | Only word in hardware mode.
Software enable immediately to skip waiting the first frame done |
| 2 | reg\_order\_u\_even | RW | 1 |
- 0: U is odd byte of UV frame / V is even byte of UV frame
- 1: U is even byte of UV frame / V is odd byte of UV frame
|
| 1 | reg\_mjpeg\_bit\_order | RW | 1 | MJPEG bit stream byte order adjustment |
| 0 | reg\_mjpeg\_enable | RW | 0 | MJPEG enable |
### mjpeg\_control\_2
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021004
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:16 | reg\_mjpeg\_wait\_cycle | RW | 0x100 | Cycle count in wait state |
| 15:13 | reg\_uv\_dvp2axi\_sel | RW | 0x1 | DVP2AXI selection for UV frame (Don't care if using software
mode) |
| 12:10 | reg\_yy\_dvp2axi\_sel | RW | 0 | DVP2AXI selection for Y frame(Don't care if using software mode) |
| 9 | reg\_mjpeg\_sw\_run | RW | 0 | MJPEG software mode run (should enable reg\_mjpeg\_sw\_mode before
reg\_mjpeg\_sw\_run) |
| 8 | reg\_mjpeg\_sw\_mode | RW | 0 | MJPEG software mode enable (should enable reg\_mjpeg\_sw\_mode before
reg\_mjpeg\_sw\_run) |
| 7 | reg\_sw\_kick\_mode | RW | 0 | MJPEG software mode hblk kick mode
- 0: Software frame mode
- 1: Software kick mode
|
| 6 | reg\_sw\_kick | W1P | 0 | MJPEG software mode hblk kick |
| 5 | RSVD | | | |
| 4:0 | reg\_sw\_frame | RW | 0 | MJPEG software mode frame count |
### mjpeg\_yy\_frame\_addr
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021008
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:0 | reg\_yy\_addr\_start | RW | 0x80000000 | Memory start address of Y frame |
### mjpeg\_uv\_frame\_addr
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x3002100c
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:0 | reg\_uv\_addr\_start | RW | 0x80000000 | Memory start address of UV frame |
### mjpeg\_yuv\_mem
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021010
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:29 | RSVD | | | |
| 28:16 | reg\_uv\_mem\_hblk | RW | 0x2 | Memory to store block line for UV frame |
| 15:13 | RSVD | | | |
| 12:0 | reg\_yy\_mem\_hblk | RW | 0x2 | Memory to store block line for Y frame |
### jpeg\_frame\_addr
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021014
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:0 | reg\_w\_addr\_start | RW | 0x80400000 | Memory start address of JPEG frame |
### jpeg\_store\_memory
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021018
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:0 | reg\_w\_burst\_cnt | RW | 0x4000 | Memory to store jpeg image burst count |
### mjpeg\_control\_3
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x3002101c
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31 | RSVD | | | |
| 30 | sts\_swap\_int | R | 0 | Swap memory block interrupt status |
| 29 | reg\_int\_swap\_en | RW | 0 | Swap memory block interrupt enable |
| 28:24 | frame\_valid\_cnt | R | 0 | Frame count valid in status |
| 23 | RSVD | | | |
| 22 | sts\_idle\_int | R | 0 | Normal write interrupt status |
| 21 | reg\_int\_idle\_en | RW | 0 | Back idle interrupt enable |
| 20:16 | reg\_frame\_cnt\_trgr\_int | RW | 0 | Frame threshold to issue interrupt |
| 15 | axi\_write\_idle | R | 0 | AXI write bus idle state |
| 14 | axi\_read\_idle | R | 0 | AXI read bus idle state |
| 13 | mjpeg\_manf | R | 0 | MJPEG in software run state |
| 12 | mjpeg\_mans | R | 0 | MJPEG in software set state |
| 11 | mjpeg\_flsh | R | 0 | MJPEG in flush state |
| 10 | mjpeg\_wait | R | 0 | MJPEG in wait state |
| 9 | mjpeg\_func | R | 0 | MJPEG in hardware function state |
| 8 | mjpeg\_idle | R | 1 | MJPEG in idle state |
| 7 | sts\_frame\_int | R | 0 | Frame OverWrite interrupt status |
| 6 | sts\_mem\_int | R | 0 | Memory OverWrite interrupt status |
| 5 | sts\_cam\_int | R | 0 | CAM OverWrite interrupt status (fatal) |
| 4 | sts\_normal\_int | R | 0 | Normal write interrupt status |
| 3 | reg\_int\_frame\_en | RW | 0 | Frame OverWrite interrupt enable |
| 2 | reg\_int\_mem\_en | RW | 0 | JPEG frame memory OverWrite interrupt enable |
| 1 | reg\_int\_cam\_en | RW | 1 | YUV frame memory OverWrite interrupt enable (fatal) |
| 0 | reg\_int\_normal\_en | RW | 1 | Normal write interrupt enable |
### mjpeg\_frame\_fifo\_pop
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021020
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:14 | RSVD | | | |
| 13 | reg\_int\_swap\_clr | W1P | 0 | Write this bit with 1 to trigger swap interrupt clear |
| 12 | reg\_int\_idle\_clr | W1P | 0 | Write this bit with 1 to trigger back idle interrupt clear |
| 11 | reg\_int\_frame\_clr | W1P | 0 | Write this bit with 1 to trigger frame overwrite interrupt
clear |
| 10 | reg\_int\_mem\_clr | W1P | 0 | Write this bit with 1 to trigger memory overwrite interrupt
clear |
| 9 | reg\_int\_cam\_clr | W1P | 0 | Write this bit with 1 to trigger YUV overwrite interrupt clear |
| 8 | reg\_int\_normal\_clr | W1P | 0 | Write this bit with 1 to trigger normal interrupt clear |
| 7:2 | RSVD | | | |
| 1 | reg\_w\_swap\_clr | W1P | 0 | Free current read memory block |
| 0 | rfifo\_pop | W1P | 0 | Write this bit with 1 to trigger JPEG frame FIFO pop |
### mjpeg\_frame\_size
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021024
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:28 | RSVD | | | |
| 27:16 | reg\_frame\_hblk | RW | 0x14 | Frame total vertical block count |
| 15:12 | RSVD | | | |
| 11:0 | reg\_frame\_wblk | RW | 0xF | Frame total horizontal block count |
### mjpeg\_header\_byte
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021028
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:30 | reg\_v0\_order | RW | 0x3 | V order in interleave mode |
| 29:28 | reg\_y1\_order | RW | 0x2 | Y1 order in interleave mode |
| 27:26 | reg\_u0\_order | RW | 0x1 | U order in interleave mode |
| 25:24 | reg\_y0\_order | RW | 0 | Y0 order in interleave mode |
| 23:17 | RSVD | | | |
| 16 | reg\_tail\_exp | RW | 0 | Auto fill tail 0xFF and 0xD9 |
| 15:12 | RSVD | | | |
| 11:0 | reg\_head\_byte | RW | 0 | Preserve head memory space for each frame |
### mjpeg\_swap\_mode
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021030
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:13 | RSVD | | | |
| 12 | sts\_swap\_fend | R | 0 | Current read memory block is frame end |
| 11 | sts\_swap\_fstart | R | 0 | Current read memory block is frame start |
| 10 | sts\_read\_swap\_idx | R | 0 | Current read memory block index
- 0: memory block0
- 1: memory block1
|
| 9 | sts\_swap1\_full | R | 0 | Memory block1 is full |
| 8 | sts\_swap0\_full | R | 0 | Memory block0 is full |
| 7:1 | RSVD | | | |
| 0 | reg\_w\_swap\_mode | RW | 0 | Enable write swap mode |
### mjpeg\_swap\_bit\_cnt
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021034
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:0 | frame\_swap\_end\_bit\_cnt | R | 0 | In swap mode frame remain bit count in the last block
Only valid when 'sts\_swap\_fend==1' |
### mjpeg\_yuv\_mem\_sw
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021038
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:13 | RSVD | | | |
| 12:0 | reg\_sw\_kick\_hblk | RW | 0x2 | Memory to store block line for frame on software kick |
### mjpeg\_Y\_frame\_read\_status\_1
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021040
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:29 | RSVD | | | |
| 28:16 | yy\_frm\_hblk\_r | R | 0 | Y frame vertical block read status |
| 15:13 | RSVD | | | |
| 12:0 | yy\_mem\_hblk\_r | R | 0 | Y memory vertical block read status |
### mjpeg\_Y\_frame\_read\_status\_2
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021044
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:24 | yy\_frm\_cnt\_r | R | 0 | Y frame read count |
| 23:16 | yy\_mem\_rnd\_r | R | 0 | Y memory read round |
| 15:13 | RSVD | | | |
| 12:0 | yy\_wblk\_r | R | 0 | Y frame horizontal block read status |
### mjpeg\_Y\_frame\_write\_status
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021048
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:24 | yy\_frm\_cnt\_w | R | 0 | Y frame write count |
| 23:16 | yy\_mem\_rnd\_w | R | 0 | Y memory write round |
| 15:13 | RSVD | | | |
| 12:0 | yy\_mem\_hblk\_w | R | 0 | Y memory vertical block write status |
### mjpeg\_UV\_frame\_read\_status\_1
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x3002104c
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:29 | RSVD | | | |
| 28:16 | uv\_frm\_hblk\_r | R | 0 | UV frame vertical block read status |
| 15:13 | RSVD | | | |
| 12:0 | uv\_mem\_hblk\_r | R | 0 | UV memory vertical block read status |
### mjpeg\_UV\_frame\_read\_status\_2
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021050
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:24 | uv\_frm\_cnt\_r | R | 0 | UV frame read count |
| 23:16 | uv\_mem\_rnd\_r | R | 0 | UV memory read round |
| 15:13 | RSVD | | | |
| 12:0 | uv\_wblk\_r | R | 0 | UV frame horizontal block read status |
### mjpeg\_UV\_frame\_write\_status
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021054
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:24 | uv\_frm\_cnt\_w | R | 0 | UV frame write count |
| 23:16 | uv\_mem\_rnd\_w | R | 0 | UV memory write round |
| 15:13 | RSVD | | | |
| 12:0 | uv\_mem\_hblk\_w | R | 0 | UV memory vertical block write status |
### mjpeg\_frame\_w\_hblk\_status
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021058
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:29 | RSVD | | | |
| 28:16 | uv\_frm\_hblk\_w | R | 0 | UV frame vertical block write status |
| 15:13 | RSVD | | | |
| 12:0 | yy\_frm\_hblk\_w | R | 0 | YY frame vertical block write status |
### mjpeg\_start\_addr0
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021080
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:0 | frame\_start\_addr\_0 | R | 0 | MJPEG FRAME0 Start address |
### mjpeg\_bit\_cnt0
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021084
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:0 | frame\_bit\_cnt\_0 | R | 0 | MJPEG FRAME0 total bit count |
### mjpeg\_start\_addr1
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021088
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:0 | frame\_start\_addr\_1 | R | 0 | MJPEG FRAME1 Start address |
### mjpeg\_bit\_cnt1
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x3002108c
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:0 | frame\_bit\_cnt\_1 | R | 0 | MJPEG FRAME1 total bit count |
### mjpeg\_start\_addr2
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021090
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:0 | frame\_start\_addr\_2 | R | 0 | MJPEG FRAME2 Start address |
### mjpeg\_bit\_cnt2
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021094
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:0 | frame\_bit\_cnt\_2 | R | 0 | MJPEG FRAME2 total bit count |
### mjpeg\_start\_addr3
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021098
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:0 | frame\_start\_addr\_3 | R | 0 | MJPEG FRAME3 Start address |
### mjpeg\_bit\_cnt3
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x3002109c
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:0 | frame\_bit\_cnt\_3 | R | 0 | MJPEG FRAME3 total bit count |
### mjpeg\_q\_enc
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021100
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:26 | RSVD | | | |
| 25 | sts\_q\_sram\_enc | R | 0 | Current quantize SRAM selection for encode |
| 24 | reg\_q\_sram\_sw | W1P | 0 | Quantize SRAM switch |
| 23:4 | RSVD | | | |
| 3 | frame\_q\_sram\_3 | R | 0 | MJPEG FRAME3 quantize SRAM selection |
| 2 | frame\_q\_sram\_2 | R | 0 | MJPEG FRAME2 quantize SRAM selection |
| 1 | frame\_q\_sram\_1 | R | 0 | MJPEG FRAME1 quantize SRAM selection |
| 0 | frame\_q\_sram\_0 | R | 0 | MJPEG FRAME0 quantize SRAM selection |
### mjpeg\_frame\_id\_10
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021110
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:16 | frame\_id\_1 | R | 0 | JPEG PIC 1 ID |
| 15:0 | frame\_id\_0 | R | 0 | JPEG PIC 0 ID |
### mjpeg\_frame\_id\_32
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x30021114
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:16 | frame\_id\_3 | R | 0 | JPEG PIC 3 ID |
| 15:0 | frame\_id\_2 | R | 0 | JPEG PIC 2 ID |
### mjpeg\_debug
Source: [https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html](https://docs.qualcomm.com/doc/80-58740-1/topic/mjpeg.html)
Address: 0x300211f0
| Bits | **Name** | **Type** | **Reset** | **Description** |
| --- | --- | --- | --- | --- |
| 31:12 | RSVD | | | |
| 11:8 | reg\_id\_latch\_hblk | RW | 1 | ID latch timing (hblk count) |
| 7:4 | reg\_mjpeg\_dbg\_sel | RW | 0 | MJPEG debug flag selection |
| 3:1 | RSVD | | | |
| 0 | reg\_mjpeg\_dbg\_en | RW | 0 | MJPEG debug flag enable |
Last Published: Feb 11, 2026