# Overview

Source: [https://docs.qualcomm.com/doc/80-70014-10/topic/1-performance-overview.html](https://docs.qualcomm.com/doc/80-70014-10/topic/1-performance-overview.html)

The performance capabilities of the Qualcomm® Linux platform allow developers to
        enhance system efficiency.

Monitoring performance metrics ensures optimal utilization of system resources. For
            example, performance metrics can be used to gauge power consumption efficiency and also
            to enhance thermal management.

This guide provides instructions on how to measure, fine-tune, and enhance the
            performance of software running on the Linux platform.

It includes the following information related to system performance:

- [Features](https://docs.qualcomm.com/doc/80-70014-10/topic/2-performance-features.html) that impact performance
- [Analysis tools](https://docs.qualcomm.com/doc/80-70014-10/topic/13-performance_tools.html) to analyze hotspots (parts of
                    application and system software) that impact performance
- [Configure](https://docs.qualcomm.com/doc/80-70014-10/topic/14-configure.html) and [Customize](https://docs.qualcomm.com/doc/80-70014-10/topic/18-customize.html) to tune
                    the basic parameters of the Linux features to enhance performance
- [Troubleshooting](https://docs.qualcomm.com/doc/80-70014-10/topic/24-debug.html) methods for performance issues
- [Performance dashboards for QCS6490](https://docs.qualcomm.com/doc/80-70014-10/topic/46-performance-dashbaord.html), measurement procedures, and [Performance dashboards for QCS5430](https://docs.qualcomm.com/doc/80-70014-10/topic/46-performance-dashboard-qcs5430.html) for reference purposes.

## Subsystem dependencies

The performance of the software is influenced by the CPU subsystem, GPU, and DDR. The
                Qualcomm Linux system is powered by the Qualcomm® Kryo™ CPU, which consists of the
                following clusters:

- Prime cluster for high-performance CPU cores
- Gold cluster for CPU cores offering balanced power and performance
- Silver cluster for low-power CPU cores, ideal for light-weight applications

Cache memory is categorized into three levels: L1, L2, and L3:

- L1 is the smallest and fastest cache level, storing both instructions (L1 I) and
                    data (L1 D).
- L2 and L3 are larger but slower cache levels, dedicated to data storage
                    only.

Note: The Qualcomm Linux platform
                allows you to develop applications for QCS6490 and QCS5430.

The following tables list the specifications for the subsystems on QCS6490 and
                QCS5430:

| Specifications | QCS6490 | QCS6490 | QCS6490 |
| --- | --- | --- | --- |
| Core type | Kryo Prime | Kryo Gold | Kryo Silver |
| Number of CPUs | 1 | 3 | 4 |
| CPU maximum frequency | 2.7 GHz | 2.4 GHz | 1.9 GHz |
| L1 I cache | 32 kB | 32 kB/core | 32 kB/core |
| L1 D cache | 32 kB | 32 kB/core | 32 kB/core |
| L2 cache | 256 kB | 256 kB/core | 128 kB/core |
| L3 cache | 2 MB | 2 MB | 2 MB |
| GPU | Qualcomm^®^Adreno^™^ 643 GPU | Qualcomm^®^Adreno^™^ 643 GPU | Qualcomm^®^Adreno^™^ 643 GPU |
| GPU maximum frequency | 812 MHz | 812 MHz | 812 MHz |
| GPU memory (GMEM) | 512 kB | 512 kB | 512 kB |
| DDRSS | <ul class="ul" id="peformanceoverview__ul_al4_r5f_51c_caharris_03-19-24-151-39-614"><br>                                        <li class="li">Supports dual-channel non-package-on-package high-speed<br>                                            LPDDR5/LPDDR4 SDRAM.</li><br><br>                                        <li class="li">LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>                                            16‑bit).</li><br><br>                                        <li class="li">LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>                                            16‑bit).</li><br><br>                                    </ul> | <ul class="ul" id="peformanceoverview__ul_al4_r5f_51c_caharris_03-19-24-151-39-614"><br>                                        <li class="li">Supports dual-channel non-package-on-package high-speed<br>                                            LPDDR5/LPDDR4 SDRAM.</li><br><br>                                        <li class="li">LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>                                            16‑bit).</li><br><br>                                        <li class="li">LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>                                            16‑bit).</li><br><br>                                    </ul> | <ul class="ul" id="peformanceoverview__ul_al4_r5f_51c_caharris_03-19-24-151-39-614"><br>                                        <li class="li">Supports dual-channel non-package-on-package high-speed<br>                                            LPDDR5/LPDDR4 SDRAM.</li><br><br>                                        <li class="li">LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>                                            16‑bit).</li><br><br>                                        <li class="li">LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>                                            16‑bit).</li><br><br>                                    </ul> |

| Specifications | QCS5430 FP1<br>                                    (Feature pack 1) | QCS5430 FP1<br>                                    (Feature pack 1) | QCS5430 FP2 (Feature<br>                                    pack 2) | QCS5430 FP2 (Feature<br>                                    pack 2) | QCS5430 FP2 (Feature<br>                                    pack 2) |
| --- | --- | --- | --- | --- | --- |
| Core type | Kryo Gold | Kryo Silver | Kryo Prime | Kryo Gold | Kryo Silver |
| Number of CPUs | 2 | 4 | 1 | 3 | 4 |
| CPU maximum frequency | 2.1 GHz | 1.8 GHz | 2.2 GHz | 2.1 GHz | 1.8 GHz |
| L1 I cache | 32 kB/core | 32 kB/core | 32 kB | 32 kB/core | 32 kB/core |
| L1 D cache | 32 kB/core | 32 kB/core | 32 kB | 32 kB/core | 32 kB/core |
| L2 cache | 256 kB/core | 128 kB/core | 256 kB | 256 kB/core | 128 kB/core |
| L3 cache | 2 MB | 2 MB | 2 MB | 2 MB | 2 MB |
| GPU | Qualcomm^®^Adreno^™^ 642L GPU | Qualcomm^®^Adreno^™^ 642L GPU | Qualcomm^®^Adreno^™^ 642L GPU | Qualcomm^®^Adreno^™^ 642L GPU | Qualcomm^®^Adreno^™^ 642L GPU |
| GPU maximum frequency | 315 MHz | 315 MHz | 315 MHz | 315 MHz | 315 MHz |
| GPU memory (GMEM) | 512 kB | 512 kB | 512 kB | 512 kB | 512 kB |
| DDRSS | <ul class="ul" id="peformanceoverview__ul_trp_d44_mbc_sshewale_05-23-24-1518-48-897"><br>                                        <li class="li">Supports dual-channel non-package-on-package high-speed<br>                                            LPDDR5/LPDDR4 SDRAM.</li><br><br>                                        <li class="li">LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>                                            16‑bit).</li><br><br>                                        <li class="li">LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>                                            16‑bit).</li><br><br>                                    </ul> | <ul class="ul" id="peformanceoverview__ul_trp_d44_mbc_sshewale_05-23-24-1518-48-897"><br>                                        <li class="li">Supports dual-channel non-package-on-package high-speed<br>                                            LPDDR5/LPDDR4 SDRAM.</li><br><br>                                        <li class="li">LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>                                            16‑bit).</li><br><br>                                        <li class="li">LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>                                            16‑bit).</li><br><br>                                    </ul> | <ul class="ul" id="peformanceoverview__ul_trp_d44_mbc_sshewale_05-23-24-1518-48-897"><br>                                        <li class="li">Supports dual-channel non-package-on-package high-speed<br>                                            LPDDR5/LPDDR4 SDRAM.</li><br><br>                                        <li class="li">LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>                                            16‑bit).</li><br><br>                                        <li class="li">LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>                                            16‑bit).</li><br><br>                                    </ul> | <ul class="ul" id="peformanceoverview__ul_trp_d44_mbc_sshewale_05-23-24-1518-48-897"><br>                                        <li class="li">Supports dual-channel non-package-on-package high-speed<br>                                            LPDDR5/LPDDR4 SDRAM.</li><br><br>                                        <li class="li">LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>                                            16‑bit).</li><br><br>                                        <li class="li">LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>                                            16‑bit).</li><br><br>                                    </ul> | <ul class="ul" id="peformanceoverview__ul_trp_d44_mbc_sshewale_05-23-24-1518-48-897"><br>                                        <li class="li">Supports dual-channel non-package-on-package high-speed<br>                                            LPDDR5/LPDDR4 SDRAM.</li><br><br>                                        <li class="li">LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>                                            16‑bit).</li><br><br>                                        <li class="li">LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>                                            16‑bit).</li><br><br>                                    </ul> |

Last Published: Jul 12, 2024

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