# Overview Source: [https://docs.qualcomm.com/doc/80-70015-10/topic/1-performance-overview.html](https://docs.qualcomm.com/doc/80-70015-10/topic/1-performance-overview.html) This guide explains how to measure, fine-tune, and enhance the performance of the Qualcomm® Linux® software. Additionally, it discusses: - Features that impact performance - Tools to identify and analyze performance issues in software - Options to configure and customize the Linux settings for enhanced performance - Methods to troubleshoot performance issues - Procedures to measure performance - Performance dashboards for QCS6490 and QCS5430 Note: See [Hardware SoCs](https://docs.qualcomm.com/bundle/publicresource/topics/80-70015-115/soc.html) that are supported on Qualcomm Linux. ## Subsystem dependencies The performance of the software depends on the CPU, GPU, and DDR subsystems. Qualcomm Linux uses the Qualcomm® Kryo™ CPU, which has the following clusters: - Prime cluster for high-performance CPU cores - Gold cluster for balanced power and performance - Silver cluster for low-power CPU cores, ideal for light-weight applications Cache memory is categorized into three levels: L1, L2, and L3: - L1 is the smallest and fastest cache level, storing both instructions (L1 I) and data (L1 D) - L2 and L3 are larger but slower cache levels, mainly for data storage The following tables list the specifications for the subsystems on supported chip products: | Specifications | QCS6490 | QCS6490 | QCS6490 | | --- | --- | --- | --- | | Core type | Kryo Prime | Kryo Gold | Kryo Silver | | Number of CPUs | 1 | 3 | 4 | | CPU maximum frequency | 2.7 GHz | 2.4 GHz | 1.9 GHz | | L1 I cache | 32 kB | 32 kB/core | 32 kB/core | | L1 D cache | 32 kB | 32 kB/core | 32 kB/core | | L2 cache | 256 kB | 256 kB/core | 128 kB/core | | L3 cache | 2 MB | 2 MB | 2 MB | | GPU | Qualcomm^®^
Adreno^™^ 643 GPU | Qualcomm^®^
Adreno^™^ 643 GPU | Qualcomm^®^
Adreno^™^ 643 GPU | | GPU maximum frequency | 812 MHz | 812 MHz | 812 MHz | | DDRSS |

Supports dual-channel non-package-on-package high-speed
LPDDR5/LPDDR4 SDRAM.

LPDDR5 SDRAM is designed for a 3200 MHz clock (2 ×
16‑bit).

LPDDR4 SDRAM is designed for a 2133 MHz clock (2 ×
16‑bit).

Supports dual-channel non-package-on-package high-speed
LPDDR5/LPDDR4 SDRAM.

LPDDR5 SDRAM is designed for a 3200 MHz clock (2 ×
16‑bit).

LPDDR4 SDRAM is designed for a 2133 MHz clock (2 ×
16‑bit).

Supports dual-channel non-package-on-package high-speed
LPDDR5/LPDDR4 SDRAM.

LPDDR5 SDRAM is designed for a 3200 MHz clock (2 ×
16‑bit).

LPDDR4 SDRAM is designed for a 2133 MHz clock (2 ×
16‑bit).

| | Specifications | QCS5430 FP 1 (feature pack 1) | QCS5430 FP 1 (feature pack 1) | QCS5430
FP 2 | QCS5430
FP 2 | QCS5430
FP 2 | | --- | --- | --- | --- | --- | --- | | Core type | Kryo Gold | Kryo Silver | Kryo Prime | Kryo Gold | Kryo Silver | | Number of CPUs | 2 | 4 | 1 | 3 | 4 | | CPU maximum frequency | 2.1 GHz | 1.8 GHz | 2.2 GHz | 2.1 GHz | 1.8 GHz | | L1 I cache | 32 kB/core | 32 kB/core | 32 kB | 32 kB/core | 32 kB/core | | L2 cache | 256 kB/core | 128 kB/core | 256 kB | 256 kB/core | 128 kB/core | | L3 cache | 2 MB | 2 MB | 2 MB | 2 MB | 2 MB | | GPU | Qualcomm Adreno 642L
GPU | Qualcomm Adreno 642L
GPU | Qualcomm Adreno 642L
GPU | Qualcomm Adreno 642L
GPU | Qualcomm Adreno 642L
GPU | | GPU maximum frequency | 315 MHz | 315 MHz | 315 MHz | 315 MHz | 315 MHz | | DDRSS |

Supports dual-channel non-package-on-package high-speed
LPDDR5/LPDDR4 SDRAM.

LPDDR5 SDRAM is designed for a 3200 MHz clock (2 ×
16‑bit).

LPDDR4 SDRAM is designed for a 2133 MHz clock (2 ×
16‑bit).

Supports dual-channel non-package-on-package high-speed
LPDDR5/LPDDR4 SDRAM.

LPDDR5 SDRAM is designed for a 3200 MHz clock (2 ×
16‑bit).

LPDDR4 SDRAM is designed for a 2133 MHz clock (2 ×
16‑bit).

Supports dual-channel non-package-on-package high-speed
LPDDR5/LPDDR4 SDRAM.

LPDDR5 SDRAM is designed for a 3200 MHz clock (2 ×
16‑bit).

LPDDR4 SDRAM is designed for a 2133 MHz clock (2 ×
16‑bit).

Supports dual-channel non-package-on-package high-speed
LPDDR5/LPDDR4 SDRAM.

LPDDR5 SDRAM is designed for a 3200 MHz clock (2 ×
16‑bit).

LPDDR4 SDRAM is designed for a 2133 MHz clock (2 ×
16‑bit).

Supports dual-channel non-package-on-package high-speed
LPDDR5/LPDDR4 SDRAM.

LPDDR5 SDRAM is designed for a 3200 MHz clock (2 ×
16‑bit).

LPDDR4 SDRAM is designed for a 2133 MHz clock (2 ×
16‑bit).

| | Specifications | QCS5430 FP 2.5 | QCS5430 FP 2.5 | QCS5430 FP 2.5 | QCS5430 FP 3 | QCS5430 FP 3 | QCS5430 FP 3 | | --- | --- | --- | --- | --- | --- | --- | | Core type | Kryo Prime | Kryo Gold | Kryo Silver | Kryo Prime | Kryo Gold | Kryo Silver | | Number of CPUs | 1 | 3 | 4 | 1 | 3 | 4 | | CPU maximum frequency | 2.38 GHz | 2.4 GHz | 1.8 GHz | 2.38 GHz | 2.4 GHz | 1.8 GHz | | L1 I cache | 32 kB | 32 kB/core | 32 kB/core | 32 kB | 32 kB/core | 32 kB/core | | L2 cache | 256 kB | 256 kB/core | 128 kB/core | 256 kB | 256 kB/core | 128 kB/core | | L3 cache | 2 MB | 2 MB | 2 MB | 2 MB | 2 MB | 2 MB | | GPU | Qualcomm Adreno 642L
GPU | Qualcomm Adreno 642L
GPU | Qualcomm Adreno 642L
GPU | Qualcomm Adreno 642L
GPU | Qualcomm Adreno 642L
GPU | Qualcomm Adreno 642L
GPU | | GPU maximum frequency | 550 MHz | 550 MHz | 550 MHz | 550 MHz | 550 MHz | 550 MHz | | DDRSS |

Supports dual-channel non-package-on-package high-speed
LPDDR5/LPDDR4 SDRAM.

LPDDR5 SDRAM is designed for a 3200 MHz clock (2 ×
16‑bit).

LPDDR4 SDRAM is designed for a 2133 MHz clock (2 ×
16‑bit).

Supports dual-channel non-package-on-package high-speed
LPDDR5/LPDDR4 SDRAM.

LPDDR5 SDRAM is designed for a 3200 MHz clock (2 ×
16‑bit).

LPDDR4 SDRAM is designed for a 2133 MHz clock (2 ×
16‑bit).

Supports dual-channel non-package-on-package high-speed
LPDDR5/LPDDR4 SDRAM.

LPDDR5 SDRAM is designed for a 3200 MHz clock (2 ×
16‑bit).

LPDDR4 SDRAM is designed for a 2133 MHz clock (2 ×
16‑bit).

Supports dual-channel non-package-on-package high-speed
LPDDR5/LPDDR4 SDRAM.

LPDDR5 SDRAM is designed for a 3200 MHz clock (2 ×
16‑bit).

LPDDR4 SDRAM is designed for a 2133 MHz clock (2 ×
16‑bit).

Supports dual-channel non-package-on-package high-speed
LPDDR5/LPDDR4 SDRAM.

LPDDR5 SDRAM is designed for a 3200 MHz clock (2 ×
16‑bit).

LPDDR4 SDRAM is designed for a 2133 MHz clock (2 ×
16‑bit).

Supports dual-channel non-package-on-package high-speed
LPDDR5/LPDDR4 SDRAM.

LPDDR5 SDRAM is designed for a 3200 MHz clock (2 ×
16‑bit).

LPDDR4 SDRAM is designed for a 2133 MHz clock (2 ×
16‑bit).

| | **Specifications** | **QCS9075** | **QCS9075** | | --- | --- | --- | | Core type | **Kryo Prime** | **Kryo Prime** | | Number of CPUs | 4 | 4 | | CPU maximum frequency | 2.36 GHz | 2.36 GHz | | L1I cache | 64 kB/core | 64 kB/core | | L1D cache | 64 kB/core | 64 kB/core | | L2 cache | 512 kB/core | 512 kB/core | | L3 cache | 2 MB/core (shared per
cluster) | 2 MB/core (shared per
cluster) | | GPU | Qualcomm Adreno 663 GPU | Qualcomm Adreno 663 GPU | | GPU maximum frequency | 800 MHz | 800 MHz | | DDRSS | Six-channel high-speed memory –
3200 MHz LPDDR5 SDRAM (6 × 16‑bit) | Six-channel high-speed memory –
3200 MHz LPDDR5 SDRAM (6 × 16‑bit) | Last Published: Oct 14, 2024 [Next Topic Getting started](https://docs.qualcomm.com/bundle/publicresource/80-70015-10/topics/get-started.md)