# TLMM

Source: [https://docs.qualcomm.com/doc/80-70015-4/topic/tlmm-developer-touchpoints.html](https://docs.qualcomm.com/doc/80-70015-4/topic/tlmm-developer-touchpoints.html)

The hardware controls the multiplexing of general-purpose input/output (GPIO) and
        alternate functions through the top-level mode multiplexer (TLMM). You can configure the
        GPIOs during the boot process using the DT properties for TLMM.

You can edit the following file paths to update the properties on the Linux host
            machine:

- /boot\_images/boot/Settings/Soc/&lt;Chipset&gt;/Core/SocInfra/TLMM/&lt;Chipset&gt;-pinctrl.dtsi
- /boot\_images/boot/Settings/Soc/&lt;Chipset&gt;/Core/SocInfra/TLMM/tlmm.dtsi

The table lists the properties that describe how to configure the default value of a GPIO
            based on the requirements of the Qualcomm reference device.

Table : TLMM DT properties

| Property name | Property description | Data type | Possible values/value range | Device behavior |
| --- | --- | --- | --- | --- |
| QCOM, sleep-config | GPIO configuration settings as defined in<br>                                &lt;Chipset&gt;-pinctrl.dtsi. The configurations<br>                            are applied on device boot up. | UINT32 | Pin direction:<br><ul class="ul" id="tlmm-developer-touchpoints__ul_emt_cmk_l1c"><br>                                <li class="li"> GPIO_INPUT – 0x1</li><br><br>                                <li class="li"> GPIO_OUTPUT – 0x2</li><br><br>                            </ul><br><br>Pin pull configuration:<br><ul class="ul" id="tlmm-developer-touchpoints__ul_bc5_yln_vcc"><br>                                <li class="li"> GPIO_PULL_DOWN – 0x4</li><br><br>                                <li class="li"> GPIO_PULL_UP – 0x8</li><br><br>                                <li class="li"> GPIO_NO_PULL – 0x10</li><br><br>                                <li class="li"> GPIO_KEEPER – 0x20 </li><br><br>                            </ul>Pin output:<ul class="ul" id="tlmm-developer-touchpoints__ul_h51_4bp_xcc"><br>                                <li class="li"> GPIO_OUT_LOW – 0x40</li><br><br>                                <li class="li"> GPIO_OUT_HIGH – 0x80</li><br><br>                                <li class="li">GPIO_PRG_YES – 0x100</li><br><br>                                <li class="li">GPIO_PRG_NO – 0x000</li><br><br>                            </ul> | <ul class="ul" id="tlmm-developer-touchpoints__ul_jzt_kmk_l1c"><br>                                <li class="li">The default value is GPIO_INPUT<ul class="ul" id="tlmm-developer-touchpoints__ul_khh_lmk_l1c"><br>                                        <li class="li">GPIO_INPUT: Allows the state of an input pin to be read </li><br><br>                                        <li class="li">GPIO_OUTPUT: Controls the state of an output pin</li><br><br>                                    </ul><br></li><br><br>                            </ul><ul class="ul" id="tlmm-developer-touchpoints__ul_wbp_lmk_l1c"><br>                                <li class="li">The default value is GPIO_PULL_DOWN.<ul class="ul" id="tlmm-developer-touchpoints__ul_ows_lmk_l1c"><br>                                        <li class="li">GPIO_PULL_DOWN: Logic 0, consider as connected to<br>                                            Ground</li><br><br>                                        <li class="li"><br>                                            <p class="p">GPIO_PULL_UP:  Logic 1, connected to Vdd supply</p><br><br>                                        </li><br><br>                                        <li class="li"><br>                                            <p class="p"> GPIO_NO_PULL:  Floating/High Impedance state</p><br><br>                                        </li><br><br>                                        <li class="li"><br>                                            <p class="p">GPIO_KEEPER: Maintain the previous state of the GPIO.<br>                                                When a SoC enters the deepest power-saving mode,<br>                                                this configuration is applied.</p><br><br>                                        </li><br><br>                                    </ul><br></li><br><br>                            </ul><ul class="ul" id="tlmm-developer-touchpoints__ul_xbm_4mk_l1c"><br>                                <li class="li">The default value is GPIO_OUT_LOW<p class="p">GPIO_OUT_HIGH:  Logic high,<br>                                        consider as connected to Vdd. </p><br></li><br><br>                            </ul><ul class="ul" id="tlmm-developer-touchpoints__ul_tdt_4mk_l1c"><br>                                <li class="li">The default value is GPIO_PRG_NO.<p class="p">GPIO_PRG_YES:  Ensures that<br>                                        any unused GPIOs remain in a low-power state after<br>                                        bootup</p><br></li><br><br>                            </ul><br><br>                            <br><br><br><br>                            <br>Example:<br><br><br>                            <br>(GPIO_INPUT | GPIO_PULL_DOWN | GPIO_OUT_LOW | GPIO_PRG_NO) /* PIN 10 */Copy to clipboard |
| Compatible | Compatible property contains a read-only string that points to the<br>                                compatible chipset. | String | – | Example:<br><br>compatible =<br>                                "qcom,&lt;chipset&gt;-pinctrl" |
| reg | Represents the read only GPIO base address and size. | UINT32 | reg = <0xf100000 0x100000>;Copy to clipboard | In a `reg` property tuple, the first index contains<br>                                the base address, and the second index contains the size. Example:<br> |
| ngpios | Number of read only GPIO pins in chipset. | UINT32 | – | Example:<br><br><br>                            <br>ngpios = <175>;Copy to clipboard |
| width | Each GPIO pin has its own set of read only control registers. Width<br>                                indicates pin to pin register offset. | – | – | Example:<br><br><br>                            <br>width = <0x1000>;Copy to clipboard |
| id | Hardware instance of read only GPIO pad ID. | UINT32 | – | Example:<br><br><br>                            <br>id = <0x0>;Copy to clipboard |
| version | GPIO read only driver version. Driver 1.0 refers as 0x1. | UINT32 | – | Example:<br><br><br>                            <br>version = <0x1>;Copy to clipboard |
| gpio-controller | Identifier to represent the read only connected device as a GPIO<br>                                device. | String | – | – |
| phandles for pin configurations | Mux configuration that is used to configure the alternative<br>                                functionality of GPIOs. For more information, see [Pin descriptions](https://docs.qualcomm.com/bundle/80-23889-1/resource/80-23889-1_REV_AM_QCS6490_QCS5430_Data_Sheet.pdf). | – | `sdc4_data_1: sdc4_data_1 { mux = <13 3>; };`<br> | On bootup, the GPIO configures to alternate functionality of<br>                                GPIO.<br>Example:<br><br><br>sdc4_data_1: sdc4_data_1 { mux = <13 3>; };Copy to clipboard<br><br><br>In this example, 13 refers to the GPIO number and 3 indicates the<br>                                alternate function selection. |

**Parent Topic:** [Interfaces](https://docs.qualcomm.com/doc/80-70015-4/topic/interfaces.html)

Last Published: Oct 04, 2024

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