# References
Source: [https://docs.qualcomm.com/doc/80-70015-8/topic/references.html](https://docs.qualcomm.com/doc/80-70015-8/topic/references.html)
## QUP v3 overview
Source: [https://docs.qualcomm.com/doc/80-70015-8/topic/references.html](https://docs.qualcomm.com/doc/80-70015-8/topic/references.html)
The QUP v3 is a highly flexible and programmable hardware for supporting a wide range of
serial interface. A single QUP v3 serial engine hardware core provides up to eight
serial interfaces. The two QUP v3 hardware cores are as follows:
- 16-serial engine core
- SSC QUP v3 hardware core with five serial engines available in the SSC\_I/Os
The QUP v3 supports access from multiple hardware entities in the system. Each entity has
its own execution environment (EE), a separate address space, and an interrupt line. For
information on the various transfer modes that can be configured in QUP v3, see [Supported transfer modes in QUP v3](https://docs.qualcomm.com/doc/80-70015-8/topic/references.html#qup-v3-supported-transfer-modes).
The following figure shows one GSI core/engine connected with up to eight serial engines
(SE). You have the flexibility to customize configurations depending on the use case or
the protocol of the serial engine. For information on how to customize configurations,
see [QUP v3 access control customization](https://docs.qualcomm.com/doc/80-70015-8/topic/references.html#customize-access-control-of-qup). To verify if the QUP v3
firmware is correctly flashed, see [QUP v3 firmware status verification](https://docs.qualcomm.com/doc/80-70015-8/topic/references.html#verify-qup-firmware-status).
Figure : QUP v3 block diagram
## QUP v3 mapping to protocols and GPIOs in QCS6490 and QCS5430
Source: [https://docs.qualcomm.com/doc/80-70015-8/topic/references.html](https://docs.qualcomm.com/doc/80-70015-8/topic/references.html)
The QCS6490 and QCS5430 chip products contain 21 QUP v3 serial engines. Of these, 16
QUP v3 serial engines are allocated for the application processor and 5 QUP v3 serial
engines are allocated for the sensor low-power island (SLPI) on the application digital
signal processor (aDSP).
Only one protocol can be selected in one QUP v3 serial engine at a time. For example,
simultaneous UART and I2C functions are not supported. Each QUP v3 serial engine has up
to seven lanes (I/O), which are numbered from 0 to 6.
Note: The top-level QUP v3 serial engines are used as the application
processor and boot image. The low-power island (LPI) QUP v3 serial engines are used for
the sensor subsystem and TrustZone use cases.
The default QUP v3 mapping to protocols and GPIOs are listed in the following
tables.
| QUP v3 serial engine | QUP v3 serial engine | Protocols | Protocols | Protocols | Protocols | Protocols | QUP lane to GPIO mapping | QUP lane to GPIO mapping | QUP lane to GPIO mapping | QUP lane to GPIO mapping | QUP lane to GPIO mapping | QUP lane to GPIO mapping | QUP lane to GPIO mapping |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| QUP v3 serial engine | QUP v3 serial engine | UART | I3C | HS UART | SPI-M | I2C | L0 | L1 | L2 | L3 | L4 | L5 | L6 |
| QUP\_0 | SE0 | Yes | Yes | – | Yes | Yes | 0 | 1 | 2 | 3 | – | – | – |
| QUP\_0 | SE1 | Yes | Yes | – | Yes | Yes | 4 | 5 | 6 | 7 | – | – | – |
| QUP\_0 | SE2 | Yes | – | – | Yes | Yes | 8 | 9 | 10 | 11 | – | – | – |
| QUP\_0 | SE3 | Yes | – | – | Yes | Yes | 12 | 13 | 14 | 15 | – | – | – |
| QUP\_0 | SE4 | Yes | – | – | Yes | Yes | 16 | 17 | 18 | 19 | – | – | – |
| QUP\_0 | SE5 | Yes | – | – | Yes | Yes | 20 | 21 | 22 | 23 | – | – | – |
| QUP\_0 | SE6 | Yes | – | Yes | Yes | Yes | 24 | 25 | 26 | 27 | – | – | – |
| QUP\_0 | SE7 | Yes | – | Yes | Yes | Yes | 28 | 29 | 30 | 31 | 2 | 3 | 6 |
| QUP\_1 | SE0 | Yes | Yes | – | Yes | Yes | 32 | 33 | 34 | 35 | – | – | – |
| QUP\_1 | SE1 | Yes | Yes | – | Yes | Yes | 36 | 37 | 38 | 39 | – | – | – |
| QUP\_1 | SE2 | Yes | – | – | Yes | Yes | 40 | 41 | 42 | 43 | – | – | – |
| QUP\_1 | SE3 | Yes | – | – | Yes | Yes | 44 | 45 | 45 | 47 | – | – | – |
| QUP\_1 | SE4 | Yes | – | – | Yes | Yes | 48 | 49 | 50 | 51 | 55 | 54 | 38 |
| QUP\_1 | SE5 | Yes | – | – | Yes | Yes | 52 | 53 | 54 | 55 | – | – | – |
| QUP\_1 | SE6 | Yes | – | Yes | Yes | Yes | 56 | 57 | 58 | 59 | 62 | 63 | 50 |
| QUP\_1 | SE7 | Yes | – | Yes | Yes | Yes | 60 | 61 | 62 | 63 | – | – | – |
| LPI\_QUP | SE0 | – | Yes | – | – | Yes | 159 | 160 | – | – | – | – | – |
| LPI\_QUP | SE1 | – | Yes | – | – | Yes | 161 | 162 | – | – | – | – | – |
| LPI\_QUP | SE2 | – | Yes | – | Yes | Yes | 163 | 164 | 165 | 166 | 161 | – | – |
| LPI\_QUP | SE5 | Yes | – | – | – | Yes | 171 | 172 | 171 | 172 | – | – | – |
| LPI\_QUP | SE6 | Yes | – | Yes | – | – | 159 | 159 | – | – | – | – | – |
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## QUP v3 mapping to protocols and GPIOs in QCS9075
Source: [https://docs.qualcomm.com/doc/80-70015-8/topic/references.html](https://docs.qualcomm.com/doc/80-70015-8/topic/references.html)
The QCS9075 chip product contains 26 QUP v3 serial engines. The protocol and GPIO mapping
is listed in the following tables.
| QUP v3 serial engine | QUP v3 serial engine | Protocols | Protocols | Protocols | Protocols | QUP lane to GPIO mapping | QUP lane to GPIO mapping | QUP lane to GPIO mapping | QUP lane to GPIO mapping | QUP lane to GPIO mapping | QUP lane to GPIO mapping | QUP lane to GPIO mapping |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| QUP v3 serial engine | QUP v3 serial engine | UART | HS UART | I2C-M | SPI-M | L0 | L1 | L2 | L3 | L4 | L5 | L6 |
| QUP\_0 | SE0 | Yes | – | Yes | Yes | 20 | 21 | 22 | 23 | – | – | – |
| QUP\_0 | SE1 | Yes | – | Yes | Yes | 24 | 25 | 26 | 27 | – | – | – |
| QUP\_0 | SE2 | Yes | Yes | Yes | Yes | 36 | 37 | 38 | 39 | – | – | – |
| QUP\_0 | SE3 | Yes | Yes | Yes | Yes | 28 | 29 | 30 | 31 | – | – | – |
| QUP\_0 | SE4 | Yes | – | Yes | Yes | 32 | 33 | 34 | 35 | – | – | – |
| QUP\_0 | SE5 | Yes | – | Yes | Yes | 36 | 37 | 38 | 39 | – | – | – |
| QUP\_1 | SE0 | Yes | – | Yes | Yes | 40 | 41 | 42 | 43 | – | – | – |
| QUP\_1 | SE1 | Yes | – | Yes | Yes | 42 | 43 | 40 | 41 | – | – | – |
| QUP\_1 | SE2 | Yes | Yes | Yes | Yes | 46 | 47 | 44 | 45 | – | – | – |
| QUP\_1 | SE3 | Yes | Yes | Yes | Yes | 44 | 45 | 46 | 47 | – | – | – |
| QUP\_1 | SE4 | Yes | – | Yes | Yes | 48 | 49 | 50 | 51 | – | – | – |
| QUP\_1 | SE5 | Yes | – | Yes | Yes | 52 | 53 | 54 | 55 | – | – | – |
| QUP\_1 | SE6 | Yes | – | Yes | Yes | 56 | 57 | 56 | 57 | – | – | – |
| QUP\_2 | SE0 | Yes | – | Yes | Yes | 80 | 81 | 82 | 83 | – | – | – |
| QUP\_2 | SE1 | Yes | – | Yes | Yes | 84 | 85 | 99 | 100 | – | – | – |
| QUP\_2 | SE2 | Yes | Yes | Yes | Yes | 86 | 87 | 88 | 89 | 90 | – | – |
| QUP\_2 | SE3 | Yes | Yes | Yes | Yes | 91 | 92 | 93 | 94 | – | – | – |
| QUP\_2 | SE4 | Yes | – | Yes | Yes | 95 | 96 | 97 | 98 | – | – | – |
| QUP\_2 | SE5 | Yes | – | Yes | Yes | 99 | 100 | 84 | 85 | – | – | – |
| QUP\_2 | SE6 | Yes | – | Yes | Yes | 97 | 98 | 95 | 96 | – | – | – |
| QUP\_3 | SE0 | Yes | – | Yes | Yes | 13 | 14 | 15 | 16 | 17 | 18 | 19 |
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## Supported transfer modes in QUP v3
Source: [https://docs.qualcomm.com/doc/80-70015-8/topic/references.html](https://docs.qualcomm.com/doc/80-70015-8/topic/references.html)
The following modes can be configured in the QUP v3 serial engine.
- **FIFO mode**
1. ①: The application processor configures the generic interface (GENI).
2. ②: The application processor processes Rx/Tx data. The data is
transferred between GENI and memory.
- **DMA mode**
1. ①: The application processor initializes DMA.
2. ②: The serial engine configures GENI, and initiates the transfer
process.
- **GSI mode**
1. ①: The application processor prepares TRE.
2. ②: The application processor informs QUP (GSI).
3. ③: The GSI processes TRE.
4. ④: After the TRE completes processing, it is sent to GENI.
5. ⑤: The serial engine processes the Rx/Tx data.
Note: The QUP v3 UART serial engine does not support the GSI
mode.
## QUP v3 access control customization
Source: [https://docs.qualcomm.com/doc/80-70015-8/topic/references.html](https://docs.qualcomm.com/doc/80-70015-8/topic/references.html)
The QUP v3 user access file `QUPAC_Access.c` specifies the owners of the
serial engine resource. Initially, it is populated according to the system I/O GPIO
allocation. All serial engines must be listed to access the subsystem. It is flexible
enough to list only the available serial engine on a particular device.
To customize the access control for the required serial engine protocol, configure the
parameters in the QUPAC\_Access.c file. The TrustZone image for the
QUPAC\_Access.c file is
at /firmware/qualcomm-linux-spf-1-0\_ap\_standard\_oem\_nomodem/TZ.XF.5.0/trustzone\_images/core/settings/buses/qup\_accesscontrol/qupv3/config/<chipset>/QUPAC\_Access.c.
To specify the owner of the serial engine resource, modify the
QUPAC\_Access.c file to suit the board design.
The following use case specifies the default protocol that operates on an enabled serial
engine. You can modify the code according to your board design.
### Nonsecure mode use case in QUP v3 serial engine
The following nonsecure mode use cases are supported in the QUP v3 serial engine.
const QUPv3_se_security_permissions_type qupv3_perms_iot_rb3[] =
{
/* PeriphID, ProtocolID, Mode, NsOwner, bAllowFifo, bLoad, bModExcl */
{ QUPV3_0_SE0, QUPV3_PROTOCOL_I2C, QUPV3_MODE_FIFO, AC_HLOS, TRUE, TRUE, FALSE }, // LT9611 and QPS615 I2C
{ QUPV3_0_SE1, QUPV3_PROTOCOL_I2C, QUPV3_MODE_FIFO, AC_HLOS, TRUE, TRUE, FALSE }, // APPS I2C - PCIE/ USB Type C
{ QUPV3_0_SE2, QUPV3_PROTOCOL_I2C, QUPV3_MODE_FIFO, AC_HLOS, TRUE, TRUE, FALSE }, // SMB / LS1 I2C
{ QUPV3_0_SE3, QUPV3_PROTOCOL_SPI, QUPV3_MODE_FIFO, AC_HLOS, TRUE, TRUE, FALSE }, // CAN SPI
{ QUPV3_0_SE4, QUPV3_PROTOCOL_UART_4W, QUPV3_MODE_FIFO, AC_HLOS, TRUE, TRUE, FALSE }, // LS1 UART
{ QUPV3_0_SE5, QUPV3_PROTOCOL_UART_2W, QUPV3_MODE_FIFO, AC_HLOS, TRUE, FALSE, FALSE }, // Debug UART
{ QUPV3_0_SE6, QUPV3_PROTOCOL_UART_2W, QUPV3_MODE_FIFO, AC_HLOS, TRUE, TRUE, FALSE }, // WLAN UART
{ QUPV3_0_SE7, QUPV3_PROTOCOL_UART_4W, QUPV3_MODE_FIFO, AC_HLOS, TRUE, TRUE, FALSE }, // Hastings BT
{ QUPV3_1_SE0, QUPV3_PROTOCOL_SPMI, QUPV3_MODE_FIFO, AC_ADSP_Q6_ELF, TRUE, TRUE, FALSE }, // QuP SPMI
{ QUPV3_1_SE1, QUPV3_PROTOCOL_I2C, QUPV3_MODE_FIFO, AC_HLOS, TRUE, TRUE, FALSE }, // NFC I2C
{ QUPV3_1_SE2, QUPV3_PROTOCOL_I2C, QUPV3_MODE_FIFO, AC_HLOS, TRUE, TRUE, FALSE }, // HDMI OUT for VIDEOIOBoard
{ QUPV3_1_SE3, QUPV3_PROTOCOL_SPI, QUPV3_MODE_FIFO, AC_HLOS, FALSE, TRUE, TRUE }, // LS1 SPI
{ QUPV3_1_SE4, QUPV3_PROTOCOL_SPI, QUPV3_MODE_GSI, AC_TZ, FALSE, TRUE, TRUE }, // SPI -NFC ESE
{ QUPV3_1_SE5, QUPV3_PROTOCOL_I2C, QUPV3_MODE_GSI, AC_HLOS, FALSE, TRUE, FALSE}, // Legacy Touch
{ QUPV3_1_SE6, QUPV3_PROTOCOL_SPI, QUPV3_MODE_GSI, AC_HLOS, FALSE, TRUE, FALSE}, // FP
/*QUPV3_1_SE7*/
};Copy to clipboard
### QUP v3 serial engine access list description
The following variables are passed into the
`QUPv3_se_security_permissions_type` structure.
Table : Security permission variables for QUP v3
| Variables | Description |
| --- | --- |
| `PeriphID` | Serial engine peripheral to configure and assign. |
| `ProtocolID` | Macro of the required protocol. |
| `Mode` | Macro of FIFO/GSI/DMA modes. |
| `NsOwner` | Holds a macro of the image that needs access. |
| `bAllowFifo` | The boolean flag is set to `True` if the mode is
`FIFO`, else the flag is set to
`False`. |
| `bLoad` | The boolean flag value is set to `True` to load
the protocol firmware. |
| `bModExcl` | This flag is exclusively for TrustZone. It is set to
`True` when `NsOwner` is AC\_TZ. |
For more information on this macro,
see settings/buses/qup\_accesscontrol/qupv3/interface/QupACCommonIds.h.
## QUP v3 firmware status verification
Source: [https://docs.qualcomm.com/doc/80-70015-8/topic/references.html](https://docs.qualcomm.com/doc/80-70015-8/topic/references.html)
For serial engines to work, the QUP firmware must be flashed correctly. The firmware is
delivered through the metabuild at
`common/core_qupv3fw//qupv3fw.elf`. You can verify the
firmware status by checking `GENI_FW_REVISION_RO (0xa8c068)`. For
example, identify the register in the kernel log for the `0000ffff`
value. In the following log, the `0000ffff` error indicates that the
firmware is not flashed
correctly.
0a8c068: 0000ffff //Invalid firmware or firmware not loaded
00a80068: 00000126 //SPI
00a88068: 00000338 //I2C
Copy to clipboard
Modify the `QUPAC_Access.c` file configuration only if you intend to use a
protocol different from the default configuration.
The following sample log is displayed when configurations do not match after loading.
msm_geni_serial 898000.qcom,qup_uart:msm_geni_serial_startup: Invalid FW
255 loadedCopy to clipboard
## Related documents
Source: [https://docs.qualcomm.com/doc/80-70015-8/topic/references.html](https://docs.qualcomm.com/doc/80-70015-8/topic/references.html)
| Title | Resource |
| --- | --- |
| **Qualcomm Technologies, Inc.** | **Qualcomm Technologies, Inc.** |
| Secure shell | [https://docs.qualcomm.com/bundle/publicresource/topics/80-70015-254/how_to.html#how-to-ssh-](https://docs.qualcomm.com/bundle/publicresource/topics/80-70015-254/how_to.html#how-to-ssh-) |
| QDTE | [https://docs.qualcomm.com/bundle/publicresource/topics/80-70015-4/qdte-tools.html](https://docs.qualcomm.com/bundle/publicresource/topics/80-70015-4/qdte-tools.html) |
| **Resources** | **Resources** |
| PCI bus subsystem | [https://www.kernel.org/doc/html/latest/PCI/index.html](https://www.kernel.org/doc/html/latest/PCI/index.html) |
| Linux user space examples | [https://github.com/Digilent/linux-userspace-examples/tree/master/uart_example_linux/src](https://github.com/Digilent/linux-userspace-examples/tree/master/uart_example_linux/src) |
| DTSI configuration examples | [https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts](https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts) |
| Test tools and methods for the UART serial interface driver | [https://docs.kernel.org/admin-guide/serial-console.html](https://docs.kernel.org/admin-guide/serial-console.html) |
| UART Linux APIs | [https://github.com/torvalds/linux/blob/master/include/linux/tty.h](https://github.com/torvalds/linux/blob/master/include/linux/tty.h) |
| UART upstream device tree reference | [https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/sc7280.dtsi](https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/sc7280.dtsi) |
| Qualcomm Robotics RB3 Gen 2 Development Kit device tree node | [https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts](https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts) |
| SPI samples | [https://github.com/Digilent/linux-userspace-examples/tree/master](https://github.com/Digilent/linux-userspace-examples/tree/master) |
| SPI Linux APIs | |
| SPI kernel tools | [https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/tools/spi](https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/tools/spi) |
| SPI upstream device tree reference | [https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/sc7280.dtsi](https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/sc7280.dtsi) |
| I2C samples | |
| I2C Linux APIs | |
| I2C upstream kernel test applications and I2C tool | [https://layers.openembedded.org/layerindex/recipe/27859/](https://layers.openembedded.org/layerindex/recipe/27859/) |
| I2C upstream device tree reference | [https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/sc7280.dtsi](https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/sc7280.dtsi) |
| PCIe device initialization and enumeration process | [https://www.kernel.org/doc/html/latest/PCI/index.html](https://www.kernel.org/doc/html/latest/PCI/index.html) |
| PCIe framework and client driver PCIe registrations | [https://www.kernel.org/doc/html/latest/PCI/index.html](https://www.kernel.org/doc/html/latest/PCI/index.html) |
| Add MSI groups supported for a PCIe instance | [https://lore.kernel.org/linux-arm-msm/f1168212-bc6e-4570-869c-2870d6f248ad@linaro.org/T/](https://lore.kernel.org/linux-arm-msm/f1168212-bc6e-4570-869c-2870d6f248ad@linaro.org/T/) |
| PCIe debugging | [https://pcisig.com/specifications](https://pcisig.com/specifications) |
| PCIe upstream device tree reference | |
| USB `Qscratch` wrapper driver | [https://github.com/torvalds/linux/blob/master/drivers/usb/dwc3/dwc3-qcom.c](https://github.com/torvalds/linux/blob/master/drivers/usb/dwc3/dwc3-qcom.c) |
| Controller core driver | [https://github.com/torvalds/linux/blob/master/drivers/usb/dwc3/core.c](https://github.com/torvalds/linux/blob/master/drivers/usb/dwc3/core.c) |
| USB software interface drivers for Type-C connector | |
| LPM support | [https://lore.kernel.org/all/20231017131851.8299-1-quic_kriskura@quicinc.com/](https://lore.kernel.org/all/20231017131851.8299-1-quic_kriskura@quicinc.com/) |
| USB DW3C driver | [https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/usb/dwc3/dwc3-qcom.c?h=v6.6.2](https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/usb/dwc3/dwc3-qcom.c?h=v6.6.2) |
| Qualcomm Synopsys femto PHY | [https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c?h=v6.6.2](https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c?h=v6.6.2) |
| QMP DisplayPort combo PHY | [https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/phy/qualcomm/phy-qcom-qmp-combo.c?h=v6.6.2](https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/phy/qualcomm/phy-qcom-qmp-combo.c?h=v6.6.2) |
| USB ADB | [https://developer.android.com/tools/adb](https://developer.android.com/tools/adb) |
| `f_fs.c` | [https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/usb/gadget/function/f_fs.c?h=v6.6.2](https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/usb/gadget/function/f_fs.c?h=v6.6.2) |
| Mass storage | [https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/usb/gadget/function/f_mass_storage.c?h=v6.6.2](https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/usb/gadget/function/f_mass_storage.c?h=v6.6.2) |
| Platform tools (adb/fastboot) | [https://developer.android.com/tools/releases/platform-tools](https://developer.android.com/tools/releases/platform-tools) |
| UVC LibUVC | |
| UVC gadget | [https://github.com/wlhe/uvc-gadget](https://github.com/wlhe/uvc-gadget) |
| UVC streamer | [https://github.com/bsapundzhiev/uvc-streamer](https://github.com/bsapundzhiev/uvc-streamer) |
| UVC Video4Linux (v4l2-utils) | [https://linuxtv.org/downloads/v4l-dvb-apis/driver-api/v4l2-core.html](https://linuxtv.org/downloads/v4l-dvb-apis/driver-api/v4l2-core.html) |
| USB upstream device tree reference | [https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/sc7280.dtsi](https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/sc7280.dtsi) |
| Qualcomm Linux chip product device-tree node | [https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts](https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts) |
| RPM changes in the USB driver and other examples | [https://patchwork.kernel.org/project/linux-usb/list/?series=793939&archive=both](https://patchwork.kernel.org/project/linux-usb/list/?series=793939&archive=both) |
| Flatten a device tree | |
## Acronyms and terms
Source: [https://docs.qualcomm.com/doc/80-70015-8/topic/references.html](https://docs.qualcomm.com/doc/80-70015-8/topic/references.html)
| Acronym or term | Definition |
| --- | --- |
| aDSP | Application digital signal processor |
| ADB | Android debug bridge |
| ASPM | Active state power management |
| BDF | Bus device function |
| CAN | Controller area network |
| CRC | Cyclic redundancy check |
| CTS | Clear to send |
| DLLP | Data link layer packet |
| DTS | Device tree source |
| ECRC | End-to-end CRC |
| EE | Execution environment |
| ESE | Execute secure environment |
| FP | Fingerprint |
| GPIO | General-purpose input/output |
| GSI | Generic software interface |
| HID | Human interface device |
| I/O | Input/output |
| I2C | Interintegrated circuit |
| I3C | Improved interintegrated circuit |
| LSP | List processor |
| MS | Mass storage |
| MSI | Message signaled interrupt |
| NCM | Network control modem |
| NFC | Near-field communication |
| PCIe | Peripheral component interconnect express |
| QoS | Quality of service |
| QIM | Qualcomm intelligent multimedia |
| RTS | Request to send |
| SCL | Serial clock line |
| SDK | Software development kit |
| SDL | Serial data line |
| SE | Serial engine |
| SLPI | Sensor low-power island |
| SPI | Serial peripheral interface |
| SPMI | System power management interface |
| SSC | Snapdragon sensor core |
| TC | Traffic class |
| TLP | Transaction layer packet |
| TZ | TrustZone |
| UEFI | Unified extensible firmware interface |
| UAC | USB audio class |
| UART | Universal asynchronous receiver-transmitter |
| UCSI | USB Type-C connector system software interface |
| V4L2 | Video4Linux2 |
| VC | Virtual channel |
| Yavta | Yet another V4L2 test application |
Last Published: Oct 15, 2024
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