VBackground-1

# UART Source: [https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html](https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html) UART devices transmit data asynchronously. Hence, a clock signal does not synchronize the output of bits from the transmitting UART to the sampling of bits by the receiving UART. Instead of a clock signal, the transmitting UART adds start and stop bits to the data packet being transferred. These bits define the beginning and end of the data packet, so the receiving UART knows when to start reading the bits. When the receiving UART detects a start bit, it starts to read the incoming bits at a specific frequency known as the baud rate. Figure : Data transfer between two UART devices The parameters that determine successful transmission are as follows: - Baud rate - Start bit - Stop bit - Parity bit - Data bits - Flow control The following figure shows a sample UART data packet. Figure : UART data packet ## UART features Source: [https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html](https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html) This section describes the UART transfer modes for applications that use low-speed and high-speed transfer modes (FIFO/DMA). Table : UART transfer modes | Subsystem | Transfer mode | Description | | :--- | :--- | :--- | | Linux |

FIFO (low speed)

CPU DMA (high speed)

Supports baud rates from 300 bps up to 4 Mbps.

FIFO mode transfers data between its Rx/Tx buffers and system
memory

DMA mode transfers data between its Rx/Tx buffers and system
memory. Better performance is achieved with high-speed UART
drivers supporting higher baud rates and bigger data packages.
For example, the Bluetooth wireless technology connectivity
module.

| | Boot | FIFO |

Rx/Tx 5 bits to 8 bits per character.

Supports a maximum baud rate of 115200.

| | aDSP | FIFO |

Rx/Tx 5 bits to 8 bits per character.

Supported baud rates: 115200, 230400, 460800, 921600, 1000000,
3000000, and 6000000.

| ## UART interface Source: [https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html](https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html) This section provides the paths of UART driver configurations for the different subsystems. Table : UART interface: Linux | File type | Description | | --- | --- | | Device tree source | For device tree configurations of QUP v3 serial engine interface
device nodes, and low and high-speed UART device nodes, see the
following DTSI files.

QCS6490 and QCS5430: https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/sc7280.dtsi

QCS9075: https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/sa8775p.dtsi

| | `Pinctrl` settings | For device tree properties of GPIO settings for the QUP v3 serial
engine interface for UART device nodes, see the following file
paths.

The pin control table for the corresponding QUP v3 serial
engine is
at <workspace_path_of_LINUX_kernel_image>/sources/kernel/kernel_platform/kernel/arch/arm64/boot/dts/qcom/<chipset>.dts.

For DTSI configuration examples to override the chip
product, see the following DTSI files.
- QCS6490 and QCS5430: https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/sc7280.dtsi
- QCS9075: https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/sa8775p.dtsi

| | TrustZone settings | For TrustZone access control settings to load the QUP v3 serial
engine UART firmware for different subsystems,
see /firmware/qualcomm-linux-spf-1-0\_ap\_standard\_oem\_nomodem/TZ.XF.5.0/trustzone\_images/core/settings/buses/qup\_accesscontrol/qupv3/config/<chipset>/QUPAC\_Access.c. | Table : UART interface: Boot (UEFI-only) | File type | Description | | --- | --- | | QUP v3 serial engine configuration | For QUP v3 serial engine configurations in the boot subsystem to
enable the UART serial engine,
see /firmware/qualcomm-linux-spf-1-0\_ap\_standard\_oem\_nomodem/BOOT.MXF.1.0.c1/boot\_images/boot/QcomPkg/SocPkg/<chipset>/Settings/UART/UartSettings.c | | TrustZone settings | For TrustZone access control settings in QUP v3 serial engine
firmware to configure UART for different subsystems,
see /firmware/qualcomm-linux-spf-1-0\_ap\_standard\_oem\_nomodem/TZ.XF.5.0/trustzone\_images/core/settings/buses/qup\_accesscontrol/qupv3/config/<chipset>/QUPAC\_Access.c | Table : UART interface: aDSP/SLPI | File type | Description | | --- | --- | | QUP v3 serial engine configuration | For QUP v3 serial engine configuration settings in the aDSP
subsystem to enable UART, see the following files.

/firmware/qualcomm-linux-spf-1-0_ap_standard_oem_nomodem/ADSP.HT.5.5.c8/adsp_proc/core/settings/buses/qup_common/config/<chipset>/adsp/ssc/qup_devcfg.c

/firmware/qualcomm-linux-spf-1-0_ap_standard_oem_nomodem/ADSP.HT.5.5.c8/adsp_proc/core/settings/buses/qup_fw/config/<chipset>/fw_devcfg.c

| | Firmware configuration settings | For QUP v3 serial engine firmware settings to configure UART in
aDSP software, see the following files.

/firmware/qualcomm-linux-spf-1-0_ap_standard_oem_nomodem/ADSP.HT.5.5.c8/adsp_proc/core/settings/buses/qup_fw/config/<chipset>/fw_devcfg.c

/firmware/qualcomm-linux-spf-1-0_ap_standard_oem_nomodem/ADSP.HT.5.5.c8/adsp_proc/core/settings/buses/qup_fw/config/<chipset>/fw_devcfg.xml

| ### UART APIs Source: [https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html](https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html) UART APIs for the following subsystems are listed in this section. - Linux: [https://github.com/torvalds/linux/blob/master/include/linux/tty.h](https://github.com/torvalds/linux/blob/master/include/linux/tty.h) - Boot: QcomPkg/Include/HSUart.h - aDSP: adsp\_proc/core/api/buses/uart.h ## UART software Source: [https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html](https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html) This section provides information on the UART device tree configuration, and documentation for the device nodes. ### Linux For information on Kernel device instances, see [https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/serial/qcom%2Cserial-geni-qcom.yaml](https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/serial/qcom%2Cserial-geni-qcom.yaml). For information on the UART driver files, see [https://github.com/torvalds/linux/blob/master/drivers/tty/serial/qcom_geni_serial.c](https://github.com/torvalds/linux/blob/master/drivers/tty/serial/qcom_geni_serial.c) uart7: serial@99c000 { /* Manufacturer model of serial driver */ compatible = "qcom,geni-uart"; /* SE address and size */ reg = <0 0x0099c000 0 0x4000>; /*Clocks for SE */ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; clock-names = "se"; /* pinctrl setting */ pinctrl-names = "default"; pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; interrupts = ; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; /* To enable QUPV3 serial engine instance for UART protocol, change Status to OK */ status = "disabled"; }; }Copy to clipboard For configuration settings of the serial engine GPIOs, see the following DTSI files. - QCS6490 and QCS5430: [https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/sc7280.dtsi](https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/sc7280.dtsi) - QCS9075: [https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/sa8775p.dtsi](https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/sa8775p.dtsi) qup_uart7_cts: qup-uart7-cts-state { pins = "gpio28"; function = "qup07"; }; qup_uart7_rts: qup-uart7-rts-state { pins = "gpio29"; function = "qup07"; }; qup_uart7_tx: qup-uart7-tx-state { pins = "gpio30"; function = "qup07"; }; qup_uart7_rx: qup-uart7-rx-state { pins = "gpio31"; function = "qup07"; }; Copy to clipboard The TrustZone configurations must be aligned in the QUPAC\_Access.c file to ensure that the GPIO/QUP v3 can be used. You can access the TrustZone images at /firmware/qualcomm-linux-spf-1-0\_ap\_standard\_oem\_nomodem/TZ.XF.5.0/trustzone\_images/core/settings/buses/qup\_accesscontrol/qupv3/config/<chipset>/QUPAC\_Access.c. Modify the required settings or see the default settings assigned for particular instances of the QUP v3 serial engine. QUP v3 supports both 4-wire UART with flow-control enabled, and 2-wire UART without flow control enabled. The following example for TrustZone access controls entry for both. The QUP v3 serial engine configurations to enable the UART protocol are as follows: - Default configuration enabled for SE7 as HS UART { QUPV3_0_SE7, QUPV3_PROTOCOL_UART_4W, QUPV3_MODE_FIFO, AC_HLOS, TRUE, TRUE, FALSE }, Copy to clipboard - 2-wire UART configuration for SE5 uart5: serial@994000 { compatible = "qcom,geni-uart"; reg = <0 0x00994000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>; interrupts = ; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; };Copy to clipboard { QUPV3_0_SE5, QUPV3_PROTOCOL_UART_2W, QUPV3_MODE_FIFO, AC_HLOS, TRUE, FALSE, FALSE },Copy to clipboard ### Boot The QUP v3 serial engine can be configured to UART in boot using the /firmware/qualcomm-linux-spf-1-0\_ap\_standard\_oem\_nomodem/BOOT.MXF.1.0.c1/boot\_images/boot/QcomPkg/SocPkg/<chipset>/Settings/UART/UartSettings.c file. UART_PROPERTIES devices = { // MAIN_PORT 0x00994000, // Serial Engine Base address 0x009C0000,// qup_common base address 0x2001c161, // GPIO TX pin Config 0x2000c171, // GPIO RX Pin Config 0, // gpio_cts_config 0, // gpio_rfr_config 0, // clock_id_index (void*)0, // bus_clock_id (void*)CLK_QUPV3_WRAP0_S5, // core_clock_id 0, // irq number not used 0, //TCSR base 0, // TCSR offset 0 // TCSR value }; Copy to clipboard **GPIO configuration** The GPIO configuration is listed in the following table. Table : UART GPIO configuration | Bits | Parameters | | :---: | --- | | [0:3] | GPIO function | | [4:13] | GPIO number | | [14] | Direction | | [15:17] | Pull type | | [18:21] | Drive strength | You must configure each GPIO based on the following bit fields. /* | RESERVED | GPIO NUM | DRIVE | FUNC | PULL | DIR | ------------------------------------------------------------------------- | 0000 | 0000 | 0001 | 1110 | 0001 | 0001 | 0010 | 0001 | ------------------------------------------------------------------------- */Copy to clipboard ### aDSP The firmware loads SSC QUP during the bootup sequence of the aDSP subsystem. Hence, the configuration file is present in the aDSP build at /firmware/qualcomm-linux-spf-1-0\_ap\_standard\_oem\_nomodem/ADSP.HT.5.5.c8/adsp\_proc/core/settings/buses/qup\_fw/config/<chipset>/fw\_devcfg.c. The following configuration is a sample of SSC QUP SE5/6 loaded with the UART firmware in the FIFO mode. offset, protocol, mode, load_fw, dfs_mode se_cfg se0_cfg = { 0x80000, SE_PROTOCOL_I3C, GSI, TRUE, TRUE }; se_cfg se1_cfg = { 0x84000, SE_PROTOCOL_I2C, GSI, TRUE, TRUE }; se_cfg se2_cfg = { 0x88000, SE_PROTOCOL_I2C, GSI, TRUE, TRUE }; se_cfg se3_cfg = { 0x8C000, SE_PROTOCOL_I2C, GSI, FALSE, TRUE }; se_cfg se4_cfg = { 0x90000, SE_PROTOCOL_SPI, GSI, TRUE, TRUE }; se_cfg se5_cfg = { 0x94000, SE_PROTOCOL_UART, FIFO, TRUE,FALSE }; se_cfg se6_cfg = { 0x98000, SE_PROTOCOL_UART, FIFO, TRUE,FALSE }; Copy to clipboard GPIO configuration: Each serial engine in the QUP common driver is configured with the default GPIO configuration per protocol in the chip product-specific configurations. The QUP v3 common driver picks the GPIO configuration according to the protocol loaded in the serial engine from /firmware/qualcomm-linux-spf-1-0\_ap\_standard\_oem\_nomodem/ADSP.HT.5.5.c8/adsp\_proc/core/settings/buses/qup\_common/config/<chipset>/adsp/ssc/qup\_instance\_mapping.c. The default GPIO configuration can be overwritten as follows. { .instance_id = 6 , //Instance ID .qup = QUP_SSC, //QUP Type .se_index = 5, //SE ID .se_data = NULL, //devcfg_map .protocol_io_cfg = { TLMM_MAP(TLMM_GPIO_KEEPER ,TLMM_GPIO_2MA,TLMM_GPIO_KEEPER ), //SLEEP CFG TLMM_MAP(TLMM_GPIO_NO_PULL,TLMM_GPIO_6MA,TLMM_GPIO_KEEPER ), //SPI CFG TLMM_MAP(TLMM_GPIO_NO_PULL,TLMM_GPIO_2MA,TLMM_GPIO_NO_PULL), //UART CFG TLMM_MAP(TLMM_GPIO_PULL_UP,TLMM_GPIO_2MA,TLMM_GPIO_NO_PULL), //I2C CFG TLMM_MAP(TLMM_GPIO_PULL_UP,TLMM_GPIO_2MA,TLMM_GPIO_KEEPER ) //I3C CFG }, .se_exclusive = TRUE, } Copy to clipboard TLMM\_MAP is a macro to initialize the active and sleep state GPIO configurations. For example, sample usage of the TLMM\_MAP macro. TLMM_MAP (active state pull type, drive strength, sleep state pull type)Copy to clipboard ## UART tools Source: [https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html](https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html) This section provides information on various test tools and methods for the UART serial interface driver to confirm the UART data transfers. ### Linux For more details, see [https://docs.kernel.org/admin-guide/serial-console.html](https://docs.kernel.org/admin-guide/serial-console.html). ## UART configuration Source: [https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html](https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html) This section provides information on how to enable UART in the kernel. ### Linux The following driver kernel configurations are required to support the UART interface. - UART driver: [https://github.com/torvalds/linux/blob/master/drivers/tty/serial/qcom_geni_serial.c](https://github.com/torvalds/linux/blob/master/drivers/tty/serial/qcom_geni_serial.c) - Kernel `defconfig` file path: <workspace\_path\_of\_LINUX\_kernel\_image>/sources/kernel /kernel\_platform/kernel/arch/arm64/configs/qcom\_defconfig The following kernel configurations are to be enabled. - `CONFIG_QCOM_GENI_SE=y` - `CONFIG_SERIAL_QCOM_GENI=y` To enable a serial node for the loopback validation, apply the following patch to the /arch/arm64/boot/dts/qcom/<chipset>.dtsi file. --- a/arch/arm64/boot/dts/qcom/.dtsi +++ b/arch/arm64/boot/dts/qcom/.dtsi @@ -70,6 +70,7 @@ spi13 = &spi13; spi14 = &spi14; spi15 = &spi15; + serial1 = &uart7; }; + +&uart7 { + status = "ok"; +}; Copy to clipboard Note: You should compile the kernel configuration and device tree changes. After compilation, you can load the images to the device to verify the interface. For information on interface verification, see the [UART verification](https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html#uart_verification) section. ### Boot/aDSP For customizations, see the [UART software](https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html#uart_software) section. ## UART customization Source: [https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html](https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html) For information on customizing UART software, see [QUP v3 access control customization](https://docs.qualcomm.com/doc/80-70015-8/topic/references.html#customize-access-control-of-qup). ## UART verification Source: [https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html](https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html) This section describes the validation procedure for the UART drivers, and the test results for the Qualcomm drivers. ### Linux To enable the UART nodes, do the following and compile the kernel configuration. 1. To change the UART status to OKand aliases to the specific UART node, edit the following DTSI files. - QCS6490 and QCS5430: [https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/sc7280.dtsi](https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/sc7280.dtsi) - QCS9075: [https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/sa8775p.dtsi](https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/sa8775p.dtsi) Note: Enable the SSH shell or serial console to run the commands and display the output in the SSH shell (console) window. aliases { i2c0 = &i2c0; spi15 = &spi15; ++serial1 = &uart7; }; uart7: serial@99c000 { compatible = "qcom,geni-uart"; reg = <0 0x0099c000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; interrupts = ; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; ++status = "ok"; };Copy to clipboard 2. Disable the `if` condition in the qcom\_geni\_serial.c at [https://github.com/torvalds/linux/blob/master/drivers/tty/serial/qcom_geni_serial.c](https://github.com/torvalds/linux/blob/master/drivers/tty/serial/qcom_geni_serial.c) file for the loopback test. //if (mctrl & TIOCM_LOOP) // Disabling the if condition for loopback test port->loopback = RX_TX_CTS_RTS_SORTED;Copy to clipboard To validate the QUP v3 UART registration functionality in the Linux kernel, ensure that the UART is correctly registered with the TTY stack. 1. Disable the UART default use case in the following DTSI files. - QCS6490 and QCS5430: [https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/sc7280.dtsi](https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/sc7280.dtsi) - QCS9075: [https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/sa8775p.dtsi](https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/sa8775p.dtsi) bluetooth: bluetooth { ++ status = "disabled"; Copy to clipboard The following output is displayed. ls /dev/ttyHS1 /dev/ttyHS1 dmesg | grep ttyH [ 3.355487] 99c000.serial: ttyHS1 at MMIO 0x99c000 (irq = 137, base_baud = 0) is a MSMCopy to clipboard 2. To verify the UART driver, do the following: 1. Open the SSH shell in permissive mode. For more information on how to run SSH, see the [Use SSH](https://docs.qualcomm.com/bundle/publicresource/topics/80-70015-254/how_to.html#use-ssh) section. 2. Register the UART. ls /dev/ttyHS*Copy to clipboard The following is a sample output. ls /dev/ttyHS* /dev/ttyHS1 Copy to clipboard Map the `ttyHS1` port according to the aliases added for the `serial1 = &uart7` and enable the serial engine. The UART devices registered in the kernel are listed. The UART driver follows the test sequence to enable loopback. After enabling the UART node in the DUT, run the following commands to verify that the UART instance is enabled in the DTSI file. Note: Open two SSH shells or terminals to write and read the data for the UART loopback. 1. Open the SSH shell in permissive mode. For more information on how to run SSH, see the [Use SSH](https://docs.qualcomm.com/bundle/publicresource/topics/80-70015-254/how_to.html#use-ssh) section. 2. Transfer data with the `echo` command. echo "This Document Is Very Much Helpful" > /dev/ttyHS1Copy to clipboard 3. Read data in the UART device node. cat /dev/ttyHS1Copy to clipboard ## UART debugging Source: [https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html](https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html) This section provides information about enabling the debug logs in the UART software driver. ### Linux UART driver logging is enabled through the dynamic debugging method. Enable `CONFIG_DYNAMIC_DEBUG` in <workspace\_path\_of\_LINUX\_kernel\_image>/sources/kernel/kernel\_platform/kernel/arch/arm64/configs/qcom\_defconfig to support the dynamic debugging for kernel drivers. To enable and view the UART driver logs in the kernel logs (`dmesg`), run the following command. mount -t debugfs none /sys/kernel/debug echo -n "file qcom_geni_serial.c +p" > /sys/kernel/debug/dynamic_debug/control echo -n "file qcom-geni-se.c +p" > /sys/kernel/debug/dynamic_debug/control echo -n "file serial_core.c +p" > /sys/kernel/debug/dynamic_debug/control echo -n "file gpi.c +p" > /sys/kernel/debug/dynamic_debug/control Copy to clipboard ## UART examples Source: [https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html](https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html) For information on the upstream device tree reference, see the following DTSI files. - QCS6490 and QCS5430: [https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/sc7280.dtsi](https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/sc7280.dtsi) - QCS9075: [https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/sa8775p.dtsi](https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/sa8775p.dtsi) For information on the Qualcomm Linux chip product device-tree node, see the following DTSI files. - QCS6490 and QCS5430: [https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts](https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts) - QCS9075: [https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/sa8775p.dtsi](https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/sa8775p.dtsi) Last Published: Oct 15, 2024 [Previous Topic Getting started](https://docs.qualcomm.com/bundle/publicresource/80-70015-8/topics/get-started.md) [Next Topic SPI](https://docs.qualcomm.com/bundle/publicresource/80-70015-8/topics/spi.md)