VBackground-1

# Architecture Tab QCS6490/QCS5430 Tab QCS9100/QCS9075 The following figure shows the architecture and its components involved in communicating data over Ethernet on RB3 Gen 2 Development Kit. Ethernet architecture on RB3 Gen 2 Development Kit The following table describes the components of Ethernet architecture. | Component | Description | | --- | --- | | Application processor subsystem (APSS) | Runs on a Linux-based operating system. | | Ethernet driver |

A software driver in the Linux kernel.

Provides data connectivity over a wired Ethernet interface.

| | PHY driver |

A low-level driver dedicated to manage the Ethernet physical layer.

Implements a software statemachine required to handle the lifecycle of PHY, from initialization to link establishment.

Interacts with an underlying management data input/output (MDIO) to access the PHY register and perform operations such as detecting alive and/or linked PHYs.

| | Ethernet hardware (RB3 Gen 2 Development Kit) |

Both QEP and AQR PHYs are validated on RB3 Gen 2 Development Kit.

QEP PHY for 2.5 GbE is available by default on SGMII interface. It is enabled and verified on a 1 x QEP8121 IX connector.

USB2ETH interface with 1 GbE is available by default and verified on RJ45 connector.

AQR PHY for 10 GbE is optional and may not be available on the development kit. If available, it is verified on a 1 x AQR113C IX connector.

Note

The sample outputs shown in the subsequent sections are based on the verification of QEP8121 PHY, USB2ETH, and AQR113C PHY.

To bring up hardware configurations other than the configuration provided by Qualcomm, see Bring up alternate hardware enablement.

For information on how to configure USB2ETH, see Configure Ethernet with RJ45

| The following figure shows both standard and DPDK architectures, and the components involved in communicating data over Ethernet on the IQ-9 Beta EVK. Ethernet architecture on IQ-9 Beta EVK The following table describes the components on Ethernet architecture. | Component | Description | | --- | --- | | Application processor subsystem (APSS) | Runs on a Linux-based operating system. | | Ethernet driver |

A software driver in the Linux kernel.

Provides data connectivity over a wired Ethernet interface.

| | PHY driver |

A low-level driver dedicated to manage the Ethernet physical layer.

Implements a software statemachine required to handle the lifecycle of PHY, from initialization to link establishment.

Interacts with an underlying management data input/output (MDIO) to access the PHY register and perform operations such as detecting alive and/or linked PHYs.

| | Ethernet hardware (IQ-9 Beta EVK) |

AQR PHYs are validated on IQ-9 Beta EVK.

2 x AQR115 PHY for 2.5 GbE are available by default.

Both AQR115 PHYs are enabled by RJ45 connectors.

DPDK is supported on QCS9100 and works only with Intel® Ethernet Converged Network Adapter X550-T2.

Note

Intel® Ethernet Converged Network Adapter X550-T2 is optional and may not be available on the IQ-9 Beta EVK. | Last Published: Dec 24, 2024 [Previous Topic Features](https://docs.qualcomm.com/bundle/publicresource/80-70017-26/topics/features.md) [Next Topic Tools](https://docs.qualcomm.com/bundle/publicresource/80-70017-26/topics/tools.md)