# I3C
Source: [https://docs.qualcomm.com/doc/80-70018-8/topic/i3c.html](https://docs.qualcomm.com/doc/80-70018-8/topic/i3c.html)
The improved interintegrated circuit (I3C) interface has been developed to provide a
fast, low-cost, low-power, 2-wire digital interface for connected I3C devices. The I3C
interface is intended to improve upon the features of the I2C interface, preserving
backward compatibility.
The 2-wire serial interface supports up to 12.5 MHz. Legacy I2C devices co-exist on the
same bus. The I3C bus supports in‑band support, hot join, synchronous timing supports
and asynchronous time stamping. During the write operation, the transition bit is of
8‑bit data parity. During read, the controller uses the transition bit to either proceed
with the next data or abort the read.
The data phase can be either push-pull or open-drain, based on the I3C capability of the
device (for mixed bus, the I3C controller can address the I2C target).
- The address followed by the START condition is open-drain (arbitration
phase).
- The address followed by a repeated START condition is push-pull.
The following figure illustrates the I3C hardware and software entities.
Figure : I3C block diagram
The main features of the I3C architecture are as follows:
- I3C controller driver software: software-privileged entity, capable of
enumeration and bus configuration.
- I3C client software: software entities that use the I3C bus for read/write to
devices.
### I3C packet frame structure
A frame begins with START, command (8), data (8), transition (1), and STOP.
Figure : I3C packet frame
Where,
- ACK: Acknowledge (SDA low)
- S: Start condition
- Sr: Repeat start condition
- P: Stop condition
- T: Transition bit alternative to ACK/NACK
Figure : I3C sequence
### I3C bus initialization
The I3C bus initialization procedure is as follows:
1. The I3C controller driver software initializes the I3C controller (firmware
and configuration settings).
2. The I3C controller driver software reads the I3C configuration and the
device database, including:
- List of I2C static address devices.
- List of I3C static address devices.
- List of expected I3C dynamic devices: vendor ID, device ID,
predefined dynamic address, and associated drivers.
- Optional hot-join allowed devices (vendor ID, device ID, and
predefined address).
3. Using the I3C controller software, the driver enumerates the devices on the
bus (set local addresses).
4. The I3C controller driver software writes an I3C controller with the
required devices and the bus characteristic information:
- Operation frequency
- Pure/legacy I2C mode
- SDR/HDR enable/disable (and types)
- IBI capable devices and expected data bytes
5. The I3C client software stack receives the following information about the
I3C configuration and device database.
- List of I2C, static address devices.
- List of I3C, static address devices.
- List of expected I3C dynamic devices: vendor ID, device ID,
predefined dynamic address, and associated drivers.
- Optional hot-join allowed devices (vendor ID, device ID, and
predefined address).
## I3C features
Source: [https://docs.qualcomm.com/doc/80-70018-8/topic/i3c.html](https://docs.qualcomm.com/doc/80-70018-8/topic/i3c.html)
The aDSP/SDC I3C subsystem supports the following features.
- Address phase at frequency 400 kHz.
- Data phase at frequency 12,500 kHz.
- Backward compatibility with legacy I2C.
- Dynamic addressing of targets.
- Single data rate (SDR) mode.
- CCC commands according to the MIPI I3C specification
## I3C interface
Source: [https://docs.qualcomm.com/doc/80-70018-8/topic/i3c.html](https://docs.qualcomm.com/doc/80-70018-8/topic/i3c.html)
I3C use cases in the aDSP/SLPI software support sensor device communication.
Note: I3C doesn't support Linux use cases.
The software driver
and the configuration support for the I3C functionality for device communication are
listed in the following table.
Table : aDSP/SLPI/SDC
| File type | Description |
| --- | --- |
| QUP v3 serial engine configuration |
|
## I3C software
Source: [https://docs.qualcomm.com/doc/80-70018-8/topic/i3c.html](https://docs.qualcomm.com/doc/80-70018-8/topic/i3c.html)
The I3C firmware for the QUP v3 serial engine is loaded with SSC QUP during the bootup
sequence. The configuration file is present in the aDSP build. The source code path to
enable the I3C configuration for a specific QUP v3 serial engine instance is at /firmware/qualcomm-linux-spf-1-0\_ap\_standard\_oem\_nomodem/ADSP.HT.5.5.c8/adsp\_proc/core/settings/buses/qup\_fw/config/<chipset>/fw\_devcfg.c
and /firmware/qualcomm-linux-spf-1-0\_ap\_standard\_oem\_nomodem/ADSP.HT.5.5.c8/adsp\_proc/core/settings/buses/qup\_fw/config/<chipset>/fw\_devcfg.xml.
Sample of SSC QUP SE0 or SE1 loaded with the I3C firmware.
se_cfg se0_cfg = { 0x80000, SE_PROTOCOL_I3C, GSI, TRUE, TRUE };
se_cfg se1_cfg = { 0x84000, SE_PROTOCOL_I3C, GSI, TRUE, TRUE };Copy to clipboard
**GPIO configuration**: Each serial engine in the QUP common driver is configured with
the default GPIO configuration. The QUP common driver selects the GPIO configuration
according to the protocol loaded in the serial engine. The source code path for the GPIO
configuration of a specific I3C serial engine instance
is /firmware/qualcomm-linux-spf-1-0\_ap\_standard\_oem\_nomodem/ADSP.HT.5.5.c8/adsp\_proc/core/settings/buses/qup\_common/config/<chipset>/adsp/ssc/qup\_instance\_mapping.c.
The default GPIO configuration can be overwritten as follows:
{ .instance_id = 1 , //Instance ID
.qup = QUP_SSC, //QUP Type
.se_index = 0, //SE ID
.se_data = NULL, //devcfg_map
.protocol_io_cfg = {
TLMM_MAP(TLMM_GPIO_KEEPER ,TLMM_GPIO_2MA,TLMM_GPIO_KEEPER ), // SLEEP CFG
TLMM_MAP(TLMM_GPIO_NO_PULL,TLMM_GPIO_6MA,TLMM_GPIO_KEEPER ), //SPI CFG
TLMM_MAP(TLMM_GPIO_NO_PULL,TLMM_GPIO_2MA,TLMM_GPIO_NO_PULL), // UART CFG
TLMM_MAP(TLMM_GPIO_PULL_UP,TLMM_GPIO_2MA,TLMM_GPIO_NO_PULL), //I2C CFG
TLMM_MAP(TLMM_GPIO_PULL_UP,TLMM_GPIO_2MA,TLMM_GPIO_KEEPER ) //I3C CFG
},
.se_exclusive = TRUE,
}
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TLMM\_MAP is a macro to initialize the active and sleep state GPIO configurations. For
example, a sample usage of the TLMM\_MAP macro is as
follows:
TLMM_MAP (active state pull type, drive strength, sleep state pull type)Copy to clipboard
Last Published: Mar 26, 2025
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