# Ethernet architecture

The following figure shows the architecture and its components involved in communicating data over Ethernet on the reference kits.

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Ethernet architecture on reference kits

Tab QCS6490
Tab IQ-9075
Tab IQ-8275
Tab IQ-615

The following table describes the components of Ethernet architecture on QCS6490.

| Component | Description |
| --- | --- |
| Application processor subsystem (APSS) | Runs on a Linux-based operating system. |
| Ethernet driver | <ul class="simple"><br><li><p>A software driver in the Linux kernel.</p></li><br><li><p>Provides data connectivity over a wired Ethernet interface.</p></li><br></ul> |
| PHY driver | <ul class="simple"><br><li><p>A low-level driver dedicated to manage the Ethernet physical layer.</p></li><br><li><p>Implements a software state machine required to handle the lifecycle of PHY, from initialization to link establishment.</p></li><br><li><p>Interacts with an underlying management data input/output (MDIO) to access the PHY register and perform operations such as detecting alive and/or linked PHYs.</p></li><br></ul> |
| Ethernet hardware (RB3 Gen 2 Development Kit) | <ul class="simple"><br><li><p>Both QEP and AQR PHYs are validated on <a href="https://docs.qualcomm.com/bundle/publicresource/topics/80-70022-251/rb3_hardware_overview.html#mainboard-and-interposer-connectors" rel="noopener noreferrer" target="_blank" class="xref cursorpointer" onclick="Window.BookmapComponent.navigateExternalFile('https://docs.qualcomm.com/bundle/publicresource/topics/80-70022-251/rb3_hardware_overview.html#mainboard-and-interposer-connectors')">RB3 Gen 2 Development Kit</a>.</p></li><br><li><p>QEP PHY for 2.5 GbE is available by default on SGMII interface. It is enabled and verified on a 1 x QEP8121 IX connector.</p></li><br><li><p>USB2ETH interface with 1 GbE is available by default and verified on RJ45 connector.</p></li><br><li><p>AQR PHY for 10 GbE is optional and may not be available on the development kit. If available, it is verified on a 1 x AQR113C IX connector.</p></li><br></ul><br><br>Note<br><br><br>The sample outputs shown in tools for ethernet operations are based on the verification of QEP8121 PHY, USB2ETH, and AQR113C PHY.<br><br><ul class="simple"><br><li><p>To bring up hardware configurations other than the configuration provided by Qualcomm, see <a href="https://docs.qualcomm.com/doc/80-70022-26/topic/bring_up-ethernet.html#bring-up-alternate-hardware-enablement"><span class="std std-ref">Bring up alternate hardware enablement</span></a>.</p></li><br><li><p>For information on how to configure RJ45 based USB2ETH, see <a href="https://docs.qualcomm.com/bundle/publicresource/topics/80-70022-254/how_to.html#configure-ethernet-with-rj45-port" rel="noopener noreferrer" target="_blank" class="xref cursorpointer" onclick="Window.BookmapComponent.navigateExternalFile('https://docs.qualcomm.com/bundle/publicresource/topics/80-70022-254/how_to.html#configure-ethernet-with-rj45-port')">Configure Ethernet with RJ45</a></p></li><br></ul> |

The following table describes the components of Ethernet architecture on IQ-9075.

| Component | Description |
| --- | --- |
| Application processor subsystem (APSS) | Runs on a Linux-based operating system. |
| Ethernet driver | <ul class="simple"><br><li><p>A software driver in the Linux kernel.</p></li><br><li><p>Provides data connectivity over a wired Ethernet interface.</p></li><br></ul> |
| PHY driver | <ul class="simple"><br><li><p>A low-level driver dedicated to manage the Ethernet physical layer.</p></li><br><li><p>Implements a software state machine required to handle the lifecycle of PHY, from initialization to link establishment.</p></li><br><li><p>Interacts with an underlying management data input/output (MDIO) to access the PHY register and perform operations such as detecting alive and/or linked PHYs.</p></li><br></ul> |
| Ethernet hardware | 1 x QEP8121 PHY for 10/100/1000 Mbps is validated on [IQ-9075 EVK](https://docs.qualcomm.com/bundle/publicresource/topics/80-70022-261/iq9-ug-hw-overview.html#evk-ports-and-interfaces) and enabled by RJ45 connector.<br><br><br>Note<br><br><br>The IQ-9075 EVK software does not support 2.5 GbE with QEP8121. |

The following table describes the components of Ethernet architecture on IQ-8275.

| Component | Description |
| --- | --- |
| Application processor subsystem (APSS) | Runs on a Linux-based operating system. |
| Ethernet driver | <ul class="simple"><br><li><p>A software driver in the Linux kernel.</p></li><br><li><p>Provides data connectivity over a wired Ethernet interface.</p></li><br></ul> |
| PHY driver | <ul class="simple"><br><li><p>A low-level driver dedicated to manage the Ethernet physical layer.</p></li><br><li><p>Implements a software state machine required to handle the lifecycle of PHY, from initialization to link establishment.</p></li><br><li><p>Interacts with an underlying management data input/output (MDIO) to access the PHY register and perform operations such as detecting alive and/or linked PHYs.</p></li><br></ul> |
| Ethernet hardware | 1 x QEP8121 PHY for 10/100/1000 Mbps is validated on IQ-8275 EVK and enabled by RJ45 connector.<br><br><br>Note<br><br><br>The IQ-8275 EVK software does not support 2.5 GbE with QEP8121. |

The following table describes the components of Ethernet architecture on IQ-615.

| Component | Description |
| --- | --- |
| Application processor subsystem (APSS) | Runs on a Linux-based operating system. |
| Ethernet driver | <ul class="simple"><br><li><p>A software driver in the Linux kernel.</p></li><br><li><p>Provides data connectivity over a wired Ethernet interface.</p></li><br></ul> |
| PHY driver | <ul class="simple"><br><li><p>A low-level driver dedicated to manage the Ethernet physical layer.</p></li><br><li><p>Implements a software state machine required to handle the lifecycle of PHY, from initialization to link establishment.</p></li><br><li><p>Interacts with an underlying management data input/output (MDIO) to access the PHY register and perform operations such as detecting alive and/or linked PHYs.</p></li><br></ul> |
| Ethernet hardware (IQ-615 EVK) | 1 x KSZ9031RNX PHY for 10/100/1000 Mbps is validated on IQ-615 EVK and enabled by RJ45 connector. |

Last Published: Nov 10, 2025

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