# Configure UFS Linux kernel device tree

The SoC DTSI node specifies register address space, clocks, interrupts, and reset information. The platform DTSI node specifies power supply, voltage, and current levels.
The `Ufs_mem_hc` node that describes the on-chip UFS device host controller is typically within the SoC DTSI file. For example, `<workspace_root_path>/sources/kernel/kernel_platform/kernel/arch/arm64/boot/dts/qcom/sc7280.dtsi`.

For `Ufs_mem_hc` node in Dragonwing IQ-9075, see `<workspace_root_path>/sources/kernel/kernel_platform/kernel/arch/arm64/boot/dts/qcom/sa8775p.dtsi`.

Note

These parameters are only for information purposes. Don’t change them.

| Property | Description |
| --- | --- |
| `Compatible` | Qualcomm SoCs must contain strings such as `qcom`, `ufshc`. |
| `Interrupts` | Interrupt mapping for UFS host controller IRQ. |
| `Reg` | UFS host registers address mapping. |
| `Phys` | `phandle` to UFS device PHY node. |
| `lanes-per-direction` | Specify the number of lanes available per direction. Either 1 or 2. |
| `clock-names` | List of clock input name strings. |
| `Clocks` | List of `phandle` and clock specifier pairs. |
| `freq-table-hz` | Array of &lt;minimum maximum&gt; operating frequencies stored in the same order as the clocks property. |
| `reset-gpios` | A `phandle` and GPIO specifier denoting the GPIO that is connected. |
| `Resets` | Reset node register. |

The `Ufs_mem_phy` node describes the on-chip UFS device PHY hardware and is typically within the SoC DTSI file. For example, `<workspace_root_path>/sources/kernel/kernel_platform/kernel/arch/arm64/boot/dts/qcom/sc7280.dtsi` file.

| Property | Description |
| --- | --- |
| `Compatible` | Specify compatible string such as `qcom`, `qmp-ufs-phy`. |
| `#phy-cells` | Set the property to 0. |
| `Reg` | Should contain PHY register address space. |
| `reg-names` | <ul class="simple"><br><li><p>Indicates various resources passed to driver (through the reg property) by name.</p></li><br><li><p>The required <code class="docutils literal notranslate"><span class="pre">reg-names</span></code> is <code class="docutils literal notranslate"><span class="pre">phy_mem</span></code>.</p></li><br></ul> |
| `lanes-per-direction` | Number of lanes available per direction; either 1 or 2. |
| `clock-names` | List of clock input name strings. |
| `clocks` | List of phandle and clock specifier pairs. |
| `vdda-phy-supply` | `phandle` to main PHY supply for analog domain. |
| `vdda-pll-supply` | `phandle` to PHY PLL and Power-Gen block power supply. |
| `Resets` | Specifies the PHY reset in the UFS device controller. |

For more information about DTS parameters, see `/kernel_platform/msm-kernel/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml`.

# Configure SDHCI (eMMC and SD card internal) Linux kernel device tree

The SoC DTSI node specifies register address space, clocks, interrupts, and reset information. The platform DTSI node specifies power supply, voltage, and current levels.
The `sdhc_2: mmc@8804000` node describes the on-chip SDHC host controller and is typically within the SoC DTSI file. For example, `<workspace_root_path>/sources/kernel/kernel_platform/kernel/arch/arm64/boot/dts/qcom/sc7280.dtsi` file.

Note

These parameters are only for information purposes. Don’t modify them.

| Property | Description |
| --- | --- |
| `Compatible` | Specify compatible strings such as `qcom,sc7280-sdhci`, `qcom,sdhci-msm-v5`. |
| `Pinctrl-names` | Defines name of the pin control states. |
| `Pinctrl-0 &amp;1` | Points to pin control settings. This is an array defines pin  control settings for multiple states. |
| `Interrupts` | Interrupt mapping for SDHC IRQ. |
| `Interrupt-names` | Lists the names corresponding to each interrupt defined in the `interrupts` property. |
| `reg` | SDHC host registers address mapping. |
| `iommus` | `Iommus` specifies the IOMMU node and stream ID. |
| `clock-names` | List of clock input name strings. |
| `clocks` | List of phandle and clock specifier pairs. |
| `interconnects` | Defines the interconnect paths for the device. |
| `interrupt-names` | Lists the names to each interconnect path defined in `interconnects` property. |
| `power-domains` | Specifies the power domain used by the SDHC. |
| `bus-width` | Specifies the number of data lines used for communication. |
| `dma-coherent` | Specifies that the SDHCI and CPU maintain cache coherency. |
| `qcom,dll-config` | Platform specific settings for `DLL_CONFIG` reg. |
| `resets` | Reset node register. |
| `sdhc2_opp_table` | This table defines various operating points supported by the SDHCI. |

Last Published: Oct 10, 2025

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