# Dragonwing IQ-8275 interface overview

Source: [https://docs.qualcomm.com/doc/80-70022-8/topic/qcs8275-interface-overview.html](https://docs.qualcomm.com/doc/80-70022-8/topic/qcs8275-interface-overview.html)

The following table lists the device interface features for the Dragonwing IQ-8275.

| **2xQUP v3 serial                                engine** | **2xQUP v3 serial                                engine** | **2xQUP v3 serial                                engine** |
| --- | --- | --- |
| Serial engine instances | QUPV3\_0 | QUPV3\_1 |
| Application processor QUP v3<br>                            serial engine | 8 | 8 |
| **2xUSB                                controller** | **2xUSB                                controller** | **2xUSB                                controller** |
| Controller address | 0xa600000 | 0xa400000 |
| Maximum speed | USB 3.x SuperSpeed | USB 2.0 high speed |
| HS/SS PHY power<br>                            rails | L17A: VDDA-PHY-SUPPLY | L17A: VDDA-PLL-SUPPLY |
| HS/SS PHY power<br>                            rails | L15A: VDDA-PLL-SUPPLY | L17C: VDDA18-SUPPLY |
| HS/SS PHY power<br>                            rails | L17A: VDDA-PLL-SUPPLY | L19A: VDDA33-SUPPLY |
| HS/SS PHY power<br>                            rails | L18C: VDDA | – |
| HS/SS PHY power<br>                            rails | L19A: VDDA33-SUPPLY | – |
| **2xPCIe controller** | **2xPCIe controller** | **2xPCIe controller** |
| Root complex | RC1 | RC0 |
| Speed | Gen4 2L (16 GT/s) | Gen4 4L (16 GT/s) |
| Configuration space | 0x40100000 (0x100000) 1 MB | 0x60100000 (0x100000) 1 MB |
| I/O space | 0x40200000 (0x100000) 1 MB | 0x60200000 (0x100000) 1 MB |
| Base address Register space<br>                            (BAR) | 0x40300000 (0x1fd00000) 509 MB | 0x60300000 (0x1fd00000) 509 MB |
| Power rails | vreg\_l6a (VDD\_A\_PCIE\_0\_CORE) | vreg\_l5a (VDD\_A\_PCIE\_1\_CORE) |
| Power rails | vreg\_l5a (VDD\_A\_PCIE\_0\_PLL\_1P2) | vreg\_l6a (VDD\_A\_PCIE\_1\_PLL\_1P2) |
| Interrupts | MSI and PCI legacy interrupts | MSI and PCI legacy interrupts |
| Power management | ASPM (L1/L1ss, L0s) | ASPM (L1/L1ss, L0s) |
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## QUP v3 mapping to protocols and GPIOs in Dragonwing IQ-8275

Dragonwing IQ-8275 has two QUP v3 serial engines. The following table lists the protocol and
                GPIO mapping.

| QUP v3 serial engine | QUP v3 serial engine | Protocols | Protocols | Protocols | Protocols | QUP lane to<br>                                GPIO mapping | QUP lane to<br>                                GPIO mapping | QUP lane to<br>                                GPIO mapping | QUP lane to<br>                                GPIO mapping | QUP lane to<br>                                GPIO mapping | QUP lane to<br>                                GPIO mapping | QUP lane to<br>                                GPIO mapping |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| QUP v3 serial engine | QUP v3 serial engine | UART | HS UART | I2C-M | SPI-M | L0 | L1 | L2 | L3 | L4 | L5 | L6 |
| QUP\_0 | SE0 | Yes | – | Yes | Yes | 17 | 18 | 19 | 20 | – | – | – |
| QUP\_0 | SE1 | Yes | – | Yes | Yes | 19 | 20 | 17 | 18 | – | – | – |
| QUP\_0 | SE2 | Yes | Yes | Yes | Yes | 33 | 34 | 35 | 36 | – | – | – |
| QUP\_0 | SE3 | Yes | Yes | Yes | Yes | 25 | 26 | 27 | 28 | – | – | – |
| QUP\_0 | SE4 | Yes | – | Yes | Yes | 29 | 30 | 31 | 32 | – | – | – |
| QUP\_0 | SE5 | Yes | – | Yes | Yes | 21 | 22 | 23 | 24 | – | – | – |
| QUP\_0 | SE6 | Yes | – | Yes | Yes | 80 | 81 | 82 | 83 | – | – | – |
| QUP\_0 | SE7 | Yes | – | Yes | Yes | 43 | 44 | 43 | 44 | – | – | – |
| QUP\_2 | SE0 | Yes | – | Yes | Yes | 37 | 38 | 39 | 40 | – | – | – |
| QUP\_2 | SE1 | Yes | – | Yes | Yes | 39 | 40 | 37 | 38 | – | – | – |
| QUP\_2 | SE2 | Yes | Yes | Yes | Yes | 84 | 85 | 86 | 87 | 88 | – | – |
| QUP\_2 | SE3 | Yes | Yes | Yes | Yes | 41 | 42 | 41 | 42 | – | – | – |
| QUP\_2 | SE4 | Yes | – | Yes | Yes | 45 | 46 | 47 | 48 | – | – | – |
| QUP\_2 | SE5 | Yes | – | Yes | Yes | 49 | 50 | 51 | 52 | – | – | – |
| QUP\_2 | SE6 | Yes | – | Yes | Yes | 89 | 90 | 91 | 92 | – | – | – |
| QUP\_2 | SE7 | Yes | – | Yes | Yes | 91 | 92 | 89 | 90 | – | – | – |
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**Parent Topic:** [Overview of peripheral interfaces](https://docs.qualcomm.com/doc/80-70022-8/topic/overview-of-wired-interfaces.html)

Last Published: Sep 19, 2025

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