# References
Source: [https://docs.qualcomm.com/doc/80-70022-8/topic/references.html](https://docs.qualcomm.com/doc/80-70022-8/topic/references.html)
## QUP v3 overview
Source: [https://docs.qualcomm.com/doc/80-70022-8/topic/references.html](https://docs.qualcomm.com/doc/80-70022-8/topic/references.html)
The QUP v3 is a highly flexible and programmable hardware for supporting a wide range of
serial interface. A single QUP v3 serial engine hardware core provides up to eight
serial interfaces. The two QUP v3 hardware cores are as follows:
- 16-serial engine core
- SSC QUP v3 hardware core with five serial engines available in the SSC\_I/Os
The QUP v3 supports access from multiple hardware entities in the system. Each entity has
its own execution environment (EE), a separate address space, and an interrupt line. For
information about the various transfer modes that can be configured in QUP v3, see [Supported transfer modes in QUP v3](https://docs.qualcomm.com/doc/80-70022-8/topic/references.html#qup-v3-supported-transfer-modes).
The following figure shows one GSI core/engine connected with up to eight serial engines
(SE). You have the flexibility to customize configurations depending on the use case or
the protocol of the serial engine. For information about how to customize
configurations, see [QUP v3 access control customization](https://docs.qualcomm.com/doc/80-70022-8/topic/references.html#customize-access-control-of-qup). To verify if
the QUP v3 firmware is correctly flashed, see [QUP v3 firmware status verification](https://docs.qualcomm.com/doc/80-70022-8/topic/references.html#verify-qup-firmware-status).
Figure : QUP v3 block diagram
## Supported transfer modes in QUP v3
Source: [https://docs.qualcomm.com/doc/80-70022-8/topic/references.html](https://docs.qualcomm.com/doc/80-70022-8/topic/references.html)
The following modes can be configured in the QUP v3 serial engine.
- **FIFO mode**
1. ①: The application processor configures the generic interface (GENI).
2. ②: The application processor processes Rx/Tx data. The data is
transferred between GENI and memory.
- **DMA mode**
1. ①: The application processor initializes DMA.
2. ②: The serial engine configures GENI, and initiates the transfer
process.
- **GSI mode**
1. ①: The application processor prepares TRE.
2. ②: The application processor informs QUP (GSI).
3. ③: The GSI processes TRE.
4. ④: After the TRE completes processing, it's sent to GENI.
5. ⑤: The serial engine processes the Rx/Tx data.
Note: The QUP v3 UART serial engine doesn't support the GSI
mode.
## QUP v3 access control customization
Source: [https://docs.qualcomm.com/doc/80-70022-8/topic/references.html](https://docs.qualcomm.com/doc/80-70022-8/topic/references.html)
The QUP v3 user access file `QUPAC_Access.c` specifies the owners of the
serial engine resource. Initially, it's populated according to the system I/O GPIO
allocation. All serial engines must be listed to access the subsystem. It's flexible
enough to list only the available serial engine on a particular device.
To customize the access control for the required serial engine protocol, configure the
parameters in the QUPAC\_Access.c file. The Qualcomm TEE image for
the QUPAC\_Access.c file is
at /firmware/qualcomm-linux-spf-1-0\_ap\_standard\_oem\_nomodem/TZ.XF.5.0/trustzone\_images/core/settings/buses/qup\_accesscontrol/qupv3/config/<chipset>/QUPAC\_Access.c.
To specify the owner of the serial engine resource, modify the
QUPAC\_Access.c file to suit the board design.
The following use case specifies the default protocol that operates on an enabled serial
engine. You can modify the code according to your board design.
### Nonsecure mode use case in QUP v3 serial engine
The following nonsecure mode use cases are supported in the QUP v3 serial engine.
const QUPv3_se_security_permissions_type qupv3_perms_iot_rb3[] =
{
/* PeriphID, ProtocolID, Mode, NsOwner, bAllowFifo, bLoad, bModExcl */
{ QUPV3_0_SE0, QUPV3_PROTOCOL_I2C, QUPV3_MODE_FIFO, AC_HLOS, TRUE, TRUE, FALSE }, // LT9611 and QPS615 I2C
{ QUPV3_0_SE1, QUPV3_PROTOCOL_I2C, QUPV3_MODE_FIFO, AC_HLOS, TRUE, TRUE, FALSE }, // APPS I2C - PCIE/ USB Type C
{ QUPV3_0_SE2, QUPV3_PROTOCOL_I2C, QUPV3_MODE_FIFO, AC_HLOS, TRUE, TRUE, FALSE }, // SMB / LS1 I2C
{ QUPV3_0_SE3, QUPV3_PROTOCOL_SPI, QUPV3_MODE_FIFO, AC_HLOS, TRUE, TRUE, FALSE }, // CAN SPI
{ QUPV3_0_SE4, QUPV3_PROTOCOL_UART_4W, QUPV3_MODE_FIFO, AC_HLOS, TRUE, TRUE, FALSE }, // LS1 UART
{ QUPV3_0_SE5, QUPV3_PROTOCOL_UART_2W, QUPV3_MODE_FIFO, AC_HLOS, TRUE, FALSE, FALSE }, // Debug UART
{ QUPV3_0_SE6, QUPV3_PROTOCOL_UART_2W, QUPV3_MODE_FIFO, AC_HLOS, TRUE, TRUE, FALSE }, // WLAN UART
{ QUPV3_0_SE7, QUPV3_PROTOCOL_UART_4W, QUPV3_MODE_FIFO, AC_HLOS, TRUE, TRUE, FALSE }, // Hastings BT
{ QUPV3_1_SE0, QUPV3_PROTOCOL_SPMI, QUPV3_MODE_FIFO, AC_ADSP_Q6_ELF, TRUE, TRUE, FALSE }, // QuP SPMI
{ QUPV3_1_SE1, QUPV3_PROTOCOL_I2C, QUPV3_MODE_FIFO, AC_HLOS, TRUE, TRUE, FALSE }, // NFC I2C
{ QUPV3_1_SE2, QUPV3_PROTOCOL_I2C, QUPV3_MODE_FIFO, AC_HLOS, TRUE, TRUE, FALSE }, // HDMI OUT for VIDEOIOBoard
{ QUPV3_1_SE3, QUPV3_PROTOCOL_SPI, QUPV3_MODE_FIFO, AC_HLOS, FALSE, TRUE, TRUE }, // LS1 SPI
{ QUPV3_1_SE4, QUPV3_PROTOCOL_SPI, QUPV3_MODE_GSI, AC_TZ, FALSE, TRUE, TRUE }, // SPI -NFC ESE
{ QUPV3_1_SE5, QUPV3_PROTOCOL_I2C, QUPV3_MODE_GSI, AC_HLOS, FALSE, TRUE, FALSE}, // Legacy Touch
{ QUPV3_1_SE6, QUPV3_PROTOCOL_SPI, QUPV3_MODE_GSI, AC_HLOS, FALSE, TRUE, FALSE}, // FP
/*QUPV3_1_SE7*/
};Copy to clipboard
### QUP v3 serial engine access list description
The following variables are passed into the
`QUPv3_se_security_permissions_type` structure.
Table : Security permission variables for QUP v3
| Variables | Description |
| --- | --- |
| `PeriphID` | Serial engine peripheral to configure and assign. |
| `ProtocolID` | Macro of the required protocol. |
| `Mode` | Macro of FIFO/GSI/DMA modes. |
| `NsOwner` | Holds a macro of the image that needs access. |
| `bAllowFifo` | The boolean flag is set to `True` if the mode is `FIFO`, else the flag is set to `False`. |
| `bLoad` | The boolean flag value is set to `True` to load the protocol firmware. |
| `bModExcl` | This flag is exclusively for Qualcomm TEE. It's set to `True` when `NsOwner` is AC\_TZ. |
For more information about this macro,
see settings/buses/qup\_accesscontrol/qupv3/interface/QupACCommonIds.h.
## QUP v3 firmware status verification
Source: [https://docs.qualcomm.com/doc/80-70022-8/topic/references.html](https://docs.qualcomm.com/doc/80-70022-8/topic/references.html)
For serial engines to work, the QUP firmware must be flashed correctly. The firmware is
delivered through the metabuild at
`common/core_qupv3fw//qupv3fw.elf`. You can verify the
firmware status by checking `GENI_FW_REVISION_RO (0xa8c068)`. For
example, identify the register in the kernel log for the `0000ffff`
value. In the following log, the `0000ffff` error indicates that the
firmware isn't flashed
correctly.
0a8c068: 0000ffff //Invalid firmware or firmware not loaded
00a80068: 00000126 //SPI
00a88068: 00000338 //I2C
Copy to clipboard
Modify the `QUPAC_Access.c` file configuration only if you intend to use a
protocol different from the default configuration.
The following sample log is displayed when configurations don't match after loading.
msm_geni_serial 898000.qcom,qup_uart:msm_geni_serial_startup: Invalid FW
255 loadedCopy to clipboard
## Related documents
Source: [https://docs.qualcomm.com/doc/80-70022-8/topic/references.html](https://docs.qualcomm.com/doc/80-70022-8/topic/references.html)
| Title | Resource |
| --- | --- |
| **Qualcomm Technologies, Inc.** | **Qualcomm Technologies, Inc.** |
| Secure shell | [https://docs.qualcomm.com/bundle/publicresource/topics/80-70022-254/how_to.html](https://docs.qualcomm.com/bundle/publicresource/topics/80-70022-254/how_to.html) |
| QDTE | [https://docs.qualcomm.com/bundle/publicresource/topics/80-70022-4/tools.html#qdte](https://docs.qualcomm.com/bundle/publicresource/topics/80-70022-4/tools.html#qdte) |
| **Resources** | **Resources** |
| PCI bus subsystem | [https://www.kernel.org/doc/html/latest/PCI/index.html](https://www.kernel.org/doc/html/latest/PCI/index.html) |
| Linux user space examples | [https://github.com/Digilent/linux-userspace-examples/tree/master/uart_example_linux/src](https://github.com/Digilent/linux-userspace-examples/tree/master/uart_example_linux/src) |
| DTSI configuration examples | [https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts](https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts) |
| Test tools and methods for the UART serial interface driver | [https://docs.kernel.org/admin-guide/serial-console.html](https://docs.kernel.org/admin-guide/serial-console.html) |
| UART Linux APIs | [https://github.com/torvalds/linux/blob/master/include/linux/tty.h](https://github.com/torvalds/linux/blob/master/include/linux/tty.h) |
| UART upstream device tree reference | [https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/sc7280.dtsi](https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/sc7280.dtsi) |
| Qualcomm Dragonwing RB3 Gen 2 Development Kit device tree node | [https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts](https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts) |
| SPI samples | [https://github.com/Digilent/linux-userspace-examples/tree/master](https://github.com/Digilent/linux-userspace-examples/tree/master) |
| SPI Linux APIs |