# PCIe
Source: [https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html](https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html)
如下图所示，PCIe 采用双向连接同时发送和接收信息。
Figure : PCIe 设备连接链路
设备间的路径称为 链路。由一个或多个发送/接收对组成。一对链路称为一个 通道。Qualcomm Linux 设备中的 PCIe 设备连接支持 16 个通道。通道数量或 链路宽度 为 x4。关于 PCIe 的更多信息，请参阅 [https://pcisig.com/specifications/pciexpress/technical_library/pciexpress_whitepaper.pdf](https://pcisig.com/specifications/pciexpress/technical_library/pciexpress_whitepaper.pdf)。
下表列出了设备的 PCIe 连接类型。
Table : PCIe 连接
| PCIe 类型 | 说明 |
| :---: | --- |
| 根复合体 (RC) | 将 CPU 连接到 PCIe 拓扑。 |
| Switch | 连接 2 个以上端口并充当数据包路由器 |
| 桥接器 | 连接不同的总线，例如 PCIe 连接到 PCIe，或者 PCIe 连接到外设组件互连 (PCI)。 |
| 端点 (EP) | 位于 PCIe 拓扑树结构的底部，只有一个上游端口。 |
| 传统端点 | 使用较旧的 PCI 总线操作来支持向后兼容性 |
## PCIe 主机模式枚举功能
Source: [https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html](https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html)
当系统首次通电时，系统主机处理器上运行的配置软件知道存在总线 0（如果支持 PCIe）。该软件并不了解总线拓扑或连接到总线的任何设备。枚举过程将发现系统中存在的各种总线、设备和功能。
当枚举完成后，将对系统中的下述每一条总线进行编号：
- 主总线编号为直连到桥接器主接口（朝向根复合体）的总线的编号。
- 辅助总线编号标示与桥接器直连的辅助接口（远离根复合体）的总线。
- 从属总线编号标明存在于桥接器下游侧的最大编号总线。
BDF 编号是每个设备的唯一标识码。事务层数据包 (TLP) 的基于 ID 的路由方法使用该编号。PCIe 主机模式枚举过程涉及以下操作：
1. 链路训练
2. 扫描总线上的设备
3. 注册
有关 PCIe 设备初始化和枚举过程的更多信息，可访问 [https://www.kernel.org/doc/html/latest/PCI/index.html](https://www.kernel.org/doc/html/latest/PCI/index.html)。
## PCIe 分层架构
Source: [https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html](https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html)
下图所示为 PCIe 的分层架构模型。
Figure : PCIe 分层架构
各层交换的传输单元如下。
- 物理层实体之间交换有序集合。
- 数据链路层实体之间交换数据链路层数据包 (DLLP)。
- 事务层实体之间交换事务层数据包 (TLP)。
下表列出了 PCIe 架构中的三个层及其相应的功能。
| 层 | 功能 |
| --- | --- |
| 物理层 | 逻辑子块：链路训练、初始化和维护。 |
| 物理层 | 物理子模块：8b/10b 编解码、并串转换和串并转换。 |
| 数据链路层 | 对 DLLP 数据包进行组装和拆解。 |
| 数据链路层 | 生成和验证链路层 CRC (LCRC)。 |
| 数据链路层 | 应答和无应答协议（重放错误的 TLP）。 |
| 事务层 | 对 TLP 数据包进行组装和拆解。 |
| 事务层 | 生成和验证端到端 CRC (ECRC)。 |
| 事务层 | 流量控制接收关于可使用 DLLP 接收缓存大小信息的实体广播。 |
| 事务层 | 服务质量 (QoS)：流量类别 (TC) 到虚拟通道 (VC) 的映射。 |
| 事务层 | 事务排序：在 VC 内实施事务排序规则。 |
| | |
| | |
| | |
| | |
PCI 为每个功能定义了一个专用的配置地址空间块，如下图所示。软件将确定存在的功能、对其进行配置并检查和控制其状态。
Figure : PCIe 配置地址空间
## PCIe 软件驱动程序配置
Source: [https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html](https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html)
PCIe 控制器驱动程序用于初始化 PCIe 资源并执行链路训练。当训练成功后，控制器驱动程序将调用 PCIe 框架进行链路枚举，例如发现端点、识别客户端驱动程序，以及探测这些驱动程序。有关 PCIe 框架和客户端驱动程序 PCIe 注册的更多信息，请参阅 [https://www.kernel.org/doc/html/latest/PCI/index.html](https://www.kernel.org/doc/html/latest/PCI/index.html)。
### 链路训练
链路训练包括以下操作：
1. [https://github.com/torvalds/linux/blob/master/drivers/pci/controller/dwc/pcie-qcom.c](https://github.com/torvalds/linux/blob/master/drivers/pci/controller/dwc/pcie-qcom.c) 处的 PCIe 驱动程序
`pcie-qcom.c`
文件从设备树中获取所需的资源，例如调节器、时钟。
2. PCIe 驱动程序调用 Synopsys DesignWare® 核心主机驱动程序
pcie-designware-host.c 文件（位于
[https://github.com/torvalds/linux/blob/master/drivers/pci/controller/dwc/pcie-designware-host.c](https://github.com/torvalds/linux/blob/master/drivers/pci/controller/dwc/pcie-designware-host.c)）来初始化根复合体。
3. Synopsys DesignWare 核心驱动程序执行所有必要的初始化。
4. Synopsys DesignWare 核心驱动程序调用函数指针来执行主机初始化。
5. Qualcomm PCIe 驱动程序执行 PHY 开机，启用所有调节器和时钟。
6. Synopsys DesignWare 核心驱动程序通过调用函数指针来启动链路训练。
### 硬件初始化
驱动程序初始化和配置 PCIe 硬件模块并执行链路训练。初始化发生在调用 `platform _probe()`驱动程序函数之后。
static int qcom_pcie_probe(struct platform_device *pdev)
{
// get PCIe resources
ret = dw_pcie_host_init(pp); // call DWC framework to host intialisation like MSI, MSIx and controller init
if (ret) {
dev_err(dev, "cannot initialize host\n");
goto err_phy_exit;
}
};
static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
{}
};
static struct platform_driver qcom_pcie_driver = {
.probe = qcom_pcie_probe,
.driver = {
.name = "qcom-pcie",
.suppress_bind_attrs = true,
.of_match_table = qcom_pcie_match,
},
};Copy to clipboard
当对 Synopsys DesignWare 核心驱动程序进行初始化时，也会初始化 MSI、MSIx 和控制器。驱动程序调用 Qualcomm 函数指针来启动链路训练。
static int qcom_pcie_start_link(struct dw_pcie *pci)
{
struct qcom_pcie *pcie = to_qcom_pcie(pci);
/* Enable Link Training state machine */
if (pcie->cfg->ops->ltssm_enable)
pcie->cfg->ops->ltssm_enable(pcie);
return 0;
}
static int qcom_pcie_link_up(struct dw_pcie *pci)
{
u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
return !!(val & PCI_EXP_LNKSTA_DLLLA); // checks the link is up or not
}
static const struct dw_pcie_ops dw_pcie_ops = {
.link_up = qcom_pcie_link_up,
.start_link = qcom_pcie_start_link,
};Copy to clipboard
Synopsys DesignWare 核心驱动程序等待链路激活以枚举 PCI 框架。Qualcomm PCIe 驱动程序仅启用链路训练。
Note: WLAN EP 连接默认启用 PCIE\_0 根复合体实例。
## 启用 QPS615 PCIe switch
Source: [https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html](https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html)
本节介绍如何在 Qualcomm Linux 硬件 SoC 中启用 QPS615 PCIe switch。`PCIe1` 实例支持 QPS615
switch 端点。下图显示了 QPS615 端点和连接。
Figure : QPS615 PCIe switch 连接图
可在以下位置访问 Qualcomm PCIe 驱动程序文档：
- [https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/pci/qcom%2Cpcie-sc8280xp.yaml](https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/pci/qcom%2Cpcie-sc8280xp.yaml)
- [https://elixir.bootlin.com/linux/v6.6.48/source/Documentation/devicetree/bindings/pci/qcom,pcie.yaml](https://elixir.bootlin.com/linux/v6.6.48/source/Documentation/devicetree/bindings/pci/qcom,pcie.yaml)
- [https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/phy/qcom%2Csc8280xp-qmp-pcie-phy.yaml](https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/phy/qcom%2Csc8280xp-qmp-pcie-phy.yaml)
### PCIe 相关配置
默认情况下，将启用以下配置来支持 QPS615 switch。禁用 QPS615 switch 默认支持（通过还原代码更改）可将其用于其他 PCIe 端点。
请将以下补丁应用至 /arch/arm64/configs/qcom\_addons.config 文件，以便启用 PCIe
相关的
`configs`。
QCLINUX: arm64: defconfig: qcom:
diff --git a/arch/arm64/configs/qcom_addons.config b/arch/arm64/configs/qcom_addons.config
index 46555f9..a83f417 100644
--- a/arch/arm64/configs/qcom_addons.config
+++ b/arch/arm64/configs/qcom_addons.config
@@ -25,3 +25,4 @@
CONFIG_VIRT_DRIVERS=y
CONFIG_QCOM_SMP2P_SLEEPSTATE=m
CONFIG_QCOM_SOC_DEBUG=y
+CONFIG_QCOM_QPS615_PCIE_SWITCH=y
diff --git a/arch/arm64/configs/qcom_defconfig b/arch/arm64/configs/qcom_defconfig
index 7293680..730122c 100644
--- a/arch/arm64/configs/qcom_defconfig
+++ b/arch/arm64/configs/qcom_defconfig
@@ -173,6 +173,7 @@
CONFIG_HOTPLUG_PCI=y
CONFIG_HOTPLUG_PCI_ACPI=y
CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCIE_DW_PLAT_HOST=y
CONFIG_PCIE_QCOM=y
CONFIG_PCI_ENDPOINT=y
CONFIG_PCI_ENDPOINT_CONFIGFS=y
@@ -793,3 +794,5 @@
CONFIG_CORESIGHT_TPDM=m
CONFIG_CORESIGHT_DUMMY=m
CONFIG_MEMTEST=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_POWER_SUPERSAVE=y
Copy to clipboard
### 向端点提供 always-on 的 refclk 信号
在 PCIe 低功耗状态（例如 L1.1 或 L1.2）下，PHY 停止向端点提供 `refclk`。但是，必须向端点提供
`refclk` 信号。如果端点通过将 `clkreq` 置为有效恢复与 L0
的链接，则根复合体必须向端点提供 `refclk`。由于开关板设计方面的原因，某些配备 PCIe QPS615 switch 的设备无法将
`clkreq` 信号从端点向主机驱动。用户可以添加一个标志，以确保 `refclk`
始终提供给端点。
请将以下补丁应用于 [https://github.com/torvalds/linux/blob/master/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c](https://github.com/torvalds/linux/blob/master/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c) 处的 phy-qcom-qmp-pcie.c
文件，以便使 `refclk` 保持 always-on
状态。
phy: qcom-qmp-pcie:
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -43,6 +43,8 @@
/* QPHY_PCS_STATUS bit */
#define PHYSTATUS BIT(6)
#define PHYSTATUS_4_20 BIT(7)
+/* PCS_PCIE_ENDPOINT_REFCLK_CNTRL */
+#define EPCLK_ALWAYS_ON_EN BIT(6)
#define PHY_INIT_COMPLETE_TIMEOUT 10000
@@ -2293,6 +2295,8 @@
struct phy *phy;
int mode;
+ bool refclk_always_on;
+
struct clk_fixed_rate pipe_clk_fixed;
};
@@ -3238,6 +3242,10 @@
qmp_pcie_configure(pcs, tbls->pcs, tbls->pcs_num);
qmp_pcie_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num);
+ if (qmp->refclk_always_on && cfg->regs[QPHY_PCS_ENDPOINT_REFCLK_CNTRL])
+ qphy_setbits(pcs_misc, cfg->regs[QPHY_PCS_ENDPOINT_REFCLK_CNTRL],
+ EPCLK_ALWAYS_ON_EN);
+
if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) {
qmp_pcie_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num);
qmp_pcie_init_port_b(qmp, tbls);
@@ -3760,6 +3768,12 @@
if (ret)
goto err_node_put;
+ qmp->refclk_always_on = of_property_read_bool(dev->of_node, "qcom,refclk-always-on");
+ if (qmp->refclk_always_on && !qmp->cfg->regs[QPHY_PCS_ENDPOINT_REFCLK_CNTRL]) {
+ dev_err(dev, "refclk is always on is present but refclk cntrl offset is not present\n");
+ goto err_node_put;
+ }
+
ret = phy_pipe_clk_register(qmp, np);
if (ret)
goto err_node_put;
Copy to clipboard
### 消息信号中断 (MSI)
当前 MSI 映射未包含所有向量。Qualcomm Linux 硬件 SoC 支持八个向量。每个向量支持 32 个 MSI。因此，总共支持 256 个 MSI。
有关添加该 PCIe 实例支持的所有 MSI 组的信息，可访问 [https://lore.kernel.org/linux-arm-msm/f1168212-bc6e-4570-869c-2870d6f248ad@linaro.org/T/](https://lore.kernel.org/linux-arm-msm/f1168212-bc6e-4570-869c-2870d6f248ad@linaro.org/T/)。
### QPS615 switch 支持
当添加用于控制对 QPS615 PCIe switch 供电的所有 GPIO 作为固定调压器时，QPS615 驱动程序将启用通过调压器框架进行供电。此外，还会执行 I2C
写操作来配置 QPS615 switch。添加 PCIe 节点作为 QPS615 节点的依赖项可以使 PCIe 驱动程序在 QPS615
驱动程序探测之后进行探测，从而确保 switch 已上电并准备好进行枚举。当 QPS615 无法切换时，CLKREQ
引脚会导致设备崩溃。这是一个已知的限制。因此，`refclk` 设置为 always-on。
### QPS615 switch 设备树绑定
要添加 QPS615 switch 设备树绑定，应对
/arch/arm64/boot/dts/qcom/<chipset>-addons-rb3.dts
文件应用以下补丁。
QCLINUX: dt-bindings: pci: qps615:
diff --git a/arch/arm64/boot/dts/qcom/-addons-rb3.dts b/arch/arm64/boot/dts/qcom/-addons-rb3.dts
index 109ad08..7baf505 100644
--- a/arch/arm64/boot/dts/qcom/-addons-rb3.dts
+++ b/arch/arm64/boot/dts/qcom/-addons-rb3.dts
@@ -14,6 +14,82 @@
/ {
model = "Qualcomm Technologies, Inc. -addons RB3 platform";
compatible = "qcom,-addons-rb3","qcom,sc7280";
+
+ qps615_0p9_vreg: qps615-0p9-vreg {
+ compatible = "regulator-fixed";
+ regulator-name = "qps615_0p9_vreg";
+ gpio = <&pm8350c_gpios 2 0>;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ enable-active-high;
+ regulator-enable-ramp-delay = <4300>;
+ };
+
+ qps615_1p8_vreg: qps615-1p8-vreg {
+ compatible = "regulator-fixed";
+ regulator-name = "qps615_1p8_vreg";
+ gpio = <&pm8350c_gpios 3 0>;
+ vin-supply = <&qps615_0p9_vreg>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ enable-active-high;
+ regulator-enable-ramp-delay = <10000>;
+ };
+
+ qps615_rsex_vreg: qps615-rsex-vreg {
+ compatible = "regulator-fixed";
+ regulator-name = "qps615_rsex_vreg";
+ gpio = <&pm8350c_gpios 1 0>;
+ vin-supply = <&qps615_1p8_vreg>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ enable-active-high;
+ regulator-enable-ramp-delay = <10000>;
+ };
+
+ usb_hub_1p05_vreg: usb-hub-1p05-vreg {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_hub_1p05_vreg";
+ gpio = <&pm7250b_gpios 4 0>;
+ vin-supply = <&qps615_rsex_vreg>;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ enable-active-high;
+ regulator-enable-ramp-delay = <5000>;
+ };
+
+ usb_hub_3p3_vreg: usb-hub-3p3-vreg {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_hub_3p3_vreg";
+ gpio = <&pm7250b_gpios 1 0>;
+ vin-supply = <&usb_hub_1p05_vreg>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ regulator-enable-ramp-delay = <10000>;
+ };
+
+ usb_hub_rest_vreg: usb-hub-rest-vreg {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_hub_rest_vreg";
+ gpio = <&pm8350c_gpios 4 0>;
+ vin-supply = <&usb_hub_3p3_vreg>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ };
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ qps615_switch: pcie-switch@77 {
+ compatible = "qcom,switch-i2c";
+ reg = <0x77>;
+ vdda-supply = <&usb_hub_rest_vreg>;
+ status = "okay";
+ };
};
&i2c1 {
@@ -216,6 +292,14 @@
};
};
+&pcie1 {
+ dummy-supply = <&qps615_switch>;
+};
+
+&pcie1_phy {
+ qcom,refclk-always-on;
+};
+
&pm8350c_gpios {
pm8008i-reset-state {
pm8008i_active: pm8008i-active-pins {
Documentation/devicetree/bindings/pci/qps615-switch.yaml Documentation/devicetree/bindings/pci/qps615-switch.yaml
new file mode 100644
index 0000000..f59e068
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qps615-switch.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qps615-switch.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. (QTI) PCIe switch
+
+maintainers:
+ - Chundru Krishna chaitanya
+
+properties:
+ compatible:
+ enum:
+ - qcom,switch-i2c
+
+ reg:
+ maxItems: 1
+
+ vdda-supply:
+ description: A phandle to the core analog power supply
+
+required:
+ - compatible
+ - reg
+ - vdda-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qps615: pcie-switch@77 {
+ compatible = "qcom,switch-i2c";
+ reg = <0x077>;
+ vdda-supply = <&foo>;
+ };
Copy to clipboard
### QPS615 switch 驱动程序
添加了用于 QPS615 PCIe switch 上电的驱动程序。它通过 I2C 执行基本初始化。初始化序列位于驱动程序通过
request\_firmware API 请求的固件镜像中。
要添加 QPS615 switch 驱动程序，应在 /drivers/pci/controller/Kconfig
文件中应用以下补丁。
QCLINUX: pci: controller: misc:
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index c0c3f28..d68e701 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -345,4 +345,5 @@
source "drivers/pci/controller/cadence/Kconfig"
source "drivers/pci/controller/dwc/Kconfig"
source "drivers/pci/controller/mobiveil/Kconfig"
+source "drivers/pci/controller/misc/Kconfig"
endmenu
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index 37c8663..015f711b 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -43,6 +43,7 @@
# pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
obj-y += dwc/
obj-y += mobiveil/
+obj-y += misc/
# The following drivers are for devices that use the generic ACPI
diff --git a/drivers/pci/controller/misc/Kconfig b/drivers/pci/controller/misc/Kconfig
new file mode 100644
index 0000000..0acea3f
--- /dev/null
+++ b/drivers/pci/controller/misc/Kconfig
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0
+config QCOM_QPS615_PCIE_SWITCH
+ bool "QCOM QPS615 PCIe Switch Driver"
+ depends on PCuart
+ help
+ This adds support to enable QPS615 PCIe switch power. And after powering on the switch do
+ switch initialization through I2C writes. The I2C data is parsed from the requested
+ firmware.
+
+ Say Y to compile this driver.
diff --git a/drivers/pci/controller/misc/Makefile b/drivers/pci/controller/misc/Makefile
new file mode 100644
index 0000000..1c2b99e
--- /dev/null
+++ b/drivers/pci/controller/misc/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_QCOM_QPS615_PCIE_SWITCH) += qps615.o
Change in arm64: dts: qcom: -rb3g2: Add PCIe nodes.
Enable PCIe1 controller and its corresponding PHY nodes on
-rb3g2 platform. As there are multiple endpoints connected through PCIe switch add smmu id for each BDF.
diff --git a/arch/arm64/boot/dts/qcom/-rb3.dts b/arch/arm64/boot/dts/qcom/-rb3.dts
index 5adce1f..f995a53 100644
--- a/arch/arm64/boot/dts/qcom/-rb3.dts
+++ b/arch/arm64/boot/dts/qcom/-rb3.dts
@@ -512,6 +512,32 @@
bias-bus-hold;
};
+&pcie1 {
+ perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>;
+ pinctrl-names = "default";
+
+ iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
+ <0x100 &apps_smmu 0x1c81 0x1>,
+ <0x208 &apps_smmu 0x1c84 0x1>,
+ <0x210 &apps_smmu 0x1c85 0x1>,
+ <0x218 &apps_smmu 0x1c86 0x1>,
+ <0x300 &apps_smmu 0x1c87 0x1>,
+ <0x400 &apps_smmu 0x1c88 0x1>,
+ <0x500 &apps_smmu 0x1c89 0x1>,
+ <0x501 &apps_smmu 0x1c90 0x1>;
+
+ status = "okay";
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l10c_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+
+ status = "okay";
+};
+
&qup_uart5_rx {
drive-strength = <2>;
bias-pull-up;
@@ -604,6 +630,21 @@
bias-disable;
};
+ pcie1_reset_n: pcie1-reset-n-state {
+ pins = "gpio2";
+ function = "gpio";
+ drive-strength = <16>;
+ output-low;
+ bias-disable;
+ };
+
+ pcie1_wake_n: pcie1-wake-n-state {
+ pins = "gpio3";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
qup_uart7_sleep_cts: qup-uart7-sleep-cts-state {
pins = "gpio28";
function = "gpio";
Copy to clipboard
### 保存和恢复配置空间 QPS615 switch
在电源管理待机状态下保留 PCIe 桥接设备的配置空间。在电源管理恢复状态下恢复 PCIe 桥接设备的配置空间。对于使用 QPS615 PCIe switch 连接的 PCIe 端点来说，此方法至关重要，能确保其正常运行。
diff --git a/drivers/pci/controller/misc/qps615.c b/drivers/pci/controller/misc/qps615.c
index 7d63efb..10048cd 100644
--- a/drivers/pci/controller/misc/qps615.c
+++ b/drivers/pci/controller/misc/qps615.c
@@ -5,6 +5,7 @@
#include
#include
#include
+#include
#define DRV_NAME "qps615-switch-i2c"
@@ -235,6 +236,24 @@
}
module_init(qps615_i2c_init);
+static void qcom_pcie_resume_early(struct pci_dev *pdev)
+{
+ pci_restore_state(pdev);
+}
+
+DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID,
+ PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI_NORMAL, 0,
+ qcom_pcie_resume_early);
+
+static void qcom_pcie_suspend_late(struct pci_dev *pdev)
+{
+ pci_save_state(pdev);
+}
+
+DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(PCI_ANY_ID,
+ PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI_NORMAL, 0,
+ qcom_pcie_suspend_late);
+
MODULE_AUTHOR("Krishna Chaitanya Chundru ");
MODULE_DESCRIPTION("QPS615 PCIE Switch driver");
MODULE_LICENSE("GPL");
Copy to clipboard
以下是来自 QPS615 设备枚举的 PCIe 内核驱动程序日志示例。
[ 7.254674] qcom-pcie 1c08000.pci: supply vdda not found, using dummy regulator
[ 7.285224] qcom-pcie 1c08000.pci: supply vddpe-3v3 not found, using dummy regulator
[ 7.299688] qcom-pcie 1c08000.pci: host bridge /soc@0/pci@1c08000 ranges:
[ 7.313713] qcom-pcie 1c08000.pci: IO 0x0040200000..0x00402fffff -> 0x0000000000
[ 7.329778] qcom-pcie 1c08000.pci: MEM 0x0040300000..0x005fffffff -> 0x0040300000
[ 7.479174] qcom-pcie 1c08000.pci: iATU: unroll T, 8 ob, 8 ib, align 4K, limit 1024G
[ 7.577792] qcom-pcie 1c08000.pci: PCIe Gen.3 x2 link up
[ 7.648353] qcom-pcie 1c08000.pci: PCI host bridge to bus 0001:00
[ 7.654618] pci_bus 0001:00: root bus resource [bus 00-ff]
[ 7.654620] pci_bus 0001:00: root bus resource [io 0x0000-0xfffff]
[ 7.654622] pci_bus 0001:00: root bus resource [mem 0x40300000-0x5fffffff]
[ 7.654633] pci 0001:00:00.0: [17cb:010b] type 01 class 0x060400
[ 7.665893] pci 0001:00:00.0: reg 0x10: [mem 0x00000000-0x00000fff]
[ 7.684913] pci 0001:00:00.0: PME# supported from D0 D3hot D3cold
[ 7.700502] pci 0001:01:00.0: [1179:0623] type 01 class 0x060400
[ 7.710817] pci 0001:01:00.0: PME# supported from D0 D3hot D3cold
[ 7.733698] pci 0001:01:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 7.738818] pci 0001:02:01.0: [1179:0623] type 01 class 0x060400
[ 7.751157] pci 0001:02:01.0: PME# supported from D0 D3hot D3cold
[ 7.763174] pci 0001:02:02.0: [1179:0623] type 01 class 0x060400
[ 7.777084] pci 0001:02:02.0: PME# supported from D0 D3hot D3cold
[ 7.792832] pci 0001:02:03.0: [1179:0623] type 01 class 0x060400
[ 7.815659] pci 0001:02:03.0: PME# supported from D0 D3hot D3cold
Copy to clipboard
## 通过 PCIe switch 启用 USB 接口
Source: [https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html](https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html)
本节提供有关如何通过 Qualcomm Linux 硬件 SoC 中的 PCIe switch 激活 USB 接口的说明。PCIE1 实例连接到 QPS615 switch 的端点，QPS615 的下游端口连接到 PCIe 转 USB 端点。有关使用 QPS615 进行 PCIe 转 USB 端点连接的信息，请参见 [https://docs.qualcomm.com/bundle/publicresource/topics/80-70022-251/rb3_hardware_overview.html](https://docs.qualcomm.com/bundle/publicresource/topics/80-70022-251/rb3_hardware_overview.html) 中的主板和转接板框图。
Note: Dragonwing IQ-9075 PCIe 软件不支持 USB。
### 启用 PCIe 转 USB 控制器的电源
为通过 QPS615 switch 连接的 PCIe 转 USB 控制器开启电源，并使用 GPIO162 对连接的外部 USB 集线器进行复位操作。本方法是正确检测 USB 外设并使其正常工作的必要条件。
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-addons-rb3gen2.dtsi b/arch/arm64/boot/dts/qcom/qcs6490-addons-rb3gen2.dtsi
index bf95b66..4a76a36 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-addons-rb3gen2.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs6490-addons-rb3gen2.dtsi
@@ -40,6 +40,37 @@
regulator-enable-ramp-delay = <10000>;
};
+ upd_3p3_vreg: upd_3p3_vreg {
+ compatible = "regulator-fixed";
+ regulator-name = "upd_3p3_vreg";
+ gpio = <&pm7250b_gpios 1 0>;
+ vin-supply = <&qps615_rsex_vreg>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ regulator-enable-ramp-delay = <10000>;
+ regulator-always-on;
+ };
+
+ upd_rest_vreg: upd_rest_vreg {
+ compatible = "regulator-fixed";
+ regulator-name = "upd_rest_vreg";
+ gpio = <&pm8350c_gpios 4 0>;
+ vin-supply = <&upd_3p3_vreg>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ usbhub_rest_vreg: usbhub_rest_vreg {
+ compatible = "regulator-fixed";
+ regulator-name = "usbhub_rest_vreg";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_usb_hub_reset_default>;
+ gpio = <&tlmm 162 GPIO_ACTIVE_LOW>;
+ enable-active-high;
+ };
};
&i2c0 {
@@ -165,6 +196,14 @@
bias-pull-down;
input-enable;
};
+
+ pcie1_usb_hub_reset_default: pcie1_usb_hub_reset_default {
+ pins = "gpio162";
+ function = "gpio";
+ drive-strength = <2>;
+ output-high;
+ bias-pull-down;
+ };
};
Copy to clipboard
### 避免 PCIe 转 USB 控制器过早切换
由于固件未加载，请确保 PCIe 转 USB 控制器跳过 `usb_early-handoff`。采取此预防措施是为了避免对启动时长造成任何不利影响。
diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c
index 2665832..c3d488f 100644
--- a/drivers/usb/host/pci-quirks.c
+++ b/drivers/usb/host/pci-quirks.c
@@ -1260,6 +1260,11 @@
return;
}
+ /* Skip handoff for Renesas PCI USB controller on QCOM SOC */
+ if ((pdev->vendor == PCI_VENDOR_ID_RENESAS) &&
+ (pcie_find_root_port(pdev)->vendor == PCI_VENDOR_ID_QCOM))
+ return;
+
if (pdev->class != PCI_CLASS_SERIAL_USB_UHCI &&
pdev->class != PCI_CLASS_SERIAL_USB_OHCI &&
pdev->class != PCI_CLASS_SERIAL_USB_EHCI &&
Copy to clipboard
### 下载 PCIe 转 USB 控制器固件
要访问 [https://www.renesas.com/us/en/products/interface/usb-switches-hubs/upd720201-usb-30-host-controller#design_development](https://www.renesas.com/us/en/products/interface/usb-switches-hubs/upd720201-usb-30-host-controller#design_development) 下载固件，应先进行注册并登录 [https://www.renesas.com/](https://www.renesas.com/)。
Note: 为防止命令失败，请在更新 Renesas 固件之前，按照[设置设备](https://docs.qualcomm.com/bundle/publicresource/topics/80-70022-251/set_up_the_device.html)部分中的说明更新软件。
1. 通过在 Linux 主机上运行以下命令来创建 `usb_fw.img` 镜像并复制 USB 固件。
dd if=/dev/zero of=usb_fw.img bs=4k count=240Copy to clipboard
mkfs -t ext4 usb_fw.imgCopy to clipboard
mkdir usb_fwCopy to clipboard
sudo mount -o loop usb_fw.img usb_fw/Copy to clipboard
sudo cp -rf renesas_usb_fw.mem usb_fwCopy to clipboard
sudo umount usb_fwCopy to clipboard
2. 以 fastboot 模式启动设备。
adb rootCopy to clipboard
adb shellCopy to clipboard
reboot bootloaderCopy to clipboard
3. 当设备处于 fastboot 模式时，运行以下命令。
fastboot devicesCopy to clipboard
示例输出：
7dc85f5e fastbootCopy to clipboard
4. 将 `usb_fw.img`
镜像刷写到设备。
fastboot erase usb_fwCopy to clipboard
fastboot flash usb_fw usb_fw.imgCopy to clipboard
fastboot rebootCopy to clipboard
命令失败示例：
c:\>fastboot erase usb_fw
Erasing 'usb_fw' FAILED (remote: 'Check device console.')
fastboot: error: Command failedCopy to clipboard
5. 要验证固件是否已成功更新，请运行以下命令。
dmesgCopy to clipboard
固件更新成功后的日志示例。
[ 6.589462] usbcore: registered new device driver onboard-usb-hub
[ 6.653277] usb 2-1: new SuperSpeed USB device number 2 using xhci_hcd
[ 7.013061] usb 2-1.1: new SuperSpeed USB device number 3 using xhci_hcd
[ 7.120657] ax88179_178a 2-1.1:1.0 eth0: register 'ax88179_178a' at usb-0001:04:00.0-1.1, ASIX AX88179 USB 3.0 Gigabit Ethernet, 3e:9e:5e:ff:d3:fb
[ 7.120767] usbcore: registered new interface driver ax88179_178a
Copy to clipboard
### PCIe 转 USB 设备枚举参考的 PCIe 内核驱动程序日志
可以运行以下命令查看设备信息：
- 要显示 USB 中的设备信息，请运行以下命令。
lsusbCopy to clipboard
随即显示以下消息。
Bus 002 Device 003: ID 0b95:1790 ASIX Electronics Corp. AX88179 Gigabit Ethernet
Bus 002 Device 002: ID 05e3:0625 Genesys Logic, Inc. USB3.2 Hub
Bus 002 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 001 Device 002: ID 05e3:0610 Genesys Logic, Inc. Hub
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Copy to clipboard
- 要显示 PCIe 中的设备信息，请运行以下命令。
lspciCopy to clipboard
随即显示以下消息。
0001:00:00.0 PCI bridge: Qualcomm Device 010b
0001:01:00.0 PCI bridge: Toshiba Corporation Device 0623
0001:02:01.0 PCI bridge: Toshiba Corporation Device 0623
0001:02:02.0 PCI bridge: Toshiba Corporation Device 0623
0001:02:03.0 PCI bridge: Toshiba Corporation Device 0623
0001:04:00.0 USB controller: Renesas Technology Corp. uPD720201 USB 3.0 Host Controller (rev 03)
0001:05:00.0 Ethernet controller: Toshiba Corporation Device 0220
0001:05:00.1 Ethernet controller: Toshiba Corporation Device 0220
Copy to clipboard
## 级联连接 QPS615 switch
Source: [https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html](https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html)
级联连接 QPS615 switch 以启用额外的以太网、PCIe 和 USB 端口。
Note: 仅 QCS6490 支持此功能。
下图显示了两台 QPS615 switch 级联连接到 PCIE1，另一台 QPS615 switch 连接到 PCIE2。
要启动所有端点的链路训练和枚举，请执行以下操作：
1. 要复位 QPS615 switch，请切换 QPS615 #1 和 QPS615 #2 的 RESX GPIO。
2. 要控制端点复位，请触发 PERST。两台 switch 共享 PERST。
这些设备可以直接连接到 QPS615 switch。PCIe RC0 连接到 WLAN 端点。以下差异是由于 PCIe 节点层次结构造成的。
- Switch 连接设备：
- QPS615 PCIe 树节点层次结构是静态固定的。
- 所有用于切换 USP 和 DSP 端口的节点均在 PCIe 初始化期间创建。
- Switch DSP 端口之一代表 WLAN。
- 如果禁用 WLAN 节点，则会禁用 WLAN 设备，但 PCIe 下游端口保持启用状态并返回默认的最大链路宽度。
- 直连 WLAN 设备：
- 仅禁用单个节点。
- 当 WLAN 禁用时，返回 Invalid 参数。
## 启用 NVMe over PCIe
Source: [https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html](https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html)
本节介绍可如何启用 NVMe over PCIe 进行存储扩展。要验证 NVMe 是否通过 PCIe 接口连接，请执行以下操作：
1. 要显示 PCIe 设备信息，请运行以下命令。
lspciCopy to clipboard
输出：
0000:00:00.0 PCI bridge: Qualcomm Device 01150000:01:00.0 Network controller: Qualcomm QCNFA765 Wireless Network Adapter (rev 01)0001:00:00.0 PCI bridge: Qualcomm Device 01150001:01:00.0 Non-Volatile memory controller: Samsung Electronics Co Ltd NVMe SSD Controller PM9A1/PM9A3/980PROCopy to clipboard
2. 找到 PCIe 日志。
dmesg | grep pcieCopy to clipboard
输出：
[ 0.000000] Kernel command line: root=/dev/disk/by-partlabel/system rw rootwait console=ttyMSM0,115200n8
pcie_pme=nomsi net.ifnames=0 pci=noaer kpti=off kasan=off kasan.stacktrace=off swiotlb=128 earlycon reboot=panic_warm page_owner=on qcom_scm.download_mode=1 slub_debug=FZP,
zs_handle,zspage;FZPU mitigations=auto kernel.sched_pelt_multiplier=4 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 no-steal-acc vfio_iommu_type1.allow_unsafe_interrupts=1 fw_devlink.strict=1[ 3.842071] qcom-pcie 1c00000.pci: supply vdda not found, using dummy regulator[ 3.845339] qcom-pcie 1c10000.pci: supply vdda not found, using dummy regulator[ 3.845428] qcom-pcie 1c10000.pci: supply vddpe-3v3 not found, using dummy regulator[ 3.845508] qcom-pcie 1c10000.pci: host bridge /pci@1c10000 ranges:[ 3.845519] qcom-pcie 1c10000.pci: IO 0x0060200000..0x00602fffff -> 0x0000000000[ 3.845526] qcom-pcie 1c10000.pci: MEM 0x0060300000..0x007fffffff -> 0x0060300000[ 3.848154] qcom-pcie 1c00000.pci: supply vddpe-3v3 not found, using dummy regulator[ 3.854556] qcom-pcie 1c00000.pci: host bridge /pci@1c00000 ranges:[ 3.860574] qcom-pcie 1c00000.pci: IO 0x0040200000..0x00402fffff -> 0x0000000000[ 3.867362] qcom-pcie 1c00000.pci: MEM 0x0040300000..0x005fffffff -> 0x0040300000[ 3.963275] qcom-pcie 1c10000.pci: iATU: unroll T, 32 ob, 8 ib, align 4K, limit 1024G[ 3.990385] qcom-pcie 1c00000.pci: iATU: unroll T, 32 ob, 8 ib, align 4K, limit 1024G[ 4.072091] qcom-pcie 1c10000.pci: PCIe Gen.4 x2 link up[ 4.080241] qcom-pcie 1c10000.pci: PCI host bridge to bus 0001:00[ 4.291824] pcieport 0001:00:00.0: Adding to iommu group 9[ 4.551677] pcieport 0001:00:00.0: PME: Signaling with IRQ 256[ 4.572484] WARNING: CPU: 3 PID: 89 at drivers/pci/controller/dwc/pcie-qcom.c:1430 qcom_pcie_icc_update+0xf8/0x144[ 4.595291] pc : qcom_pcie_icc_update+0xf8/0x144[ 4.595293] lr : qcom_pcie_icc_update+0x9c/0x144[ 4.640742] qcom_pcie_icc_update+0xf8/0x144[ 4.640745] qcom_pcie_probe+0x234/0x30c[ 4.988519] qcom-pcie 1c00000.pci: Phy link never came up[ 5.302179] qcom-pcie 1c00000.pci: PCI host bridge to bus 0000:00[ 5.372008] pcieport 0000:00:00.0: Adding to iommu group 10[ 5.378905] pcieport 0000:00:00.0: PME: Signaling with IRQ 257[ 11.564590] pcieport 0000:00:00.0: BAR 14: assigned [mem 0x40400000-0x405fffff]Copy to clipboard
3. 要找到 NVMe 目录，请运行以下命令。
ls -lh /dev/nvme*Copy to clipboard
输出：
crw-------. 1 root root 508, 0 Jan 1 00:00 /dev/nvme0brw-rw----. 1 root disk 259, 30 Jan 1 00:00 /dev/nvme0n1Copy to clipboard
## PCIe 客户端驱动程序示例
Source: [https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html](https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html)
客户端驱动程序定义 `device-id` 表和 `pci_driver` 结构体，并注册到 PCIe
框架。以下是一些 PCIe 客户端驱动程序示例，供参考。
- 用于保存特定于客户端的私有数据的示例数据结构。
struct sample_driver_data {
int driver_data;
};Copy to clipboard
- 示例驱动程序：用户可以根据驱动程序特定的数据结构提供数据。
struct sample_driver_data info = {};Copy to clipboard
- 包含驱动程序特定数据的示例设备 ID 表。客户端驱动程序使用 `0x306` 设备 ID
进行注册。
static const struct pci_device_id sample_pci_id_table[] = {
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, PCI_VENDOR_ID_QCOM, 0x010c),
.driver_data = (kernel_ulong_t) &info },
{ }
};
MODULE_DEVICE_TABLE(pci, sample_pci_id_table);Copy to clipboard
Note: `MODULE_DEVICE_TABLE(pci,
sample_pci_id_table);` 为必填项。
- 包含客户端驱动程序名称、 `pci-id` 表和回调的示例 `pci_driver` 数据结构。向 PCI
框架注册时会传递指向该结构的指针。
static struct pci_driver sample_pci_driver = {
.name = "Sample-PCI-Client-driver", /* Give the name that suites your driver description */
.id_table = sample_pci_id_table, /* pci core driver will compare from ids's supplied in this table with the enumerated endpoints */
.probe = sample_pci_probe, /* probe function is invoked by the PCI f/w when id matches with the endpoint id's */
.remove = sample_pci_remove, /* Remove function is invoked by PCI f/w when senses the attached endpoint/function is detached or down */
.driver.pm = &sample_pci_pm_ops /* pm ops that will be called from the pci core driver*/
};Copy to clipboard
- 要注册 PCI 固件，请从 `module_init()` 中调用
`pci_register_driver(&sample_pci_driver)`。
module_pci_driver(sample_pci_driver);Copy to clipboard
## PCIe 调通
Source: [https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html](https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html)
有关 PCIe 调通的信息，请参阅 [PCIe 相关配置](https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html#pcie-software-support-feature-for-qps615__section_xbl_hhd_l1c)和 [QPS615 switch 支持](https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html#pcie-software-support-feature-for-qps615__section_nmw_5jd_l1c)。
## PCIe 功耗优化
Source: [https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html](https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html)
PCIe 定义了两种功耗管理方法。
- 功耗管理软件，用于确定每个设备的功耗管理功能并分别对各个设备进行管理
- 不需要软件干预的系统，例如主动状态功耗管理 (ASPM)
当链路上未传输任何数据包时，设备会将链路置于节能状态。
### PCIe L0 链路状态
PCIe 功耗管理定义了以下 L0 链路状态：
- L0：活动状态，在该状态下启用所有 PCIe 事务和其他操作
- L0s：具有低恢复延迟的 ASPM 状态（节能待机状态）
### PCIe 设备状态
PCIe 功耗管理定义了以下设备状态：
- D0（必选）：设备处于完全 ON 状态，此时存在两个子状态
- D0uninitialized：当设备退出复位状态后等待枚举和配置时，该功能处于 D0uninitialized 状态。
- D0active
- 当完成枚举和配置过程后，该功能处于 D0active 状态。
- 当系统软件启用一个或多个（任意组合）功能参数（如内存空间启用、I/O 空间启用或 BME 位）时，该功能将进入 D0active 状态。
- D1（可选）：轻度休眠状态
- 除了 PME 消息之外，该功能无法发起 TLP
- 除了配置事务之外，该功能不能充当其他事务的目标对象。
- 该功能通过发出设定 PM 控制和状态寄存器的软件命令来进入 D1 状态。
- D2（可选）：深度休眠状态
- 除了 PME 消息之外，该功能无法发起 TLP
- 除了配置事务之外，该功能不能充当其他事务的目标对象。
- 该功能通过发出设定 PM 控制和状态寄存器的软件命令来进入 D2 状态。
- D3（必选）：设备处于最低功耗状态，此时该功能必须支持两种 D3 状态
- D3hot
- 除了 PME 消息之外，该功能无法发起 TLP。
- 除了配置事务之外，该功能不能充当其他事务的目标对象。
- 该功能通过设定功耗状态位域发出软件命令来进入 D3hot 状态。
- D3cold：设备进入 D3cold 状态并断电；当恢复供电时，设备进入 D0uninitialized 状态。
## PCIe 验证
Source: [https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html](https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html)
有关 PCIe 验证的信息，请参阅 [PCIe 相关配置](https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html#pcie-software-support-feature-for-qps615__section_xbl_hhd_l1c)和 [QPS615 switch 支持](https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html#pcie-software-support-feature-for-qps615__section_nmw_5jd_l1c)。
## 调试 PCIe 问题
Source: [https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html](https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html)
`lspci` 和 `setpci` 命令为 Linux
发行版的本机命令。这两条命令提供多种级别的输出，并且还可用于在某个时间点查看 PCI 总线上训练的不同组件的功能和状态。这些功能大多反映的是 PCIe
基本规范所需的配置空间寄存器。更多详细信息，可访问 [https://pcisig.com/specifications](https://pcisig.com/specifications)。如需查看使用说明，可运行以下命令。
lspci --helpCopy to clipboard
以下功能有助于解决 PCIe 问题。
- 显示设备信息
lspciCopy to clipboard
随即显示以下消息。
0001:00:00.0 PCI bridge: Qualcomm Device 010b
0001:01:00.0 PCI bridge: Toshiba Corporation Device 0623
0001:02:01.0 PCI bridge: Toshiba Corporation Device 0623
0001:02:02.0 PCI bridge: Toshiba Corporation Device 0623
0001:02:03.0 PCI bridge: Toshiba Corporation Device 0623
0001:04:00.0 USB controller: Renesas Technology Corp. uPD720201 USB 3.0 Host Controller (rev 03)
0001:05:00.0 Ethernet controller: Toshiba Corporation Device 0220
0001:05:00.1 Ethernet controller: Toshiba Corporation Device 0220Copy to clipboard
- 显示设备控制寄存器中的 PCIe 设备和厂商 ID。
lspci -nvmmCopy to clipboard
随即显示以下消息。
Slot: 0001:00:00.0
Class: 0604
Vendor: 17cb
Device: 010b
DTNode: /sys/firmware/devicetree/base/soc@0/pci@1c08000/pcie@0
IOMMUGroup: 33
Slot: 0001:01:00.0
Class: 0604
Vendor: 1179
Device: 0623
DTNode: /sys/firmware/devicetree/base/soc@0/pci@1c08000/pcie@0/pcie1_bus1_dev0_fn0
IOMMUGroup: 33
Slot: 0001:02:01.0
Class: 0604
Vendor: 1179
Device: 0623
DTNode: /sys/firmware/devicetree/base/soc@0/pci@1c08000/pcie@0/pcie1_bus1_dev0_fn0/pcie1_bus2_dev1_fn0
IOMMUGroup: 33
Slot: 0001:02:02.0
Class: 0604
Vendor: 1179
Device: 0623
DTNode: /sys/firmware/devicetree/base/soc@0/pci@1c08000/pcie@0/pcie1_bus1_dev0_fn0/pcie1_bus2_dev2_fn0
IOMMUGroup: 33
Slot: 0001:02:03.0
Class: 0604
Vendor: 1179
Device: 0623
DTNode: /sys/firmware/devicetree/base/soc@0/pci@1c08000/pcie@0/pcie1_bus1_dev0_fn0/pcie1_bus2_dev3_fn0
IOMMUGroup: 33
Slot: 0001:04:00.0
Class: 0c03
Vendor: 1912
Device: 0014
Rev: 03
ProgIf: 30
DTNode: /sys/firmware/devicetree/base/soc@0/pci@1c08000/pcie@0/pcie1_bus1_dev0_fn0/pcie1_bus2_dev2_fn0/pcie1_bus4_dev0_fn0
IOMMUGroup: 33
Slot: 0001:05:00.0
Class: 0200
Vendor: 1179
Device: 0220
SVendor: 1179
SDevice: 0001
DTNode: /sys/firmware/devicetree/base/soc@0/pci@1c08000/pcie@0/pcie1_bus1_dev0_fn0/pcie1_bus2_dev3_fn0/qps615_eth0,qps615_eth0@pcie1_rp
IOMMUGroup: 33
Slot: 0001:05:00.1
Class: 0200
Vendor: 1179
Device: 0220
SVendor: 1179
SDevice: 0001
DTNode: /sys/firmware/devicetree/base/soc@0/pci@1c08000/pcie@0/pcie1_bus1_dev0_fn0/pcie1_bus2_dev3_fn0/qps615_eth1,qps615_eth1@pcie1_rp
IOMMUGroup: 33Copy to clipboard
有关 PCIe 调试的更多信息，可访问 [https://www.kernel.org/doc/html/v4.17/driver-api/pci.html](https://www.kernel.org/doc/html/v4.17/driver-api/pci.html)。
## PCIe 示例
Source: [https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html](https://docs.qualcomm.com/doc/80-70022-8SC/topic/pcie.html)
有关上游设备树参考的信息，请参阅以下文件。
- QCS6490 和 QCS5430：[https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/sc7280.dtsi](https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/sc7280.dtsi)
- Dragonwing IQ-9075: [https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/sa8775p.dtsi](https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/sa8775p.dtsi)
- Dragonwing IQ-615: [https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git/tree/arch/arm64/boot/dts/qcom/qcs615.dtsi?h=arm64-for-6.16](https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git/tree/arch/arm64/boot/dts/qcom/qcs615.dtsi?h=arm64-for-6.16)
- [https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/dwc/pcie-qcom.c?h=v6.8-rc6#n1634](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/dwc/pcie-qcom.c?h=v6.8-rc6#n1634)
有关 Qualcomm Linux 硬件 SoC 的设备树节点的信息，请参阅以下 DTSI 文件。
- QCS6490 和 QCS5430：[https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts](https://git.linaro.org/kernel-org/linux-next.git/tree/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts)
- Dragonwing IQ-9075: [https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/sa8775p.dtsi](https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/sa8775p.dtsi)
- Dragonwing IQ-615: [https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git/tree/arch/arm64/boot/dts/qcom/qcs615.dtsi?h=arm64-for-6.16](https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git/tree/arch/arm64/boot/dts/qcom/qcs615.dtsi?h=arm64-for-6.16)
### 客户端和 PCI 驱动程序操作流程示例
下图显示了 PCIe 客户端驱动程序为客户端配置 PCIe 驱动程序的步骤。
### 客户端和 PCI 驱动程序高层调用流程示例
下图显示了 PCIe 客户端驱动程序与 PCIe 驱动程序之间的高层调用流程和调用详细信息。
Last Published: Nov 05, 2025
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