# Dragonwing IQ-615 interface overview

Source: [https://docs.qualcomm.com/doc/80-70023-8/topic/iq-615-interface-overview.html](https://docs.qualcomm.com/doc/80-70023-8/topic/iq-615-interface-overview.html)

The following table lists the device interface features in Dragonwing IQ-615.

| 2xQUP v3 serial engine | 2xQUP v3 serial engine | 2xQUP v3 serial engine |
| --- | --- | --- |
| Serial engine instances | QUPV3\_0 | QUPV3\_1 |
| Application processor QUP v3 serial engine | 4 | 3 |
| **2xUSB controller** | **2xUSB controller** | **2xUSB controller** |
| Controller address | 0xa600000 | 0xa800000 |
| Max speed | USB 3.x SuperSpeed | USB 2.0 high speed |
| HS/SS PHY power rails | L4A: VDDD\_QUSB\_0\_HS0\_0P9 | L4A:  VDDD\_QUSB\_1\_HS0\_0P9 |
| HS/SS PHY power rails | L11A: VDDA\_QUSB\_0\_HS0\_1P8 | L11A: VDDA\_QUSB\_1\_HS0\_1P8 |
| HS/SS PHY power rails | L17A: VDDA\_QUSB\_0\_HS0\_3P1 | L17A: VDDA\_QUSB\_1\_HS0\_3P1 |
| **1xPCIe controller** | **1xPCIe controller** | **1xPCIe controller** |
| Root complex | RC0 (0x1c08000) | – |
| Speed | Gen2 | – |
| Configuration space | 0x40100000 (0x100000) 1 MB | – |
| I/O space | 0x40200000 (0x100000) 1 MB | – |
| Base address Register space (BAR) | 0x40300000 (0x1fd00000) 509 MB | – |
| Power rails | L12A (vreg-1p2-supply) | – |
| Power rails | L5A (vreg-0p9-supply) | – |
| Interrupts | MSI and PCI legacy interrupts | – |
| Power management | ASPM (L1/L1ss, L0s) | – |
|  |  |  |
|  |  |  |

## QUP v3 mapping to protocols and GPIOs in Dragonwing IQ-615

Dragonwing IQ-615 has two QUP v3 serial engines. The following table list the protocol and GPIO
                mapping.

| QUP v3 serial<br>                                engine | QUP v3 serial<br>                                engine | Protocols | Protocols | Protocols | Protocols | QUP lane to GPIO mapping | QUP lane to GPIO mapping | QUP lane to GPIO mapping | QUP lane to GPIO mapping | QUP lane to GPIO mapping | QUP lane to GPIO mapping | QUP lane to GPIO mapping |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| QUP v3 serial<br>                                engine | QUP v3 serial<br>                                engine | UART | HS UART | I2C-M | SPI-M | L0 | L1 | L2 | L3 | L4 | L5 | L6 |
| QUP\_0 | SE0 | Yes | – | Yes | Yes | 20 | 21 | 22 | 23 | – | – | – |
| QUP\_0 | SE1 | – | – | Yes | – | 14 | 15 | – | – | – | – | – |
| QUP\_0 | SE2 | Yes | – | Yes | Yes | 6 | 7 | 8 | 9 | – | – | – |
| QUP\_0 | SE3 | Yes | Yes | Yes | Yes | 10 | 11 | 12 | 13 | – | – | – |
| QUP\_1 | SE1 | – | – | Yes | – | 4 | 5 | – | – | – | – | – |
| QUP\_1 | SE2 | Yes | – | Yes | Yes | 0 | 1 | 2 | 3 | – | – | – |
| QUP\_1 | SE3 | – | – | Yes | – | 18 | 19 | – | – | – | – | – |
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**Parent Topic:** [Overview of peripheral interfaces](https://docs.qualcomm.com/doc/80-70023-8/topic/overview-of-wired-interfaces.html)

Last Published: Dec 23, 2025

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