OFF: off-board DMIC (LS2 connector) | ON |
| 2 | Debug UART | ON: enable serial log (debug UART)
OFF: disable serial log (off-board UART) | ON |
| 3 | N/A | – | – |
| 4 | HDMI switch | ON: HDMI disabled
OFF: HDMI enabled | OFF |
| 5 | Sensor IMU toggle | ON: on-board IMU disabled
OFF: on-board IMU enabled | OFF |
| 6 | IMU external clock | ON: external clock to IMU
OFF: no external clock to IMU | OFF |
The following flowcharts show how the DIP switch settings on the mainboard control the routing of signals from/to connectors and components. For additional context on the signals, switches, and connectors, see [block diagram](https://docs.qualcomm.com/doc/80-70030-251/topic/rb3_hardware_overview.html#mainboard-interposer-block-diagram).
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> **Figure: Circuits controlled by DIP switches on the mainboard**
### Interposer DIP switches
The following image shows the location of the interposer DIP switches.
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> **Figure: DIP switches on the interposer**
The interposer board has three boot configuration DIP switches. The following tables list the interposer DIP switches along with their functionalities:
| DIP\_SW\_2 | Name | Details | Default |
| --- | --- | --- | --- |
| 1 | BOOT\_CONFIG\_1 [GPIO\_120] | Selects external boot devices | OFF |
| 2 | BOOT\_CONFIG\_2 [GPIO\_122] | Selects external boot devices | OFF |
| 3 | BOOT\_CONFIG\_3 [GPIO\_124] | Selects external boot devices | OFF |
| 4 | BOOT\_CONFIG\_0 [GPIO\_118] | ON: disables watchdog
ON: CSI3 input from Vision mezzanine CAM5 (GMSL) | OFF |
| 2 | PCIE\_DIP\_SW | ON: QPS 1 Lane PCIe goes to mainboard 500 pin (HS expansion PCIE2)
OFF: QPS 1 Lane PCIe goes to PCIE2USB (uPD) | OFF |
Table: Interposer DIP switch selection (DIP_SW_4)
| DIP\_SW\_4 | Name | Details | Default |
| --- | --- | --- | --- |
| 1 | CSI1\_DIP\_SW | ON: CSI1 input from interposer CPHY CAM1
OFF: CSI1 input from Vision mezzanine CAM1 | OFF |
| 2 | CSI2\_DIP\_SW | ON: CSI2 input from interposer CPHY CAM2
OFF: CSI2 input from Vision mezzanine CAM2 | OFF |
| 3 | QSPI\_CAN\_DIP\_SW | ON: not supported
OFF: SPI to CAN interface on mainboard | OFF |
| 4 | QSPI\_GPIO\_DIP\_SW | ON: not supported
OFF: SPI to CAN interface on mainboard | OFF |
The following flowcharts show how the DIP switch settings on the interposer control the routing of signals from/to connectors and components. For additional context on the signals, switches, and connectors, see [block diagram](https://docs.qualcomm.com/doc/80-70030-251/topic/rb3_hardware_overview.html#mainboard-interposer-block-diagram).
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> **Figure: Circuits controlled by DIP switches on the interposer**
### Vision mezzanine DIP switches
The following image shows the location of the DIP switches on the Vision mezzanine.
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> **Figure: Vision mezzanine DIP switches**
The following tables list the Vision mezzanine DIP switches along with their functionalities:
Table: Vision mezzanine DIP switches (DIP1)
| DIP1 | Name | Details | Default |
| --- | --- | --- | --- |
| 1 | SENSOR\_SPI\_PASSTHRU | ON: Snapdragon sensor core (SSC) sensor SPI routed to IMU\_SPI\_SELECT switch
OFF: IMU sensor SPI passthrough | OFF |
| 2 | APPS\_SPI\_PASSTHRU | ON: Application processor SPI routed to IMU\_SPI\_SELECT switch
OFF: passthrough | OFF |
| 3 | CAM2\_APPS\_SPI\_PASSTHRU | ON: SPI to CAM2 connector
OFF: passthrough | OFF |
| 4 | PRESS\_SENS\_DISCONNECT | ON: on-board
OFF: disconnected | ON |
| 5 | MAG\_SENSOR\_DISCONNECT | ON: on-board
OFF: disconnected | ON |
| 6 | UART0\_PASSTHRU | ON: on-board
OFF: passthrough | OFF |
Table: Vision mezzanine DIP switches (DIP2)
| DIP2 | Name | Details | Default |
| --- | --- | --- | --- |
| 1 | DIP\_CSI0A\_B\_SWITCH | ON: CSI0 all 4 lanes to CAM0A
OFF: CSI0 2 lanes to CAM0A, 1 lane to CAM0B | OFF |
| 2 | MIC\_DISCONNECT | ON: DMIC 2/3 connects to on-board mics
OFF: DMIC 2/3 passthrough | ON |
| 3 | IMU\_SPI\_SELECT | ON: connects IMU to APPS SPI – only if DIP 1:2 is ON
OFF: connects IMU to SSC SPI – only if DIP 1:1 is ON | OFF |
| 4 | IMU\_INT\_1\_2\_SELECT\_LOGIC1 | ON: IMU INT1 to GYRO\_INT, IMU INT2 to PMIC clock
OFF: IMU INT1 and 2 connected to IMU sensor switch | OFF |
| 5 | IMU\_INT\_1\_2\_SELECT\_LOGIC2 | ON: IMU INT1 to ACCEL\_INT, IMU INT2 to GYRO\_INT
OFF: IMU INT 1 and 2 disconnected | OFF |
| 6 | PRESSURE\_COMPASS\_SELECT | ON: Pressure/Compass connected to APPS I2C
OFF: Pressure/Compass connected to sensor core I2C | OFF |
The following flowcharts show how the DIP switch settings on the Vision mezzanine control the routing of signals from/to connectors and components. For additional context on the signals, switches, and connectors, see [block diagram](https://docs.qualcomm.com/doc/80-70030-251/topic/rb3_hardware_overview.html#mainboard-interposer-block-diagram).
**Figure: Circuits controlled by DIP switches on the Vision mezzanine**
## Connect a custom camera sensor
If your camera sensor connector matches the Dragonwing RB3 Gen 2 board, you can use it directly. For connector details, see [Design Package, RB5/RB5GEN2/RB3GEN2 Navigation Mezzanine](https://www.qualcomm.com/search?query=DP25-PV086-43#q=DP25-PV086-43&tab=all).
**Vision mezzanine camera connectors**
Otherwise, create an interface PCB to convert the pinout from the Vision mezzanine to match your camera sensor signals. The following example assumes a fisheye camera to be tested with the Dragonwing RB3 Gen 2 Development Kit. Two different flex cables (Flex\_A and Flex\_B) are also required.
**Figure: Vision mezzanine with interface PCB**
A custom Vision mezzanine board can also be designed to host more than one camera connector. See [Design Package, RB5 Generic Mezz Card Schematic and Layout, IOT](https://www.qualcomm.com/search?query=DP25-63340-1#q=DP25-63340-1&tab=all).
### Camera connectors on the Dragonwing RB3 Gen 2 Development Kit
The CAM1 and CAM2 connectors on the interposer shown in the following figure support C-PHY/D-PHY. The connectors on the [Vision mezzanine](https://docs.qualcomm.com/doc/80-70030-251/topic/references.html#vision-mezz-connectors) support D-PHY only.
**Figure: Interposer camera connectors**
The following images show details for the CAM1 and CAM2 connectors on the interposer:
**Figure: J800 connector pinout for camera (CAM1) interface**
**Figure: J900 connector pinout for camera (CAM2) interface**
### Vision mezzanine pinouts
The following table lists the pinout locations on the Vision mezzanine:
| RB5 4 Lane MIPI CSI Connectors | RB5 4 Lane MIPI CSI Connectors | RB5 4 Lane MIPI CSI Connectors | RB5 4 Lane MIPI CSI Connectors | RB5 4 Lane MIPI CSI Connectors | RB5 4 Lane MIPI CSI Connectors |
| --- | --- | --- | --- | --- | --- |
| Pin | CAM0A | CAM1 | CAM2 | CAM3 | Notes |
| 1 | Strobe (GPIO) | Strobe (GPIO) | Strobe (GPIO) | Strobe (GPIO) | Strobe not typically used by most modules |
| 2 | Spare (GPIO) | Spare (GPIO) | Spare (GPIO), Optionally SPI\_CLK | Spare (GPIO) | Spare not typically used by most modules |
| 3 | 2V8 | 2V8 | 2V8 | 2V8 or 5V | |
| 4 | GND | GND | Optionally SPI\_MOSI | GND | |
| 5 | Reset (GPIO) | Reset (GPIO) | Reset (GPIO) | Reset (GPIO) | Key GPIO |
| 6 | GND | GND | GND, for CAM2, this pin can be remapped to a 32 kHz SLEEP\_CLK. GND is the default. | GND | |
| 7 | CSI\_D2\_P | CSI\_D2\_P | CSI\_D2\_P | CSI\_D2\_P | |
| 8 | CSI\_D2\_M | CSI\_D2\_M | CSI\_D2\_M | CSI\_D2\_M | |
| 9 | GND | GND | GND | GND | |
| 10 | CSI\_D0\_P | CSI\_D0\_P | CSI\_D0\_P | CSI\_D0\_P | |
| 11 | CSI\_D0\_M | CSI\_D0\_M | CSI\_D0\_M | CSI\_D0\_M | |
| 12 | GND | GND | GND | GND | |
| 13 | CSI\_D3\_P | CSI\_D3\_P | CSI\_D3\_P | CSI\_D3\_P | |
| 14 | CSI\_D3\_M | CSI\_D3\_M | CSI\_D3\_M | CSI\_D3\_M | |
| 15 | CAM\_PWR\_SWITCH | CAM\_PWR\_SWITCH | CAM\_PWR\_SWITCH | CAM\_PWR\_SWITCH | Controls 1V1 or 1V2 selection on pin 30. Pull low to GND for 1.1V, pull high to 1V8 rail on the flex for 1V2. |
| 16 | 0R to GND | 0R to GND | 0R to GND | CAM\_PWR\_SWITCH2 | CAM3 only: Pull low to GND for normal operation (1V1/1V2, 1V8, 2V8). Pull high to Pin 28 for 5V on all three power pins. |
| 17 | CSI\_D1\_M | CSI\_D1\_M | CSI\_D1\_M | CSI\_D1\_M | |
| 18 | CSI\_D1\_P | CSI\_D1\_P | CSI\_D1\_P | CSI\_D1\_P | |
| 19 | GND | GND | GND | GND | |
| 20 | CSI\_C\_M | CSI\_C\_M | CSI\_C\_M | CSI\_C\_M | |
| 21 | CSI\_C\_P | CSI\_C\_P | CSI\_C\_P | CSI\_C\_P | |
| 22 | GND | GND | GND | GND | |
| 23 | MCLK | MCLK | MCLK | MCLK | Key GPIO |
| 24 | GND | GND | GND | GND | |
| 25 | SCL | SCL | SCL | SCL | Key GPIO |
| 26 | SDA | SDA | SDA | SDA | Key GPIO |
| 27 | PWDN/Sync to CAM0B | PWDN | Optionally SPI\_CS | PWDN | PWDN not typically used by most modules |
| 28 | 1V8 | 1V8 | 1V8 | 1V8 or 5V | |
| 29 | GND | GND | Optionally SPI\_MISO | GND | |
| 30 | 1V1 or 1V2 | 1V1 or 1V2 | 1V1 or 1V2 | 1V2 or 5V | |
| - General notes: - Only camera interfaces with 4 D-PHY lanes are shown. The Qualcomm software uses RST and MCLK only. The other GPIO pins can be used for other purposes as they aren’t nominally routed to anything in the software. CAM0A and CAM0B can be synchronized using pin 27. Optional SPI bus on CAM2 is connected to the application processor block, not the DSP block. | - General notes: - Only camera interfaces with 4 D-PHY lanes are shown. The Qualcomm software uses RST and MCLK only. The other GPIO pins can be used for other purposes as they aren’t nominally routed to anything in the software. CAM0A and CAM0B can be synchronized using pin 27. Optional SPI bus on CAM2 is connected to the application processor block, not the DSP block. | - General notes: - Only camera interfaces with 4 D-PHY lanes are shown. The Qualcomm software uses RST and MCLK only. The other GPIO pins can be used for other purposes as they aren’t nominally routed to anything in the software. CAM0A and CAM0B can be synchronized using pin 27. Optional SPI bus on CAM2 is connected to the application processor block, not the DSP block. | - General notes: - Only camera interfaces with 4 D-PHY lanes are shown. The Qualcomm software uses RST and MCLK only. The other GPIO pins can be used for other purposes as they aren’t nominally routed to anything in the software. CAM0A and CAM0B can be synchronized using pin 27. Optional SPI bus on CAM2 is connected to the application processor block, not the DSP block. | - General notes: - Only camera interfaces with 4 D-PHY lanes are shown. The Qualcomm software uses RST and MCLK only. The other GPIO pins can be used for other purposes as they aren’t nominally routed to anything in the software. CAM0A and CAM0B can be synchronized using pin 27. Optional SPI bus on CAM2 is connected to the application processor block, not the DSP block. | - General notes: - Only camera interfaces with 4 D-PHY lanes are shown. The Qualcomm software uses RST and MCLK only. The other GPIO pins can be used for other purposes as they aren’t nominally routed to anything in the software. CAM0A and CAM0B can be synchronized using pin 27. Optional SPI bus on CAM2 is connected to the application processor block, not the DSP block. |
The following figure shows the signal and power interfaces between the QCS6490 SoM, interposer, mainboard, and Vision mezzanine:
**Figure: Dragonwing RB3 Gen 2 system interconnection block diagram**
## Reference designs and related documents
- [Design Package, RB3 Gen 2 SoM and Interposer](https://www.qualcomm.com/search?query=DP25-20659-5#q=DP25-20659-5&tab=all)
- [Design Package, RB3G2 Vision Kit, Mechanical 3D Model, IOT](https://www.qualcomm.com/search?query=DP25-55695-1#q=DP25-55695-1&tab=all)
- [Design Package, RB5 Generic Mezz Card Schematic and Layout, IOT](https://www.qualcomm.com/search?query=DP25-63340-1#q=DP25-63340-1&tab=all)
- [Design Package, RB5/RB5GEN2/RB3GEN2 Main Board](https://www.qualcomm.com/search?query=DP25-PV086-42#q=DP25-PV086-42&tab=all)
- [Design Package, RB5/RB5GEN2/RB3GEN2 Navigation Mezzanine](https://www.qualcomm.com/search?query=DP25-PV086-43#q=DP25-PV086-43&tab=all)
- [Design Package, RB3GEN2 Industrial Mezzanine](https://www.qualcomm.com/search?query=DP25-PV086-44#q=DP25-PV086-44&tab=all)
- [Build guide](https://docs.qualcomm.com/bundle/publicresource/topics/80-70030-254/build_landing_page.html)
- [Yocto guide](https://docs.qualcomm.com/bundle/publicresource/topics/80-70030-27/yocto_landing_page.html)
- [Qualcomm Dragonwing RB3 Gen 2 Development Kit quickstart – Linux](https://docs.qualcomm.com/bundle/publicresource/topics/80-70030-253)
- [Qualcomm IM SDK quickstart](https://docs.qualcomm.com/bundle/publicresource/topics/80-70030-51/qmi-sdk-qsg-landing-page.html)
- [Qualcomm® IM SDK reference](https://docs.qualcomm.com/bundle/publicresource/topics/80-70030-50/overview.html)
- [Qualcomm Intelligent Robotics (QIR) SDK](https://docs.qualcomm.com/bundle/publicresource/topics/80-70023-265/qir-sdk-landing-page.html)
- [Qualcomm® AI Engine direct SDK](https://docs.qualcomm.com/bundle/publicresource/topics/80-63442-50/introduction.html)
- [Qualcomm® Neural Processing SDK](https://docs.qualcomm.com/bundle/publicresource/topics/80-63442-2/overview.html)
- [Qualcomm Lite Runtime Reference](https://docs.qualcomm.com/bundle/publicresource/topics/80-70030-54/tflite-landing-page.html)
For a comprehensive package of software, tools, and documentation, go to [Qualcomm Linux](https://www.qualcomm.com/developer/software/qualcomm-linux).
## Acronyms and terms
List of acronyms and terms used in this document.
| Acronym and term | Description |
| --- | --- |
| DMIC | Digital microphone interface |
| EDL/QDL | Emergency download mode or Qualcomm download mode |
| GMSL | Gigabit multimedia serial links |
| GNSS | Global navigation satellite system |
| GPIO | General-purpose input/output |
| QUP | Qualcomm universal peripheral |
| SoC | System-on-chip |
| SoM | System-on-module |
| UART | Universal asynchronous receiver/transmitter |
Last Published: Jul 20, 2026
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