# Hardware overview
The Qualcomm Dragonwing^TM^ IQ-9075 Evaluation Kit (EVK) has the IQ-9075M module. Learn more about the system block diagram, electrical design, features, and capabilities of the EVK.
## System block diagram
The following figure shows the system block diagram of the Dragonwing IQ-9075 EVK platform. This figure provides a visual representation of the platform’s architecture, highlighting the main components and their interactions.
**Figure : Dragonwing IQ-9075 EVK system block diagram**
## Hardware specification
The following table outlines the key hardware specification of the Dragonwing IQ-9075 EVK.
Note
For the list of interfaces supported in this release, see the [Qualcomm Linux 1.9 Release Notes](https://docs.qualcomm.com/doc/80-70030-300).
**Table : Dragonwing IQ-9075 EVK key specifications**
| Interface or feature | Description |
| --- | --- |
| SoC | IQ-9075 *(part of IQ-9075M)* |
| Memory | 6 Ă— 16 bit 36 GB LP5 3200 MHz (3x 12GB LPDDR5) *(part of IQ-9075M)* |
| PMIC | 4 Ă— PMM8650AU *(part of IQ-9075M)* |
| External MCU | Not present |
| Storage | 2 Ă— 128 GB UFS, micro-SD card, EEPROMs for MACs, eMMC on mezzanine card |
| Display | Four display ports:
> > >
>
2 Ă— mini-DP (one with MST)
>
2 Ă— DSIs (one to DSI flex, one to expansion)
>
|
| Display | DSI flex connection with touchscreen |
| Camera/Video input | 4 Ă— Quad deserializers |
| Camera/Video input | 4 Ă— CSI (C-PHY or D-PHY) cameras |
| USB | USB0 Type-C (host or device mode) |
| USB | USB1 Type-C (host mode) |
| USB | USB2 uUSB 2.0 (host or device mode) |
| WLAN/Bluetooth^®^ | m.2 module (NFA765A) |
| WLAN/Bluetooth^®^ | 2 × printed antennas (Bluetooth shared with one WLAN antenna) |
| PCIe | Mainboard supported or expanded options (selected through switch):
1 Ă— PCIe x4 slot or expansion (switch)
1 Ă— m.2 E key (WI-Fi) or expansion (switch)
|
| Audio | 1 Ă— I^2^ S mic |
| Audio | 2 Ă— I^2^ S speaker amps |
| Audio | Additional I^2^ S on GPIOs |
| Ethernet | RJ45 2.5 GbE MD |
| CAN/CAN-FD | 1 Ă— CAN/CAN-FD on low speed header on mainboard |
| Low-speed expansion | 3.3 V header for developer community with CAN, SPI, I^2^ C, UART, I^2^ S |
| Second low-speed expansion | QUPs and GPIOs on mezzanine connectors |
| Sensors | IMU: ICM-42688 |
| Sensors | QUPs on expansion |
| Trusted platform module (TPM) | ST33HTPH2x32AHE4 on mainboard |
| | |
| | |
## Exterior view
The following figures show the exterior of the Dragonwing IQ-9075 EVK with the bottom case.
**Figure : Exterior view of the EVK with bottom case**
The following figures show the side views of the Dragonwing IQ-9075 EVK, with labeled ports, connectors, and switches.
The following figure shows the top view of the core board.
**Figure : Top view of the core board**
## EVK ports and interfaces
The following figure shows a detailed view of all the connectors on the Dragonwing IQ-9075 EVK.
**Figure : Connectors on Dragonwing IQ-9075 EVK**
The following figure shows the platform with few cables plugged in.
**Figure : Platform with cables plugged in**
**Table : Connectors and functions**
| Connectors | Functions |
| --- | --- |
| JPWR | DC power (barrel connector) plug, 12 V–36 V input voltage |
| JLS1 | Low speed IO header receptacle (LS1) |
| SW1 | 8 position surface mount DIP switch |
| SW2 | 4 position surface mount DIP switch |
| SW3 | 6 position surface mount DIP switch |
| JCAM0 | MIPI CSI0 camera interconnect receptacle |
| JCAM1 | MIPI CSI1 camera interconnect receptacle |
| JCAM2 | MIPI CSI2 camera interconnect receptacle |
| JCAM3 | MIPI CSI3 camera interconnect receptacle |
| JPCIE | PCI Express v4 receptacle connector (PCIe1) |
| JEDP1 | EDP1 connector |
| JEDP0 | EDP0 connector |
| JETH | Ethernet connector (2.5 GbE) |
| JUSB1 | USB-C (USB Type-C) receptacle connector for USB1 |
| JUSB0 | USB-C (USB Type-C) receptacle connector for USB0 |
| JUSB2 | Micro-USB receptacle for USB2 |
| JRST | Tactile switch for system reset (initiates graceful shutdown) |
| J13 | Antenna for WLAN |
| S4 | Slide switch for power or automation control |
| JDISP | Connector for DSI display |
| JTAC | Micro-USB receptacle for debug UART |
| JTAG | Header connector for JTAG |
| J14 | Antenna for WLAN/Bluetooth |
| JEXP1–JEXP4 | Board-to-board 120 position connector receptacle |
## DIP switch
The following images show the location of the DIP switches on the mainboard.
**Figure : DIP switches 1, 2, and 3 on Dragonwing IQ-9075 EVK**
**Figure : DIP switches 4, 7, 8, and 9 on Dragonwing IQ-9075 EVK**
Note
If a DIP switch is facing up, it indicates that the switch is on.
The following table details DIP switch operations for the Dragonwing IQ-9075 EVK, including functions and settings for board configuration.
**Table : DIP switch position and its respective functions**
| Switch | Connection when ON | Connection when OFF (default from factory) | Notes |
| --- | --- | --- | --- |
| SW1-1 | PCIe0 is routed to mezzanine | PCIe0 is connected to the mainboard Wi-Fi module | |
| SW1-2 | PCIe1 is routed to mezzanine | PCIe1 is connected to the mainboard PCIe connector | |
| SW1-3 | SDIO is routed to mezzanine | SDIO is routed to the mainboard SD card | |
| SW1-4 | DSI is routed to mainboard flex connector | DSI is routed to mezzanine | |
| SW1-5 | CSI0 is routed to mezzanine | CSI0 is routed to the mainboard CSI flex connector | |
| SW1-6 | CSI1 is routed to mezzanine | CSI1 is routed to the mainboard CSI flex connector | |
| SW1-7 | CSI1 is routed to mezzanine | CSI2 is routed to the mainboard CSI flex connector | |
| SW1-8 | CSI2 is routed to mezzanine | CSI3 is routed to the mainboard CSI flex connector | |
| SW2-1 | Main domain forced USB boot/EDL | No impact | Currently, this switch isn’t enabled in software. |
| SW2-2 | Main domain fast boot | No impact | |
| SW2-3 | Main domain and Sail domain forced USB boot/EDL (combined) | No impact | Currently, the software implementation puts both domains into EDL mode together. It’s important for software download. |
| SW2-4 | Sail domain Fastboot mode | No impact | |
| SW3-1 | OSPI is routed to mezzanine | OSPI is connected to onboard memory for MCU | |
| SW3-2 | Force MD and MCU PS\_HOLD | No impact | |
| SW3-3 | Watchdog is disabled | RAM dump is enabled | |
| SW3-4 | Boot from eMMC | Boot from UFS | eMMC located on interface and mezzanine |
| SW3-5 | EUD enable | No impact | |
| SW3-6 | Skip MD BIST | No impact | |
| SW4-1 | Reserved for internal use | Reserved for internal use | Don’t change. |
| SW7-1 | Reserved for internal use | Reserved for internal use | Don’t change. |
| SW8-1 | Reserved for internal use | Reserved for internal use | Don’t change. |
| SW9-1 | Reserved for internal use | Reserved for internal use | Don’t change. |
## LEDs
The Dragonwing IQ-9075 EVK has status LEDs that monitor system functions such as power-on and board faults, crucial for debugging and bringup. The following table lists and summarizes the functions of the LEDs. The [Connectors on Dragonwing IQ-9075 EVK](https://docs.qualcomm.com/doc/80-70030-261/topic/iq9-ug-hw-overview.html#fig-jmq-qqy-w2c) shows the location and the LEDs present on the board.
**Table : Summary of reference designator, location, color, and function of LEDs**
| Reference designator | Location | Color | Function |
| --- | --- | --- | --- |
| DS1 | Mainboard | Green | Reserved for debugging |
| DS8 | Mainboard | Green | Ethernet status LEDs |
| DS9 | Mainboard | Green | Ethernet status LEDs |
| DS10 | Mainboard | Green | VREG\_3P3\_SIP indicator |
| DS11 | Mainboard | Orange | VREG\_3P3\_SIP indicator |
| LED1 | Mainboard | RGB | Software-controlled RGB lighting through GPIOs |
| | | | |
## Hardware components and interfaces
Review the following high-level details of Dragonwing IQ-9075 processor, power supply, memory, and various interfaces, such as camera, USB, and DisplayPort. It also includes sensors, flash memory, expansion options, a debug interface, audio support, thermal management, fan control, and accessory boards.
### Processor
The target processor used in the Dragonwing IQ-9075 EVK is the Dragonwing IQ-9075 SoC, also known as the IQ-9075. This SoC features an octa-core Kryo^™^ Gen 6 CPU built on Arm v8.2 Cortex technology, with clock support up to 2.55 GHz.
In addition to the eight high-performance CPU cores, the SoC includes a GPU and two Hexagon Tensor Processors with vector and matrix extensions, enabling the management of various concurrent compute and AI workloads simultaneously. The SoC offers extensive peripheral support, including integrated Ethernet, USB, Wi-Fi, PCIe, and Bluetooth. It’s capable of delivering up to 100 INT8 TOPS, making it suitable for powering high-performance, AI-centric, and Edge AI industrial use cases.
The target applications include:
- Factory automation
- Industrial robots
- Industrial personal computers
- Drones
- Edge AI Boxes
- Machine Vision
- Autonomous Mobile Robots (AMRs)
- Industrial gateways
The IQ-9075 SoC is integrated within the IQ-9075M module, which also houses the four PMICs and three LPDDR5 SD RAM memory components. The following figure shows the IQ-9075 SoC within IQ-9075M module.
**Figure : IQ-9075 SoC within IQ-9075M module**
### Power
The main power input to the Dragonwing IQ-9075 board is provided through the 2.10 mm barrel jack connector (JPWR, JACK-C-PC-10A-RA(R)), supporting an input voltage range of 12 V to 36 V. The EVK also includes a Type-C to barrel plug adapter. Four power management ICs manage the respective power supplies to various system blocks, including the SoC, PMIC, PCIe, and expansion ports.
The following figure shows the four PMICs on the IQ-9075M module.
**Figure : Four PMICs on the IQ-9075M module**
### Memory
The IQ-9075M module has three 12 GB LPDDR5 SDRAM ICs. The following figure shows the LPDDR5 memory ICs on the module.
**Figure : LPDDR5 memory on the IQ-9075M module**
### Camera interface
An analog switch is used for each MIPI CSI interface, allowing the MIPI CSI interfaces to be accessible through both the JCAM camera interconnect receptacle and the B2B expansion connector (JEXP4).
For more information about camera mezzanine board, see the [Qualcomm Dragonwing IQ-9075 Evaluation Kit GMSL Mezzanine Board user guide - Linux](https://docs.qualcomm.com/doc/80-70022-43/topic/).
The following table lists the CSI interfaces, their analog switch, camera connector, and B2B connector pinout.
Note
You can connect the CSI interfaces to the mainboard connector or to GMSL mezzanine through a DIP switch setting. For the correct setting, see the [Table: DIP switch position and its respective functions](https://docs.qualcomm.com/doc/80-70030-261/topic/iq9-ug-hw-overview.html#table-aqt-1vs-w2c).
**Table : CSI settings**
| CSI interface | Analog switch | Camera connector | B2B connector pinout |
| --- | --- | --- | --- |
| CSI0 | U45