# Hardware overview
The Qualcomm Dragonwing^TM^ IQ-8275 Evaluation Kit (EVK) has Qualcomm IQ-8275 SoC mounted on the mainboard. Learn more about the system block diagram, electrical design, features, and capabilities of the EVK.
## System block diagram
The following figure shows the system block diagram of the Dragonwing IQ-8275 EVK platform. This figure provides a visual representation of the platform’s architecture, highlighting the main components and their interactions.
**Figure : Dragonwing IQ-8275 EVK system block diagram**
## Hardware specification
The following table outlines the key hardware specification of the Dragonwing IQ-8275 EVK.
Note
For the list of interfaces supported in this release, see the [Qualcomm Linux 1.8 Release Notes](https://docs.qualcomm.com/bundle/publicresource/topics/80-70030-300/).
**Table : Dragonwing IQ-8275 EVK key specifications**
| Interface or feature | Description |
| --- | --- |
| SoC | IQ-8275 |
| Memory | 4 × 16 bit 12 GB LP5 3200 MHz (2 x 6 GB LPDDR5) |
| PMIC | 2 × PMM8620AU |
| External MCU | Not present |
| Storage | 1 × 128 GB UFS, micro-SD card or eMMC on main card, 1 x EEPROM for MACs. |
| Display | Four display ports:
> > >
>
2 × mini-DP (through KTM switch)
>
DSI flex connection (display not included)
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|
| Display | DSI flex connection with touchscreen |
| Camera/Video input | 3 × Quad deserializers |
| Camera/Video input | 3 × CSI (C-PHY or D-PHY) cameras |
| USB | USB0 Type-C (host or device mode) |
| USB | USB1 uUSB 2.0 (host or device mode) |
| WLAN/Bluetooth^®^ | M.2 module (NFA765A) |
| WLAN/Bluetooth^®^ | 2 × printed antennas (Bluetooth shared with one WLAN antenna) |
| PCIe | Mainboard supported or expanded options (selected through switch):
1 × PCIe x4 slot or expansion (switch)
1 × M.2 E key (WI-Fi) or expansion (switch)
QPS615 PCIe expansion is supported through a mezzanine board.
|
| Audio | 1 × I^2^ S mic |
| Audio | 2 × I^2^ S speaker amps |
| Audio | Additional I^2^ S on GPIOs |
| Ethernet | RJ45 2.5 GbE MD |
| Ethernet | Additional ethernet ports can be added using mezzanine interface cards. |
| CAN/CAN-FD | 1 × CAN/CAN-FD on low speed header on mainboard |
| Low-speed expansion | 3.3 V header for developer community with CAN, SPI, I^2^ C, UART, I^2^ S |
| Second low-speed expansion | QUPs and GPIOs on mezzanine connectors |
| Sensors | IMU: ICM-42688 |
| Sensors | QUPs on expansion |
| Trusted platform module (TPM) | ST33HTPH2x32AHE4 on mainboard |
| | |
| | |
## Exterior view
The following figures show the exterior of the Dragonwing IQ-8275 EVK with the bottom case.
**Figure : Exterior view of the EVK with bottom case**
The following figures show the side views of the Dragonwing IQ-8275 EVK, with labeled ports, connectors, and switches.
The following figure shows the top view of the core board.
**Figure : Top view of the core board**
## EVK ports and interfaces
The following figure shows a detailed view of all the connectors on the Dragonwing IQ-8275 EVK.
**Figure : Connectors on Dragonwing IQ-8275 EVK**
The following figure shows the platform with few cables plugged in.
**Figure : Platform with cables plugged in**
**Table : Connectors and functions**
| Connectors | Functions |
| --- | --- |
| JPWR | DC power (barrel connector) plug, 12 V–36 V input voltage |
| JLS1 | Low speed IO header receptacle (LS1) |
| SW1 | 8 position surface mount DIP switch |
| SW2 | 4 position surface mount DIP switch |
| SW3 | 6 position surface mount DIP switch |
| JCAM0 | MIPI CSI0 camera interconnect receptacle |
| JCAM1 | MIPI CSI1 camera interconnect receptacle |
| JCAM2 | MIPI CSI2 camera interconnect receptacle |
| JPCIE | PCI Express v4 receptacle connector (PCIe1) |
| JEDP1 | EDP1 connector |
| JEDP0 | EDP0 connector |
| JETH | Ethernet connector (2.5 GbE) |
| JUSB1 | USB-C (USB Type-C) receptacle connector for USB1 |
| JUSB0 | USB-C (USB Type-C) receptacle connector for USB0 |
| J13 | Antenna for WLAN |
| S4 | Slide switch for power or automation control |
| JDISP | Connector for DSI display |
| JTAC | Micro-USB receptacle for debug UART |
| JTAG | Header connector for JTAG |
| J14 | Antenna for WLAN/Bluetooth |
| JEXP1–JEXP4 | Board-to-board 120 position connector receptacle |
## DIP switch
The following images show the location of the DIP switches on the mainboard.
**Figure : DIP switches 1, 2, and 3 on Dragonwing IQ-8275 EVK**
Note
If a DIP switch is facing up, it indicates that the switch is on.
The following table details DIP switch operations for the Dragonwing IQ-8275 EVK, including functions and settings for board configuration.
**Table : DIP switch position and its respective functions**
| Switch | Connection when ON | Connection when OFF (default from factory) | Notes |
| --- | --- | --- | --- |
| SW1-1 | PCIe0 is routed to mezzanine | PCIe0 is connected to the mainboard Wi-Fi module | None |
| SW1-2 | PCIe1 is routed to mezzanine | PCIe1 is connected to the mainboard PCIe connector | None |
| SW1-3 | NC | NC | None |
| SW1-4 | DSI0 routed to mezzanine | DSI0 routed to mainboard DSI flex connector | None |
| SW1-5 | CSI0 is routed to mezzanine | CSI0 is routed to the mainboard CSI flex connector | None |
| SW1-6 | CSI1 is routed to mezzanine | CSI1 is routed to the mainboard CSI flex connector | None |
| SW1-7 | CSI1 is routed to mezzanine | CSI2 is routed to the mainboard CSI flex connector | None |
| SW1-8 | SDC signal will be routed to SD card | SDC signal will be routed to eMMC | None |
| SW2-1 | Main domain forced USB boot/EDL | No impact | Currently, this switch isn’t enabled in software. |
| SW2-2 | Main domain fast boot | No impact | None |
| SW2-3 | Main domain and RTSS domain forced USB boot/EDL (combined) | No impact | Currently, the software implementation puts both domains into EDL mode together. It’s important for software download. |
| SW2-4 | RTSS domain Fastboot mode | No impact | None |
| SW3-1 | OSPI is routed to mezzanine | OSPI is connected to onboard memory for MCU | None |
| SW3-2 | Force MD and MCU PS\_HOLD | No impact | None |
| SW3-3 | Watchdog is disabled | RAM dump is enabled | None |
| SW3-4 | Boot from eMMC | Boot from UFS | eMMC located on interface and mezzanine |
| SW3-5 | EUD enable | No impact | None |
| SW3-6 | Skip MD BIST | No impact | None |
| SW4-1 | PWM-MODE for fan set to low | PWM-MODE for fan set to high | Don’t change. |
| SW7-1 | RGMII voltage select 2.5V | RGMII voltage select 1.8V | None |
| SW9-1 | USB to m.2 connector for NFA765 module on mezzanine | USB to m.2 connector for NFA765 module on mainboard | None |
| SW8-1 | RTSS CAN GPIOs routed to mezzanine | RTSS CAN GPIOs routed to JLS1 connector | None |
| S17 | EMMC\_THERM selected | UFS THERM selected | None |
| S18 | UFS2.1 or eMMC version selected | UFS3.1 version is selected | None |
| S19 | USB1\_HS port selected | USB0\_HS port is selected | None |
| S20 | USB1\_SS port selected | USB0\_SS port is selected | None |
## LEDs
The Dragonwing IQ-8275 EVK has status LEDs that monitor system functions such as power-on and board faults, crucial for debugging and bringup. The following table lists and summarizes the functions of the LEDs. The [Connectors on Dragonwing IQ-8275 EVK](https://docs.qualcomm.com/doc/80-70030-281/topic/iq8-ug-hw-overview.html#fig-jmq-qqy-w2c) shows the location and the LEDs present on the board.
**Table : Summary of reference designator, location, color, and function of LEDs**
| Reference designator | Location | Color | Function |
| --- | --- | --- | --- |
| DS1 | Mainboard | Green | Reserved for debugging |
| DS8 | Mainboard | Green | Ethernet status LEDs |
| DS9 | Mainboard | Green | Ethernet status LEDs |
| DS10 | Mainboard | Green | 3.3 V LED |
| DS11 | Mainboard | Orange | 3.3 V LED |
| | | | |
## Hardware components and interfaces
The following are the high-level details of the Dragonwing IQ-8275 processor, power supply, memory, and various interfaces, such as camera, USB, and DisplayPort. It also includes sensors, flash memory, expansion options, a debug interface, audio support, thermal management, fan control, and accessory boards.
### Processor
The target processor used in the Dragonwing IQ-8275 EVK is the Dragonwing IQ-8275 SoC, also known as the QCS8275. This SoC features an octa-core Kryo^™^ Gen 6 CPU built on Arm v8.2 Cortex technology, with clock support up to 2.35 GHz.
In addition to the eight high-performance CPU cores, the SoC includes a GPU and a Hexagon Tensor Processor with vector and matrix extensions, enabling the management of various concurrent compute and AI workloads simultaneously.
The SoC offers extensive peripheral support, including integrated Ethernet, USB, Wi-Fi, PCIe, and Bluetooth. It’s capable of delivering up to 40 TOPS, making it suitable for powering high-performance, AI-centric, and Edge AI industrial use cases.
The target applications include:
- Factory automation
- Industrial robots
- Industrial personal computers
- Drones
- Edge AI Boxes
- Machine Vision
- Autonomous Mobile Robots (AMRs)
- Industrial gateways
### Power
The main power input to the Dragonwing IQ-8275 board is provided through the 2.10 mm barrel jack connector (JPWR, JACK-C-PC-10A-RA(R)), supporting an input voltage range of 12 V to 36 V.
The EVK also includes a Type-C to barrel plug adapter. Four power management ICs manage the respective power supplies to various system blocks, including the SoC, PMIC, PCIe, and expansion ports.
### Memory
The IQ-8275 EVK has two 6 GB LPDDR5 SDRAM ICs.
### Camera interface
An analog switch is used for each MIPI CSI interface, allowing the MIPI CSI interfaces to be accessible through both the JCAM camera interconnect receptacle and the B2B expansion connector (JEXP4).
To use a GMSL camera with the Dragonwing IQ-8275 EVK, connect it through the GMSL mezzanine, which must be ordered separately. The CSI ports are routed through the DIP switches, allowing configuration and setup.
The three MIPI CSI ports operate in either C-PHY or D-PHY mode and support a range of existing cameras and flexe.
The following block diagrams show various CSI interfaces.
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> **Figure : Camera CSI0 interfaces**
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> **Figure : Camera CSI1 interfaces**
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> **Figure : Camera CSI2 interfaces**
### USB interface
The board features three USB connectors: two Type-C connectors (JUSB0 and JUSB1) and one micro-USB connector (JUSB2).
The following figures show the USB interfaces and configuration.
**USB0-SS interfaces and configuration**
**USB0-HS interfaces and configuration**
**USB2-HS interfaces and configuration**
**USB interfaces and configuration**
### DisplayPort (eDP) interface
The target processor is equipped with 1 x eDP interface. EDP0 is routed to LT8713 EDP bridge as shown, with also a BYPASS option to JEDP0.
The following figure shows the eDP interfaces and configuration.
**eDP interfaces and configuration**
### DSI interface
The IQ-8275 processor supports one 4-lane MIPI-DSI with VESA DSC v1.2.
The Dragonwing IQ-8275 EVK uses an analog switch for DSI0 interface, allowing the interface to be accessible through both the JDISP LCD receptacle and the B2B expansion connector (JEXP1).
The following figure shows the DSI connectors
**Figure : DSI connectors**
### Storage interfaces
The Dragonwing IQ-8275 has three types of storage interfaces: secure digital (SD) card, universal flash storage (UFS), and electrically erasable programmable read-only memory (EEPROM).
#### SD card
The target processor supports a single SDIO interface (SDC1). The SDC pins are routed through analog switches to facilitate connections through the micro SD card connector (JSDC) on the board, and eMMC (U150).
The following figures show the SD card interfaces and configuration.
**SDIO card interfaces and configuration**
**SD card interfaces and configuration**
#### UFS
The target processor supports 1 x UFS 3.1 Gear 4 interface. UFS0 serves as the main domain boot-up device.
The following table lists the part numbers and manufacturers of these UFS devices.
**Table : Part numbers and manufacturers of UFS devices**
| Reference designator | Interface identifier | MPN | Manufacturer | Description |
| --- | --- | --- | --- | --- |
| U38 | UFS0 | THGJFGT0T25BAB8 | KIOXIA AMERICA INC | 128 GB UFS3.1 (Gear4) Q100-GR2 RoHS |
| | | THGJFGT0T25BAB8 | KIOXIA AMERICA INC | 128 GB UFS3.1 (Gear4) Q100-GR2 RoHS |
The following figure shows the UFS interfaces and configuration.
**UFS interfaces and configuration**
#### EEPROM
The Dragonwing IQ-8275 EVK platform has a single EEPROM device dedicated to storing MAC addresses for Ethernet, Wi-Fi, and Bluetooth.
The following table lists the part number and manufacturer of the EEPROM device.
**Table : Part number and manufacturer of the EEPROM device**
| Reference designator | Device | MPN | Manufacturer | Description |
| --- | --- | --- | --- | --- |
| U20 | EEPROM | 93LC46B-I/SN | Microchip Technology Inc. | 1 Kbit low-voltage serial electrically erasable PROMs (EEPROM) |
### On-board sensors
The Dragonwing IQ-8275 EVK platform includes an on-board IMU and a temperature sensor. They are connected to the real-time subsystem (RTSS) domain of IQ-8275 EVK.
Note
Currently, the software doesn’t support the IMU and temperature sensors. Contact Qualcomm software team for details if you wish to enable them.
The following table lists the part numbers and manufacturers of these sensors.
**Table : Part numbers and manufacturers of the sensors**
| Reference designator | Sensor type | Communication protocol used | MPN | Manufacturer |
| --- | --- | --- | --- | --- |
| U97 | IMU sensor | I^2^C | ICM-42688 | TDK InvenSense |
| U109 | Temperature sensor | SPI | TMP411DQDGKRQ1 | Texas Instruments |
### PCIe interface
The target processor supports two PCIe interfaces: PCIe0 and PCIe1. PCIe0 is Gen4 2-lane and PCIe1 is Gen4 4-lane PCIe interface.
Both PCIe interfaces are connected to an A/B switch, which by default, connects them to the expansion mezzanine. For DIP switch settings, see the [Table: DIP switch position and its respective functions](https://docs.qualcomm.com/doc/80-70030-281/topic/iq8-ug-hw-overview.html#table-aqt-1vs-w2c).
The following figures show the PCIe interfaces and configuration.
**Figure : PCIe0 interfaces and configuration**
**Figure : PCIe1 interfaces and configuration**
### Flash memory
The Dragonwing IQ-8275 EVK uses OSPI interface to support 2GBIT flash memory. The analog switch for OSPI interface allows the interface to be accessible through both the flash memory device and the B2B expansion connector (JEXP2).
Note
Due to the analog switch, you can connect the OSPI to the memory device or to B2B connector through DIP switch settings. For the intended OSPI settings, see the [Table: DIP switch position and its respective functions](https://docs.qualcomm.com/doc/80-70030-281/topic/iq8-ug-hw-overview.html#table-aqt-1vs-w2c).
The following figure shows the flash memory interfaces and configuration.
**Figure : Flash memory interfaces and configuration**
The main board provides CAN0, and the JEXP1 connector provides CAN1-7.
The following figures show controller area network (CAN) block diagram and interfaces.
**Figure : CAN0 interfaces**
### Expansion headers
The Dragonwing IQ-8275 EVK features four high-speed expansion connectors (JEXP1-4, 10139781-121422LF). Connect accessory cards such as GMSL mezzanine and RBx adapters to these connectors. Additionally, other interfaces mentioned throughout this document are also routed to these connectors, see the [Connectors on Dragonwing IQ-8275 EVK](https://docs.qualcomm.com/doc/80-70030-281/topic/iq8-ug-hw-overview.html#fig-jmq-qqy-w2c).
The following table details the pin mapping for the **JEXP1** connector.
**Table : Pin mapping for the JEXP1 connector**
| Pin name | Pin number | Pin number | Pin name |
| --- | --- | --- | --- |
| GND | 61 | 1 | VREG\_SYSTEM\_PWR |
| DSI0\_A0\_LN0\_P\_CONN | 62 | 2 | VREG\_SYSTEM\_PWR |
| DSI0\_B0\_LN0\_M\_CONN | 63 | 3 | VREG\_SYSTEM\_PWR |
| GND | 64 | 4 | VREG\_SYSTEM\_PWR |
| DSI0\_C0\_LN1\_P\_CONN | 65 | 5 | VREG\_SYSTEM\_PWR |
| DSI0\_A1\_LN1\_M\_CONN | 66 | 6 | GND |
| GND | 67 | 7 | GND |
| DSI0\_B1\_CLK\_P\_CONN | 68 | 8 | GND |
| DSI0\_C1\_CLK\_M\_CONN | 69 | 9 | GND |
| GND | 70 | 10 | VREG\_PMIC\_IN\_3P3 |
| DSI0\_A2\_LN2\_P\_CONN | 71 | 11 | VREG\_PMIC\_IN\_3P3 |
| DSI0\_B2\_LN2\_M\_CONN | 72 | 12 | GND |
| GND | 73 | 13 | GND |
| DSI0\_C2\_LN3\_P\_CONN | 74 | 14 | PME\_GPIO\_3\_USB1\_FAULT\_3P3\_N |
| DSI0\_NC\_LN3\_M\_CONN | 75 | 15 | PME\_GPIO\_4\_USB0\_FAULT\_3P3\_N |
| GND | 76 | 16 | MD\_GPIO\_17\_MDPX3\_1P8 |
| VREG\_L6C\_SENSOR\_IO\_1P8 | 77 | 17 | MD\_GPIO\_18\_MDPX3\_1P8 |
| GND | 78 | 18 | SGMII0\_MDC\_MDPX3\_1P8 |
| VREG\_MDPX3\_1P8 | 79 | 19 | SGMII0\_MDIO\_MDPX3\_1P8 |
| GND | 80 | 20 | SGMII0\_CONN\_RX\_P |
| IOEXPAN1\_INT\_MDPX3\_1P8\_N | 81 | 21 | SGMII0\_CONN\_RX\_M |
| IOEXP5\_IO\_P2\_1P8 | 82 | 22 | SGMII0\_CONN\_TX\_P |
| Not connected | 83 | 23 | SGMII0\_CONN\_TX\_M |
| Not connected | 84 | 24 | SGMII0\_INT\_MDPX3\_1P8\_N |
| Not connected | 85 | 25 | SGMII0\_RST\_MDPX3\_1P8\_N |
| Not connected | 86 | 26 | JEXP1\_MD\_GPIO\_45\_MDPX3\_1P8 |
| IOEXP5\_IO\_P7\_1P8 | 87 | 27 | JEXP1\_MD\_GPIO\_46\_MDPX3\_1P8 |
| Not connected | 88 | 28 | JEXP1\_MD\_GPIO\_47\_MDPX3\_1P8 |
| RTSS\_ERR0\_SPX3\_1P8 | 89 | 29 | JEXP1\_MD\_GPIO\_48\_MDPX3\_1P8 |
| RTSS\_CAN\_SPI\_MISO\_SPX3\_1P8 | 90 | 30 | RTSS\_CAN0\_TX\_SPX3\_1P8 |
| RTSS\_SPI\_MISO\_SPX3\_1P8 | 91 | 31 | RTSS\_CAN0\_RX\_SPX3\_1P8 |
| RTSS\_CAN\_SPI\_MOSI\_SPX3\_1P8 | 92 | 32 | RTSS\_CAN1\_TX\_SPX3\_1P8 |
| RTSS\_CAN\_SPI\_SCLK\_SPX3\_1P8 | 93 | 33 | RTSS\_CAN1\_RX\_SPX3\_1P8 |
| RTSS\_CAN\_SPI\_CS\_0\_SPX3\_1P8 | 94 | 34 | RTSS\_CAN2\_TX\_SPX3\_1P8 |
| RTSS\_CAN\_SPI\_CS\_1\_SPX3\_1P8 | 95 | 35 | RTSS\_CAN2\_RX\_SPX3\_1P8 |
| RTSS\_IO\_47\_SPX3\_1P8 | 96 | 36 | RTSS\_CAN3\_TX\_SPX3\_1P8 |
| RTSS\_IO\_48\_SPX3\_1P8 | 97 | 37 | RTSS\_CAN3\_RX\_SPX3\_1P8 |
| RTSS\_IO\_49\_SPX3\_1P8 | 98 | 38 | Not connected |
| RTSS\_IO\_50\_SPX3\_1P8 | 99 | 39 | Not connected |
| RTSS\_PMIC\_INT\_SPX3\_1P8\_N | 100 | 40 | Not connected |
| RTSS\_INT\_SPX3\_1P8\_N | 101 | 41 | Not connected |
| RTSS\_PWR\_READY\_SPX3\_1P8 | 102 | 42 | Not connected |
| RTSS\_SLP\_EN\_SPX3\_1P8 | 103 | 43 | Not connected |
| RTSS\_DBG\_UART\_TX\_M\_SPX3\_1P8 | 104 | 44 | Not connected |
| RTSS\_DBG\_UART\_RX\_M\_SPX3\_1P8 | 105 | 45 | Not connected |
| GND | 106 | 46 | RTSS\_CAN\_INT0\_SPX3\_1P8 |
| PCIE0\_MEZZCONN\_CLK\_P | 107 | 47 | Not connected |
| PCIE0\_MEZZCONN\_CLK\_N | 108 | 48 | RTSS\_CAN\_STB\_0\_SPX3\_1P8 |
| GND | 109 | 49 | Not connected |
| PCIE0\_MEZZCONN\_RX0\_P | 110 | 50 | Not connected |
| PCIE0\_MEZZCONN\_RX0\_N | 111 | 51 | Not connected |
| GND | 112 | 52 | RTSS\_IO\_2\_SPX3\_1P8 |
| PCIE0\_MEZZCONN\_RX1\_P | 113 | 53 | RTSS\_IO\_3\_SPX3\_1P8 |
| PCIE0\_MEZZCONN\_RX1\_N | 114 | 54 | Not connected |
| GND | 115 | 55 | PCIE0\_MEZZCONN\_RST\_1P8\_N |
| PCIE0\_MEZZCONN\_TX0\_P | 116 | 56 | PCIE0\_MEZZCONN\_CLKREQ\_1P8\_N |
| PCIE0\_MEZZCONN\_TX0\_N | 117 | 57 | PCIE0\_MEZZCONN\_WAKE\_1P8\_N |
| GND | 118 | 58 | MD\_GPIO\_78\_GNSS\_RESET\_MDPX3\_1P8 |
| PCIE0\_MEZZCONN\_TX1\_P | 119 | 59 | MD\_GPIO\_77\_GNSS\_EN\_MDPX3\_1P8 |
| PCIE0\_MEZZCONN\_TX1\_N | 120 | 60 | MD\_GPIO\_79\_GNSS\_BOOT\_MODE\_MDPX3\_1P8 |
The following table details the pin mapping for the **JEXP2** connector.
**Table : Pin mapping for the JEXP2 connector**
| Pin name | Pin number | Pin number | Pin name |
| --- | --- | --- | --- |
| VREG\_MDPX3\_1P8 | 61 | 1 | VREG\_SPX3\_1P8 |
| GND | 62 | 2 | GND |
| SOC\_MI2S\_MCLK0\_MDPX3\_1P8 | 63 | 3 | VREG\_SPX3\_1P8 |
| SOC\_MI2S1\_SCK\_MDPX3\_1P8 | 64 | 4 | GND |
| SOC\_MI2S1\_WS\_MDPX3\_1P8 | 65 | 5 | USB01\_I2C\_SDA\_MDPX3\_1P8 |
| SOC\_MI2S1\_DATA0\_MDPX3\_1P8 | 66 | 6 | USB01\_I2C\_SCL\_MDPX3\_1P8 |
| SOC\_MI2S1\_DATA1\_MDPX3\_1P8 | 67 | 7 | IOEXP5\_IO\_P1\_1P8 |
| MI2S2\_SCK\_MDPX3\_1P8 | 68 | 8 | VREG\_1P2\_EN |
| MI2S2\_WS\_MDPX3\_1P8 | 69 | 9 | USB\_VBUS\_DET\_MDPX3\_1P8 |
| MI2S2\_DATA0\_MDPX3\_1P8 | 70 | 10 | USB\_RESET\_MDPX3\_1P8\_N |
| MI2S2\_DATA1\_MDPX3\_1P8 | 71 | 11 | USB1\_ID\_MDPX3\_1P8 |
| HS0\_MI2S\_SCK\_CONN | 72 | 12 | USB0\_ID\_MDPX3\_1P8 |
| HS0\_MI2S\_WS\_CONN | 73 | 13 | IOEXP5\_IO\_P0\_1P8 |
| HS0\_MI2S\_DATA0\_CONN | 74 | 14 | IOEXP5\_IO\_P3\_1P8 |
| HS0\_MI2S\_DATA1\_CONN | 75 | 15 | USB1\_INT\_MDPX3\_1P8\_N |
| HS1\_MI2S\_SCK\_CONN | 76 | 16 | USB0\_INT\_MDPX3\_1P8\_N |
| HS1\_MI2S\_WS\_CONN | 77 | 17 | MD\_GPIO\_65\_MDPX3\_1P8 |
| HS1\_MI2S\_DATA0\_CONN | 78 | 18 | EXP\_I2C\_SDA\_MDPX3\_1P8 |
| HS1\_MI2S\_DATA1\_CONN | 79 | 19 | EXP\_I2C\_SCL\_MDPX3\_1P8 |
| HS2\_MI2S\_SCK\_CONN | 80 | 20 | FAN\_INT\_MDPX3\_1P8\_N |
| HS2\_MI2S\_WS\_CONN | 81 | 21 | HUB\_P2\_USB\_HS\_P |
| HS2\_MI2S\_DATA0\_CONN | 82 | 22 | HUB\_P2\_USB\_HS\_M |
| HS2\_MI2S\_DATA1\_CONN | 83 | 23 | HUB\_P2\_USB\_SS\_RX\_P |
| SOC\_QUA\_MI2S\_SCK\_MDPX3\_1P8 | 84 | 24 | HUB\_P2\_USB\_SS\_RX\_M |
| SOC\_QUA\_MI2S\_WS\_MDPX3\_1P8 | 85 | 25 | HUB\_P2\_USB\_SS\_TX\_P |
| SOC\_QUA\_MI2S\_DATA0\_MDPX3\_1P8 | 86 | 26 | HUB\_P2\_USB\_SS\_TX\_M |
| SOC\_QUA\_MI2S\_DATA1\_MDPX3\_1P8 | 87 | 27 | GND |
| SOC\_QUA\_MI2S\_DATA2\_MDPX3\_1P8 | 88 | 28 | HUB\_P3\_USB\_HS\_M |
| SOC\_QUA\_MI2S\_DATA3\_MDPX3\_1P8 | 89 | 29 | HUB\_P3\_USB\_HS\_P |
| SOC\_I2S1\_SCK\_MDPX3\_1P8 | 90 | 30 | HUB\_P3\_USB\_SS\_TX\_P |
| SOC\_I2S1\_WS\_MDPX3\_1P8 | 91 | 31 | HUB\_P3\_USB\_SS\_TX\_M |
| SOC\_I2S1\_DATA0\_MDPX3\_1P8 | 92 | 32 | HUB\_P3\_USB\_SS\_RX\_P |
| SOC\_I2S1\_DATA1\_MDPX3\_1P8 | 93 | 33 | HUB\_P3\_USB\_SS\_RX\_M |
| LPI\_I2S2\_CLK\_MDPX3\_1P8 | 94 | 34 | GND |
| LPI\_I2S2\_WS\_MDPX3\_1P8 | 95 | 35 | HUB\_P4\_USB\_HS\_M\_2 |
| LPI\_I2S2\_DATA0\_MDPX3\_1P8 | 96 | 36 | HUB\_P4\_USB\_HS\_P\_2 |
| LPI\_I2S2\_DATA1\_MDPX3\_1P8 | 97 | 37 | HUB\_P4\_USB\_SS\_TX\_P |
| SOC\_I2S3\_SCK\_MDPX3\_1P8 | 98 | 38 | HUB\_P4\_USB\_SS\_TX\_M |
| SOC\_I2S3\_WS\_MDPX3\_1P8 | 99 | 39 | HUB\_P4\_USB\_SS\_RX\_P |
| SOC\_I2S3\_DATA0\_MDPX3\_1P8 | 100 | 40 | HUB\_P4\_USB\_SS\_RX\_M |
| SOC\_I2S3\_DATA1\_MDPX3\_1P8 | 101 | 41 | GND |
| I2S4\_SCK\_MDPX3\_1P8 | 102 | 42 | RTSS\_RGMII\_RESET\_SPX3\_N |
| I2S4\_WS\_MDPX3\_1P8 | 103 | 43 | RTSS\_RGMII\_INT\_SPX3\_N |
| I2S4\_DATA0\_MDPX3\_1P8 | 104 | 44 | RTSS\_RGMII\_MDIO\_SPX3 |
| I2S4\_DATA1\_MDPX3\_1P8 | 105 | 45 | RTSS\_RGMII\_MDC\_SPX3 |
| RTSS\_CONN\_OSPI0\_CS0\_SPX3\_1P8\_N | 106 | 46 | RTSS\_RGMII\_RX\_CTL\_SPX3 |
| RTSS\_CONN\_OSPI0\_DQS\_SPX3\_1P8 | 107 | 47 | RTSS\_RGMII\_RXC\_SPX3 |
| RTSS\_CONN\_OSPI0\_WR\_SPX3\_1P8\_N | 108 | 48 | RTSS\_RGMII\_RXD0\_SPX3 |
| RTSS\_CONN\_OSPI0\_CLK\_SPX3\_1P8 | 109 | 49 | RTSS\_RGMII\_RXD1\_SPX3 |
| RTSS\_CONN\_OSPI0\_DATA\_0\_SPX3\_1P8 | 110 | 50 | RTSS\_RGMII\_RXD2\_SPX3 |
| RTSS\_CONN\_OSPI0\_DATA\_1\_SPX3\_1P8 | 111 | 51 | RTSS\_RGMII\_RXD3\_SPX3 |
| RTSS\_CONN\_OSPI0\_DATA\_2\_SPX3\_1P8 | 112 | 52 | RTSS\_RGMII\_TX\_CTL\_SPX3 |
| RTSS\_CONN\_OSPI0\_DATA\_3\_SPX3\_1P8 | 113 | 53 | RTSS\_RGMII\_TXC\_SPX3 |
| RTSS\_CONN\_OSPI0\_DATA\_4\_SPX3\_1P8 | 114 | 54 | RTSS\_RGMII\_TXD0\_SPX3 |
| RTSS\_CONN\_OSPI0\_DATA\_5\_SPX3\_1P8 | 115 | 55 | RTSS\_RGMII\_TXD1\_SPX3 |
| RTSS\_CONN\_OSPI0\_DATA\_6\_SPX3\_1P8 | 116 | 56 | RTSS\_RGMII\_TXD2\_SPX3 |
| RTSS\_CONN\_OSPI0\_DATA\_7\_SPX3\_1P8 | 117 | 57 | RTSS\_RGMII\_TXD3\_SPX3 |
| RTSS\_RESOUT\_SPX3\_1P8\_N | 118 | 58 | GND |
| MD\_GPIO\_47\_MDPX3\_1P8 | 119 | 59 | VREG\_5P0 |
| MD\_GPIO\_48\_MDPX3\_1P8 | 120 | 60 | VREG\_5P0 |
The following table details the pin mapping for the **JEXP3** connector.
**Table : Pin mapping for the JEXP3 connector**
| Pin name | Pin number | Pin number | Pin name |
| --- | --- | --- | --- |
| MD\_GPIO\_25\_MDPX3\_1P8 | 61 | 1 | EDP2\_LN0\_P |
| MD\_GPIO\_26\_MDPX3\_1P8 | 62 | 2 | EDP2\_LN0\_M |
| MD\_GPIO\_27\_MDPX3\_1P8 | 63 | 3 | GND |
| MD\_GPIO\_28\_MDPX3\_1P8 | 64 | 4 | EDP2\_LN1\_P |
| MD\_RESOUT\_MDPX3\_1P8\_N | 65 | 5 | EDP2\_LN1\_M |
| MD\_GPIO\_54\_WLAN\_EN\_1P8 | 66 | 6 | GND |
| HST\_SW\_CTRL\_MDPX3\_1P8 | 67 | 7 | EDP2\_LN2\_P |
| MD\_GPIO\_55\_BT\_EN\_1P8 | 68 | 8 | EDP2\_LN2\_M |
| BT0\_UART\_CTS\_MDPX3\_1P8 | 69 | 9 | GND |
| BT0\_UART\_RFR\_MDPX3\_1P8 | 70 | 10 | EDP2\_LN3\_P |
| BT0\_UART\_TX\_MDPX3\_1P8 | 71 | 11 | EDP2\_LN3\_M |
| BT0\_UART\_RX\_MDPX3\_1P8 | 72 | 12 | GND |
| MD\_GPIO\_10\_MDPX3\_1P8 | 73 | 13 | EDP2\_AUX\_P |
| SDCARD\_DET\_MDPX3\_1P8\_N | 74 | 14 | EDP2\_AUX\_M |
| BTLE\_UART\_TX\_MDPX3\_1P8 | 75 | 15 | GND |
| BTLE\_UART\_RX\_MDPX3\_1P8 | 76 | 16 | Not connected |
| Not connected | 77 | 17 | Not connected |
| GND | 78 | 18 | GND |
| Not connected | 79 | 19 | Not connected |
| Not connected | 80 | 20 | Not connected |
| GND | 81 | 21 | GND |
| Not connected | 82 | 22 | Not connected |
| Not connected | 83 | 23 | Not connected |
| GND | 84 | 24 | GND |
| Not connected | 85 | 25 | Not connected |
| Not connected | 86 | 26 | Not connected |
| GND | 87 | 27 | GND |
| Not connected | 88 | 28 | Not connected |
| Not connected | 89 | 29 | Not connected |
| GND | 90 | 30 | MDP\_VSYNC\_MDPX3\_1P8 |
| Not connected | 91 | 31 | VREG\_5P0\_PGOOD |
| Not connected | 92 | 32 | PG\_VREG\_3P3\_SIP |
| GND | 93 | 33 | EDP2\_HPD\_1P8 |
| PMC\_GPIO\_4\_IPA\_PWR\_EN\_1P8 | 94 | 34 | Not connected |
| WLAN\_PWR\_EN2\_1P8 | 95 | 35 | MD\_GPIO\_72\_MDPX3\_1P8 |
| PMC\_GPIO\_6\_WLAN\_DBU4\_EN\_1P8 | 96 | 36 | DISP\_RST\_MDPX3\_1P8\_N |
| Not connected | 97 | 37 | DISP\_INT\_MDPX3\_1P8\_N |
| Not connected | 98 | 38 | DES0\_LOCK\_1P8 |
| IOEXP6\_IO\_P4\_1P8 | 99 | 39 | LCD\_RESET\_MDPX3\_1P8 |
| SENSOR\_I2C\_SDA\_MDPX3\_1P8 | 100 | 40 | I2C\_TO\_SPI\_MISO\_1P8 |
| SENSOR\_I2C\_SCL\_MDPX3\_1P8 | 101 | 41 | I2C\_TO\_SPI\_MOSI\_1P8 |
| TX3\_DDC\_SCL\_1P8 | 102 | 42 | I2C\_TO\_SPI\_CLK\_1P8 |
| TX3\_DDC\_SDA\_1P8 | 103 | 43 | I2C\_TO\_SPI\_CS0\_1P8 |
| AUDIO\_PRI\_SPI\_MISO\_MDPX3\_1P8 | 104 | 44 | MD\_GPIO\_41\_MDPX3\_1P8 |
| AUDIO\_PRI\_SPI\_MOSI\_MDPX3\_1P8 | 105 | 45 | MD\_GPIO\_42\_MDPX3\_1P8 |
| AUDIO\_PRI\_SPI\_SCLK\_MDPX3\_1P8 | 106 | 46 | USB0\_VBUS\_ON\_MDPX3\_1P8 |
| AUDIO\_PRI\_SPI\_CS\_0\_MDPX3\_1P8 | 107 | 47 | IOEXP3\_IO\_P2\_1P8 |
| AUDIO\_PRI\_SPI\_CS\_1\_MDPX3\_1P8 | 108 | 48 | SENSOR\_SLP\_CLK\_MDPX3\_1P8 |
| MD\_GPIO\_124\_MDPX3\_1P8 | 109 | 49 | DISP\_I2C\_SDA\_MDPX3\_1P8 |
| MD\_GPIO\_71\_MDPX3\_1P8 | 110 | 50 | DISP\_I2C\_SCL\_MDPX3\_1P8 |
| MD\_DBG\_UART\_TX\_MDPX3\_1P8 | 111 | 51 | MD\_GPIO\_80\_MDPX3\_1P8 |
| MD\_DBG\_UART\_RX\_MDPX3\_1P8 | 112 | 52 | MD\_GPIO\_81\_MDPX3\_1P8 |
| MD\_GPIO\_40\_MDPX3\_1P8 | 113 | 53 | MD\_GPIO\_82\_MDPX3\_1P8 |
| MD\_GPIO\_39\_MDPX3\_1P8 | 114 | 54 | MD\_GPIO\_83\_MDPX3\_1P8 |
| PMA\_GPIO\_02\_POFF\_COMPLETE\_3P3\_N | 115 | 55 | JEXP3\_MD\_GPIO\_49\_MDPX3\_1P8 |
| PMA\_GPIO\_06\_AOSS\_SLP\_ENT\_3P3 | 116 | 56 | JEXP3\_MD\_GPIO\_50\_MDPX3\_1P8 |
| VREG\_WLAN\_BT\_CORE\_VH\_1P95 | 117 | 57 | JEXP3\_MD\_GPIO\_51\_MDPX3\_1P8 |
| VREG\_WLAN\_BT\_CORE\_VL\_1P05 | 118 | 58 | JEXP3\_MD\_GPIO\_52\_MDPX3\_1P8 |
| VREG\_WLAN\_BT\_CORE\_VM\_1P35 | 119 | 59 | CCI\_TIMER3\_MDPX3\_1P8 |
| USB1\_VBUS\_ON\_MDPX3\_1P8 | 120 | 60 | MD\_GPIO\_64\_MDPX3\_1P8 |
The following table details the pin mapping for the **JEXP4** connector.
**Table : Pin mapping for the JEXP4 connector**
| Pin name | Pin number | Pin number | Pin name |
| --- | --- | --- | --- |
| | 61 | 1 | SD\_CARD\_PWR\_EN |
| Not connected | 62 | 2 | PCIE1\_MEZZCONN\_CLK\_N |
| Not connected | 63 | 3 | PCIE1\_MEZZCONN\_CLK\_P |
| Not connected | 64 | 4 | GND |
| Not connected | 65 | 5 | PCIE1\_MEZZCONN\_RX0\_N |
| Not connected | 66 | 6 | PCIE1\_MEZZCONN\_RX0\_P |
| Not connected | 67 | 7 | GND |
| Not connected | 68 | 8 | PCIE1\_MEZZCONN\_RX1\_N |
| Not connected | 69 | 9 | PCIE1\_MEZZCONN\_RX1\_P |
| Not connected | 70 | 10 | GND |
| Not connected | 71 | 11 | PCIE1\_MEZZCONN\_RX2\_N |
| MD\_GPIO\_63\_MDPX3\_1P8 | 72 | 12 | PCIE1\_MEZZCONN\_RX2\_P |
| PCIE\_SWITCH\_PWR\_EN\_1P8 | 73 | 13 | GND |
| IOEXP4\_IO\_P0\_1P8 | 74 | 14 | PCIE1\_MEZZCONN\_RX3\_N |
| PCIE1\_MEZZCONN\_RST\_1P8\_N | 75 | 15 | PCIE1\_MEZZCONN\_RX3\_P |
| PCIE1\_MEZZCONN\_CLKREQ\_1P8\_N | 76 | 16 | GND |
| PCIE1\_MEZZCONN\_WAKE\_1P8\_N | 77 | 17 | PCIE1\_MEZZCONN\_TX0\_N |
| IOEXP6\_IO\_P3\_1P8 | 78 | 18 | PCIE1\_MEZZCONN\_TX0\_P |
| PMA\_GPIO\_09\_USB2\_ID | 79 | 19 | GND |
| CCI4\_I2C\_SDA\_MDPX3\_1P8 | 80 | 20 | PCIE1\_MEZZCONN\_TX1\_N |
| CCI4\_I2C\_SCL\_MDPX3\_1P8 | 81 | 21 | PCIE1\_MEZZCONN\_TX1\_P |
| IOEXP6\_IO\_P2\_1P8 | 82 | 22 | GND |
| Not connected | 83 | 23 | PCIE1\_MEZZCONN\_TX2\_N |
| IOEXP6\_IO\_P1\_1P8 | 84 | 24 | PCIE1\_MEZZCONN\_TX2\_P |
| Not connected | 85 | 25 | GND |
| CAM2\_PWR\_EN\_MDPX3\_1P8 | 86 | 26 | PCIE1\_MEZZCONN\_TX3\_N |
| Not connected | 87 | 27 | PCIE1\_MEZZCONN\_TX3\_P |
| CCI4\_I2C\_SDA\_MDPX3\_1P8 | 88 | 28 | GND |
| CCI4\_I2C\_SCL\_MDPX3\_1P8 | 89 | 29 | Not connected |
| CAM2\_MCLK\_MDPX3\_1P8 | 90 | 30 | Not connected |
| CAM2\_PWDN\_MDPX3\_1P8 | 91 | 31 | Not connected |
| CAM2\_STROBE\_MDPX3\_1P8 | 92 | 32 | Not connected |
| CAM2\_SPARE\_GPIO\_MDPX3\_1P8 | 93 | 33 | Not connected |
| CAM1\_PWR\_EN\_MDPX3\_1P8 | 94 | 34 | Not connected |
| IOEXP5\_IO\_P4\_1P8 | 95 | 35 | Not connected |
| CCI2\_I2C\_SDA\_MDPX3\_1P8 | 96 | 36 | Not connected |
| CCI2\_I2C\_SCL\_MDPX3\_1P8 | 97 | 37 | Not connected |
| CAM1\_MCLK\_MDPX3\_1P8 | 98 | 38 | Not connected |
| RTSS\_PMIC\_I2C\_SDA\_SPX3\_1P8 | 99 | 39 | GND |
| CAM1\_STROBE\_MDPX3\_1P8 | 100 | 40 | CSI2\_CONN\_NC\_CLK\_P |
| CAM1\_SPARE\_GPIO\_MDPX3\_1P8 | 101 | 41 | CSI2\_CONN\_A0\_CLK\_M |
| CAM0\_PWR\_EN\_MDPX3\_1P8 | 102 | 42 | CSI2\_CONN\_B0\_LN0\_P |
| IOEXP5\_IO\_P5\_1P8 | 103 | 43 | CSI2\_CONN\_C0\_LN0\_M |
| CCI0\_I2C\_SDA\_MDPX3\_1P8 | 104 | 44 | CSI2\_CONN\_A1\_LN1\_P |
| CCI0\_I2C\_SCL\_MDPX3\_1P8 | 105 | 45 | CSI2\_CONN\_B1\_LN1\_M |
| CAM0\_MCLK\_MDPX3\_1P8 | 106 | 46 | CSI2\_CONN\_C1\_LN2\_P |
| RTSS\_PMIC\_I2C\_SCL\_SPX3\_1P8 | 107 | 47 | CSI2\_CONN\_A2\_LN2\_M |
| CAM0\_STROBE\_MDPX3\_1P8 | 108 | 48 | CSI2\_CONN\_B2\_LN3\_P |
| CAM0\_SPARE\_GPIO\_MDPX3\_1P8 | 109 | 49 | CSI2\_CONN\_C2\_LN3\_M |
| GND | 110 | 50 | GND |
| CSI0\_CONN\_NC\_CLK\_P | 111 | 51 | CSI1\_CONN\_NC\_CLK\_P |
| CSI0\_CONN\_A0\_CLK\_M | 112 | 52 | CSI1\_CONN\_A0\_CLK\_M |
| CSI0\_CONN\_B0\_LN0\_P | 113 | 53 | CSI1\_CONN\_B0\_LN0\_P |
| CSI0\_CONN\_C0\_LN0\_M | 114 | 54 | CSI1\_CONN\_C0\_LN0\_M |
| CSI0\_CONN\_A1\_LN1\_P | 115 | 55 | CSI1\_CONN\_A1\_LN1\_P |
| CSI0\_CONN\_B1\_LN1\_M | 116 | 56 | CSI1\_CONN\_B1\_LN1\_M |
| CSI0\_CONN\_C1\_LN2\_P | 117 | 57 | CSI1\_CONN\_C1\_LN2\_P |
| CSI0\_CONN\_A2\_LN2\_M | 118 | 58 | CSI1\_CONN\_A2\_LN2\_M |
| CSI0\_CONN\_B2\_LN3\_P | 119 | 59 | CSI1\_CONN\_B2\_LN3\_P |
| CSI0\_CONN\_C2\_LN3\_M | 120 | 60 | CSI1\_CONN\_C2\_LN3\_M |
### Debug interface
The platform includes a micro-USB connector receptacle (JTAC, part number: 0475890001) connected to an FTDI chip (U19, part number: FT4232HL-REEL), which is used for debugging purposes.
For the location of the debug interface connector on the platform, see the [Connectors on Dragonwing IQ-8275 EVK](https://docs.qualcomm.com/doc/80-70030-281/topic/iq8-ug-hw-overview.html#fig-jmq-qqy-w2c).
### JTAG interface
The JTAG connector header on the board is a 20-position pin interconnect with a 0.050” (1.27 mm) pitch and 0.050” (1.27 mm) row spacing. The reference designator for the JTAG connector component is JTAG, and its part number is FTSH-110-01-L-D-RA-K. To use a traditional JTAG connector, an adapter such as the 65-PM339-1 may be required.
For the location of the JTAG connectors on the platform, see the [Connectors on Dragonwing IQ-8275 EVK](https://docs.qualcomm.com/doc/80-70030-281/topic/iq8-ug-hw-overview.html#fig-jmq-qqy-w2c).
### Audio
For speaker and audio support, the HS0\_MI2S interface is used for the two onboard audio amplifiers, and the HS2\_MI2S interface is used for the I^2^S microphone on the mainboard. Both interfaces can optionally be switched to the mezzanine connectors for expansion purposes.
Consider the following details about speakers and microphones on the device:
- **Speakers:** Onboard speakers (with MAX98357 I^2^S-amps); HS0\_MI2S is shared between both left and right speakers to enable stereo sound.
- **Microphones:** The EVK includes a single onboard microphone (MMICT5848) that uses the HS2\_MI2S interface. By default, the microphone is configured to the left channel.
The following figure shows the audio connections.
**Figure : Audio connections**
The following figure shows the Dragonwing IQ-8275 EVK connected to two mini speakers.
**Figure : Dragonwing IQ-8275 EVK connected to two mini speakers**
## Next steps
- [Set up the device.](https://docs.qualcomm.com/doc/80-70030-281/topic/iq8-ug-set-up-the-device.html#iq8-ug-set-up-the-device)
- [Run sample applications.](https://docs.qualcomm.com/doc/80-70030-281/topic/iq8-ug-run-sample-apps.html#iq8-ug-run-sample-applications)
- [Develop an application.](https://docs.qualcomm.com/doc/80-70030-281/topic/iq8-ug-develop-an-app.html#iq8-ug-develop-an-app)
Last Published: Jul 27, 2026
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Source: [https://docs.qualcomm.com/doc/80-70030-281/topic/iq8-ug-hw-overview.html](https://docs.qualcomm.com/doc/80-70030-281/topic/iq8-ug-hw-overview.html)