Power architecture .. container:: shortdesc > > > The CPU subsystem architecture describes the organization of CPU cores > and their power domains. Understanding the architecture helps you to > monitor the CPU core usage and balance the power > consumption and performance of the device. > > > Tab QCS6490/QCS5430 > Tab IQ-9075 > Tab IQ-8275 > Tab IQ-615 > > APSS is a set of CPUs organized into clusters. All CPU cores in a > cluster operate at a similar frequency. Each CPU core in a cluster has a > dedicated L1 and L2 cache. > > > The CPU subsystem consists of three clusters and L3 cache as follows: > > > - Qualcomm^®^ Kryo^™^ CPU Prime cluster, which has a performance CPU core > - Kryo Gold cluster, which has CPU cores with balanced power and performance > - Kryo Silver cluster, which has low power CPU cores for lightweight applications > - Common L3 cache > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > **Figure : QCS6490/QCS5430 APSS CPU subsystem architecture** > > The CPU subsystem operates on two power domains, each supplied by a dedicated switched mode power supply (SMPS) rail. > > > The following are the supported power domains: > > > > > > > > > Table : Power domains and their descriptions > > > > > > | Power domains | Description | > > | --- | --- | > > | `VDD_APC0` | Power domain for the Silver cluster CPU cores and L3 cache digital circuit | > > | `VDD_APC1` | Power domain for the Gold and Prime clusters CPU cores | > > | `Chip_MX` | Power domain for the L1, L2, and L3 cache memories | > > > > > > > > Note > > > > > > To know more about CPU core arrangement, see [QCS6490 Data Sheet](https://docs.qualcomm.com/bundle/publicresource/topics/80-23889-1/device-description.html) > > and [QCS5430 Data Sheet](https://docs.qualcomm.com/bundle/publicresource/topics/80-23889-1/device-description.html). > > The CPU subsystem consists of two clusters with a dedicated L3 cache for each cluster. > Each CPU core in a cluster has a dedicated L1 and L2 cache. All CPU > cores in a cluster operate at a similar frequency. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > **Figure : IQ-9075 APSS CPU subsystem architecture** > > The CPU subsystem operates on two power domains, each supplied by a > dedicated SMPS rail. > > > The following are the supported power domains: > > > > Table : Power domains and their descriptions > > > | Power domains | Description | > | --- | --- | > | `VDD_APC0` | Power domain for Cluster0 CPU cores and L3 cache digital circuit | > | `VDD_APC1` | Power domain for Cluster1 CPU cores and L3 cache digital circuit | > | `Chip_MX` | Power domain for the L1, L2, and L3 cache memories | > > > > To know more about CPU core arrangement, see [IQ-9075 Data > Sheet](https://docs.qualcomm.com/bundle/publicresource/topics/80-73417-1/device-description.html). > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > APSS is a set of CPUs organized into clusters. All CPU cores in a cluster operate at a similar frequency. Each CPU core in a cluster has a > > > dedicated L1 and L2 cache. > > > > > > > > > The CPU subsystem consists of three clusters and L3 cache as follows: > > > > > > - Kryo Prime cluster with performance CPU cores > > - Kryo Gold cluster, which has CPU cores with balanced power and performance > > - Kryo Silver cluster, which has low power CPU cores for lightweight applications > > - Silver cluster has a dedicated L3 cache > > - Gold and Prime clusters share a dedicated L3 cache > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > **Figure : IQ-8275 APSS CPU subsystem architecture** > > > > > > The CPU subsystem operates on two power domains, each supplied by a > > > dedicated SMPS rail. > > > > > > > > > The following are the supported power domains: > > > > > > > > > > > > Table : Power domains and their descriptions > > > > > > > > > | Power domains | Description | > > > | --- | --- | > > > | `VDD_APC0` | Power domain for the Gold and Prime cluster CPU cores and L3 cache digital circuit | > > > | `VDD_APC1` | Power domain for the Silver cluster CPU cores and L3 cache digital circuit | > > > | `Chip_MX` | Power domain for the L1, L2, and L3 cache memories | > > > > To know more about CPU core arrangement, see [IQ-8275 Data > Sheet](https://docs.qualcomm.com/bundle/publicresource/topics/80-73475-1/device-description.html). > > > > > > > APSS is a set of CPUs organized into clusters. All CPU cores in a cluster operate at a similar frequency. Each CPU core in a cluster has a > > dedicated L1 and L2 cache. > > > > The CPU subsystem consists of two clusters and L3 cache as follows: > > - Qualcomm^®^ Kryo^™^ Gold cluster, which has CPU cores with balanced power and performance > - Kryo Silver cluster, which has low power CPU cores for lightweight applications > - Common L3 cache > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > **Figure : IQ-615 APSS CPU subsystem architecture** > > > > The CPU subsystem operates on two power domains, each supplied by a > > dedicated SMPS rail. > > > > > > The following are the supported power domains: > > > > > > > > Table : Power domains and their descriptions > > > > > > | Power domains | Description | > > | --- | --- | > > | `VDD_APC0` | Power domain for the Silver cluster CPU cores and L3 cache digital circuit | > > | `VDD_APC1` | Power domain for the Gold cluster CPU cores | > > | `Chip_MX` | Power domain for the L1, L2, and L3 cache memories | > > > > To know more about CPU core arrangement, see [IQ-615 Data > Sheet](https://docs.qualcomm.com/bundle/publicresource/topics/80-73480-1/device-description.html). # Next steps - [Power states and features](https://docs.qualcomm.com/doc/80-70030-30/topic/powerfeatures.html#powerandthermalfeatures) Last Published: Jun 22, 2026 [Previous Topic Get started with power optimization workflow](https://docs.qualcomm.com/bundle/publicresource/80-70030-30/topics/get-started.md) [Next Topic Power states and features](https://docs.qualcomm.com/bundle/publicresource/80-70030-30/topics/powerfeatures.md)