# System-on-chip sleep states A system-on-chip (SoC) sleep state is a low power mode that the entire SoC enters when the device is idle or not actively running any use cases. 1. Review SoC Sleep state functionality. > > > The SoC supports many sleep states based on resource availability: > > > > > > > > > - DDR (Double data rate memory) > > - XO (Crystal oscillator) clock > > - `(Chip_CX)` (Digital power supply) > > - `(Chip_MX)` (Memory domains power supply) Note The SoC sleep states are enabled on QCS6490/QCS5430 and Qualcomm® Dragonwing™ IQ-615. 2. Understand sleep transition. As the device transitions from active state to SoC sleep state, the power consumption decreases. For example, when the device is idle with no use cases running, it’s in the SoC sleep state (AOSD). This is the deepest sleep state and consumes the least power. In this state, the resources, such as, XO clock, memory, and power supply of digital and memory domains also enter their respective sleep states. 3. Learn the SoC sleep states and their resource states: Note The SoC sleep states listed in the table are for reference only. You can’t enable or disable SoC sleep states. Table : SoC sleep states | SoC sleep states | Resource states | | --- | --- | | Active |
XO clock on
Chip_CX (Digital) and Chip_MX (Memory) power
domains operate at active voltage level
Memory in Self-Refresh mode
XO clock on
Chip_CX and Chip_MX power domains are configured
with active voltage
Memory in Self-Refresh mode
XO clock off
Chip_CX power domain configured with least voltage
Chip_MX configured with active voltage
The deepest system sleep state where the system is
expected to achieve the lowest sleep power, which is the
most preferred state for optimal power management
Memory in Self-Refresh mode
XO clock off
Chip_CX and Chip_MX power domains configured with the
least voltage
Indicates the number of times the SoC entered a
particular power state
A nonzero count indicates that the SoC has exercised
sleep states