# Dragonwing IQ-9075 interface overview

Source: [https://docs.qualcomm.com/doc/80-70030-8/topic/qcs9075-interface-overview.html](https://docs.qualcomm.com/doc/80-70030-8/topic/qcs9075-interface-overview.html)

The following table lists the device interface features in Dragonwing IQ-9075.

| **2xQUP v3 serial                                engine** | **2xQUP v3 serial                                engine** | **2xQUP v3 serial                                engine** | **2xQUP v3 serial                                engine** | **2xQUP v3 serial                                engine** |
| --- | --- | --- | --- | --- |
| Serial engine instances | QUPV3\_1 | QUPV3\_1 | QUPV3\_2 | QUPV3\_3 |
| Application processor QUP v3 serial engine | 7 | 7 | 7 | 1 |
| **3xUSB                                controller** | **3xUSB                                controller** | **3xUSB                                controller** | **3xUSB                                controller** | **3xUSB                                controller** |
| Controller address | 0xa600000 | 0xa800000 | 0xa400000 | 0xa400000 |
| Maximum speed | USB 3.x SuperSpeed | USB 3.x SuperSpeed | USB 2.0 high speed | USB 2.0 high speed |
| HS/SS PHY power rails | <ul class="ul" id="qcs9075-interface-overview__ul_yf2_z4d_ncc"><br>                                <li class="li">L7A: VDD_A_USBHS_0_0P9</li><br><br>                                <li class="li">L6C: VDD_A_USBHS_0_1P8 L9A: VDD_A_USBHS_0_3P1</li><br><br>                                <li class="li">L7A: VDD_A_USBSS_0_0P9</li><br><br>                                <li class="li">L1C: VDD_A_USBSS_0_1P2</li><br><br>                            </ul> | <ul class="ul" id="qcs9075-interface-overview__ul_otg_cpd_ncc"><br>                                <li class="li">L7A:VDD_A_USBHS_1_0P9</li><br><br>                                <li class="li">L6C:VDD_A_USBHS_1_1P8</li><br><br>                                <li class="li">L9A:VDD_A_USBHS_1_3P1</li><br><br>                                <li class="li">L7A:VDD_A_USBSS_1_0P9</li><br><br>                                <li class="li">L1C:VDD_A_USBSS_1_1P2</li><br><br>                            </ul> | <ul class="ul" id="qcs9075-interface-overview__ul_vrd_hpd_ncc"><br>                                <li class="li">VDD_A_USBHS_2_1P8 </li><br><br>                                <li class="li">VDD_A_USBHS_2_3P1</li><br><br>                            </ul> | <ul class="ul" id="qcs9075-interface-overview__ul_vrd_hpd_ncc"><br>                                <li class="li">VDD_A_USBHS_2_1P8 </li><br><br>                                <li class="li">VDD_A_USBHS_2_3P1</li><br><br>                            </ul> |
| **2xPCIe                                controller** | **2xPCIe                                controller** | **2xPCIe                                controller** | **2xPCIe                                controller** | **2xPCIe                                controller** |
| Root complex | RC1 | RC1 | RC0 | RC0 |
| Speed | Gen4 2L (16 GT/s) | Gen4 2L (16 GT/s) | Gen4 4L (16 GT/s) | Gen4 4L (16 GT/s) |
| Configuration space | 0x40100000 (0x100000) 1 MB | 0x40100000 (0x100000) 1 MB | 0x60100000 (0x100000) 1 MB | 0x60100000 (0x100000) 1 MB |
| I/O space | 0x40200000 (0x100000) 1 MB | 0x40200000 (0x100000) 1 MB | 0x60200000 (0x100000) 1 MB | 0x60200000 (0x100000) 1 MB |
| Base address Register space (BAR) | 0x40300000 (0x1fd00000) 509 MB | 0x40300000 (0x1fd00000) 509 MB | 0x60300000 (0x1fd00000)<br>                            509 MB | 0x60300000 (0x1fd00000)<br>                            509 MB |
| Power rails | <ul class="ul" id="qcs9075-interface-overview__ul_u2p_bqd_ncc"><br>                                <li class="li">vreg_l5a (VDD_A_PCIE_0_CORE)</li><br><br>                                <li class="li">vreg_l1c (VDD_A_PCIE_0_PLL_1P2)</li><br><br>                            </ul> | <ul class="ul" id="qcs9075-interface-overview__ul_u2p_bqd_ncc"><br>                                <li class="li">vreg_l5a (VDD_A_PCIE_0_CORE)</li><br><br>                                <li class="li">vreg_l1c (VDD_A_PCIE_0_PLL_1P2)</li><br><br>                            </ul> | <ul class="ul" id="qcs9075-interface-overview__ul_xxg_1rd_ncc"><br>                                <li class="li">vreg_l5a (VDD_A_PCIE_1_CORE)</li><br><br>                                <li class="li">vreg_l1c (VDD_A_PCIE_1_PLL_1P2)</li><br><br>                            </ul> | <ul class="ul" id="qcs9075-interface-overview__ul_xxg_1rd_ncc"><br>                                <li class="li">vreg_l5a (VDD_A_PCIE_1_CORE)</li><br><br>                                <li class="li">vreg_l1c (VDD_A_PCIE_1_PLL_1P2)</li><br><br>                            </ul> |
| Interrupts | MSI and PCI earlier interrupts | MSI and PCI earlier interrupts | MSI and PCI earlier<br>                            interrupts | MSI and PCI earlier<br>                            interrupts |
| Power management | ASPM (L1/L1ss, L0s) | ASPM (L1/L1ss, L0s) | ASPM (L1/L1ss, L0s) | ASPM (L1/L1ss, L0s) |

## QUP v3 mapping to protocols and GPIOs in Dragonwing IQ-9075

Dragonwing IQ-9075 has 26 QUP v3 serial engines. The following table list the protocol and GPIO
                mapping.

| QUP v3 serial<br>                                    engine | QUP v3 serial<br>                                    engine | Protocols | Protocols | Protocols | Protocols | QUP lane to GPIO<br>                                    mapping | QUP lane to GPIO<br>                                    mapping | QUP lane to GPIO<br>                                    mapping | QUP lane to GPIO<br>                                    mapping | QUP lane to GPIO<br>                                    mapping | QUP lane to GPIO<br>                                    mapping | QUP lane to GPIO<br>                                    mapping |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| QUP v3 serial<br>                                    engine | QUP v3 serial<br>                                    engine | UART | HS UART | I2C-M | SPI-M | L0 | L1 | L2 | L3 | L4 | L5 | L6 |
| QUP\_0 | SE0 | Yes | – | Yes | Yes | 20 | 21 | 22 | 23 | – | – | – |
| QUP\_0 | SE1 | Yes | – | Yes | Yes | 24 | 25 | 26 | 27 | – | – | – |
| QUP\_0 | SE2 | Yes | Yes | Yes | Yes | 36 | 37 | 38 | 39 | – | – | – |
| QUP\_0 | SE3 | Yes | Yes | Yes | Yes | 28 | 29 | 30 | 31 | – | – | – |
| QUP\_0 | SE4 | Yes | – | Yes | Yes | 32 | 33 | 34 | 35 | – | – | – |
| QUP\_0 | SE5 | Yes | – | Yes | Yes | 36 | 37 | 38 | 39 | – | – | – |
| QUP\_1 | SE0 | Yes | – | Yes | Yes | 40 | 41 | 42 | 43 | – | – | – |
| QUP\_1 | SE1 | Yes | – | Yes | Yes | 42 | 43 | 40 | 41 | – | – | – |
| QUP\_1 | SE2 | Yes | Yes | Yes | Yes | 46 | 47 | 44 | 45 | – | – | – |
| QUP\_1 | SE3 | Yes | Yes | Yes | Yes | 44 | 45 | 46 | 47 | – | – | – |
| QUP\_1 | SE4 | Yes | – | Yes | Yes | 48 | 49 | 50 | 51 | – | – | – |
| QUP\_1 | SE5 | Yes | – | Yes | Yes | 52 | 53 | 54 | 55 | – | – | – |
| QUP\_1 | SE6 | Yes | – | Yes | Yes | 56 | 57 | 56 | 57 | – | – | – |
| QUP\_2 | SE0 | Yes | – | Yes | Yes | 80 | 81 | 82 | 83 | – | – | – |
| QUP\_2 | SE1 | Yes | – | Yes | Yes | 84 | 85 | 99 | 100 | – | – | – |
| QUP\_2 | SE2 | Yes | Yes | Yes | Yes | 86 | 87 | 88 | 89 | 90 | – | – |
| QUP\_2 | SE3 | Yes | Yes | Yes | Yes | 91 | 92 | 93 | 94 | – | – | – |
| QUP\_2 | SE4 | Yes | – | Yes | Yes | 95 | 96 | 97 | 98 | – | – | – |
| QUP\_2 | SE5 | Yes | – | Yes | Yes | 99 | 100 | 84 | 85 | – | – | – |
| QUP\_2 | SE6 | Yes | – | Yes | Yes | 97 | 98 | 95 | 96 | – | – | – |
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**Parent Topic:** [Overview of peripheral interfaces](https://docs.qualcomm.com/doc/80-70030-8/topic/overview-of-wired-interfaces.html)

Last Published: Jul 03, 2026

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