# QCS9075 high-level block diagram and FCBGA1723+HS package outline drawing Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/high-level-block-diagram-and-package-outline-drawing.html](https://docs.qualcomm.com/doc/80-73417-1/topic/high-level-block-diagram-and-package-outline-drawing.html) Connectivity Multimedia Memory support Real-time subsystem QCS9075 UFS SDC 4-lane DSI (x2) 4-lane CSI (x4) RTSS_IO (x79) GPIO (x149) PCIe Gen 4 (x 2 lane) SGMII (x2) EBI0-1 LPDDR5 LPDDR5 EBI2-3 Powermanagement SPMI USB 3.1 Gen 2 (x2)(HS + SS) USB 2.0 (x1) eDP/DP (x4) LS-I 2 S/TDM/PCM (x10)** HS-I 2 S (x5)* * 2 of the 5 HS-I 2 S interfaces are muxed behind I 2 S interfaces.** 10 LS I 2 S interfaces include 7 dedicated LS I 2 S and 3 dedicated HS I 2 S reconfigured as LS I 2 S interfaces. LPDDR5 EBI4-5 RGMII NORflash OSPI Processors System functions SPI UART I3C I2C CAN eMMC or SD card SPI UART I2C I3C Ethernetswitches/PHY SGMII LPASS / Main Audio CODEC/MIC/Amplifiers QUPs PCIe Gen 4 (x 4 lane) UFS UFS Gear 4, 2L x2 PCIe slots/switches eDP/DP connectors/display bridges Display connectors/bridges Camera connectors/bridges Last Published: Jun 30, 2026 [Previous Topic Key features](https://docs.qualcomm.com/bundle/publicresource/80-73417-1/topics/key-features.md) [Next Topic Introduction](https://docs.qualcomm.com/bundle/publicresource/80-73417-1/topics/introduction.md)