# Introduction
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-73417-1/topic/introduction.html)
**Document updates**
See the [Revision history](https://docs.qualcomm.com/doc/80-73417-1/topic/revision-history.html#topic.dita_4df2cfbc-6e4a-48bd-bd56-5f335899a177) for details on the changes included in this revision.
Note: All the information provided is preliminary and is subject to change before CS.
## Functional block diagram
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-73417-1/topic/introduction.html)
Figure : QCS9075 functional block diagram
## QCS9075 features
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-73417-1/topic/introduction.html)
The following table lists the comprehensive features of the QCS9075 chipset and its
capabilities.
Note: Some of the hardware features integrated within the QCS9075
must be enabled by software. See the latest revision of the applicable software release notes
to identify the enabled QCS9075 features.
| Function | Qualcomm Dragonwing IQ-9075 | Qualcomm Dragonwing IQ-9075 |
| --- | --- | --- |
| SKU | QCS9075-AC | QCS9075-AA |
| CPU | 8-Core Kryo Gen 6 | 8-Core Kryo Gen 6 |
| CPU | 2.1 GHz | 2.36 GHz |
| AI performance | Hexagon | Hexagon |
| AI performance | Llama 2 7B: up to 22 tokens/sec | Llama 2 7B: up to 22 tokens/sec |
| AI performance | 50 Dense TOPS | 100 Dense TOPS |
| GPU | Adreno 663 | Adreno 663 |
| GPU | 530 MHz | 800 MHz |
| Memory | 6 × 16-bit LPDDR5 at 3200 MHz | 6 × 16-bit LPDDR5 at 3200 MHz |
| Addressable memory | Up to 36 GB with inline ECC | Up to 36 GB with inline ECC |
| Audio DSP (LPASS) | 1980 MPPS
7 × TDM/I^2^S +
3 × High-Speed I^2^S for radio FE | 1980 MPPS
7 × TDM/I^2^S +
3 × High-Speed I^2^S for radio FE |
| Display support | Dual Qualcomm® Adreno™ DPU 1199, max 48 megapixel and 12 displays with no superframe
5 × 4K at 60
3 × 4K at 60 + 8x 1080P at 60
2 × DSI + 2 × DP/eDP MST2 + 2 × DP/eDP MST4 | Dual Qualcomm® Adreno™ DPU 1199, max 48 megapixel and 12 displays with no superframe
Formats: AV1, H.264, H.265, VP9, MPEG-2 | 4K at 275:
1 × 8K at 60
2 × 8K at 30
4 × 4K at 60
8 × 4K at 30
16 × 1080P at 60
32 × 1080P at 30
Formats: AV1, H.264, H.265, VP9, MPEG-2 |
| Video encode | 4K at 170:
2 × 4K at 60
4 × 4k at 30
8 × 1080P at 60
16 × 1080P at 30
Formats: H.264, H.265, HEIF/HEIC | 4K at 170:
2 × 4K at 60
4 × 4k at 30
8 × 1080P at 60
16 × 1080P at 30
Formats: H.264, H.265, HEIF/HEIC |
| Camera | Up to 16 cameras
Maximum 12 MP sensor resolution
4 × 4-lane CSI2 | Up to 16 cameras
Maximum 12 MP sensor resolution
4 × 4-lane CSI2 |
| PCIe | 2 × PCIe Gen 4: 1 × 2-lane + 1 × 4-lane (root complex and endpoint) | 2 × PCIe Gen 4: 1 × 2-lane + 1 × 4-lane (root complex and endpoint) |
| USB | 2 × USB 3.1 Gen 2 USB Type-C, 1 × USB 2.0 | 2 × USB 3.1 Gen 2 USB Type-C, 1 × USB 2.0 |
| Networking | 2 × 2.5 GbE with TSN (SGMII) | 2 × 2.5 GbE with TSN (SGMII) |
| Other I/O | 21 × QUP\_SEs [^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/introduction.html#concept.dita_ccec286c-3f72-433c-b4dc-e90f60d7d110__fn_t5w_cv1_4gc) (supports UART/I²C/SPI), 149 × GPIOs | 21 × QUP\_SEs [^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/introduction.html#concept.dita_ccec286c-3f72-433c-b4dc-e90f60d7d110__fn_t5w_cv1_4gc) (supports UART/I²C/SPI), 149 × GPIOs |
| Storage | 2 × UFS 3.1 Gen4 2-lane, 1 × 8-bit SDCC5 with eMMC, NVMe over PCIe | 2 × UFS 3.1 Gen4 2-lane, 1 × 8-bit SDCC5 with eMMC, NVMe over PCIe |
| Wi-Fi/BT/WAN | Support through companion chips: QCA6698AQ, SDX35, SDX72 | Support through companion chips: QCA6698AQ, SDX35, SDX72 |
| MCU-like subsystem | 4 × realtime cores at 1.85 GHz | 4 × realtime cores at 1.85 GHz |
| MCU-like subsystem | 1 × RGMII with TSN, 8 × CAN-FD, 5 × QUP\_SEs [^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/introduction.html#concept.dita_ccec286c-3f72-433c-b4dc-e90f60d7d110__fn_t5w_cv1_4gc) (supports UART/I²C/SPI) | 1 × RGMII with TSN, 8 × CAN-FD, 5 × QUP\_SEs [^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/introduction.html#concept.dita_ccec286c-3f72-433c-b4dc-e90f60d7d110__fn_t5w_cv1_4gc) (supports UART/I²C/SPI) |
| Power (SoC only) | 3.8 W–20 W | 3.8 W–20 W |
| OS | Linux Yocto, Linux Ubuntu | Linux Yocto, Linux Ubuntu |
| Package | 25.0 mm × 25.0 mm/0.6 mm ball pitch | 25.0 mm × 25.0 mm/0.6 mm ball pitch |
| Temperature range (Tj) | -40°C – 115°C | -40°C – 115°C |
| | | |
| | | |
^1^ Qualcomm Universal
Peripheral Serial Engines
### Processor
| Feature | Capabilities |
| --- | --- |
| CPU | Kryo Gen 6 CPU subsystem – two identical quad-core cluster with full hardware coherency in between
Quad Kryo Gold Prime cores with 512 kB L2 cache per core at 2.36 GHz
2 MB shared L3 cache per cluster
|
| Digital signal processing | Dual Hexagon Tensor Processor integrated with Qualcomm Hexagon DSP, up to 1.420 GHz, quad Hexagon Vector eXtensions (HVX), and dual Hexagon Matrix eXtensions (HMX) co-processors
Common AI processing architecture for machine learning use cases
Matrix co-processors (one HMX-Integer and one HMX-float per Hexagon Tensor Processor) for deep neural network acceleration
Audio Hexagon DSP dedicated to audio subsystem, up to 1.344 GHz and with a 2 MB L2/TCM
Two general purpose Hexagon DSPs up to 1.708 GHz and with a 1 MB L2 cache for advanced audio processing and other use cases
All Hexagon DSPs are cache-based processors with full access to DDR memory |
| Artificial intelligence (AI) | Up to 100 dense
Llama 2 7B: 22 tokens per second |
| Real-time subsystem (RTSS) |
A subsystem integrated with quad cortex-R52 CPU
Each cortex-R52 CPU frequency is up to 1.850 GHz
Independent booting capability through OSPI interface
|
| Always-on subsystem |
Always-on subsystem with always-on processor
Hardware-based resource and power management (RPMh) with hardware accelerators for voltage control and regulation, clock management, and resource communication
|
### Memory
| Feature | Capabilities |
| --- | --- |
| System memory via EBI |
1 MB L2 cache and 8 MB Vector-TCM (vTCM) for each Hexagon Tensor Processor
|
| ***External memory*** | ***External memory*** |
| Via UFS | Two UFS 3.1 gear 4 – two lanes for on-board memory (UFS0 as main domain boot up device) |
| Via eMMC | 1 × 8-bit SDIO interface (SDC1) to support eMMC 5.1. [^2^](https://docs.qualcomm.com/doc/80-73417-1/topic/introduction.html#fntarg_2_features) |
| Via Octal/Quad SPI | NOR flash memory running up to 166 MHz as RTSS domain boot up device |
| Via PCIe | NVMe (non-bootable) |
[^2^](https://docs.qualcomm.com/doc/80-73417-1/topic/introduction.html#fnsrc_2_features) 2 × UFS and 1 × eMMC
cannot be supported together. More details on the eMMC support will be added in
a future revision of this document.
### Multimedia
| Feature | Capabilities |
| --- | --- |
| Adreno display processing unit (DPU) | Dual Adreno DPU1199 |
| Display interface/performance | Two 4-lane MIPI DSI with VESA DSC v1.2
D-PHY v1.2: 2.5 Gbps/lane on four lanes per port, 10 Gbps/port, up to 20 Gbps total
C-PHY v1.1: 5.7 Gbps/trio on three trios per port, 17 Gbps/port, up to 34 Gbps total
Four Embedded DisplayPorts (eDP)/DisplayPort (DP) v1.4 at 8.1 Gbps/lane, 32.4 Gbps/port, MST and VESA DSC v1.2a and forward error correction (FEC)
Up to a maximum of 48 MP; example configuration: 5 × 4K
Data format inputs: 24 bit HDR RGGB/RCCB/RYYCy, RCCG, YUV
Data format outputs: 12/10/8 bit Y, 10/8 bit UV; RGB8 in planar or interleaved order
|
| Camera interface | Processing features: 24b HDR Bayer processing, lens distortion correction, advanced tone mapping, offset correction, lens roll off correction, bad pixel correction, directional scalers, color LUTs, color space transform, noise reduction
Four MIPI CSI interfaces configurable as D-PHY or C-PHY mode
D-PHY v1.2: 2.5 Gbps/lane on four lanes per port, 10 Gbps/port, up to 40 Gbps total. Each 4-lane port can also be configured as 1-lane + 2-lane ports or 1-lane + 1-lane ports
C-PHY v1.2: 10.2 Gbps/trio on three trios per port, 31 Gbps/port, up to 123 Gbps total. Each 3-trio port can also be configured as 1-trio + 2-trio ports, or three 1-trio ports
|
| Adreno video processing unit (VPU) |
Adreno VPU 765 – fifth-generation UHD video processing unit
Up to 10 (7 + 3) interfaces (pin multiplexed with PCM/TDM interfaces): nine (6 + 3) interfaces with two data lanes each; one interface with four data lanes for a total of 22 (16 + 6) data lanes
Three MCLKs up to 512 × 48 kHz (24.576 MHz); clock master or slave independent of the source of frame sync/word select
Supports two channels of 32-bit sample up to 384 kHz sample rate, for each data line
|
| PCM/TDM (muxed with LS-I^2^S and HS-I^2^S pins) |
Multi-lane TDM (master and slave capable)
Up to 10 (7 + 3) interfaces (pin multiplexed with I2S): nine (6 + 3) interfaces with two data lanes each; one interface with four data lanes
Short, long, and one-slot sync mode
Maximum clock frequency of 24.576 MHz (muxed with LS-I2S) or 73.728 MHz (RX, muxed with HS-I2S)
Up to 512 bits/frame, 32 bits/slot, 16 slots/interface with 48 KHz sample rate
Support TDM interfaces grouping for data synchronization
|
| HS-I^2^S(muxed with PCM/TDM pins) |
Five high-speed (up to 73.728 MHz) receive interfaces for software defined radio (SDR); two of them are muxed behind LS-I2S interfaces; all of them can be configured as LS-I2S interfaces if needed
Two receive-only data lanes per interface; clock and word select in slave mode
Note: The additional LS-I^2^S interfaces (muxed with PCM/TDM pins) are configured from the three dedicated HS-I^2^S interfaces. |
### Connectivity
| Feature | Capabilities |
| --- | --- |
| Qualcomm universal peripheral (QUP) serial engines |
21 main domain (MD) GPIO-based QUP SEs: 5 bits for QUP2_SE_2 and 4 bits for each of the other 19 QUP SEs; multiplexed serial interface functions
Five RTSS domain GPIO-based QUP SEs: 5 bits for QUP0_SE_4 and 4 bits for each of the other four QUP SEs; multiplexed serial interface functions
|
| UART (up to 4 MHz) | UART (64 B FIFO) interface available on all MD and RTSS domain QUP SEs, except MD QUP0\_SE\_2/3, QUP1\_SE\_2/3, QUP2\_SE\_2/3 and RTSS QUP0\_SE\_2/3, which also support HS-UART (128 B FIFO) |
| I^2^C master (up to 1 MHz) | I^2^C interface available on MD and RTSS domain QUP SEs, dedicated controller for each port |
| SPI master (up to 50 MHz) | SPI master interfaces available on all MD and RTSS domains QUP SEs, except for MD QUP1\_SE\_6 |
| SPI slave (up to 50 MHz) | SPI slave interface available on MD QUP0\_SE\_4/5, QUP1\_SE\_4/5, QUP2\_SE\_4/5 and RTSS QUP0\_SE\_0/1 |
| CCI I^2^C | Eight dedicated I^2^C interfaces for devices using CSI ports |
| USB | Three total USB interfaces
One USB 3.1 Gen 2 - USB0 (HS + SS, support device and host modes)
One USB 3.1 Gen 2 - USB1 (HS + SS, support device and host modes)
One USB2.0 - USB2 (HS, support device and host modes)
|
| PCIe |
One 2-lane PCIe Gen4: PCIe0 (RC + EP)
One 4-lane PCIe Gen4: PCIe1 (RC + EP)
|
| RGMII | One RTSS domain RGMII interface with MDIO for ethernet with AVB |
| CAN-FD | Eight CAN-FD interfaces located in RTSS domain, each of them supports up to 10 Mbps |
| SGMII | Two SGMII interfaces supporting up to 2.5 Gbps each |
### Configurable GPIO
| Feature | Capabilities |
| --- | --- |
| Number of main domain GPIO ports | 149 – GPIO\_0 to GPIO\_148 |
| Number of RTSS domain GPIO ports | 79 – RTSS\_IO\_0 to RTSS\_IO\_78 |
| Input configurations | Pull-up, pull-down, keeper, or no pull |
| Output configurations | Programmable drive current up to 16 mA |
| Top-level mode multiplexer | Provides a convenient way to program groups of GPIOs |
### Internal functions
| Feature | Capabilities |
| --- | --- |
| Security |
Crypto: Hardware ECC and RSA (Elliptic-Curve Cryptography), ICE, Crypto engine v5 (CE5), FIPS/CAVP certifiable, RNG (random number generation)
QFPROM: Fuse bits available for OEM use
Access control: Programmable security domain protection and sand-boxing Content Protection Zone (CPZ) supported
Secure boot and tools: Secure Boot with Sec Tools 5.4; easy to use tool set
Storage security: Secure file system (SFS); fast trusted storage