Page-1

# Pin definitions Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html) ## I/O parameter definitions Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html) | **Symbol** | **Description** | | --- | --- | | ***Pad type*** | ***Pad type*** | | AI | Analog input (does not include pad circuitry) | | AO | Analog output (does not include pad circuitry) | | B | Bidirectional digital with CMOS input | | DI | Digital input (CMOS) | | DO | Digital output (CMOS) | | H | High-voltage tolerant | | S | Schmitt trigger input | | Z | High-impedance (Hi-Z) output | | ***Padpull details for digital I/Os*** | ***Padpull details for digital I/Os*** | | nppdpukp | Programmable pull resistor. The default pull direction is indicated using capital letters and is a prefix to other programmable options:

NP: pdpukp = default no-pull with programmable options following the colon (:)

PD: nppukp = default pull-down with programmable options following the colon (:)

PU: nppdkp = default pull-up with programmable options following the colon (:)

KP: nppdpu = default keeper with programmable options following the colon (:) | | KP | Contains an internal weak keeper device (keepers cannot drive external buses) | | NP | Contains no internal pull | | PU | Contains an internal pull-up device | | PD | Contains an internal pull-down device | | ***Pad voltage groupings for baseband circuits*** | ***Pad voltage groupings for baseband circuits*** | | PX\_0 | Pad group 0 for main domain (control signals); 1.8 V | | PX\_0\_BPP | Pad group 0 \_BPP (back power protection); 1.8 V | | PX\_1 | Pad group 1 (EBI I/O); 1.1 V | | RTSS\_PX\_0 | Pad group 0 for RTSS domain (control signals); 1.8 V | | PX\_3 | Pad group 3 (most peripherals); 1.8 V | | PX\_3\_BPP | Pad group 3\_BPP (back power protection I/Os); 1.8 V | | PX\_7 | Pad group 7 (SDC1- eMMC); 1.8 V | | RTSS\_PX\_3 | Pad group 3 for RTSS domain (most peripherals); 1.8 V | | RTSS\_PX\_3\_BPP | Pad group 3\_BPP (back power protection I/Os) for RTSS; 1.8 V | | RTSS\_PX\_8 | Pad group 8 for RTSS domain (RGMII\_0); 1.8 V or 2.5 V | | PX\_9 | Pad group 9 (UFS0\_REF\_CLK and UFS0\_RESET); 1.2 V | | PX\_10 | Pad group 10 (UFS1\_REF\_CLK and UFS1\_RESET); 1.2 V | | PX\_11 | Pad group 11 (CXO); 1.8 V | | RTSS\_PX\_11 | Pad group 11 for RTSS domain (CXO); 1.8 V | ## Pin map Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html) The QCS9075 chipset is available in the FCBGA1723+HS package that includes several ground pins for electrical grounding, mechanical strength, and thermal continuity. See [Mechanical information](https://docs.qualcomm.com/doc/80-73417-1/topic/mechanical-information.html#topic.dita_a8352866-4b5c-4dd4-b631-e48a853d82e7) for package details. A high-level view of the pin assignments is shown in the following figure. [*QCS9075 + PMM8650AU Pin Assignment and GPIO Configuration Spreadsheet* (80-73417-1A)](https://docs.qualcomm.com/bundle/80-73417-1A/resource/80-73417-1A.xlsm) lists all QCS9075 pad numbers (in alphanumeric order), pad names, pad voltages, pad types, and functional descriptions. Figure : QCS9075 bottom pin assignments ## Pin descriptions Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html) The following tables describe the pin functions, pin pull types, and pin voltages. It also provides a mapping of pin numbers and pin names for all the pins on the device. These include primary pins, GPIO pins, RTSS I/O pins, MD\_LPASS pins, power-supply pins, DNC pins, and ground pins. ### Primary pins | Pin no. | Pin name | Pad voltage | Pad type | Functional description | | --- | --- | --- | --- | --- | | BG45 | CSI0\_NC\_CLK\_P | – | AI | MIPI CSI 0 (D-PHY), differential clock – plus MIPI CSI 0 (C-PHY), no
connect | | BG43 | CSI0\_A0\_CLK\_M | – | AI | MIPI CSI 0 (D-PHY), differential clock – minus MIPI CSI 0 (C-PHY), trio lane 0
– A | | BF44 | CSI0\_B0\_LN0\_P | – | AI | MIPI CSI 0 (D-PHY), differential lane 0 – plus MIPI CSI 0 (C-PHY), trio lane 0
– B | | BF42 | CSI0\_C0\_LN0\_M | – | AI | MIPI CSI 0 (D-PHY), differential lane 0 – minus MIPI CSI 0 (C-PHY), trio lane 0
– C | | BE43 | CSI0\_A1\_LN1\_P | – | AI | MIPI CSI 0 (D-PHY), differential lane 1 – plus MIPI CSI 0 (C-PHY), trio lane 1
– A | | BE41 | CSI0\_B1\_LN1\_M | – | AI | MIPI CSI 0 (D-PHY), differential lane 1 – minus MIPI CSI 0 (C-PHY), trio lane 1
– B | | BF40 | CSI0\_C1\_LN2\_P | – | AI | MIPI CSI 0 (D-PHY), differential lane 2 – plus MIPI CSI 0 (C-PHY), trio lane 1
– C | | BF38 | CSI0\_A2\_LN2\_M | – | AI | MIPI CSI 0 (D-PHY), differential lane 2 – minus MIPI CSI 0 (C-PHY), trio lane 2
– A | | BG39 | CSI0\_B2\_LN3\_P | – | AI | MIPI CSI 0 (D-PHY), differential lane 3 – plus MIPI CSI 0 (C-PHY), trio lane 2
– B | | BG37 | CSI0\_C2\_LN3\_M | – | AI | MIPI CSI 0 (D-PHY), differential lane 3 – minus MIPI CSI 0 (C-PHY), trio lane 2
– C | | BG55 | CSI1\_NC\_CLK\_P | – | AI | MIPI CSI 1 (D-PHY), differential clock – plus MIPI CSI 1 (C-PHY), no
connect | | BG53 | CSI1\_A0\_CLK\_M | – | AI | MIPI CSI 1 (D-PHY), differential clock – minus MIPI CSI 1 (C-PHY), trio lane 0
– A | | BF54 | CSI1\_B0\_LN0\_P | – | AI | MIPI CSI 1 (D-PHY), differential lane 0 – plus MIPI CSI 1 (C-PHY), trio lane 0
– B | | BF52 | CSI1\_C0\_LN0\_M | – | AI | MIPI CSI 1 (D-PHY), differential lane 0 – minus MIPI CSI 1 (C-PHY), trio lane 0
– C | | BE53 | CSI1\_A1\_LN1\_P | – | AI | MIPI CSI 1 (D-PHY), differential lane 1 – plus MIPI CSI 1 (C-PHY), trio lane 1
– A | | BE51 | CSI1\_B1\_LN1\_M | – | AI | MIPI CSI 1 (D-PHY), differential lane 1 – minus MIPI CSI 1 (C-PHY), trio lane 1
– B | | BF50 | CSI1\_C1\_LN2\_P | – | AI | MIPI CSI 1 (D-PHY), differential lane 2 – plus MIPI CSI 1 (C-PHY), trio lane 1
– C | | BF48 | CSI1\_A2\_LN2\_M | – | AI | MIPI CSI 1 (D-PHY), differential lane 2 – minus MIPI CSI 1 (C-PHY), trio lane 2
– A | | BG49 | CSI1\_B2\_LN3\_P | – | AI | MIPI CSI 1 (D-PHY), differential lane 3 – plus MIPI CSI 1 (C-PHY), trio lane 2
– B | | BG47 | CSI1\_C2\_LN3\_M | – | AI | MIPI CSI 1 (D-PHY), differential lane 3 – minus MIPI CSI 1 (C-PHY), trio lane 2
– C | | BD58 | CSI2\_NC\_CLK\_P | – | AI | MIPI CSI 2 (D-PHY), differential clock – plus MIPI CSI 2 (C-PHY), no
connect | | BD56 | CSI2\_A0\_CLK\_M | – | AI | MIPI CSI 2 (D-PHY), differential clock – minus MIPI CSI 2 (C-PHY), trio lane 0
– A | | BC57 | CSI2\_B0\_LN0\_P | – | AI | MIPI CSI 2 (D-PHY), differential lane 0 – plus MIPI CSI 2 (C-PHY), trio lane 0
– B | | BC55 | CSI2\_C0\_LN0\_M | – | AI | MIPI CSI 2 (D-PHY), differential lane 0 – minus MIPI CSI 2 (C-PHY), trio lane 0
– C | | BB56 | CSI2\_A1\_LN1\_P | – | AI | MIPI CSI 2 (D-PHY), differential lane 1 – plus MIPI CSI 2 (C-PHY), trio lane 1
– A | | BB54 | CSI2\_B1\_LN1\_M | – | AI | MIPI CSI 2 (D-PHY), differential lane 1 – minus MIPI CSI 2 (C-PHY), trio lane 1
– B | | BC53 | CSI2\_C1\_LN2\_P | – | AI | MIPI CSI 2 (D-PHY), differential lane 2 – plus MIPI CSI 2 (C-PHY), trio lane 1
– C | | BC51 | CSI2\_A2\_LN2\_M | – | AI | MIPI CSI 2 (D-PHY), differential lane 2 – minus MIPI CSI 2 (C-PHY), trio lane 2
– A | | BD52 | CSI2\_B2\_LN3\_P | – | AI | MIPI CSI 2 (D-PHY), differential lane 3 – plus MIPI CSI 2 (C-PHY), trio lane 2
– B | | BD50 | CSI2\_C2\_LN3\_M | – | AI | MIPI CSI 2 (D-PHY), differential lane 3 – minus MIPI CSI 2 (C-PHY), trio lane 2
– C | | BG65 | CSI3\_NC\_CLK\_P | – | AI | MIPI CSI 3 (D-PHY), differential clock – plus MIPI CSI 3 (C-PHY), no
connect | | BG63 | CSI3\_A0\_CLK\_M | – | AI | MIPI CSI 3 (D-PHY), differential clock – minus MIPI CSI 3 (C-PHY), trio lane 0
– A | | BF64 | CSI3\_B0\_LN0\_P | – | AI | MIPI CSI 3 (D-PHY), differential lane 0 – plus MIPI CSI 3 (C-PHY), trio lane 0
– B | | BF62 | CSI3\_C0\_LN0\_M | – | AI | MIPI CSI 3 (D-PHY), differential lane 0 – minus MIPI CSI 3 (C-PHY), trio lane 0
– C | | BE63 | CSI3\_A1\_LN1\_P | – | AI | MIPI CSI 3 (D-PHY), differential lane 1 – plus MIPI CSI 3 (C-PHY), trio lane 1
– A | | BE61 | CSI3\_B1\_LN1\_M | – | AI | MIPI CSI 3 (D-PHY), differential lane 1 – minus MIPI CSI 3 (C-PHY), trio lane 1
– B | | BF60 | CSI3\_C1\_LN2\_P | – | AI | MIPI CSI 3 (D-PHY), differential lane 2 – plus MIPI CSI 3 (C-PHY), trio lane 1
– C | | BF58 | CSI3\_A2\_LN2\_M | – | AI | MIPI CSI 3 (D-PHY), differential lane 2 – minus MIPI CSI 3 (C-PHY), trio lane 2
– A | | BG59 | CSI3\_B2\_LN3\_P | – | AI | MIPI CSI 3 (D-PHY), differential lane 3 – plus MIPI CSI 3 (C-PHY), trio lane 2
– B | | BG57 | CSI3\_C2\_LN3\_M | – | AI | MIPI CSI 3 (D-PHY), differential lane 3 – minus MIPI CSI 3 (C-PHY), trio lane 2
– C | | AV76 | CXO\_0 | PX\_11 | DI | Core crystal oscillator 0 | | G37 | CXO\_1 | PX\_11 | DI | Core crystal oscillator 1 | | AH80 | DDR\_RESET\_N | PX\_1 | DO | LPDDRx reset (shared by EBIs) | | BG35 | DSI0\_A0\_LN0\_P | – | AO | MIPI DSI 0 (D-PHY), differential lane 0 – plus MIPI DSI 0 (C-PHY), trio lane 0
– A | | BG33 | DSI0\_B0\_LN0\_M | – | AO | MIPI DSI 0 (D-PHY), differential lane 0 – minus MIPI DSI 0 (C-PHY), trio lane 0
– B | | BF34 | DSI0\_C0\_LN1\_P | – | AO | MIPI DSI 0 (D-PHY), differential lane 1 – plus MIPI DSI 0 (C-PHY), trio lane 0
– C | | BF32 | DSI0\_A1\_LN1\_M | – | AO | MIPI DSI 0 (D-PHY), differential lane 1 – minus MIPI DSI 0 (C-PHY), trio lane 1
– A | | BE33 | DSI0\_B1\_CLK\_P | – | AO | MIPI DSI 0 (D-PHY), differential clock – P – plus MIPI DSI 0 (C-PHY), trio lane
1 – B | | BE31 | DSI0\_C1\_CLK\_M | – | AO | MIPI DSI 0 (D-PHY), differential clock – M – minus MIPI DSI 0 (C-PHY), trio
lane 1 – C | | BF30 | DSI0\_A2\_LN2\_P | – | AO | MIPI DSI 0 (D-PHY), differential lane 2 – plus MIPI DSI 0 (C-PHY), trio lane 2
– A | | BF28 | DSI0\_B2\_LN2\_M | – | AO | MIPI DSI 0 (D-PHY), differential lane 2 – minus MIPI DSI 0 (C-PHY), trio lane 2
– B | | BG29 | DSI0\_C2\_LN3\_P | – | AO | MIPI DSI 0 (D-PHY), differential lane 3 – plus MIPI DSI 0 (C-PHY), trio lane 2
– C | | BG27 | DSI0\_NC\_LN3\_M | – | AO | MIPI DSI 0 (D-PHY), differential lane 3 – minus MIPI DSI 0 (C-PHY), no
connect | | BC49 | DSI1\_A0\_LN0\_P | – | AO | MIPI DSI 1 (D-PHY), differential lane 0 – plus MIPI DSI 1 (C-PHY), trio lane 0
– A | | BC47 | DSI1\_B0\_LN0\_M | – | AO | MIPI DSI 1 (D-PHY), differential lane 0 – minus MIPI DSI 1 (C-PHY), trio lane 0
– B | | BB48 | DSI1\_C0\_LN1\_P | – | AO | MIPI DSI 1 (D-PHY), differential lane 1 – plus MIPI DSI 1 (C-PHY), trio lane 0
– C | | BB46 | DSI1\_A1\_LN1\_M | – | AO | MIPI DSI 1 (D-PHY), differential lane 1 – minus MIPI DSI 1 (C-PHY), trio lane 1
– A | | BA47 | DSI1\_B1\_CLK\_P | – | AO | MIPI DSI 1 (D-PHY), differential clock – P – plus MIPI DSI 1 (C-PHY), trio lane
1 – B | | BA45 | DSI1\_C1\_CLK\_M | – | AO | MIPI DSI 1 (D-PHY), differential clock – M – minusMIPI DSI 1 (C-PHY), trio lane
1 – C | | BB44 | DSI1\_A2\_LN2\_P | – | AO | MIPI DSI 1 (D-PHY), differential lane 2 – plus MIPI DSI 1 (C-PHY), trio lane 2
– A | | BB42 | DSI1\_B2\_LN2\_M | – | AO | MIPI DSI 1 (D-PHY), differential lane 2 – minus MIPI DSI 1 (C-PHY), trio lane 2
– B | | BC43 | DSI1\_C2\_LN3\_P | – | AO | MIPI DSI 1 (D-PHY), differential lane 3 – plus MIPI DSI 1 (C-PHY), trio lane 2
– C | | BC41 | DSI1\_NC\_LN3\_M | – | AO | MIPI DSI 1 (D-PHY), differential lane 3 – minus MIPI DSI 1 (C-PHY), no
connect | | AH78 | DS\_EN | PX\_0 | DI | Deep sleep handshake between PMIC and SoC | | H12 | EBI01\_CAL | – | DO | EBI calibration resistor | | C21 | EBI0\_CA0 | – | DO | EBI0 LPDDR5 command/address bit 0 | | B20 | EBI0\_CA1 | – | DO | EBI0 LPDDR5 command/address bit 1 | | D18 | EBI0\_CA2 | – | DO | EBI0 LPDDR5 command/address bit 2 | | D16 | EBI0\_CA3 | – | DO | EBI0 LPDDR5 command/address bit 3 | | B16 | EBI0\_CA4 | – | DO | EBI0 LPDDR5 command/address bit 4 | | A15 | EBI0\_CA5 | – | DO | EBI0 LPDDR5 command/address bit 5 | | C15 | EBI0\_CA6 | – | DO | EBI0 LPDDR5 command/address bit 6 | | A19 | EBI0\_CK\_C | – | DO | EBI0 LPDDR5 differential clock – minus | | A17 | EBI0\_CK\_T | – | DO | EBI0 LPDDR5 differential clock – plus | | C19 | EBI0\_CS0 | – | DO | EBI0 LPDDR5 chip select 0 | | A21 | EBI0\_CS1 | – | DO | EBI0 LPDDR5 chip select 1 | | C7 | EBI0\_DMI0 | – | DO | EBI0 LPDDR5 data mask for byte 0 | | D28 | EBI0\_DMI1 | – | DO | EBI0 LPDDR5 data mask for byte 1 | | D2 | EBI0\_DQ0 | – | B | EBI0 LPDDR5 data bit 0 | | D4 | EBI0\_DQ1 | – | B | EBI0 LPDDR5 data bit 1 | | B4 | EBI0\_DQ2 | – | B | EBI0 LPDDR5 data bit 2 | | C5 | EBI0\_DQ3 | – | B | EBI0 LPDDR5 data bit 3 | | C11 | EBI0\_DQ4 | – | B | EBI0 LPDDR5 data bit 4 | | C13 | EBI0\_DQ5 | – | B | EBI0 LPDDR5 data bit 5 | | A13 | EBI0\_DQ6 | – | B | EBI0 LPDDR5 data bit 6 | | A11 | EBI0\_DQ7 | – | B | EBI0 LPDDR5 data bit 7 | | C33 | EBI0\_DQ8 | – | B | EBI0 LPDDR5 data bit 8 | | C31 | EBI0\_DQ9 | – | B | EBI0 LPDDR5 data bit 9 | | A33 | EBI0\_DQ10 | – | B | EBI0 LPDDR5 data bit 10 | | D30 | EBI0\_DQ11 | – | B | EBI0 LPDDR5 data bit 11 | | C25 | EBI0\_DQ12 | – | B | EBI0 LPDDR5 data bit 12 | | A23 | EBI0\_DQ13 | – | B | EBI0 LPDDR5 data bit 13 | | C23 | EBI0\_DQ14 | – | B | EBI0 LPDDR5 data bit 14 | | A31 | EBI0\_DQ15 | – | B | EBI0 LPDDR5 data bit 15 | | A7 | EBI0\_DQS0\_C | – | DI | EBI0 LPDDR5 differential read data strobe for byte 0 – minus | | A5 | EBI0\_DQS0\_T | – | DI | EBI0 LPDDR5 differential read data strobe for byte 0 – plus | | B28 | EBI0\_DQS1\_C | – | DI | EBI0 LPDDR5 differential read data strobe for byte 1 – minus | | B30 | EBI0\_DQS1\_T | – | DI | EBI0 LPDDR5 differential read data strobe for byte 1 – plus | | B10 | EBI0\_WCK0\_C | – | DO | EBI0 LPDDR5 differential write clock for byte 0 – minus | | B8 | EBI0\_WCK0\_T | – | DO | EBI0 LPDDR5 differential write clock for byte 0 – plus | | A25 | EBI0\_WCK1\_C | – | DO | EBI0 LPDDR5 differential write clock for byte 1 – minus | | A27 | EBI0\_WCK1\_T | – | DO | EBI0 LPDDR5 differential write clock for byte 1 – plus | | D14 | EBI1\_CA0 | – | DO | EBI1 LPDDR5 command/address bit 0 | | G13 | EBI1\_CA1 | – | DO | EBI1 LPDDR5 command/address bit 1 | | G15 | EBI1\_CA2 | – | DO | EBI1 LPDDR5 command/address bit 2 | | F20 | EBI1\_CA3 | – | DO | EBI1 LPDDR5 command/address bit 3 | | E19 | EBI1\_CA4 | – | DO | EBI1 LPDDR5 command/address bit 4 | | E21 | EBI1\_CA5 | – | DO | EBI1 LPDDR5 command/address bit 5 | | D20 | EBI1\_CA6 | – | DO | EBI1 LPDDR5 command/address bit 6 | | F18 | EBI1\_CK\_C | – | DO | EBI1 LPDDR5 differential clock – minus | | F16 | EBI1\_CK\_T | – | DO | EBI1 LPDDR5 differential clock – plus | | G19 | EBI1\_CS0 | – | DO | EBI1 LPDDR5 chip select 0 | | E15 | EBI1\_CS1 | – | DO | EBI1 LPDDR5 chip select 1 | | D10 | EBI1\_DMI0 | – | DO | EBI1 LPDDR5 data mask for byte 0 | | E25 | EBI1\_DMI1 | – | DO | EBI1 LPDDR5 data mask for byte 1 | | G1 | EBI1\_DQ0 | – | B | EBI1 LPDDR5 data bit 0 | | E1 | EBI1\_DQ1 | – | B | EBI1 LPDDR5 data bit 1 | | F2 | EBI1\_DQ2 | – | B | EBI1 LPDDR5 data bit 2 | | G5 | EBI1\_DQ3 | – | B | EBI1 LPDDR5 data bit 3 | | F12 | EBI1\_DQ4 | – | B | EBI1 LPDDR5 data bit 4 | | E13 | EBI1\_DQ5 | – | B | EBI1 LPDDR5 data bit 5 | | F10 | EBI1\_DQ6 | – | B | EBI1 LPDDR5 data bit 6 | | E9 | EBI1\_DQ7 | – | B | EBI1 LPDDR5 data bit 7 | | E33 | EBI1\_DQ8 | – | B | EBI1 LPDDR5 data bit 8 | | G33 | EBI1\_DQ9 | – | B | EBI1 LPDDR5 data bit 9 | | E31 | EBI1\_DQ10 | – | B | EBI1 LPDDR5 data bit 10 | | G31 | EBI1\_DQ11 | – | B | EBI1 LPDDR5 data bit 11 | | F24 | EBI1\_DQ12 | – | B | EBI1 LPDDR5 data bit 12 | | G21 | EBI1\_DQ13 | – | B | EBI1 LPDDR5 data bit 13 | | E23 | EBI1\_DQ14 | – | B | EBI1 LPDDR5 data bit 14 | | D26 | EBI1\_DQ15 | – | B | EBI1 LPDDR5 data bit 15 | | E7 | EBI1\_DQS0\_C | – | DI | EBI1 LPDDR5 differential read data strobe for byte 0 – minus | | E5 | EBI1\_DQS0\_T | – | DI | EBI1 LPDDR5 differential read data strobe for byte 0 – plus | | F28 | EBI1\_DQS1\_C | – | DI | EBI1 LPDDR5 differential read data strobe for byte 1 – minus | | F30 | EBI1\_DQS1\_T | – | DI | EBI1 LPDDR5 differential read data strobe for byte 1 – plus | | G9 | EBI1\_WCK0\_C | – | DO | EBI1 LPDDR5 differential write clock for byte 0 – minus | | G7 | EBI1\_WCK0\_T | – | DO | EBI1 LPDDR5 differential write clock for byte 0 – plus | | G25 | EBI1\_WCK1\_C | – | DO | EBI1 LPDDR5 differential write clock for byte 1 – minus | | G27 | EBI1\_WCK1\_T | – | DO | EBI1 LPDDR5 differential write clock for byte 1 – plus | | H48 | EBI23\_CAL | – | DO | EBI calibration resistor | | E55 | EBI2\_CA0 | – | DO | EBI2 LPDDR5 command/address bit 0 | | D56 | EBI2\_CA1 | – | DO | EBI2 LPDDR5 command/address bit 1 | | G57 | EBI2\_CA2 | – | DO | EBI2 LPDDR5 command/address bit 2 | | E61 | EBI2\_CA3 | – | DO | EBI2 LPDDR5 command/address bit 3 | | D60 | EBI2\_CA4 | – | DO | EBI2 LPDDR5 command/address bit 4 | | G63 | EBI2\_CA5 | – | DO | EBI2 LPDDR5 command/address bit 5 | | G61 | EBI2\_CA6 | – | DO | EBI2 LPDDR5 command/address bit 6 | | F60 | EBI2\_CK\_C | – | DO | EBI2 LPDDR5 differential clock – minus | | F58 | EBI2\_CK\_T | – | DO | EBI2 LPDDR5 differential clock – plus | | E57 | EBI2\_CS0 | – | DO | EBI2 LPDDR5 chip select 0 | | F56 | EBI2\_CS1 | – | DO | EBI2 LPDDR5 chip select 1 | | E51 | EBI2\_DMI0 | – | DO | EBI2 LPDDR5 data mask for byte 0 | | D66 | EBI2\_DMI1 | – | DO | EBI2 LPDDR5 data mask for byte 1 | | E43 | EBI2\_DQ0 | – | B | EBI2 LPDDR5 data bit 0 | | G43 | EBI2\_DQ1 | – | B | EBI2 LPDDR5 data bit 1 | | E45 | EBI2\_DQ2 | – | B | EBI2 LPDDR5 data bit 2 | | G45 | EBI2\_DQ3 | – | B | EBI2 LPDDR5 data bit 3 | | F52 | EBI2\_DQ4 | – | B | EBI2 LPDDR5 data bit 4 | | G55 | EBI2\_DQ5 | – | B | EBI2 LPDDR5 data bit 5 | | E53 | EBI2\_DQ6 | – | B | EBI2 LPDDR5 data bit 6 | | D50 | EBI2\_DQ7 | – | B | EBI2 LPDDR5 data bit 7 | | G73 | EBI2\_DQ8 | – | B | EBI2 LPDDR5 data bit 8 | | F72 | EBI2\_DQ9 | – | B | EBI2 LPDDR5 data bit 9 | | D74 | EBI2\_DQ10 | – | B | EBI2 LPDDR5 data bit 10 | | E73 | EBI2\_DQ11 | – | B | EBI2 LPDDR5 data bit 11 | | F64 | EBI2\_DQ12 | – | B | EBI2 LPDDR5 data bit 12 | | E63 | EBI2\_DQ13 | – | B | EBI2 LPDDR5 data bit 13 | | F66 | EBI2\_DQ14 | – | B | EBI2 LPDDR5 data bit 14 | | E67 | EBI2\_DQ15 | – | B | EBI2 LPDDR5 data bit 15 | | F48 | EBI2\_DQS0\_C | – | DI | EBI2 LPDDR5 differential read data strobe for byte 0 – minus | | F46 | EBI2\_DQS0\_T | – | DI | EBI2 LPDDR5 differential read data strobe for byte 0 – plus | | E69 | EBI2\_DQS1\_C | – | DI | EBI2 LPDDR5 differential read data strobe for byte 1 – minus | | E71 | EBI2\_DQS1\_T | – | DI | EBI2 LPDDR5 differential read data strobe for byte 1 – plus | | G51 | EBI2\_WCK0\_C | – | DO | EBI2 LPDDR5 differential write clock for byte 0 – minus | | G49 | EBI2\_WCK0\_T | – | DO | EBI2 LPDDR5 differential write clock for byte 0 – plus | | G67 | EBI2\_WCK1\_C | – | DO | EBI2 LPDDR5 differential write clock for byte 1 – minus | | G69 | EBI2\_WCK1\_T | – | DO | EBI2 LPDDR5 differential write clock for byte 1 – plus | | C61 | EBI3\_CA0 | – | DO | EBI3 LPDDR5 command/address bit 0 | | A61 | EBI3\_CA1 | – | DO | EBI3 LPDDR5 command/address bit 1 | | D58 | EBI3\_CA2 | – | DO | EBI3 LPDDR5 command/address bit 2 | | C57 | EBI3\_CA3 | – | DO | EBI3 LPDDR5 command/address bit 3 | | B56 | EBI3\_CA4 | – | DO | EBI3 LPDDR5 command/address bit 4 | | A55 | EBI3\_CA5 | – | DO | EBI3 LPDDR5 command/address bit 5 | | C55 | EBI3\_CA6 | – | DO | EBI3 LPDDR5 command/address bit 6 | | A59 | EBI3\_CK\_C | – | DO | EBI3 LPDDR5 differential clock – minus | | A57 | EBI3\_CK\_T | – | DO | EBI3 LPDDR5 differential clock – plus | | C59 | EBI3\_CS0 | – | DO | EBI3 LPDDR5 chip select 0 | | B60 | EBI3\_CS1 | – | DO | EBI3 LPDDR5 chip select 1 | | D48 | EBI3\_DMI0 | – | DO | EBI3 LPDDR5 data mask for byte 0 | | C69 | EBI3\_DMI1 | – | DO | EBI3 LPDDR5 data mask for byte 1 | | C43 | EBI3\_DQ0 | – | B | EBI3 LPDDR5 data bit 0 | | C45 | EBI3\_DQ1 | – | B | EBI3 LPDDR5 data bit 1 | | A43 | EBI3\_DQ2 | – | B | EBI3 LPDDR5 data bit 2 | | D46 | EBI3\_DQ3 | – | B | EBI3 LPDDR5 data bit 3 | | C51 | EBI3\_DQ4 | – | B | EBI3 LPDDR5 data bit 4 | | C53 | EBI3\_DQ5 | – | B | EBI3 LPDDR5 data bit 5 | | A53 | EBI3\_DQ6 | – | B | EBI3 LPDDR5 data bit 6 | | A45 | EBI3\_DQ7 | – | B | EBI3 LPDDR5 data bit 7 | | B74 | EBI3\_DQ8 | – | B | EBI3 LPDDR5 data bit 8 | | C73 | EBI3\_DQ9 | – | B | EBI3 LPDDR5 data bit 9 | | A73 | EBI3\_DQ10 | – | B | EBI3 LPDDR5 data bit 10 | | C71 | EBI3\_DQ11 | – | B | EBI3 LPDDR5 data bit 11 | | C65 | EBI3\_DQ12 | – | B | EBI3 LPDDR5 data bit 12 | | A63 | EBI3\_DQ13 | – | B | EBI3 LPDDR5 data bit 13 | | C63 | EBI3\_DQ14 | – | B | EBI3 LPDDR5 data bit 14 | | A65 | EBI3\_DQ15 | – | B | EBI3 LPDDR5 data bit 15 | | B48 | EBI3\_DQS0\_C | – | DI | EBI3 LPDDR5 differential read data strobe for byte 0 – minus | | B46 | EBI3\_DQS0\_T | – | DI | EBI3 LPDDR5 differential read data strobe for byte 0 – plus | | A69 | EBI3\_DQS1\_C | – | DI | EBI3 LPDDR5 differential read data strobe for byte 1 – minus | | A71 | EBI3\_DQS1\_T | – | DI | EBI3 LPDDR5 differential read data strobe for byte 1 – plus | | A51 | EBI3\_WCK0\_C | – | DO | EBI3 LPDDR5 differential write clock for byte 0 – minus | | A49 | EBI3\_WCK0\_T | – | DO | EBI3 LPDDR5 differential write for byte 0 – plus | | B66 | EBI3\_WCK1\_C | – | DO | EBI3 LPDDR5 differential write clock for byte 1 – minus | | B68 | EBI3\_WCK1\_T | – | DO | EBI3 LPDDR5 differential write clock for byte 1 – plus | | L69 | EBI45\_CAL | – | DO | EBI calibration resistor | | T70 | EBI4\_CA0 | – | DO | EBI4 LPDDR5 command/address bit 0 | | T74 | EBI4\_CA1 | – | DO | EBI4 LPDDR5 command/address bit 1 | | V76 | EBI4\_CA2 | – | DO | EBI4 LPDDR5 command/address bit 2 | | Y76 | EBI4\_CA3 | – | DO | EBI4 LPDDR5 command/address bit 3 | | W71 | EBI4\_CA4 | – | DO | EBI4 LPDDR5 command/address bit 4 | | AA71 | EBI4\_CA5 | – | DO | EBI4 LPDDR5 command/address bit 5 | | Y74 | EBI4\_CA6 | – | DO | EBI4 LPDDR5 command/address bit 6 | | W73 | EBI4\_CK\_C | – | DO | EBI4 LPDDR5 differential clock – minus | | V74 | EBI4\_CK\_T | – | DO | EBI4 LPDDR5 differential clock – plus | | U73 | EBI4\_CS0 | – | DO | EBI4 LPDDR5 chip select 0 | | U71 | EBI4\_CS1 | – | DO | EBI4 LPDDR5 chip select 1 | | N75 | EBI4\_DMI0 | – | DO | EBI4 LPDDR5 data mask for byte 0 | | AC77 | EBI4\_DMI1 | – | DO | EBI4 LPDDR5 data mask for byte 1 | | H72 | EBI4\_DQ0 | – | B | EBI4 LPDDR5 data bit 0 | | J71 | EBI4\_DQ1 | – | B | EBI4 LPDDR5 data bit 1 | | J75 | EBI4\_DQ2 | – | B | EBI4 LPDDR5 data bit 2 | | K72 | EBI4\_DQ3 | – | B | EBI4 LPDDR5 data bit 3 | | P72 | EBI4\_DQ4 | – | B | EBI4 LPDDR5 data bit 4 | | R71 | EBI4\_DQ5 | – | B | EBI4 LPDDR5 data bit 5 | | P74 | EBI4\_DQ6 | – | B | EBI4 LPDDR5 data bit 6 | | N71 | EBI4\_DQ7 | – | B | EBI4 LPDDR5 data bit 7 | | AG71 | EBI4\_DQ8 | – | B | EBI4 LPDDR5 data bit 8 | | AG75 | EBI4\_DQ9 | – | B | EBI4 LPDDR5 data bit 9 | | AG77 | EBI4\_DQ10 | – | B | EBI4 LPDDR5 data bit 10 | | AF70 | EBI4\_DQ11 | – | B | EBI4 LPDDR5 data bit 11 | | AB74 | EBI4\_DQ12 | – | B | EBI4 LPDDR5 data bit 12 | | AA73 | EBI4\_DQ13 | – | B | EBI4 LPDDR5 data bit 13 | | AC73 | EBI4\_DQ14 | – | B | EBI4 LPDDR5 data bit 14 | | AD72 | EBI4\_DQ15 | – | B | EBI4 LPDDR5 data bit 15 | | L75 | EBI4\_DQS0\_C | – | DI | EBI4 LPDDR5 differential read data strobe for byte 0 – minus | | K74 | EBI4\_DQS0\_T | – | DI | EBI4 LPDDR5 differential read data strobe for byte 0 – plus | | AE73 | EBI4\_DQS1\_C | – | DI | EBI4 LPDDR5 differential read data strobe for byte 1 – minus | | AF74 | EBI4\_DQS1\_T | – | DI | EBI4 LPDDR5 differential read data strobe for byte 1 – plus | | M72 | EBI4\_WCK0\_C | – | DO | EBI4 LPDDR5 differential write clock for byte 0 – minus | | L71 | EBI4\_WCK0\_T | – | DO | EBI4 LPDDR5 differential write clock for byte 0 – plus | | AD76 | EBI4\_WCK1\_C | – | DO | EBI4 LPDDR5 differential write clock for byte 1 – minus | | AE77 | EBI4\_WCK1\_T | – | DO | EBI4 LPDDR5 differential write clock for byte 1 – plus | | U77 | EBI5\_CA0 | – | DO | EBI5 LPDDR5 command/address bit 0 | | T80 | EBI5\_CA1 | – | DO | EBI5 LPDDR5 command/address bit 1 | | R77 | EBI5\_CA2 | – | DO | EBI5 LPDDR5 command/address bit 2 | | N77 | EBI5\_CA3 | – | DO | EBI5 LPDDR5 command/address bit 3 | | M80 | EBI5\_CA4 | – | DO | EBI5 LPDDR5 command/address bit 4 | | M78 | EBI5\_CA5 | – | DO | EBI5 LPDDR5 command/address bit 5 | | L77 | EBI5\_CA6 | – | DO | EBI5 LPDDR5 command/address bit 6 | | P80 | EBI5\_CK\_C | – | DO | EBI5 LPDDR5 differential clock – minus | | N81 | EBI5\_CK\_T | – | DO | EBI5 LPDDR5 differential clock – plus | | R81 | EBI5\_CS0 | – | DO | EBI5 LPDDR5 chip select 0 | | T78 | EBI5\_CS1 | – | DO | EBI5 LPDDR5 chip select 1 | | H78 | EBI5\_DMI0 | – | DO | EBI5 LPDDR5 data mask for byte 0 | | AA77 | EBI5\_DMI1 | – | DO | EBI5 LPDDR5 data mask for byte 1 | | E77 | EBI5\_DQ0 | – | B | EBI5 LPDDR5 data bit 0 | | F76 | EBI5\_DQ1 | – | B | EBI5 LPDDR5 data bit 1 | | D80 | EBI5\_DQ2 | – | B | EBI5 LPDDR5 data bit 2 | | G77 | EBI5\_DQ3 | – | B | EBI5 LPDDR5 data bit 3 | | J77 | EBI5\_DQ4 | – | B | EBI5 LPDDR5 data bit 4 | | K78 | EBI5\_DQ5 | – | B | EBI5 LPDDR5 data bit 5 | | K80 | EBI5\_DQ6 | – | B | EBI5 LPDDR5 data bit 6 | | E81 | EBI5\_DQ7 | – | B | EBI5 LPDDR5 data bit 7 | | AG81 | EBI5\_DQ8 | – | B | EBI5 LPDDR5 data bit 8 | | AE81 | EBI5\_DQ9 | – | B | EBI5 LPDDR5 data bit 9 | | AF80 | EBI5\_DQ10 | – | B | EBI5 LPDDR5 data bit 10 | | AD80 | EBI5\_DQ11 | – | B | EBI5 LPDDR5 data bit 11 | | W77 | EBI5\_DQ12 | – | B | EBI5 LPDDR5 data bit 12 | | U81 | EBI5\_DQ13 | – | B | EBI5 LPDDR5 data bit 13 | | V80 | EBI5\_DQ14 | – | B | EBI5 LPDDR5 data bit 14 | | W79 | EBI5\_DQ15 | – | B | EBI5 LPDDR5 data bit 15 | | G81 | EBI5\_DQS0\_C | – | DI | EBI5 LPDDR5 differential read data strobe for byte 0 – minus | | AB80 | EBI5\_DQS1\_C | – | DI | EBI5 LPDDR5 differential read data strobe for byte 1 – minus | | F80 | EBI5\_DQS0\_T | – | DI | EBI5 LPDDR5 differential read data strobe for byte 0 – plus | | AC81 | EBI5\_DQS1\_T | – | DI | EBI5 LPDDR5 differential read data strobe for byte 1 – plus | | J81 | EBI5\_WCK0\_C | – | DO | EBI5 LPDDR5 differential write clock for byte 0 – minus | | Y80 | EBI5\_WCK1\_C | – | DO | EBI5 LPDDR5 differential write clock for byte 1 – minus | | H80 | EBI5\_WCK0\_T | – | DO | EBI5 LPDDR5 differential write clock for byte 0 – plus | | AA81 | EBI5\_WCK1\_T | – | DO | EBI5 LPDDR5 differential write clock for byte 1 – plus | | BE75 | EDP0\_AUX\_M | – | AI, AO | eDP/DP 0 auxiliary channel – minus | | BD76 | EDP0\_AUX\_P | – | AI, AO | eDP/DP 0 auxiliary channel – plus | | BA73 | EDP0\_TX0\_M | – | AO | eDP/DP 0 transmit channel 0 – minus | | AY74 | EDP0\_TX0\_P | – | AO | eDP/DP 0 transmit channel 0 – plus | | BB76 | EDP0\_TX1\_M | – | AO | eDP/DP 0 transmit channel 1 – minus | | BA75 | EDP0\_TX1\_P | – | AO | eDP/DP 0 transmit channel 1 – plus | | BC75 | EDP0\_TX2\_M | – | AO | eDP/DP 0 transmit channel 2 – minus | | BB74 | EDP0\_TX2\_P | – | AO | eDP/DP 0 transmit channel 2 – plus | | BD74 | EDP0\_TX3\_M | – | AO | eDP/DP 0 transmit channel 3 – minus | | BC73 | EDP0\_TX3\_P | – | AO | eDP/DP 0 transmit channel 3 – plus | | BF66 | EDP1\_AUX\_M | – | AI, AO | eDP/DP 1 auxiliary channel – minus | | BF68 | EDP1\_AUX\_P | – | AI, AO | eDP/DP 1 auxiliary channel – plus | | BE71 | EDP1\_TX0\_M | – | AO | eDP/DP 1 transmit channel 0 – minus | | BE73 | EDP1\_TX0\_P | – | AO | eDP/DP 1 transmit channel 0 – plus | | BG71 | EDP1\_TX1\_M | – | AO | eDP/DP 1 transmit channel 1 – minus | | BG73 | EDP1\_TX1\_P | – | AO | eDP/DP 1 transmit channel 1 – plus | | BF70 | EDP1\_TX2\_M | – | AO | eDP/DP 1 transmit channel 2 – minus | | BF72 | EDP1\_TX2\_P | – | AO | eDP/DP 1 transmit channel 2 – plus | | BG67 | EDP1\_TX3\_M | – | AO | eDP/DP 1 transmit channel 3 – minus | | BG69 | EDP1\_TX3\_P | – | AO | eDP/DP 1 transmit channel 3 – plus | | BC65 | EDP2\_AUX\_M | – | AI, AO | eDP/DP 2 auxiliary channel – minus | | BC67 | EDP2\_AUX\_P | – | AI, AO | eDP/DP 2 auxiliary channel – plus | | BB70 | EDP2\_TX0\_M | – | AO | eDP/DP 2 transmit channel 0 – minus | | BB72 | EDP2\_TX0\_P | – | AO | eDP/DP 2 transmit channel 0 – plus | | BD70 | EDP2\_TX1\_M | – | AO | eDP/DP 2 transmit channel 1 – minus | | BD72 | EDP2\_TX1\_P | – | AO | eDP/DP 2 transmit channel 1 – plus | | BC69 | EDP2\_TX2\_M | – | AO | eDP/DP 2 transmit channel 2 – minus | | BC71 | EDP2\_TX2\_P | – | AO | eDP/DP 2 transmit channel 2 – plus | | BD66 | EDP2\_TX3\_M | – | AO | eDP/DP 2 transmit channel 3 – minus | | BD68 | EDP2\_TX3\_P | – | AO | eDP/DP 2 transmit channel 3 – plus | | BA57 | EDP3\_AUX\_M | – | AI, AO | eDP/DP 3 auxiliary channel – minus | | BA59 | EDP3\_AUX\_P | – | AI, AO | eDP/DP 3 auxiliary channel – plus | | AY62 | EDP3\_TX0\_M | – | AO | eDP/DP 3 transmit channel 0 – minus | | AY64 | EDP3\_TX0\_P | – | AO | eDP/DP 3 transmit channel 0 – plus | | BB62 | EDP3\_TX1\_M | – | AO | eDP/DP 3 transmit channel 1 – minus | | BB64 | EDP3\_TX1\_P | – | AO | eDP/DP 3 transmit channel 1 – plus | | BA61 | EDP3\_TX2\_M | – | AO | eDP/DP 3 transmit channel 2 – minus | | BA63 | EDP3\_TX2\_P | – | AO | eDP/DP 3 transmit channel 2 – plus | | BB58 | EDP3\_TX3\_M | – | AO | eDP/DP 3 transmit channel 3 – minus | | BB60 | EDP3\_TX3\_P | – | AO | eDP/DP 3 transmit channel 3 – plus | | BA9 | MD\_PS\_HOLD | RTSS\_PX\_3\_BPP | DI | Main domain PS\_HOLD. This is an input signal and must be externally connected to
the SoC PS\_HOLD. | | T10 | PCIE0\_REFCLK\_M | – | AI, AO | PCIe 0 Gen 4 reference clock – minus | | U9 | PCIE0\_REFCLK\_P | – | AI, AO | PCIe 0 Gen 4 reference clock – plus | | W9 | PCIE0\_RX0\_M | – | AI | PCIe 0 Gen 4 receive – minus | | Y10 | PCIE0\_RX0\_P | – | AI | PCIe 0 Gen 4 receive – plus | | V8 | PCIE0\_RX1\_M | – | AI | PCIe 0 Gen 4 receive – minus | | W7 | PCIE0\_RX1\_P | – | AI | PCIe 0 Gen 4 receive – plus | | R9 | PCIE0\_TX0\_M | – | AO | PCIe 0 Gen 4 transmit – minus | | T8 | PCIE0\_TX0\_P | – | AO | PCIe 0 Gen 4 transmit – plus | | P8 | PCIE0\_TX1\_M | – | AO | PCIe 0 Gen 4 transmit – minus | | R7 | PCIE0\_TX1\_P | – | AO | PCIe 0 Gen 4 transmit – plus | | AE7 | PCIE1\_REFCLK\_M | – | AI, AO | PCIe 1 Gen 4 reference clock – minus | | AF6 | PCIE1\_REFCLK\_P | – | AI, AO | PCIe 1 Gen 4 reference clock – plus | | AK10 | PCIE1\_RX0\_M | – | AI | PCIe 1 Gen 4 receive – minus | | AL9 | PCIE1\_RX0\_P | – | AI | PCIe 1 Gen 4 receive – plus | | AJ7 | PCIE1\_RX1\_M | – | AI | PCIe 1 Gen 4 receive – minus | | AK6 | PCIE1\_RX1\_P | – | AI | PCIe 1 Gen 4 receive – plus | | AH10 | PCIE1\_RX2\_M | – | AI | PCIe 1 Gen 4 receive – minus | | AJ9 | PCIE1\_RX2\_P | – | AI | PCIe 1 Gen 4 receive – plus | | AG9 | PCIE1\_RX3\_M | – | AI | PCIe 1 Gen 4 receive – minus | | AH8 | PCIE1\_RX3\_P | – | AI | PCIe 1 Gen 4 receive – plus | | AD10 | PCIE1\_TX0\_M | – | AO | PCIe 1 Gen 4 transmit – minus | | AE9 | PCIE1\_TX0\_P | – | AO | PCIe 1 Gen 4 transmit – plus | | AC7 | PCIE1\_TX1\_M | – | AO | PCIe 1 Gen 4 transmit – minus | | AD6 | PCIE1\_TX1\_P | – | AO | PCIe 1 Gen 4 transmit – plus | | AB10 | PCIE1\_TX2\_M | – | AO | PCIe 1 Gen 4 transmit – minus | | AC9 | PCIE1\_TX2\_P | – | AO | PCIe 1 Gen 4 transmit – plus | | AA7 | PCIE1\_TX3\_M | – | AO | PCIe 1 Gen 4 transmit – minus | | AB6 | PCIE1\_TX3\_P | – | AO | PCIe 1 Gen 4 transmit – plus | | BC39 | PS\_HOLD | PX\_3\_BPP | DO | Power supply HOLD signal driven by the SoC to the PMIC. Active HIGH. Has an
internal pull-down by default.

During boot, PS\_HOLD is set HIGH (1) to indicate a successful boot and request
the PMIC to keep the power supplies enabled.

During shutdown, watchdog expiry, thermal trip, or certain error paths, software
or hardware clears PS\_HOLD to LOW (0) to instruct the PMIC to shut down or reset
the system. | | AA11 | REFGEN\_REXT0 | – | AI | High-speed interface – external resistor 0 | | H36 | REFGEN\_REXT1 | – | AI | High-speed interface – external resistor 1 | | AJ71 | REFGEN\_REXT2 | – | AI | High-speed interface – external resistor 2 | | AY28 | REFGEN\_REXT3 | – | AI | High-speed interface – external resistor 3 | | AH72 | RESIN\_N | PX\_0 | DI | Main domain hardware reset input to the SoC, sourced from the PMIC.

It is an active-low reset pin.

RESIN_N = 0 (LOW): SoC is held in reset.

RESIN_N = 1 (HIGH): SoC reset is released and boot can proceed. Basic power
rails are turned ON.

If the SoC does not respond by driving PS\_HOLD HIGH within a certain time after
RESIN\_N goes HIGH, the PMIC will trigger a reset.

This pin connects to the PON\_RESET\_N pin on the PMIC side. | | BD40 | RESOUT\_N | PX\_3 | DO | Main domain active‑low reset output that follows RESIN\_N with a short delay. It
can be used to reset external circuitry. It is asserted or de‑asserted a few clock
cycles after a change on RESIN\_N or after a watchdog expiry status change. | | AY12 | RTSS\_CXO | RTSS\_PX\_11 | DI | Core crystal oscillator for RTSS domain (digital 19.2 Hz system clock) | | M4 | RTSS\_JTAG\_SRST\_N | RTSS\_PX\_3 | DI-PU | RTSS domain JTAG reset for debug | | M2 | RTSS\_JTAG\_TCK | RTSS\_PX\_3 | DI-PU | RTSS domain JTAG clock input | | N3 | RTSS\_JTAG\_TDI | RTSS\_PX\_3 | DI-PU:nppdkp | RTSS domain JTAG data input | | N1 | RTSS\_JTAG\_TDO | RTSS\_PX\_3 | DO-Z | RTSS domain JTAG data output | | N5 | RTSS\_JTAG\_TMS | RTSS\_PX\_3 | DI-PU:nppdkp | RTSS domain JTAG mode select input | | L5 | RTSS\_JTAG\_TRST\_N | RTSS\_PX\_3 | DI-B-PD:nppukp | RTSS domain JTAG reset | | AW11 | RTSS\_MODE\_0 | RTSS\_PX\_3 | DI-S PD | Mode control bits [1:0]
00 for mission mode

11 for boundary scan mode | | BA11 | RTSS\_MODE\_1 | RTSS\_PX\_3 | DI-S PD | Mode control bits [1:0]
00 for mission mode

11 for boundary scan mode | | AV12 | RTSS\_PS\_HOLD | RTSS\_PX\_3 | DO | When the RTSS domain is up, this signal will be HIGH. For debugging purposes, a
test point can be added to this signal.

RTSS temperature fatal events, power sequence watchdog expiration, MD PMIC fault
indications, or software faults can cause this signal to go LOW. | | BA13 | RTSS\_RESIN\_N | RTSS\_PX\_0 | DI | RTSS domain hardware reset input to the SoC, sourced from the PMIC.

This pin must be connected to the main domain RESIN\_N. | | BC9 | RTSS\_RESOUT\_N | RTSS\_PX\_3 | DO | RTSS domain reset output. RTSS domain active‑low reset output that follows
RTSS\_RESIN\_N with a short delay. It can be used to reset external circuitry. It is
asserted or de‑asserted a few clock cycles after a change on RTSS\_RESIN\_N or after a
watchdog expiry in the RTSS domain. | | AL3 | SGMII0\_RX\_M | – | AI | SGMII interface 0 serial data Rx – minus | | AM4 | SGMII0\_RX\_P | – | AI | SGMII interface 0 serial data Rx – plus | | AM2 | SGMII0\_TX\_M | – | AO | SGMII interface 0 serial data Tx – minus | | AN3 | SGMII0\_TX\_P | – | AO | SGMII interface 0 serial data Tx – plus | | AP2 | SGMII1\_RX\_M | – | AI | SGMII interface 1 serial data Rx – minus | | AR3 | SGMII1\_RX\_P | – | AI | SGMII interface 1 serial data Rx – plus | | AR1 | SGMII1\_TX\_M | – | AO | SGMII interface 1 serial data Tx – minus | | AT2 | SGMII1\_TX\_P | – | AO | SGMII interface 1 serial data Tx – plus | | BB36 | SLEEP\_CLK | PX\_3 | DI | Sleep clock | | AJ73 | SPMI\_CLK | PX\_0\_BPP | B | Slave and PBUS interface for PMICs – clock | | AH74 | SPMI\_DATA | PX\_0\_BPP | B | Slave and PBUS interface for PMICs – data | | BE79 | UFS0\_REFCLK | PX\_9 | DO | UFS 0 reference clock | | BD78 | UFS0\_RESET\_N | PX\_9 | DO | UFS 0 reset | | BF78 | UFS0\_RX0\_M | – | AI | UFS 0 receive 0 – minus | | BE77 | UFS0\_RX0\_P | – | AI | UFS 0 receive 0 – plus | | BG77 | UFS0\_RX1\_M | – | AI | UFS 0 receive 1 – minus | | BF76 | UFS0\_RX1\_P | – | AI | UFS 0 receive 1 – plus | | BC81 | UFS0\_TX0\_M | – | AO | UFS 0 transmit 0 – minus | | BD80 | UFS0\_TX0\_P | – | AO | UFS 0 transmit 0 – plus | | BB78 | UFS0\_TX1\_M | – | AO | UFS 0 transmit 1 – minus | | BC79 | UFS0\_TX1\_P | – | AO | UFS 0 transmit 1 – plus | | AW79 | UFS1\_REFCLK | PX\_10 | DO | UFS 1 reference clock | | AW81 | UFS1\_RESET\_N | PX\_10 | DO | UFS 1 reset | | BA81 | UFS1\_RX0\_M | – | AI | UFS 1 receive 0 – minus | | AY80 | UFS1\_RX0\_P | – | AI | UFS 1 receive 0 – plus | | BB80 | UFS1\_RX1\_M | – | AI | UFS 1 receive 1 – minus | | BA79 | UFS1\_RX1\_P | – | AI | UFS 1 receive 1 – plus | | AU79 | UFS1\_TX0\_M | – | AO | UFS 1 transmit 0 – minus | | AV80 | UFS1\_TX0\_P | – | AO | UFS 1 transmit 0 – plus | | AT80 | UFS1\_TX1\_M | – | AO | UFS 1 transmit 1 – minus | | AU81 | UFS1\_TX1\_P | – | AO | UFS 1 transmit 1 – plus | | C37 | USB0\_HS\_DM | – | AI, AO | USB 0 high-speed data – minus | | C35 | USB0\_HS\_DP | – | AI, AO | USB 0 high-speed data – plus | | A35 | USB0\_SS\_RX\_M | – | AI | USB 0 super-speed receive – minus | | A37 | USB0\_SS\_RX\_P | – | AI | USB 0 super-speed receive – plus | | E35 | USB0\_SS\_TX\_M | – | AO | USB 0 super-speed transmit – minus | | E37 | USB0\_SS\_TX\_P | – | AO | USB 0 super-speed transmit – plus | | C41 | USB1\_HS\_DM | – | AI, AO | USB 1 high-speed data – minus | | C39 | USB1\_HS\_DP | – | AI, AO | USB 1 high-speed data – plus | | A39 | USB1\_SS\_RX\_M | – | AI | USB 1 super-speed receive – minus | | A41 | USB1\_SS\_RX\_P | – | AI | USB 1 super-speed receive – plus | | E39 | USB1\_SS\_TX\_M | – | AO | USB 1 super-speed transmit – minus | | E41 | USB1\_SS\_TX\_P | – | AO | USB 1 super-speed transmit – plus | | G41 | USB2\_HS\_DM | – | AI, AO | USB 2 high-speed data – minus | | G39 | USB2\_HS\_DP | – | AI, AO | USB 2 high-speed data – plus | | AM6 | SDC1\_CLK | PX\_7 | DO-NP:pdpukp | Secure digital controller 1 clock for eMMC | | AL7 | SDC1\_CMD | PX\_7 | B-NP:pdpukp | Secure digital controller 1 command for eMMC | | AM10 | SDC1\_DATA0 | PX\_7 | B-NP:pdpukp | Secure digital controller 1 DATA bit 0 for eMMC | | AN7 | SDC1\_DATA1 | PX\_7 | B-NP:pdpukp | Secure digital controller 1 DATA bit 1 for eMMC | | AN9 | SDC1\_DATA2 | PX\_7 | B-NP:pdpukp | Secure digital controller 1 DATA bit 2 for eMMC | | AP8 | SDC1\_DATA3 | PX\_7 | B-NP:pdpukp | Secure digital controller 1 DATA bit 3 for eMMC | | AP10 | SDC1\_DATA4 | PX\_7 | B-NP:pdpukp | Secure digital controller 1 DATA bit 4 for eMMC | | AR7 | SDC1\_DATA5 | PX\_7 | B-NP:pdpukp | Secure digital controller 1 DATA bit 5 for eMMC | | AR9 | SDC1\_DATA6 | PX\_7 | B-NP:pdpukp | Secure digital controller 1 DATA bit 6 for eMMC | | AT8 | SDC1\_DATA7 | PX\_7 | B-NP:pdpukp | Secure digital controller 1 DATA bit 7 for eMMC | | AM8 | SDC1\_RCLK | PX\_7 | DI-PD:pdpukp | Secure digital controller 1 return clock for eMMC | | | | | | | ### GPIO pins | GPIO pins can support multiple functions. To assign GPIOs to particular functions (such as the options listed in the preceding table), designers must identify all their application’s requirements and map each GPIO to its function–carefully avoiding conflicts in GPIO assignments. See [GPIO pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_uxn_dql_5sb) for a list of all supported functions for each GPIO.

**Note** Board designers must examine each GPIO’s external connection and programmed configuration, and take steps necessary to avoid excessive leakage current. Combinations of the following factors must be controlled properly:

GPIO configuration
- Input vs. output
- Pull-up or pull-down

External connections
- Unused inputs
- Connections to high-impedance (tri-state) outputs
- Connections to external devices that may not be attached

To help designers define their products’ GPIO assignments, QTI provides an Excel spreadsheet that lists all QCS9075 GPIOs (in numeric order), pad numbers, pad voltages, pull states, and available configurations.

**Note** See the [QCS9075 + PMM8650AU Pin Assignment and GPIO
Configuration Spreadsheet (80-73417-1A)](https://docs.qualcomm.com/bundle/80-73417-1A/resource/80-73417-1A.xlsm) from the Qualcomm
website.

After successfully logging on, the document is downloaded. | | --- | | Pin no. | Pin name and/or function | Alternate function | Pad characteristics | Pad characteristics | Functional description | Wakeup function | | --- | --- | --- | --- | --- | --- | --- | | Pin no. | Pin name and/or function | Alternate function | Voltage | Type | Functional description | Wakeup function | | BF4 | GPIO\_0 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BE5 | GPIO\_1 | | PX\_3 | PU:nppdkp | Configurable I/O | Y | | BE5 | GPIO\_1 | PCIE0\_CLKREQ\_N | PX\_3 | PU:nppdkp | PCIe0 clock request | Y | | BF6 | GPIO\_2 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BE7 | GPIO\_3 | | PX\_3 | PU:nppdkp | Configurable I/O | Y | | BE7 | GPIO\_3 | PCIE1\_CLKREQ\_N | PX\_3 | PU:nppdkp | PCIe1 clock request | Y | | BG7 | GPIO\_4 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BF8 | GPIO\_5 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BD8 | GPIO\_6 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BD8 | GPIO\_6 | EMAC0\_PTP\_AUX\_TS\_I\_0 | PX\_3 | PD:nppukp | EMAC0 trigger 0 A for Auxiliary snapshot | Y | | BD8 | GPIO\_6 | EMAC0\_PTP\_PPS\_O\_0 | PX\_3 | PD:nppukp | EMAC0 configurable PPS output 0 | Y | | BD8 | GPIO\_6 | EMAC1\_PTP\_AUX\_TS\_I\_0 | PX\_3 | PD:nppukp | EMAC1 trigger 0 A for Auxiliary snapshot | Y | | BD8 | GPIO\_6 | EMAC1\_PTP\_PPS\_O\_0 | PX\_3 | PD:nppukp | EMAC1 configurable PPS output 0 | Y | | BE9 | GPIO\_7 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BE9 | GPIO\_7 | SGMII\_PHY\_INTR0\_N | PX\_3 | PD:nppukp | SGMII0 PHY interrupt | Y | | BG9 | GPIO\_8 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BG9 | GPIO\_8 | EMAC0\_MDC | PX\_3 | PD:nppukp | EMAC0 management interface clock | N | | BF10 | GPIO\_9 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BF10 | GPIO\_9 | EMAC0\_MDIO | PX\_3 | PD:nppukp | EMAC0 management interface I/O | N | | BF10 | GPIO\_9 | GP\_PDM\_MIRA[2] | PX\_3 | PD:nppukp | General-purpose PDM output 2 A | N | | BD2 | GPIO\_10 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BD2 | GPIO\_10 | USB2PHY\_AC\_EN0 | PX\_3 | PD:nppukp | USB AC coupling control for USB0 port | Y | | BD2 | GPIO\_10 | EMAC0\_PTP\_AUX\_TS\_I\_1 | PX\_3 | PD:nppukp | EMAC0 trigger 1 A for Auxiliary snapshot | Y | | BD2 | GPIO\_10 | EMAC0\_PTP\_PPS\_O\_1 | PX\_3 | PD:nppukp | EMAC0 configurable PPS output 1 | Y | | BD2 | GPIO\_10 | EMAC1\_PTP\_AUX\_TS\_I\_1 | PX\_3 | PD:nppukp | EMAC1 trigger 1 A for Auxiliary snapshot | Y | | BD2 | GPIO\_10 | EMAC1\_PTP\_PPS\_O\_1 | PX\_3 | PD:nppukp | EMAC1 configurable PPS output 1 | Y | | BD2 | GPIO\_10 | GP\_PDM\_MIRB[2] | PX\_3 | PD:nppukp | General-purpose PDM output 2 B | Y | | BD2 | GPIO\_10 | BOOT\_CONFIG[12] | PX\_3 | PD:nppukp | Boot configuration bit 12 | Y | | BD4 | GPIO\_11 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BD4 | GPIO\_11 | USB2PHY\_AC\_EN1 | PX\_3 | PD:nppukp | USB AC coupling control for USB 1 port | | | BD4 | GPIO\_11 | EMAC0\_PTP\_AUX\_TS\_I\_2 | PX\_3 | PD:nppukp | EMAC0 trigger 2 A for Auxiliary snapshot | | | BD4 | GPIO\_11 | EMAC0\_PTP\_PPS\_O\_2 | PX\_3 | PD:nppukp | EMAC0 configurable PPS output 2 | | | BD4 | GPIO\_11 | EMAC1\_PTP\_AUX\_TS\_I\_2 | PX\_3 | PD:nppukp | EMAC1 trigger 2 A for Auxiliary snapshot | | | BD4 | GPIO\_11 | EMAC1\_PTP\_PPS\_O\_2 | PX\_3 | PD:nppukp | EMAC1 configurable PPS output 2 | | | BD4 | GPIO\_11 | GP\_PDM\_MIRA[1] | PX\_3 | PD:nppukp | General-purpose PDM output 1 A | | | BD4 | GPIO\_11 | BOOT\_CONFIG[13] | PX\_3 | PD:nppukp | Boot configuration bit 13 | | | BE3 | GPIO\_12 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BE3 | GPIO\_12 | USB2PHY\_AC\_EN2 | PX\_3 | PD:nppukp | USB AC coupling control for USB 2 port | Y | | BE3 | GPIO\_12 | EMAC0\_PTP\_AUX\_TS\_I\_3 | PX\_3 | PD:nppukp | EMAC0 trigger 3 A for Auxiliary snapshot | Y | | BE3 | GPIO\_12 | EMAC0\_PTP\_PPS\_O\_3 | PX\_3 | PD:nppukp | EMAC0 configurable PPS output 3 | Y | | BE3 | GPIO\_12 | EMAC1\_PTP\_AUX\_TS\_I\_3 | PX\_3 | PD:nppukp | EMAC1 trigger 3 A for Auxiliary snapshot | Y | | BE3 | GPIO\_12 | EMAC1\_PTP\_PPS\_O\_3 | PX\_3 | PD:nppukp | EMAC1 configurable PPS output 3 | Y | | BE3 | GPIO\_12 | EMAC0\_MCG\_PST\_TRIG\_LW[0] | PX\_3 | PD:nppukp | EMAC0 trigger input 0 for Media clock generation | Y | | BE3 | GPIO\_12 | GP\_PDM\_MIRB[1] | PX\_3 | PD:nppukp | General-purpose PDM output 1 B | Y | | BE3 | GPIO\_12 | BOOT\_CONFIG[14] | PX\_3 | PD:nppukp | Boot configuration bit 14 | Y | | J1 | GPIO\_13 | | PX\_3 | PD:nppukp | Configurable I/O | N | | J1 | GPIO\_13 | EMAC0\_MCG\_PST\_TRIG\_LW[1] | PX\_3 | PD:nppukp | EMAC0 trigger input 1 for Media clock generation | | | J3 | GPIO\_14 | | PX\_3 | PD:nppukp | Configurable I/O | N | | J3 | GPIO\_14 | EMAC0\_MCG\_PST\_TRIG\_LW[2] | PX\_3 | PD:nppukp | EMAC0 trigger input 2 for Media clock generation | | | J5 | GPIO\_15 | | PX\_3 | PD:nppukp | Configurable I/O | N | | J5 | GPIO\_15 | EMAC0\_MCG\_PST\_TRIG\_LW[3] | PX\_3 | PD:nppukp | EMAC0 trigger input 3 for Media clock generation | | | K2 | GPIO\_16 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | K2 | GPIO\_16 | EMAC1\_MCG\_PST\_TRIG\_LW[3] | PX\_3 | PD:nppukp | EMAC1 trigger input 0 for Media clock generation | | | K4 | GPIO\_17 | | PX\_3 | PD:nppukp | Configurable I/O | N | | K4 | GPIO\_17 | EMAC1\_MCG\_PST\_TRIG\_LW[1] | PX\_3 | PD:nppukp | EMAC1 trigger input 1 for Media clock generation | | | L1 | GPIO\_18 | | PX\_3 | PD:nppukp | Configurable I/O | N | | L1 | GPIO\_18 | EMAC1\_MCG\_PST\_TRIG\_LW[2] | PX\_3 | PD:nppukp | EMAC1 trigger input 2 for Media clock generation | | | L3 | GPIO\_19 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | L3 | GPIO\_19 | EMAC1\_MCG\_PST\_TRIG\_LW[3] | PX\_3 | PD:nppukp | EMAC1 trigger input 3 for Media clock generation | | | BG21 | GPIO\_20 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BG21 | GPIO\_20 | QUP0\_SE0\_L0 | PX\_3 | PD:nppukp | QUP0 SE0 lane 0: UART\_CTS/I2C\_SDA/SPI-M\_MISO | Y | | BG21 | GPIO\_20 | EMAC1\_MDC | PX\_3 | PD:nppukp | EMAC1 management interface clock | Y | | BG19 | GPIO\_21 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BG19 | GPIO\_21 | QUP0\_SE0\_L1 | PX\_3 | PD:nppukp | QUP0 SE0 lane 1: UART\_RFR/I2C\_SCL/SPI-M\_MOSI | N | | BG19 | GPIO\_21 | EMAC1\_MDIO | PX\_3 | PD:nppukp | EMAC1 management interface I/O | N | | BE21 | GPIO\_22 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BE21 | GPIO\_22 | QUP0\_SE0\_L2 | PX\_3 | PD:nppukp | QUP0 SE0 lane 2: UART\_TX/SPI-M\_SCLK | N | | BF20 | GPIO\_23 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BF20 | GPIO\_23 | QUP0\_SE0\_L3 | PX\_3 | PD:nppukp | QUP0 SE0 lane 3: UART\_RX/SPI-M\_CS0 | Y | | BD20 | GPIO\_24 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BD20 | GPIO\_24 | QUP0\_SE1\_L0 | PX\_3 | PD:nppukp | QUP0 SE1 lane 0: UART\_CTS/I2C\_SDA/SPI-M\_MISO | Y | | BE19 | GPIO\_25 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BE19 | GPIO\_25 | QUP0\_SE1\_L1 | PX\_3 | PD:nppukp | QUP0 SE1 lane 1: UART\_RFR/I2C\_SCL/SPI-M\_MOSI | N | | BF18 | GPIO\_26 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BF18 | GPIO\_26 | SGMII\_PHY\_INTR1\_N | PX\_3 | PD:nppukp | SGMII1 PHY interrupt | Y | | BF18 | GPIO\_26 | QUP0\_SE1\_L2 | PX\_3 | PD:nppukp | QUP0 SE1 lane 2: UART\_TX/SPI-M\_SCLK | Y | | BD18 | GPIO\_27 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BD18 | GPIO\_27 | QUP0\_SE1\_L3 | PX\_3 | PD:nppukp | QUP0 SE1 lane 3: UART\_RX/SPI-M\_CS0 | Y | | BG15 | GPIO\_28 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BG15 | GPIO\_28 | QUP0\_SE3\_L0 | PX\_3 | PD:nppukp | QUP0 SE3 lane 0: UART\_CTS/HS-UART\_CTS/I2C\_SDA/SPI-M\_MISO | Y | | BE17 | GPIO\_29 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BE17 | GPIO\_29 | QUP0\_SE3\_L1 | PX\_3 | PD:nppukp | QUP0 SE3 lane 1: UART\_RFR/HS-UART\_RFR/I2C\_SCL/SPI-M\_MOSI | Y | | BF16 | GPIO\_30 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BF16 | GPIO\_30 | QUP0\_SE3\_L2 | PX\_3 | PD:nppukp | QUP0 SE3 lane 2: UART\_TX/HS-UART\_TX/SPI-M\_SCLK | Y | | BD16 | GPIO\_31 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BD16 | GPIO\_31 | QUP0\_SE3\_L3 | PX\_3 | PD:nppukp | QUP0 SE3 lane 3: UART\_RX/HS-UART\_RX/SPI-M\_CS0 | Y | | BG13 | GPIO\_32 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BG13 | GPIO\_32 | QUP0\_SE4\_L0 | PX\_3 | PD:nppukp | QUP0 SE4 lane 0: UART\_CTS/I2C\_SDA/SPI-M\_MISO/SPI-S\_MISO | Y | | BE15 | GPIO\_33 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BE15 | GPIO\_33 | QUP0\_SE4\_L1 | PX\_3 | PD:nppukp | QUP0 SE4 lane 1: UART\_RFR/I2C\_SCL/SPI-M\_MOSI/SPI-S\_MOSI | N | | BE15 | GPIO\_33 | GCC\_GP4\_CLK\_MIRA | PX\_3 | PD:nppukp | General-purpose Clock 4 A | N | | BF14 | GPIO\_34 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BF14 | GPIO\_34 | QUP0\_SE4\_L2 | PX\_3 | PD:nppukp | QUP0 SE4 lane 2: UART\_TX/SPI-M\_SCLK/SPI-S\_SCLK | N | | BF14 | GPIO\_34 | GCC\_GP5\_CLK\_MIRA | PX\_3 | PD:nppukp | General-purpose Clock 5 A | N | | BE13 | GPIO\_35 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BE13 | GPIO\_35 | QUP0\_SE4\_L3 | PX\_3 | PD:nppukp | QUP0 SE4 lane 3: UART\_RX/SPI-M\_CS0/SPI-M\_CS | Y | | BE13 | GPIO\_35 | GP\_MN | PX\_3 | PD:nppukp | General-purpose M/N:D counter output | Y | | BF12 | GPIO\_36 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BF12 | GPIO\_36 | QUP0\_SE2\_L0 | PX\_3 | PD:nppukp | QUP0 SE2 lane 0: UART\_CTS/HS-UART\_CTS/I2C\_SDA/SPI-M\_MISO | Y | | BF12 | GPIO\_36 | QUP0\_SE5\_L0 | PX\_3 | PD:nppukp | QUP0 SE5 lane 0: UART\_CTS/I2C\_SDA/SPI-M\_MISO/SPI-S\_MISO | Y | | BD12 | GPIO\_37 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BD12 | GPIO\_37 | QUP0\_SE2\_L1 | PX\_3 | PD:nppukp | QUP0 SE2 lane 1: UART\_RFR/HS-UART\_RFR/I2C\_SCL/SPI-M\_MOSI | N | | BD12 | GPIO\_37 | QUP0\_SE5\_L1 | PX\_3 | PD:nppukp | QUP0 SE5 lane 1: UART\_RFR/I2C\_SCL/SPI-M\_MOSI/SPI-S\_MOSI | N | | BE11 | GPIO\_38 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BE11 | GPIO\_38 | QUP0\_SE5\_L2 | PX\_3 | PD:nppukp | QUP0 SE5 lane 2: UART\_TX/SPI-M\_SCLK/SPI-S\_SCLK | N | | BE11 | GPIO\_38 | QUP0\_SE2\_L2 | PX\_3 | PD:nppukp | QUP0 SE2 lane 2: UART\_TX/HS-UART\_TX/SPI-M\_SCLK | N | | BE11 | GPIO\_38 | BOOT\_CONFIG[1] | PX\_3 | PD:nppukp | Boot configuration bit 1 | N | | BD10 | GPIO\_39 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BD10 | GPIO\_39 | QUP0\_SE5\_L3 | PX\_3 | PD:nppukp | QUP0 SE5 lane 3: UART\_RX/SPI-M\_CS0/SPI-S\_CS | Y | | BD10 | GPIO\_39 | QUP0\_SE2\_L3 | PX\_3 | PD:nppukp | QUP0 SE2 lane 3: UART\_RX/HS-UART\_RX/SPI-M\_CS0 | Y | | BD30 | GPIO\_40 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BD30 | GPIO\_40 | QUP1\_SE0\_L0 | PX\_3 | PD:nppukp | QUP1 SE0 lane 0: UART\_CTS/I2C\_SDA/SPI-M\_MISO | Y | | BD30 | GPIO\_40 | QUP1\_SE1\_L2 | PX\_3 | PD:nppukp | QUP1 SE1 lane 2: UART\_TX/SPI-M\_SCLK | Y | | BE27 | GPIO\_41 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BE27 | GPIO\_41 | QUP1\_SE0\_L1 | PX\_3 | PD:nppukp | QUP1 SE0 lane 1: UART\_RFR/I2C\_SCL/SPI-M\_MOSI | Y | | BE27 | GPIO\_41 | QUP1\_SE1\_L3 | PX\_3 | PD:nppukp | QUP1 SE1 lane 3: UART\_RX/SPI-M\_CS0 | Y | | BD38 | GPIO\_42 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BD38 | GPIO\_42 | QUP1\_SE1\_L0 | PX\_3 | PD:nppukp | QUP1 SE1 lane 0: UART\_CTS/I2C\_SDA/SPI-M\_MISO | Y | | BD38 | GPIO\_42 | QUP1\_SE0\_L2 | PX\_3 | PD:nppukp | QUP1 SE0 lane 2: UART\_TX/SPI-M\_SCLK | Y | | BD38 | GPIO\_42 | GCC\_GP5\_CLK\_MIRB | PX\_3 | PD:nppukp | General-purpose Clock 5 B | Y | | BE37 | GPIO\_43 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BE37 | GPIO\_43 | QUP1\_SE1\_L1 | PX\_3 | PD:nppukp | QUP1 SE1 lane 1: UART\_RFR/I2C\_SCL/SPI-M\_MOSI | Y | | BE37 | GPIO\_43 | QUP1\_SE0\_L3 | PX\_3 | PD:nppukp | QUP1 SE0 lane 3: UART\_RX/SPI-M\_CS0 | Y | | BD36 | GPIO\_44 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BD36 | GPIO\_44 | QUP1\_SE2\_L2 | PX\_3 | PD:nppukp | QUP1 SE2 lane 2: UART\_TX/HS-UART\_TX/SPI-M\_SCLK | N | | BD36 | GPIO\_44 | QUP1\_SE3\_L0 | PX\_3 | PD:nppukp | QUP1 SE3 lane 0: UART\_CTS/HS-UART\_CTS/I2C\_SDA/SPI-M\_MISO | N | | BC37 | GPIO\_45 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BC37 | GPIO\_45 | QUP1\_SE2\_L3 | PX\_3 | PD:nppukp | QUP1 SE2 lane 3: UART\_RX/HS-UART\_RX/SPI-M\_CS0 | Y | | BC37 | GPIO\_45 | QUP1\_SE3\_L1 | PX\_3 | PD:nppukp | QUP1 SE3 lane 1: UART\_RFR/HS-UART\_RFR/I2C\_SCL/SPI-M\_MOSI | Y | | BE35 | GPIO\_46 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BE35 | GPIO\_46 | QUP1\_SE3\_L2 | PX\_3 | PD:nppukp | QUP1 SE3 lane 2: UART\_TX/HS-UART\_TX/SPI-M\_SCLK | N | | BE35 | GPIO\_46 | QUP1\_SE2\_L0 | PX\_3 | PD:nppukp | QUP1 SE2 lane 0: UART\_CTS/HS-UART\_CTS/I2C\_SDA/SPI-M\_MISO | N | | BD34 | GPIO\_47 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BD34 | GPIO\_47 | QUP1\_SE3\_L3 | PX\_3 | PD:nppukp | QUP1 SE3 lane 3: UART\_RX/HS-UART\_RX/SPI-M\_CS0 | Y | | BD34 | GPIO\_47 | QUP1\_SE2\_L1 | PX\_3 | PD:nppukp | QUP1 SE2 lane 1: UART\_RFR/HS-UART\_RFR/I2C\_SCL/SPI-M\_MOSI | Y | | BE29 | GPIO\_48 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BE29 | GPIO\_48 | QUP1\_SE4\_L0 | PX\_3 | PD:nppukp | QUP1 SE4 lane 0: UART\_CTS/I2C\_SDA/SPI-M\_MISO/SPI-S\_MISO | Y | | BE29 | GPIO\_48 | BOOT\_CONFIG[0] | PX\_3 | PD:nppukp | Boot configuration bit 0 | Y | | BD32 | GPIO\_49 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BD32 | GPIO\_49 | QUP1\_SE4\_L1 | PX\_3 | PD:nppukp | QUP1 SE4 lane 1: UART\_RFR/I2C\_SCL/SPI-M\_MOSI/SPI-S\_MOSI | N | | BF26 | GPIO\_50 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BF26 | GPIO\_50 | QUP1\_SE4\_L2 | PX\_3 | PD:nppukp | QUP1 SE4 lane 2: UART\_TX/SPI-M\_SCLK/SPI-S\_SCLK | N | | BF26 | GPIO\_50 | CCI\_ASYNC\_IN4 | PX\_3 | PD:nppukp | Camera control interface async 4 | N | | BF26 | GPIO\_50 | FORCED\_USB\_BOOT | PX\_3 | PD:nppukp | Boot strap to enter USB0 emergency download mode. See QCS9075 Technical
Reference Manual (80-73417-5) for details. | N | | BD26 | GPIO\_51 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BD26 | GPIO\_51 | QUP1\_SE4\_L3 | PX\_3 | PD:nppukp | QUP1 SE4 lane 3: UART\_RX/SPI-M\_CS0/SPI-S\_CS | | | BD26 | GPIO\_51 | GCC\_GP1\_CLK\_MIRB | PX\_3 | PD:nppukp | General-purpose Clock 1 B | | | BE25 | GPIO\_52 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BE25 | GPIO\_52 | QUP1\_SE5\_L0 | PX\_3 | PD:nppukp | QUP1 SE5 lane 0: UART\_CTS/I2C\_SDA/SPI-M\_MISO/SPI-S\_MISO | Y | | BE25 | GPIO\_52 | CCI\_TIMER4 | PX\_3 | PD:nppukp | Camera 4 control interface timer | Y | | BE25 | GPIO\_52 | CCI\_I2C\_SDA1 | PX\_3 | PD:nppukp | Camera 1 I^2^C Data | Y | | BE25 | GPIO\_52 | GCC\_GP2\_CLK\_MIRB | PX\_3 | PD:nppukp | General-purpose Clock 2 B | Y | | BG25 | GPIO\_53 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BG25 | GPIO\_53 | QUP1\_SE5\_L1 | PX\_3 | PD:nppukp | QUP1 SE5 lane 1: UART\_RFR/I2C\_SCL/SPI-M\_MOSI/SPI-S\_MOSI | N | | BG25 | GPIO\_53 | CCI\_TIMER5 | PX\_3 | PD:nppukp | Camera 5 control interface timer | N | | BG25 | GPIO\_53 | CCI\_I2C\_SCL1 | PX\_3 | PD:nppukp | Camera 1 I^2^C clock | N | | BG25 | GPIO\_53 | GCC\_GP3\_CLK\_MIRB | PX\_3 | PD:nppukp | General-purpose Clock 3 B | N | | BF24 | GPIO\_54 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BF24 | GPIO\_54 | QUP1\_SE5\_L2 | PX\_3 | PD:nppukp | QUP1 SE5 lane 2: UART\_TX/SPI-M\_SCLK/SPI-S\_SCLK | N | | BF24 | GPIO\_54 | CCI\_TIMER6 | PX\_3 | PD:nppukp | Camera 6 control interface timer | N | | BF24 | GPIO\_54 | CCI\_I2C\_SDA3 | PX\_3 | PD:nppukp | Camera 3 I^2^C Data | N | | BD24 | GPIO\_55 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BD24 | GPIO\_55 | QUP1\_SE5\_L3 | PX\_3 | PD:nppukp | QUP1 SE5 lane 3: UART\_RX/SPI-M\_CS0/SPI-M\_CS | Y | | BD24 | GPIO\_55 | CCI\_TIMER7 | PX\_3 | PD:nppukp | Camera 7 control interface timer | Y | | BD24 | GPIO\_55 | CCI\_I2C\_SCL3 | PX\_3 | PD:nppukp | Camera 3 I^2^C clock | Y | | BD24 | GPIO\_55 | GCC\_GP4\_CLK\_MIRB | PX\_3 | PD:nppukp | General-purpose Clock 4 B | Y | | BE23 | GPIO\_56 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BE23 | GPIO\_56 | QUP1\_SE6\_L0 | PX\_3 | PD:nppukp | QUP1 SE6 lane 0: UART\_CTS/I2C\_SDA | Y | | BE23 | GPIO\_56 | QUP1\_SE6\_L2 | PX\_3 | PD:nppukp | QUP1 SE6 lane 2: UART\_TX | Y | | BE23 | GPIO\_56 | CCI\_TIMER8 | PX\_3 | PD:nppukp | Camera 8 control interface timer | Y | | BE23 | GPIO\_56 | CCI\_I2C\_SDA5 | PX\_3 | PD:nppukp | Camera 5 I^2^C Data | Y | | BF22 | GPIO\_57 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BF22 | GPIO\_57 | QUP1\_SE6\_L1 | PX\_3 | PD:nppukp | QUP1 SE6 lane 1: UART\_RFR/I2C\_SCL | Y | | BF22 | GPIO\_57 | QUP1\_SE6\_L3 | PX\_3 | PD:nppukp | QUP1 SE6 lane 3: UART\_RX | Y | | BF22 | GPIO\_57 | CCI\_TIMER9 | PX\_3 | PD:nppukp | Camera 9 control interface timer | Y | | BF22 | GPIO\_57 | CCI\_I2C\_SCL5 | PX\_3 | PD:nppukp | Camera 5 I^2^C Clock | Y | | BB10 | GPIO\_58 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BB10 | GPIO\_58 | CCI\_I2C\_SDA7 | PX\_3 | PD:nppukp | Camera 7 I^2^C Data | Y | | BB10 | GPIO\_58 | BOOT\_CONFIG[11] | PX\_3 | PD:nppukp | Boot configuration bit 11 | Y | | BC11 | GPIO\_59 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BC11 | GPIO\_59 | CCI\_I2C\_SCL7 | PX\_3 | PD:nppukp | Camera 7 I^2^C clock | Y | | BB12 | GPIO\_60 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BB12 | GPIO\_60 | CCI\_I2C\_SDA0 | PX\_3 | PD:nppukp | Camera 0 I^2^C Data | N | | BC13 | GPIO\_61 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BC13 | GPIO\_61 | CCI\_I2C\_SCL0 | PX\_3 | PD:nppukp | Camera 0 I^2^C clock | N | | BB14 | GPIO\_62 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BB14 | GPIO\_62 | CCI\_I2C\_SDA2 | PX\_3 | PD:nppukp | Camera 2 I^2^C Data | N | | AY14 | GPIO\_63 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AY14 | GPIO\_63 | CCI\_I2C\_SCL2 | PX\_3 | PD:nppukp | Camera 2 I^2^C clock | N | | BA15 | GPIO\_64 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BA15 | GPIO\_64 | CCI\_I2C\_SDA4 | PX\_3 | PD:nppukp | Camera 4 I^2^C Data | N | | BC15 | GPIO\_65 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BC15 | GPIO\_65 | CCI\_I2C\_SCL4 | PX\_3 | PD:nppukp | Camera 4 I^2^C clock | N | | BB16 | GPIO\_66 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BB16 | GPIO\_66 | CCI\_I2C\_SDA6 | PX\_3 | PD:nppukp | Camera 6 I^2^C Data | N | | BB16 | GPIO\_66 | CCI\_ASYNC\_IN5 | PX\_3 | PD:nppukp | Camera control interface async 5 | N | | AY16 | GPIO\_67 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AY16 | GPIO\_67 | CCI\_I2C\_SCL6 | PX\_3 | PD:nppukp | Camera 6 I^2^C clock | N | | BC33 | GPIO\_68 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BC33 | GPIO\_68 | CCI\_TIMER0 | PX\_3 | PD:nppukp | Camera 0 control interface timer | N | | BC33 | GPIO\_68 | CCI\_ASYNC\_IN0 | PX\_3 | PD:nppukp | Camera control interface async 0 | N | | BA35 | GPIO\_69 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BA35 | GPIO\_69 | CCI\_TIMER1 | PX\_3 | PD:nppukp | Camera 1 control interface timer | N | | BA35 | GPIO\_69 | CCI\_ASYNC\_IN1 | PX\_3 | PD:nppukp | Camera control interface async 1 | N | | AY36 | GPIO\_70 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AY36 | GPIO\_70 | CCI\_TIMER2 | PX\_3 | PD:nppukp | Camera 2 control interface timer | N | | AY36 | GPIO\_70 | CCI\_ASYNC\_IN2 | PX\_3 | PD:nppukp | Camera control interface async 2 | N | | BB34 | GPIO\_71 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BB34 | GPIO\_71 | CCI\_TIMER3 | PX\_3 | PD:nppukp | Camera 3 control interface timer | N | | BB34 | GPIO\_71 | CCI\_ASYNC\_IN3 | PX\_3 | PD:nppukp | Camera control interface async 3 | N | | BB32 | GPIO\_72 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BB32 | GPIO\_72 | CAM\_MCLK0 | PX\_3 | PD:nppukp | Camera 0 MCLK | Y | | BA33 | GPIO\_73 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BA33 | GPIO\_73 | CAM\_MCLK1 | PX\_3 | PD:nppukp | Camera 1 MCLK | Y | | AY34 | GPIO\_74 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AY34 | GPIO\_74 | CAM\_MCLK2 | PX\_3 | PD:nppukp | Camera 2 MCLK | Y | | BA31 | GPIO\_75 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BA31 | GPIO\_75 | CAM\_MCLK3 | PX\_3 | PD:nppukp | Camera 3 MCLK | Y | | BC29 | GPIO\_76 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BB30 | GPIO\_77 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AY32 | GPIO\_78 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AY30 | GPIO\_79 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BC27 | GPIO\_80 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BC27 | GPIO\_80 | QUP2\_SE0\_L0 | PX\_3 | PD:nppukp | QUP2 SE0 lane 0: UART\_CTS/I2C\_SDA/SPI-M\_MISO | Y | | BC27 | GPIO\_80 | GP\_PDM\_MIRA[0] | PX\_3 | PD:nppukp | General-purpose PDM output 0 A | Y | | BA27 | GPIO\_81 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BA27 | GPIO\_81 | QUP2\_SE0\_L1 | PX\_3 | PD:nppukp | QUP2 SE0 lane 1: UART\_RFR/I2C\_SCL/SPI-M\_MOSI | N | | BA27 | GPIO\_81 | GP\_PDM\_MIRB[0] | PX\_3 | PD:nppukp | General-purpose PDM output 0 B | N | | AY26 | GPIO\_82 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AY26 | GPIO\_82 | QUP2\_SE0\_L2 | PX\_3 | PD:nppukp | QUP2 SE0 lane 2: UART\_TX/SPI-M\_SCLK | N | | AY26 | GPIO\_82 | MDP\_VSYNC\_S | PX\_3 | PD:nppukp | MDP vertical sync | N | | AY26 | GPIO\_82 | GCC\_GP1\_CLK\_MIRA | PX\_3 | PD:nppukp | General-purpose Clock 1 A | N | | BB26 | GPIO\_83 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BB26 | GPIO\_83 | QUP2\_SE0\_L3 | PX\_3 | PD:nppukp | QUP2 SE0 lane 3: UART\_RX/SPI-M\_CS0 | Y | | BB26 | GPIO\_83 | MDP\_VSYNC\_E | PX\_3 | PD:nppukp | MDP vertical sync – external | Y | | BB26 | GPIO\_83 | GCC\_GP2\_CLK\_MIRA | PX\_3 | PD:nppukp | General-purpose Clock 2 A | Y | | BC25 | GPIO\_84 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BC25 | GPIO\_84 | QUP2\_SE1\_L0 | PX\_3 | PD:nppukp | QUP2 SE1 lane 0: UART\_CTS/I2C\_SDA/SPI-M\_MISO | Y | | BC25 | GPIO\_84 | QUP2\_SE5\_L2 | PX\_3 | PD:nppukp | QUP2 SE5 lane 2: UART\_TX/SPI-M\_SCLK/SPI-S\_SCLK | Y | | BC25 | GPIO\_84 | MDP\_VSYNC\_P | PX\_3 | PD:nppukp | MDP vertical sync – Primary | Y | | BC25 | GPIO\_84 | GCC\_GP3\_CLK\_MIRA | PX\_3 | PD:nppukp | General-purpose Clock 3 A | Y | | BA25 | GPIO\_85 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BA25 | GPIO\_85 | QUP2\_SE1\_L1 | PX\_3 | PD:nppukp | QUP2 SE1 lane 1: UART\_RFR/I2C\_SCL/SPI-M\_MOSI | Y | | BA25 | GPIO\_85 | QUP2\_SE5\_L3 | PX\_3 | PD:nppukp | QUP2 SE5 lane 3: UART\_RX/SPI-M\_CS0/SPI-M\_CS | Y | | AY24 | GPIO\_86 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AY24 | GPIO\_86 | QUP2\_SE2\_L0 | PX\_3 | PD:nppukp | QUP2 SE2 lane 0: UART\_CTS/HS-UART\_CTS/I2C\_SDA/SPI-M\_MISO | Y | | BC23 | GPIO\_87 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BC23 | GPIO\_87 | QUP2\_SE2\_L1 | PX\_3 | PD:nppukp | QUP2 SE2 lane 1: UART\_RFR/HS-UART\_RFR/I2C\_SCL/SPI-M\_MOSI | N | | AY22 | GPIO\_88 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AY22 | GPIO\_88 | QUP2\_SE2\_L2 | PX\_3 | PD:nppukp | QUP2 SE2 lane 2: UART\_TX/HS-UART\_TX/SPI-M\_SCLK | N | | BA23 | GPIO\_89 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BA23 | GPIO\_89 | QUP2\_SE2\_L3 | PX\_3 | PD:nppukp | QUP2 SE2 lane 3: UART\_RX/HS-UART\_RX/SPI-M\_CS0 | Y | | BB22 | GPIO\_90 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BB22 | GPIO\_90 | QUP2\_SE2\_L4 | PX\_3 | PD:nppukp | QUP2 SE2 lane 4: SPI-M\_CS1 | N | | BC21 | GPIO\_91 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BC21 | GPIO\_91 | QUP2\_SE3\_L0 | PX\_3 | PD:nppukp | QUP2 SE3 lane 0: UART\_CTS/HS-UART\_CTS/I2C\_SDA/SPI-M\_MISO | Y | | BA21 | GPIO\_92 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BA21 | GPIO\_92 | QUP2\_SE3\_L1 | PX\_3 | PD:nppukp | QUP2 SE3 lane 1: UART\_RFR/HS-UART\_RFR/I2C\_SCL/SPI-M\_MOSI | N | | AY20 | GPIO\_93 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AY20 | GPIO\_93 | QUP2\_SE3\_L2 | PX\_3 | PD:nppukp | QUP2 SE3 lane 2: UART\_TX/HS-UART\_TX/SPI-M\_SCLK | N | | BB20 | GPIO\_94 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BB20 | GPIO\_94 | QUP2\_SE3\_L3 | PX\_3 | PD:nppukp | QUP2 SE3 lane 3: UART\_RX/HS-UART\_RX/SPI-M\_CS0 | Y | | BC19 | GPIO\_95 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BC19 | GPIO\_95 | QUP2\_SE4\_L0 | PX\_3 | PD:nppukp | QUP2 SE4 lane 0: UART\_CTS/I2C\_SDA/SPI-M\_MISO/SPI-S\_MISO | Y | | BC19 | GPIO\_95 | QUP2\_SE6\_L2 | PX\_3 | PD:nppukp | QUP2 SE6 lane 2: UART\_TX/SPI-M\_SCLK | Y | | BA19 | GPIO\_96 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BA19 | GPIO\_96 | QUP2\_SE4\_L1 | PX\_3 | PD:nppukp | QUP2 SE4 lane 1: UART\_RFR/I2C\_SCL/SPI-M\_MOSI/SPI-S\_MOSI | Y | | BA19 | GPIO\_96 | QUP2\_SE6\_L3 | PX\_3 | PD:nppukp | QUP2 SE6 lane 3: UART\_RX/SPI-M\_CS0 | Y | | AY18 | GPIO\_97 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AY18 | GPIO\_97 | QUP2\_SE6\_L0 | PX\_3 | PD:nppukp | QUP2 SE6 lane 0: UART\_CTS/I2C\_SDA/SPI-M\_MISO | Y | | AY18 | GPIO\_97 | QUP2\_SE4\_L2 | PX\_3 | PD:nppukp | QUP2 SE4 lane 2: UART\_TX/SPI-M\_SCLK/SPI-S\_SCLK | Y | | BB18 | GPIO\_98 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BB18 | GPIO\_98 | QUP2\_SE6\_L1 | PX\_3 | PD:nppukp | QUP2 SE6 lane 1: UART\_RFR/I2C\_SCL/SPI-M\_MOSI | Y | | BB18 | GPIO\_98 | QUP2\_SE4\_L3 | PX\_3 | PD:nppukp | QUP2 SE4 lane 3: UART\_RX/SPI-M\_CS0/SPI-M\_CS | Y | | BA17 | GPIO\_99 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BA17 | GPIO\_99 | QUP2\_SE5\_L0 | PX\_3 | PD:nppukp | QUP2 SE5 lane 0: UART\_CTS/I2C\_SDA/SPI-M\_MISO/SPI-S\_MISO | Y | | BA17 | GPIO\_99 | QUP2\_SE1\_L2 | PX\_3 | PD:nppukp | QUP2 SE1 lane 2: UART\_TX/SPI-M\_SCLK | Y | | BC17 | GPIO\_100 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BC17 | GPIO\_100 | QUP2\_SE5\_L1 | PX\_3 | PD:nppukp | QUP2 SE5 lane 1: UART\_RFR/I2C\_SCL/SPI-M\_MOSI/SPI-S\_MOSI | Y | | BC17 | GPIO\_100 | QUP2\_SE1\_L3 | PX\_3 | PD:nppukp | QUP2 SE1 lane 3: UART\_RX/SPI-M\_CS0 | Y | | BA37 | GPIO\_101 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BA37 | GPIO\_101 | EDP0\_HOT\_PLUG\_DETECT | PX\_3 | PD:nppukp | Embedded DisplayPort 0 hot plug detect | N | | BB38 | GPIO\_102 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BB38 | GPIO\_102 | EDP1\_HOT\_PLUG\_DETECT | PX\_3 | PD:nppukp | Embedded DisplayPort 1 hot plug detect | N | | AY40 | GPIO\_103 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AY40 | GPIO\_103 | EDP3\_HOT\_PLUG\_DETECT | PX\_3 | PD:nppukp | Embedded DisplayPort 3 hot plug detect | N | | AY38 | GPIO\_104 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AY38 | GPIO\_104 | EDP2\_HOT\_PLUG\_DETECT | PX\_3 | PD:nppukp | Embedded DisplayPort 2 hot plug detect | N | | AP78 | GPIO\_105 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AP78 | GPIO\_105 | MI2S\_MCLK0 | PX\_3 | PD:nppukp | MI2S master clock 0 | Y | | AP78 | GPIO\_105 | BOOT\_CONFIG[2] | PX\_3 | PD:nppukp | Boot configuration bit 2 | Y | | AP80 | GPIO\_106 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AP80 | GPIO\_106 | MI2S1\_SCK\_OR\_HS3\_MI2S\_SCK | PX\_3 | PD:nppukp | MI2S 1 clock or high-speed 3 MI2S clock | Y | | AP80 | GPIO\_106 | BOOT\_CONFIG[3] | PX\_3 | PD:nppukp | Boot configuration bit 3 | Y | | AR71 | GPIO\_107 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AR71 | GPIO\_107 | MI2S1\_WS\_OR\_HS3\_MI2S\_WS | PX\_3 | PD:nppukp | MI2S 1 word select or high-speed 3 MI2S word select and synchronization | Y | | AR71 | GPIO\_107 | RESERVED | PX\_3 | PD:nppukp | Reserved boot configuration pin. See *QCS9075 Technical Reference Manual*
(80-73417-5) for details. | Y | | AR73 | GPIO\_108 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AR73 | GPIO\_108 | MI2S1\_DATA0\_OR\_HS3\_MI2S\_DATA0 | PX\_3 | PD:nppukp | MI2S 1 serial data channel 0 or high speed 3 MI2S serial data channel 0 | Y | | AR75 | GPIO\_109 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AR75 | GPIO\_109 | MI2S1\_DATA1\_OR\_HS3\_MI2S\_DATA1 | PX\_3 | PD:nppukp | MI2S 1 serial data channel 1 or high speed 3 MI2S serial data channel 1 | Y | | AR77 | GPIO\_110 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AR77 | GPIO\_110 | MI2S2\_SCK\_OR\_HS4\_MI2S\_SCK | PX\_3 | PD:nppukp | MI2S 2 clock or High-speed 4 MI2S clock | N | | AR77 | GPIO\_110 | BOOT\_CONFIG[4] | PX\_3 | PD:nppukp | Boot configuration bit 4 | N | | AR81 | GPIO\_111 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AR81 | GPIO\_111 | MI2S2\_WS\_OR\_HS4\_MI2S\_WS | PX\_3 | PD:nppukp | MI2S 2 serial data word select or high-speed 4 MI2S 2 serial data word select and synchronization | N | | AT70 | GPIO\_112 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AT70 | GPIO\_112 | MI2S2\_DATA0\_OR\_HS4\_MI2S\_DATA0 | PX\_3 | PD:nppukp | MI2S 2 serial data channel 0 or high speed 4 MI2S serial data channel 0 | N | | AT72 | GPIO\_113 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AT72 | GPIO\_113 | MI2S2\_DATA1\_OR\_HS4\_MI2S\_DATA1 | PX\_3 | PD:nppukp | MI2S 2 serial data channel 1 or high speed 4 MI2S serial data channel 1 | N | | AT72 | GPIO\_113 | AUDIO\_REF\_CLK | PX\_3 | PD:nppukp | Audio reference clock | N | | AT76 | GPIO\_114 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AT76 | GPIO\_114 | HS\_I2S0\_SCK | PX\_3 | PD:nppukp | High-speed 0 MI2S clock | N | | AT78 | GPIO\_115 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AT78 | GPIO\_115 | HS\_I2S0\_WS | PX\_3 | PD:nppukp | High-speed 0 MI2S word select | N | | AU71 | GPIO\_116 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AU71 | GPIO\_116 | HS\_I2S0\_DATA0 | PX\_3 | PD:nppukp | High-speed 0 MI2S data 0 | N | | AU73 | GPIO\_117 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AU73 | GPIO\_117 | HS\_I2S0\_DATA1 | PX\_3 | PD:nppukp | High-speed 0 MI2S data 1 | N | | AU73 | GPIO\_117 | MI2S\_MCLK1 | PX\_3 | PD:nppukp | MI2S master clock 1 | N | | AU75 | GPIO\_118 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AU75 | GPIO\_118 | HS\_I2S1\_WS | PX\_3 | PD:nppukp | High-speed 1 MI2S word select | N | | AU77 | GPIO\_119 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AU77 | GPIO\_119 | HS\_I2S1\_SCK | PX\_3 | PD:nppukp | High-speed 1 MI2S clock | N | | AV70 | GPIO\_120 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AV70 | GPIO\_120 | HS\_I2S1\_DATA0 | PX\_3 | PD:nppukp | High-speed 1 MI2S data 0 | N | | AV72 | GPIO\_121 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AV72 | GPIO\_121 | HS\_I2S1\_DATA1 | PX\_3 | PD:nppukp | High-speed 1 MI2S data 1 | N | | AW71 | GPIO\_122 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AW71 | GPIO\_122 | HS\_I2S2\_SCK | PX\_3 | PD:nppukp | High-speed 2 MI2S clock | N | | AW73 | GPIO\_123 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AW73 | GPIO\_123 | HS\_I2S2\_WS | PX\_3 | PD:nppukp | High-speed 2 MI2S word select | N | | AW75 | GPIO\_124 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AW75 | GPIO\_124 | HS\_I2S2\_DATA0 | PX\_3 | PD:nppukp | High-speed 2 MI2S data 0 | N | | AW77 | GPIO\_125 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AW77 | GPIO\_125 | HS\_I2S2\_DATA1 | PX\_3 | PD:nppukp | High-speed 2 MI2S data 1 | N | | AJ77 | GPIO\_126 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AJ77 | GPIO\_126 | LPASS\_0 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | N | | AK72 | GPIO\_127 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AK72 | GPIO\_127 | LPASS\_1 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | N | | AK76 | GPIO\_128 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AK76 | GPIO\_128 | LPASS\_2 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | N | | AK78 | GPIO\_129 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AK78 | GPIO\_129 | LPASS\_3 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | N | | AK80 | GPIO\_130 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AK80 | GPIO\_130 | LPASS\_4 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | N | | AL71 | GPIO\_131 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AL71 | GPIO\_131 | LPASS\_5 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | N | | AL73 | GPIO\_132 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AL73 | GPIO\_132 | LPASS\_6 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | N | | AL75 | GPIO\_133 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AL75 | GPIO\_133 | LPASS\_7 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | N | | AL77 | GPIO\_134 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AL77 | GPIO\_134 | LPASS\_8 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | N | | AL81 | GPIO\_135 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AL81 | GPIO\_135 | LPASS\_9 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | N | | AM70 | GPIO\_136 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AM70 | GPIO\_136 | LPASS\_10 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | N | | AM72 | GPIO\_137 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AM72 | GPIO\_137 | LPASS\_11 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | N | | AM76 | GPIO\_138 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AM76 | GPIO\_138 | LPASS\_15 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | N | | AM78 | GPIO\_139 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AM78 | GPIO\_139 | LPASS\_16 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | N | | AM80 | GPIO\_140 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AM80 | GPIO\_140 | LPASS\_14 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | N | | AN71 | GPIO\_141 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AN71 | GPIO\_141 | LPASS\_12 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | N | | AN73 | GPIO\_142 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AN73 | GPIO\_142 | LPASS\_13 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | N | | AN75 | GPIO\_143 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AN75 | GPIO\_143 | LPASS\_17 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | N | | AN77 | GPIO\_144 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AN77 | GPIO\_144 | LPASS\_18 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | N | | AN81 | GPIO\_145 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AN81 | GPIO\_145 | LPASS\_19 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | Y | | AP70 | GPIO\_146 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AP70 | GPIO\_146 | LPASS\_20 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | Y | | AP72 | GPIO\_147 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AP72 | GPIO\_147 | LPASS\_21 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | N | | AP76 | GPIO\_148 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AP76 | GPIO\_148 | LPASS\_22 | PX\_3 | PD:nppukp | See [MD_LPASS pins](https://docs.qualcomm.com/doc/80-73417-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_2) for details | N | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ### RTSS I/O pins | Pin number | RTSS I/O | Alternate functions | Pad voltage | Pad type | Functional description | Wakeup function | | --- | --- | --- | --- | --- | --- | --- | | P4 | RTSS\_IO\_0 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | P4 | RTSS\_IO\_0 | RTSS\_QUP0\_SE0\_L0 | RTSS\_PX\_3 | PD:nppukp | RTSS QUP0 SE0 lane 0: UART\_CTS/ I2C\_SDA/SPI-M\_MISO/SPI-S\_MISO | N | | P2 | RTSS\_IO\_1 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | P2 | RTSS\_IO\_1 | RTSS\_QUP0\_SE0\_L1 | RTSS\_PX\_3 | PD:nppukp | RTSS QUP0 SE0 lane 1: UART\_RFR/I2C\_SCL/SPI-M\_MOSI/SPI-S\_MOSI | N | | R3 | RTSS\_IO\_2 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | R3 | RTSS\_IO\_2 | RTSS\_QUP0\_SE1\_L0 | RTSS\_PX\_3 | PD:nppukp | RTSS QUP0 SE1 lane 0: UART\_CTS/I2C\_SDA/SPI-M\_MISO/SPI-S\_MISO | Y | | R5 | RTSS\_IO\_3 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | R5 | RTSS\_IO\_3 | RTSS\_QUP0\_SE1\_L1 | RTSS\_PX\_3 | PD:nppukp | RTSS QUP0 SE1 lane 1: UART\_RFR/I2C\_SCL/SPI-M\_MOSI/SPI-S\_MOSI | N | | T2 | RTSS\_IO\_4 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | T2 | RTSS\_IO\_4 | RTSS\_QUP0\_SE1\_L2 | RTSS\_PX\_3 | PD:nppukp | RTSS QUP0 SE1 lane 2: UART\_TX/SPI-M\_SCLK/SPI-S\_SCLK | N | | T2 | RTSS\_IO\_4 | RTSS\_QUP0\_SE3\_L2 | RTSS\_PX\_3 | PD:nppukp | RTSS QUP0 SE3 lane 2: UART\_TX/HS UART\_TX/SPI-M\_SCLK | N | | T4 | RTSS\_IO\_5 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | T4 | RTSS\_IO\_5 | RTSS\_QUP0\_SE1\_L3 | RTSS\_PX\_3 | PD:nppukp | RTSS QUP0 SE1 lane 3: UART\_RX/SPI-M\_CS0/SPI-S\_CS | N | | T4 | RTSS\_IO\_5 | RTSS\_QUP0\_SE3\_L3 | RTSS\_PX\_3 | PD:nppukp | RTSS QUP0 SE3 lane 3: UART\_RX/HS-UART\_RX/SPI-M\_CS0 | N | | U1 | RTSS\_IO\_6 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | U1 | RTSS\_IO\_6 | RTSS\_QUP0\_SE2\_L2 | RTSS\_PX\_3 | PD:nppukp | RTSS QUP0 SE2 lane 2: UART\_TX/HS UART\_TX/SPI-M\_SCLK | N | | U1 | RTSS\_IO\_6 | RTSS\_QUP0\_SE0\_L2 | RTSS\_PX\_3 | PD:nppukp | RTSS QUP0 SE0 lane 2: UART\_TX/SPI-M\_SCLK/SPI-S\_SCLK | N | | U1 | RTSS\_IO\_6 | RTSS\_BOOT\_CONFIG[13] | RTSS\_PX\_3 | PD:nppukp | RTSS Boot configuration bit 13 | N | | U3 | RTSS\_IO\_7 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | U3 | RTSS\_IO\_7 | RTSS\_QUP0\_SE2\_L3 | RTSS\_PX\_3 | PD:nppukp | RTSS QUP0 SE2 lane 3: UART\_RX/HS-UART\_RX/SPI-M\_CS0 | Y | | U3 | RTSS\_IO\_7 | RTSS\_QUP0\_SE0\_L3 | RTSS\_PX\_3 | PD:nppukp | RTSS QUP0 SE0 lane 3: UART\_RX/SPI-M\_CS0/SPI-S\_CS | Y | | U3 | RTSS\_IO\_7 | RTSS\_BOOT\_CONFIG[14] | RTSS\_PX\_3 | PD:nppukp | RTSS Boot configuration bit 14 | Y | | U5 | RTSS\_IO\_8 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | U5 | RTSS\_IO\_8 | RTSS\_QUP0\_SE3\_L0 | RTSS\_PX\_3 | PD:nppukp | RTSS QUP0 SE3 lane 0: UART\_CTS/HS-UART\_CTS/I2C\_SDA/SPI-M\_MISO | N | | U5 | RTSS\_IO\_8 | RTSS\_QUP0\_SE2\_L0 | RTSS\_PX\_3 | PD:nppukp | RTSS QUP0 SE2 lane 0: UART\_CTS/HS-UART\_CTS/I2C\_SDA/SPI-M\_MISO | N | | V2 | RTSS\_IO\_9 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | V2 | RTSS\_IO\_9 | RTSS\_QUP0\_SE3\_L1 | RTSS\_PX\_3 | PD:nppukp | RTSS QUP0 SE3 lane 1: UART\_RFR/HS-UART\_RFR/I2C\_SCL/ SPI-M\_MOSI | N | | V2 | RTSS\_IO\_9 | RTSS\_QUP0\_SE2\_L1 | RTSS\_PX\_3 | PD:nppukp | RTSS QUP0 SE2 lane 1: UART\_RFR/HS-UART\_RFR /I2C\_SCL/SPI-M\_MOSI | N | | V4 | RTSS\_IO\_10 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | V4 | RTSS\_IO\_10 | RTSS\_QUP0\_SE4\_L0 | RTSS\_PX\_3 | PD:nppukp | RTSS QUP0 SE4 lane 0: UART\_CTS/I2C\_SDA/ SPI-M\_MISO | Y | | W3 | RTSS\_IO\_11 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | W3 | RTSS\_IO\_11 | RTSS\_QUP0\_SE4\_L1 | RTSS\_PX\_3 | PD:nppukp | RTSS QUP0 SE4 lane 1: UART\_RFR/ /I2C\_SCL/ SPI-M\_MOSI | N | | W5 | RTSS\_IO\_12 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | W5 | RTSS\_IO\_12 | RTSS\_QUP0\_SE4\_L2 | RTSS\_PX\_3 | PD:nppukp | RTSS QUP0 SE4 lane 2: UART\_TX/SPI-M\_SCLK | N | | Y2 | RTSS\_IO\_13 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | Y2 | RTSS\_IO\_13 | RTSS\_QUP0\_SE4\_L3 | RTSS\_PX\_3 | PD:nppukp | RTSS QUP0 SE4 lane 3: UART\_RX/SPI-M\_CS0 | N | | Y4 | RTSS\_IO\_14 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | Y4 | RTSS\_IO\_14 | RTSS\_QUP0\_SE4\_L4 | RTSS\_PX\_3 | PD:nppukp | RTSS QUP0 SE4 lane 4: SPI-M\_CS1 | N | | Y4 | RTSS\_IO\_14 | RTSS\_BOOT\_CONFIG[6] | RTSS\_PX\_3 | PD:nppukp | RTSS Boot configuration bit 6 | N | | AA5 | RTSS\_IO\_15 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | AA5 | RTSS\_IO\_15 | RTSS\_FORCED\_USB\_BOOT | RTSS\_PX\_3 | PD:nppukp | Bootstrap to enter USB0 emergency download mode for RTSS domain. See *QCS9075 Technical Reference Manual* (80-73417-5) for details. | | | AA3 | RTSS\_IO\_16 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | AA3 | RTSS\_IO\_16 | RTSS\_RGMII\_VOL\_SEL | RTSS\_PX\_3 | PD:nppukp | Voltage selection pin for RTSS RGMII interface | Y | | AA1 | RTSS\_IO\_17 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | AA1 | RTSS\_IO\_17 | RTSS\_BOOT\_CONFIG[11] | RTSS\_PX\_3 | PD:nppukp | RTSS Boot configuration bit 11 | Y | | T6 | RTSS\_IO\_18 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | T6 | RTSS\_IO\_18 | RTSS\_BOOT\_CONFIG[12] | RTSS\_PX\_3 | PD:nppukp | RTSS Boot configuration bit 12 | Y | | AV6 | RTSS\_IO\_19 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | AV6 | RTSS\_IO\_19 | RTSS\_ERR1 | RTSS\_PX\_3 | PD:nppukp | RTSS error 1 (default output LOW) | N | | AU5 | RTSS\_IO\_20 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | AU5 | RTSS\_IO\_20 | RTSS\_ERR2 | RTSS\_PX\_3 | PD:nppukp | RTSS SS error 1 (default output HIGH) | N | | BB8 | RTSS\_IO\_21 | | RTSS\_PX\_8 | PD:nppukp | RTSS domain configurable I/O | Y | | BB8 | RTSS\_IO\_21 | RTSS\_EMAC0\_PHY\_INTR\_N | RTSS\_PX\_8 | PD:nppukp | RTSS Ethernet interrupt 0 | Y | | BB6 | RTSS\_IO\_22 | | RTSS\_PX\_8 | PD:nppukp | RTSS domain configurable I/O | N | | BB6 | RTSS\_IO\_22 | RTSS\_RGMII0\_MDC | RTSS\_PX\_8 | PD:nppukp | RTSS RGMII 0 management interface clock | N | | BC7 | RTSS\_IO\_23 | | RTSS\_PX\_8 | PD:nppukp | RTSS domain configurable I/O | N | | BC7 | RTSS\_IO\_23 | RTSS\_RGMII0\_MDIO | RTSS\_PX\_8 | PD:nppukp | RTSS RGMII 0 management interface clock | N | | BA3 | RTSS\_IO\_24 | | RTSS\_PX\_8 | PD:nppukp | RTSS domain configurable I/O | N | | BA3 | RTSS\_IO\_24 | RTSS\_RGMII0\_RXC | RTSS\_PX\_8 | PD:nppukp | RTSS RGMII 0 receive clock signal | N | | AY4 | RTSS\_IO\_25 | | RTSS\_PX\_8 | PD:nppukp | RTSS domain configurable I/O | N | | AY4 | RTSS\_IO\_25 | RTSS\_RGMII0\_RX\_CTL | RTSS\_PX\_8 | PD:nppukp | RTSS RGMII 0 receive control | N | | AY2 | RTSS\_IO\_26 | | RTSS\_PX\_8 | PD:nppukp | RTSS domain configurable I/O | N | | AY2 | RTSS\_IO\_26 | RTSS\_RGMII0\_RXD0 | RTSS\_PX\_8 | PD:nppukp | RTSS RGMII 0 receive data 0 | N | | AW5 | RTSS\_IO\_27 | | RTSS\_PX\_8 | PD:nppukp | RTSS domain configurable I/O | N | | AW5 | RTSS\_IO\_27 | RTSS\_RGMII0\_RXD1 | RTSS\_PX\_8 | PD:nppukp | RTSS RGMII 0 receive data 1 | N | | AW3 | RTSS\_IO\_28 | | RTSS\_PX\_8 | PD:nppukp | RTSS domain configurable I/O | N | | AW3 | RTSS\_IO\_28 | RTSS\_RGMII0\_RXD2 | RTSS\_PX\_8 | PD:nppukp | RTSS RGMII 0 receive data 2 | N | | AW1 | RTSS\_IO\_29 | | RTSS\_PX\_8 | PD:nppukp | RTSS domain configurable I/O | N | | AW1 | RTSS\_IO\_29 | RTSS\_RGMII0\_RXD3 | RTSS\_PX\_8 | PD:nppukp | RTSS RGMII 0 receive data 3 | N | | BC1 | RTSS\_IO\_30 | | RTSS\_PX\_8 | PD:nppukp | RTSS domain configurable I/O | N | | BC1 | RTSS\_IO\_30 | RTSS\_RGMII0\_TXC | RTSS\_PX\_8 | PD:nppukp | RTSS RGMII 0 transmit clock signal | N | | BC3 | RTSS\_IO\_31 | | RTSS\_PX\_8 | PD:nppukp | RTSS domain configurable I/O | N | | BC3 | RTSS\_IO\_31 | RTSS\_RGMII0\_TX\_CTL | RTSS\_PX\_8 | PD:nppukp | RTSS RGMII 0 transmit control | N | | BC5 | RTSS\_IO\_32 | | RTSS\_PX\_8 | PD:nppukp | RTSS domain configurable I/O | N | | BC5 | RTSS\_IO\_32 | RTSS\_RGMII0\_TXD0 | RTSS\_PX\_8 | PD:nppukp | RTSS RGMII 0 transmit data 0 | N | | BB4 | RTSS\_IO\_33 | | RTSS\_PX\_8 | PD:nppukp | RTSS domain configurable I/O | N | | BB4 | RTSS\_IO\_33 | RTSS\_RGMII0\_TXD1 | RTSS\_PX\_8 | PD:nppukp | RTSS RGMII 0 transmit data 1 | | | BA5 | RTSS\_IO\_34 | | RTSS\_PX\_8 | PD:nppukp | RTSS domain configurable I/O | N | | BA5 | RTSS\_IO\_34 | RTSS\_RGMII0\_TXD2 | RTSS\_PX\_8 | PD:nppukp | RTSS RGMII 0 transmit data 2 | | | BB2 | RTSS\_IO\_35 | | RTSS\_PX\_8 | PD:nppukp | RTSS domain configurable I/O | N | | BB2 | RTSS\_IO\_35 | RTSS\_RGMII0\_TXD3 | RTSS\_PX\_8 | PD:nppukp | RTSS RGMII 0 transmit data 3 | | | BA7 | RTSS\_IO\_36 | | RTSS\_PX\_8 | PD:nppukp | RTSS domain configurable I/O | N | | AB2 | RTSS\_IO\_37 | | RTSS\_PX\_3 | PU:nppdkp | RTSS domain configurable I/O | N | | AB2 | RTSS\_IO\_37 | RTSS\_CAN0\_TX | RTSS\_PX\_3 | PU:nppdkp | RTSS CAN 0 transmit | N | | AB2 | RTSS\_IO\_37 | RTSS\_BOOT\_CONFIG[0] | RTSS\_PX\_3 | PU:nppdkp | RTSS Boot configuration bit 0 | N | | AB4 | RTSS\_IO\_38 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | AB4 | RTSS\_IO\_38 | RTSS\_CAN0\_RX | RTSS\_PX\_3 | PD:nppukp | RTSS CAN 0 receive | Y | | AB4 | RTSS\_IO\_38 | RTSS\_CC\_GP2\_CLK\_MIRA | RTSS\_PX\_3 | PD:nppukp | RTSS Global general-purpose clock 2 A | Y | | AD4 | RTSS\_IO\_39 | | RTSS\_PX\_3 | PU:nppdkp | RTSS domain configurable I/O | N | | AD4 | RTSS\_IO\_39 | RTSS\_CAN1\_TX | RTSS\_PX\_3 | PU:nppdkp | RTSS CAN 1 transmit | N | | AD4 | RTSS\_IO\_39 | RTSS\_BOOT\_CONFIG[1] | RTSS\_PX\_3 | PU:nppdkp | RTSS Boot configuration bit 1 | N | | AC3 | RTSS\_IO\_40 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | AC3 | RTSS\_IO\_40 | RTSS\_CAN1\_RX | RTSS\_PX\_3 | PD:nppukp | RTSS CAN 1 receive | Y | | AC3 | RTSS\_IO\_40 | RTSS\_CC\_GP2\_CLK\_MIRB | RTSS\_PX\_3 | PD:nppukp | RTSS Global general-purpose clock 2 B | Y | | AD2 | RTSS\_IO\_41 | | RTSS\_PX\_3 | PU:nppdkp | RTSS domain configurable I/O | N | | AD2 | RTSS\_IO\_41 | RTSS\_CAN2\_TX | RTSS\_PX\_3 | PU:nppdkp | RTSS CAN 2 transmit | N | | AE5 | RTSS\_IO\_42 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | AE5 | RTSS\_IO\_42 | RTSS\_CAN2\_RX | RTSS\_PX\_3 | PD:nppukp | RTSS CAN 2 receive | Y | | AE5 | RTSS\_IO\_42 | RTSS\_CC\_GP3\_CLK\_MIRA | RTSS\_PX\_3 | PD:nppukp | RTSS Global general-purpose clock 3 A | Y | | AE3 | RTSS\_IO\_43 | | RTSS\_PX\_3 | PU:nppdkp | RTSS domain configurable I/O | N | | AE3 | RTSS\_IO\_43 | RTSS\_CAN3\_TX | RTSS\_PX\_3 | PU:nppdkp | RTSS CAN 3 transmit | N | | AE3 | RTSS\_IO\_43 | RTSS\_BOOT\_CONFIG[2] | RTSS\_PX\_3 | PU:nppdkp | RTSS Boot configuration bit 2 | N | | AE1 | RTSS\_IO\_44 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | AE1 | RTSS\_IO\_44 | RTSS\_CAN3\_RX | RTSS\_PX\_3 | PD:nppukp | RTSS CAN 3 receive | Y | | AE1 | RTSS\_IO\_44 | RTSS\_CC\_GP3\_CLK\_MIRB | RTSS\_PX\_3 | PD:nppukp | RTSS Global general-purpose clock 3 B | Y | | AF4 | | | RTSS\_PX\_3 | PU:nppdkp | RTSS domain configurable I/O | N | | AF4 | RTSS\_IO\_45 | RTSS\_CAN4\_TX | RTSS\_PX\_3 | PU:nppdkp | RTSS CAN 4 transmit | N | | AF4 | RTSS\_IO\_45 | RTSS\_BOOT\_CONFIG[3] | RTSS\_PX\_3 | PU:nppdkp | RTSS Boot configuration bit 3
| N | | AF2 | RTSS\_IO\_46 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | AF2 | RTSS\_IO\_46 | RTSS\_CAN4\_RX | RTSS\_PX\_3 | PD:nppukp | RTSS CAN 4 receive | Y | | AF2 | RTSS\_IO\_46 | RTSS\_CC\_GP4\_CLK\_MIRA | RTSS\_PX\_3 | PD:nppukp | RTSS Global general-purpose clock 4 A | Y | | AG5 | RTSS\_IO\_47 | | RTSS\_PX\_3 | PU:nppdkp | RTSS domain configurable I/O | N | | AG5 | RTSS\_IO\_47 | RTSS\_CAN5\_TX | RTSS\_PX\_3 | PU:nppdkp | RTSS CAN 5 transmit | N | | AG3 | RTSS\_IO\_48 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | AG3 | RTSS\_IO\_48 | RTSS\_CAN5\_RX | RTSS\_PX\_3 | PD:nppukp | RTSS CAN 5 receive | N | | AG3 | RTSS\_IO\_48 | RTSS\_EMAC0\_PTP\_PPS\_O\_1\_MIRA | RTSS\_PX\_3 | PD:nppukp | RTSS EMAC0 configurable PPS output 1 A | N | | AG3 | RTSS\_IO\_48 | RTSS\_EMAC0\_PTP\_AUX\_TS\_I\_0\_MIRA | RTSS\_PX\_3 | PD:nppukp | RTSS EMAC0 trigger 0 A for Auxiliary snapshot | N | | AG3 | RTSS\_IO\_48 | RTSS\_CC\_GP4\_CLK\_MIRB | RTSS\_PX\_3 | PD:nppukp | RTSS Global general-purpose clock 4 B | N | | AH4 | RTSS\_IO\_49 | | RTSS\_PX\_3 | PU:nppdkp | RTSS domain configurable I/O | N | | AH4 | RTSS\_IO\_49 | RTSS\_CAN6\_TX | RTSS\_PX\_3 | PU:nppdkp | RTSS CAN 6 transmit | N | | AH4 | RTSS\_IO\_49 | RTSS\_EMAC0\_PTP\_PPS\_O\_0\_MIRA | RTSS\_PX\_3 | PU:nppdkp | RTSS EMAC0 configurable PPS output 0 A | N | | AH2 | RTSS\_IO\_50 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | AH2 | RTSS\_IO\_50 | RTSS\_CAN6\_RX | RTSS\_PX\_3 | PD:nppukp | RTSS CAN 6 receive | N | | AH2 | RTSS\_IO\_50 | RTSS\_EMAC0\_PTP\_PPS\_O\_0\_MIRB | RTSS\_PX\_3 | PD:nppukp | RTSS EMAC0 configurable PPS output 0 B | N | | AH2 | RTSS\_IO\_50 | RTSS\_CC\_GP5\_CLK\_MIRA | RTSS\_PX\_3 | PD:nppukp | RTSS Global general-purpose clock 5 A | N | | AJ5 | RTSS\_IO\_51 | | RTSS\_PX\_3 | PU:nppdkp | RTSS domain configurable I/O | N | | AJ5 | RTSS\_IO\_51 | RTSS\_CAN7\_TX | RTSS\_PX\_3 | PU:nppdkp | RTSS CAN 7 transmit | N | | AJ5 | RTSS\_IO\_51 | RTSS\_EMAC0\_PTP\_PPS\_O\_1\_MIRB | RTSS\_PX\_3 | PU:nppdkp | RTSS EMAC0 configurable PPS output 1 B | N | | AJ3 | RTSS\_IO\_52 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | AJ3 | RTSS\_IO\_52 | RTSS\_CAN7\_RX | RTSS\_PX\_3 | PD:nppukp | RTSS CAN 7 receive | Y | | AJ3 | RTSS\_IO\_52 | RTSS\_CC\_GP5\_CLK\_MIRB | RTSS\_PX\_3 | PD:nppukp | RTSS Global general-purpose clock 5 B | Y | | AV4 | RTSS\_IO\_53 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | AJ1 | RTSS\_IO\_54 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | AK4 | RTSS\_IO\_55 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | AK4 | RTSS\_IO\_55 | RTSS\_EMAC0\_PTP\_PPS\_O\_2 | RTSS\_PX\_3 | PD:nppukp | RTSS EMAC0 configurable PPS output 2 | Y | | AK2 | RTSS\_IO\_56 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | AK2 | RTSS\_IO\_56 | RTSS\_EMAC0\_PTP\_AUX\_TS\_I\_0\_MIRB | RTSS\_PX\_3 | PD:nppukp | RTSS EMAC0 trigger 0 B for Auxiliary snapshot | Y | | AK2 | RTSS\_IO\_56 | RTSS\_EMAC0\_PTP\_PPS\_O\_3 | RTSS\_PX\_3 | PD:nppukp | RTSS EMAC0 configurable PPS output 3 | Y | | AT6 | RTSS\_IO\_57 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | AT6 | RTSS\_IO\_57 | RTSS\_EMAC0\_MCG\_PST\_TRIG\_LW[0] | RTSS\_PX\_3 | PD:nppukp | RTSS EMAC0 trigger input 0 for Media clock generation | Y | | AT4 | RTSS\_IO\_58 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | AT4 | RTSS\_IO\_58 | RTSS\_EMAC0\_MCG\_PST\_TRIG\_LW[1] | RTSS\_PX\_3 | PD:nppukp | RTSS EMAC0 trigger input 1 for Media clock generation | Y | | AU3 | RTSS\_IO\_59 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | AU3 | RTSS\_IO\_59 | RTSS\_EMAC0\_MCG\_PST\_TRIG\_LW[2] | RTSS\_PX\_3 | PD:nppukp | RTSS EMAC0 trigger input 2 for Media clock generation | Y | | AU3 | RTSS\_IO\_59 | RTSS\_CC\_GP1\_CLK\_MIRA | RTSS\_PX\_3 | PD:nppukp | RTSS Global general-purpose clock 1 A | Y | | AV2 | RTSS\_IO\_60 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | AV2 | RTSS\_IO\_60 | RTSS\_EMAC0\_MCG\_PST\_TRIG\_LW[3] | RTSS\_PX\_3 | PD:nppukp | RTSS EMAC0 trigger input 3 for Media clock generation | Y | | AV2 | RTSS\_IO\_60 | RTSS\_CC\_GP1\_CLK\_MIRB | RTSS\_PX\_3 | PD:nppukp | RTSS Global general-purpose clock 1 B | Y | | AU1 | RTSS\_IO\_61 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | AY8 | RTSS\_IO\_62 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | AW9 | RTSS\_IO\_63 | | RTSS\_PX\_3 | PD:nppukp | Configurable I/O | N | | AW9 | RTSS\_IO\_63 | PRTSS\_ERR\_N | RTSS\_PX\_3 | PD:nppukp | PMIC RTSS domain error signal active low (internally pulled up to 1.8 V).
Indicates PMIC error and resulting PMIC shutdown. | N | | AV10 | RTSS\_IO\_64 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | AW7 | RTSS\_IO\_65 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | Y | | AW7 | RTSS\_IO\_65 | RTSS\_PWR\_READY | RTSS\_PX\_3 | PD:nppukp | RTSS power ready | Y | | AV8 | RTSS\_IO\_66 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | AV8 | RTSS\_IO\_66 | RTSS\_SLP\_EN | RTSS\_PX\_3 | PD:nppukp | RTSS sleep enable | N | | J7 | RTSS\_IO\_67 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | J7 | RTSS\_IO\_67 | RTSS\_OSPI0\_CS\_N\_0 | RTSS\_PX\_3 | PD:nppukp | RTSS OSPI0 chip select 0 | N | | K6 | RTSS\_IO\_68 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | K6 | RTSS\_IO\_68 | RTSS\_OSPI0\_DQS | RTSS\_PX\_3 | PD:nppukp | RTSS OSPI0 differential data strobe | N | | K8 | RTSS\_IO\_69 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | K10 | RTSS\_IO\_70 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | K10 | RTSS\_IO\_70 | RTSS\_OSPI0\_CLK | RTSS\_PX\_3 | PD:nppukp | RTSS OSPI0 clock | N | | L7 | RTSS\_IO\_71 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | L7 | RTSS\_IO\_71 | RTSS\_OSPI0\_DATA[0] | RTSS\_PX\_3 | PD:nppukp | RTSS OSPI0 data 0 | N | | L9 | RTSS\_IO\_72 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | L9 | RTSS\_IO\_72 | RTSS\_OSPI0\_DATA[1] | RTSS\_PX\_3 | PD:nppukp | RTSS OSPI0 data 1 | N | | M6 | RTSS\_IO\_73 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | M6 | RTSS\_IO\_73 | RTSS\_OSPI0\_DATA[2] | RTSS\_PX\_3 | PD:nppukp | RTSS OSPI0 data 2 | N | | M8 | RTSS\_IO\_74 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | M8 | RTSS\_IO\_74 | RTSS\_OSPI0\_DATA[3] | RTSS\_PX\_3 | PD:nppukp | RTSS OSPI0 data 3 | N | | M10 | RTSS\_IO\_75 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | M10 | RTSS\_IO\_75 | RTSS\_OSPI0\_DATA[4] | RTSS\_PX\_3 | PD:nppukp | RTSS OSPI0 data 4 | N | | N7 | RTSS\_IO\_76 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | N7 | RTSS\_IO\_76 | RTSS\_OSPI0\_DATA[5] | RTSS\_PX\_3 | PD:nppukp | RTSS OSPI0 data 5 | N | | N9 | RTSS\_IO\_77 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | N9 | RTSS\_IO\_77 | RTSS\_OSPI0\_DATA[6] | RTSS\_PX\_3 | PD:nppukp | RTSS OSPI0 data 6 | N | | P10 | RTSS\_IO\_78 | | RTSS\_PX\_3 | PD:nppukp | RTSS domain configurable I/O | N | | P10 | RTSS\_IO\_78 | RTSS\_OSPI0\_DATA[7] | RTSS\_PX\_3 | PD:nppukp | RTSS OSPI0 data 7 | N | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ### MD\_LPASS pins | LPASS I/O | Alternate function | Functional description | | --- | --- | --- | | LPASS\_0 | | (GPIO\_126) | | LPASS\_0 | LPI\_QUA\_MI2S\_SCK | LPI quad I^2^S clock | | LPASS\_1 | | (GPIO\_127) | | LPASS\_1 | LPI\_QUA\_MI2S\_WS | LPI quad I^2^S word select | | LPASS\_2 | | (GPIO\_128) | | LPASS\_2 | LPI\_QUA\_MI2S\_DATA0 | LPI quad I^2^S serial channel 0 | | LPASS\_3 | | (GPIO\_129) | | LPASS\_3 | LPI\_QUA\_MI2S\_DATA1 | LPI quad I^2^S serial channel 1 | | LPASS\_4 | | (GPIO\_130) | | LPASS\_4 | LPI\_QUA\_MI2S\_DATA2 | LPI quad I^2^S serial channel 2 | | LPASS\_5 | | (GPIO\_131) | | LPASS\_5 | LPI\_QUA\_MI2S\_DATA3 | LPI quad I^2^S serial channel 3 | | LPASS\_5 | EXT\_MCLK1\_C | MI2S external MCLK1 C | | LPASS\_6 | | (GPIO\_132) | | LPASS\_6 | LPI\_I2S1\_CLK | LPI I2S 1 clock | | LPASS\_7 | | (GPIO\_133) | | LPASS\_7 | LPI\_I2S1\_WS | LPI I2S 1 word select | | LPASS\_8 | | (GPIO\_134) | | LPASS\_8 | LPI\_I2S1\_DATA0 | LPI I2S 1 serial channel 0 | | LPASS\_9 | | (GPIO\_135) | | LPASS\_9 | LPI\_I2S1\_DATA1 | LPI I2S 1 serial channel 1 | | LPASS\_9 | EXT\_MCLK1\_B | MI2S external MCLK1 B | | LPASS\_10 | | (GPIO\_136) | | LPASS\_10 | LPI\_I2S2\_CLK | LPI I2S 2 clock | | LPASS\_11 | | (GPIO\_137) | | LPASS\_11 | LPI\_I2S2\_WS | LPI I2S 2 word select | | LPASS\_12 | | (GPIO\_141) | | LPASS\_12 | LPI\_I2S4\_CLK | LPI I2S 4 clock | | LPASS\_13 | | (GPIO\_142) | | LPASS\_13 | LPI\_I2S4\_WS | LPI I2S 4 word select | | LPASS\_13 | EXT\_MCLK1\_A | MI2S external MCLK1 A | | LPASS\_14 | | (GPIO\_140) | | LPASS\_14 | EXT\_MCLK1\_D | MI2S external MCLK1 D | | LPASS\_15 | | (GPIO\_138) | | LPASS\_15 | LPI\_I2S2\_DATA0 | LPI I2S 2 serial channel 0 | | LPASS\_16 | | (GPIO\_139) | | LPASS\_16 | LPI\_I2S2\_DATA1 | LPI I2S 2 serial channel 1 | | LPASS\_17 | | (GPIO\_143) | | LPASS\_17 | LPI\_I2S4\_DATA0 | LPI I2S 4 serial channel 0 | | LPASS\_18 | | (GPIO\_144) | | LPASS\_18 | LPI\_I2S4\_DATA1 | LPI I2S 4 serial channel 1 | | LPASS\_19 | | (GPIO\_145) | | LPASS\_19 | LPI\_I2S3\_CLK | LPI I2S 3 clock | | LPASS\_20 | | (GPIO\_146) | | LPASS\_20 | LPI\_I2S3\_WS | LPI I2S 3 word select | | LPASS\_21 | | (GPIO\_147) | | LPASS\_21 | LPI\_I2S3\_DATA0 | LPI I2S 3 serial channel 0 | | LPASS\_22 | | (GPIO\_148) | | LPASS\_22 | LPI\_I2S3\_DATA1 | LPI I2S 3 serial channel 1 | | LPASS\_22 | EXT\_MCLK1\_E | MI2S external MCLK1 E | | | | | | | | | ### Power-supply pins | Pin number | Pin name | Functional description | | --- | --- | --- | | AA53, AA57, N49, N51, N55, N57, P58, R49, R57, R59, T48, U49, U57, U59, V48, W57, W59, Y58 | VDD\_APC0 | Power for the cluster 0 of Kryo Gold Prime processors | | AA37, AA41, AA43, M38, M42, M46, N37, N47, P38, P46, R37, R47, T38, V38, V44, W37, W45, Y38 | VDD\_APC1 | Power for the cluster 1 of Kryo Gold Prime processors | | U47 | VDD\_A\_APC\_CS\_1P2 | Power for application processor current sensor 1.2 V analog circuits | | AV50 | VDD\_A\_CSI\_0\_1P2 | Power for MIPI CSI0 1.2 V analog circuits | | AT50 | VDD\_A\_CSI\_0\_1\_0P9 | Power for MIPI CSI0/CSI1 0.9 V analog circuits | | AV52 | VDD\_A\_CSI\_1\_1P2 | Power for MIPI CSI1 1.2 V analog circuits | | AV54 | VDD\_A\_CSI\_2\_1P2 | Power for MIPI CSI2 1.2 V analog circuits | | AT54 | VDD\_A\_CSI\_2\_3\_0P9 | Power for MIPI CSI2/CSI3 0.9 V analog circuits | | AV56 | VDD\_A\_CSI\_3\_1P2 | Power for MIPI CSI3 1.2 V analog circuits | | AU45 | VDD\_A\_DSI\_0\_0P9 | Power for MIPI DSI0 0.9 V analog circuits | | AV46, AV48 | VDD\_A\_DSI\_0\_1\_1P2 | Power for MIPI DSI0/DSI1 1.2 V analog circuits | | AT46 | VDD\_A\_DSI\_0\_PLL\_0P9 | Power for MIPI DSI0 PLL 0.9 V | | AU49 | VDD\_A\_DSI\_1\_0P9 | Power for MIPI DSI1 0.9 V analog circuits | | AT48 | VDD\_A\_DSI\_1\_PLL\_0P9 | Power for MIPI DSI1 PLL 0.9 V | | M26, M28, M32, M34 | VDD\_A\_EBI\_01\_0P9 | Power for EBI0/EBI1 PHY 0.9 V circuits | | M52, M54, M58, M60, R63, U63, V60, W63 | VDD\_A\_EBI\_23\_45\_0P9 | Power for EBI2/EBI3/EBI4/EBI5 PHY 0.9 V circuits | | K24, K34, K50, K58, N65, V66 | VDD\_A\_EBI\_PLL | Power for EBI PHY PLL circuits | | AJ59 | VDD\_A\_EDP\_0\_0P9 | Power for EDP 0 0.9 V circuits | | AH64 | VDD\_A\_EDP\_0\_1P2 | Power for EDP 0 1.2 V circuits | | AK60 | VDD\_A\_EDP\_1\_0P9 | Power for EDP 1 0.9 V circuits | | AK64 | VDD\_A\_EDP\_1\_1P2 | Power for EDP 1 1.2 V circuits | | AK62 | VDD\_A\_EDP\_2\_0P9 | Power for EDP 2 0.9 V circuits | | AL63 | VDD\_A\_EDP\_2\_1P2 | Power for EDP 2 1.2 V circuits | | AM62 | VDD\_A\_EDP\_3\_0P9 | Power for EDP 3 0.9 V circuits | | AL61 | VDD\_A\_EDP\_3\_1P2 | Power for EDP 3 1.2 V circuits | | AK58 | VDD\_A\_NSP0\_CS\_1P2 | Power for HTP0 current sensor 1.2 V circuits | | V32 | VDD\_A\_NSP1\_CS\_1P2 | Power for HTP1 current sensor 1.2V circuits | | T18, T20, U21 | VDD\_A\_PCIE\_0\_0P9 | Power for PCIe 0 0.9 V circuits | | V20, V22, W21, W23 | VDD\_A\_PCIE\_1\_0P9 | Power for PCIe 1 0.9V circuits | | T16 | VDD\_A\_PCIE\_0\_PLL\_1P2 | Power for PCIe 0 PLL 1.2 V circuits | | U13 | VDD\_A\_PCIE\_1\_PLL\_1P2 | Power for PCIe 1 PLL 1.2 V circuits | | AC65 | VDD\_A\_REFGEN\_0P875 | Power for high-speed interface reference generation circuits – 0.875 V | | AD66 | VDD\_A\_REFGEN\_1P2 | Power for high-speed interface reference generation circuits – 1.2 V | | Y22 | VDD\_A\_SGMII\_0\_0P9 | Power for serial gigabit media-independent interface 0

0.9 V | | AA19 | VDD\_A\_SGMII\_0\_1P2 | Power for serial gigabit media-independent interface 0

1.2 V | | AA21 | VDD\_A\_SGMII\_1\_0P9 | Power for serial gigabit media-independent interface 1

0.9 V | | AB20 | VDD\_A\_SGMII\_1\_1P2 | Power for serial gigabit media-independent interface 1

1.2 V | | AH60, AF60 | VDD\_A\_UFS\_0\_0P9 | Power for the UFS 0.9 V analog circuits | | AG63, AG61 | VDD\_A\_UFS\_0\_1P2 | Power for the UFS 1.2 V analog circuits | | K36 | VDD\_A\_USBHS\_0\_0P9 | Power for USB high-speed 0 0.9 V circuits | | J37 | VDD\_A\_USBHS\_0\_1P8 | Power for USB high-speed 0 1.8 V circuits | | J39 | VDD\_A\_USBHS\_0\_3P1 | Power for USB high-speed 0 3.1 V circuits | | K40 | VDD\_A\_USBHS\_1\_0P9 | Power for USB high-speed 1 0.9 V circuits | | J41 | VDD\_A\_USBHS\_1\_1P8 | Power for USB high-speed 1 1.8 V circuits | | J43 | VDD\_A\_USBHS\_1\_3P1 | Power for USB high-speed 1 3.1 V circuits | | L45 | VDD\_A\_USBHS\_2\_0P9 | Power for USB high-speed 2 0.9 V circuits | | K46 | VDD\_A\_USBHS\_2\_1P8 | Power for USB high-speed 2 1.8 V circuits | | K48 | VDD\_A\_USBHS\_2\_3P1 | Power for USB high-speed 2 3.1 V circuits | | L39 | VDD\_A\_USBSS\_0\_0P9 | Power for USB super-speed 0 0.9 V circuits | | K38 | VDD\_A\_USBSS\_0\_1P2 | Power for USB super-speed 0 1.2 V circuits | | L43 | VDD\_A\_USBSS\_1\_0P9 | Power for USB super-speed 1 0.9 V circuits | | K42 | VDD\_A\_USBSS\_1\_1P2 | Power for USB super-speed 1 1.2 V circuits | | AA35, AB38, AB40, AB44, AB46, AC35, AD50, AD52, AE49, AG49, AJ49, AK50, T36, U35, V34, W35, Y36, Y46 | VDD\_CX | Power for digital core circuits | | AC55, AC59, AC63, AD54, AD56, AD58, AD60, AD64 | VDD\_CX\_LPI | Power for Low-power island digital core circuits | | AA61, L23, L25, L27, L31, L33, L35, L49, L51, L53, L57, L59, L61, N61, P62, T62, V62, Y62 | VDD\_D\_EBI | Power for EBI digital circuits | | AH24, AH26, AH30, AJ23, AJ25, AJ33, AK34, AL23, AL25, AM36, AN23, AN25, AN35, AP36, AR23, AR25, AR27, AR29, AR31, AR33, AR35, AT26, AT30, AT34, AU29, AU31, AU35, AV24, AV28, AV34 | VDD\_GFX | Power for graphics | | M22, M24, M30, M36 | VDD\_IO\_EBI\_01 | Power for EBI0/EBI1 I/O circuits | | AA63, M48, M50, M56, N59, R61, U61, W61 | VDD\_IO\_EBI\_23\_45 | Power for EBI2/EBI3/EBI4/EBI5 I/O circuits | | AE35, AF36, AG35, AG37, AH34, AH46, AJ41, AJ45, AK40, AK44, AL45, AM38, AN45, AP38, AR39, AR41, AR45, AR47, AT38, AT42, AU39, AU43, AV38, AV42 | VDD\_MM | Power for multimedia subsystem circuits | | AA51, AB48, AB50, AC47, AC51, AD46, AK46, AL47, AM46, W47, Y48 | VDD\_MX\_A | Power for always-ON memory circuits | | AA33, AB34, AC33, AD34, AE33, ,AF48, AG47, AH38, AH48, AJ37, AK36, AL37 | VDD\_MX\_C | Power for collapsible memory circuits | | AB54, AB56, AB58, AB60, AB64 | VDD\_MX\_LPI | Power for Low-power island memory circuit | | AE53, AE55, AE57, AF58, AG57, AJ51, AJ53, AJ57, AK54, AK56, AM48, AM58, AM60, AP48, AP58, AP60, AR49, AR51, AR55, AR57, AR61 | VDD\_NSP0 | Power for Hexagon Tensor Processor 0 | | AA25, AB24, AC25, AC29, N21, N25, N27, N31, N33, P22, P24, P34, T22, T24,
T34, V24, V28, V30, W25, W29, W31 | VDD\_NSP1 | Power for Hexagon Tensor Processor 1 | | AB68 | VDD\_PX0 | Power for pad group 0 | | K30, K54, T66, Y66 | VDD\_PX1 | Power for pad group 1 | | AG67 | VDD\_PX10 | Power for pad group 10 | | AE63, J35 | VDD\_PX11 | Power for pad group 11 | | AB66, AU21, AV32, AV58, AW45, J33 | VDD\_PX3 | Power for pad group 3 | | AB16 | VDD\_PX7 | Power for pad group 7 | | AF66 | VDD\_PX9 | Power for pad group 9 | | AV60, AA67 | VDD\_QFPROM | Power for programming the QFPROM | | AC21 | VDD\_QFPROM\_RTSS | Power for programming the QFPROM RTSS | | AE31, AF24, AF28, AF32, AG23, AG27, AG31, AH32 | VDD\_RTSS\_CX | Power for RTSS digital core circuits | | AD26, AD30, AE23, AE27, AE29 | VDD\_RTSS\_MX | Power for RTSS On-chip memory circuits | | AT20 | VDD\_RTSS\_PX0 | Power for RTSS pad group 0 | | AR19 | VDD\_RTSS\_PX11 | Power for RTSS pad group 11 | | AF18, AK20, AP20 | VDD\_RTSS\_PX3 | Power for RTSS pad group 3 | | AH20 | VDD\_RTSS\_PX8 | Power for RTSS pad group 8 | | AD20 | VBIAS\_RTSS\_RGMII | Power for RTSS\_RGMII reference circuits; 0.85 V | ### Ground pins | Pin number | Pin name | Functional description | | --- | --- | --- | | A9, A29, A47, A67, A75, A77, AA13, AA15,AA17, AA23, AA39, AA45, AA47, AA49, AA55, AA59, AA65, AA75, AA79, AB8, AB12, AB14,
AB18, AB22, AB36, AB42, AB52, AB62, AB70, AB72, AB76, AB78, AC1, AC5, AC11, AC13,
AC15, AC17, AC19, AC23, AC27, AC31, AC49, AC53, AC57, AC61, AC67, AC69, AC71, AC75,
AC79, AD8, AD12, AD14, AD16, AD18, AD22, AD24, AD28, AD32, AD36, AD48, AD62, AD68,
AD70, AD74, AD78, AE11, AE13, AE15, AE17, AE19, AE25, AE47, AE51, AE59, AE61, AE65,
AE67, AE69, AE71, AE75, AE79, AF8, AF10, AF12, AF14, AF16, AF22, AF26, AF30, AF34,
AF46, AF62, AF64, AF68, AF72, AF76, AF78, AG1, AG7, AG11, AG13, AG15, AG17, AG19,
AG25, AG29, AG33, AG59, AG65, AG69, AG73, AG79, AH6, AH12, AH14, AH16, AH18, AH28,
AH36, AJ55, AH58, AH62, AH66, AH68, AH70, AH76, AJ11, AJ13, AJ15, AJ17, AJ19, AJ21,
AJ35, AJ39, AJ43, AJ47, AJ61, AJ63, AJ65, AJ67, AJ69, AJ75, AJ79, AK8, AK12, AK14,
AK16, AK18, AK22, AK24, AK38, AK42, AK48, AK52, AK66, AK68, AK70, AK74, AL1, AL5,
AL11, AL13, AL15, AL17, AL19, AL21, AL35, AL39, AL59, AL65, AL67, AL69, AL79, AM12,
AM14, AM16, AM18, AM20, AM22, AM24, AM64, AM66, AM68, AM74, AN1, AN5, AN11, AN13,
AN15, AN17, AN19, AN21, AN37, AN39, AN47, AN59, AN61, AN63, AN65, AN67, AN69, AN79,
AP4, AP6, AP12, AP14, AP16, AP18, AP22, AP24, AP46, AP62, AP64, AP66, AP68, AP74, AR5,
AR11, AR13, AR15, AR17, AR37, AR43, AR53, AR59, AR65, AR67, AR69, AR79, AT10, AT12,
AT14, AT16, AT18, AT24, AT28, AT32, AT36, AT40, AT44, AT52, AT56, AT58, AT60, AT64,
AT66, AT68, AT74, AU7, AU9, AU11, AU13, AU17, AU19, AU27, AU33, AU37, AU41, AU47,
AU51, AU53, AU55, AU57, AU59, AU61, AU63, AU65, AU67, AU69, AV14, AV16, AV18, AV20,
AV22, AV26, AV30, AV36, AV40, AV44, AV62, AV64, AV66, AV68, AV74, AV78, AW13, AW15,
AW17, AW19, AW21, AW23, AW25, AW27, AW29, AW31, AW33, AW35, AW37, AW39, AW41, AW43,
AW47, AW49, AW51, AW53, AW55, AW57, AW59, AW61, AW63, AW65, AW67, AW69, AY6, AY42,
AY44, AY46, AY48, AY50, AY52, AY54, AY56, AY58, AY60, AY66, AY68, AY70, AY72, AY76,
AY78, B6, B12, B14, B18, B22, B24, B26, B32, B34, B36, B38, B40, B42, B44, B50, B52,
B54, B58, B62, B64, B70, B72, B76, BA1, BA41, BA43, BA49, BA51, BA53, BA55, BA65,
BA67, BA69, BA71, BA77, BB24, BB50, BB52, BB66, BB68, BC31, BC35, BC45, BC59, BC61,
BC63, BC77, BD6, BD14, BD22, BD28, BD42, BD44, BD46, BD48, BD54, BD60, BD62, BD64,
BE39, BE45, BE47, BE49, BE55, BE57, BE59, BE65, BE67, BE69, BF36, BF46, BF56, BF74,
BG5, BG11, BG17, BG23, BG31, BG41, BG51, BG61, BG75, C3, C9, C17, C27, C29, C47, C49,
C67, C75, C79, D6, D8, D12, D22, D24, D32, D34, D36, D38, D40, D42, D44, D52, D54,
D62, D64, D68, D70, D72, D76, D78, E3, E11, E17, E27, E29, E47, E49, E59, E65, E75,
E79, F4, F6, F8, F14, F22, F26, F32, F34, F36, F38, F40, F42, F44, F50, F54, F62, F68,
F70, F74, F78, G3, G11, G17, G23, G29, G35, G47, G53, G59, G65, G71, G75, G79, H2, H4,
H6, H8, H10, H14, H16, H18, H20, H22, H24, H26, H30, H32, H38, H40, H42, H44, H46,
H50, H54, H56, H58, H60, H62, H66, H68, H70, H74, H76, J9, J11, J13, J15, J17, J19,
J21, J23, J25, J27, J29, J31, J47, J55, J57, J59, J61, J63, J65, J67, J69, J73, J79,
K12, K16, K18, K20, K22, K26, K28, K32, K52, K56, K60, K62, K64, K68, K70, K76, L11,
L13, L15, L17, L19, L21, L29, L37, L41, L47, L55, L63, L65, L67, L73, L79, L81, M12,
M14, M16, M18, M20, M40, M44, M62, M64, M66, M68, M70, M74, M76, N11, N13, N15, N17,
N23, N29, N35, N53, N63, N67, N69, N73, N79,
P6, P12, P14, P16, P20, P36, P48, P60, P64, P66, P68, P70, P76, P78, R1, R11, R13,
R15, R17, R19, R21, R23, R35, R65, R67, R69, R73, R75, R79, T12, T14, T46, T58, T60,
T64, T68, T72, T76, U7, U11, U23, U37, U65, U67, U69, U75, U79, V6, V10, V12, V14,
V26, V36, V46, V58, V64, V68, V70, V72, V78, W1, W11,
W13, W27, W33, W49, W65, W67, W69, W75, W81, Y6, Y8, Y12, Y14, Y20, Y24, Y34, Y44,
Y60, Y64, Y68, Y70, Y72, Y78, | GND | Ground | ### DNC pins | Pin number | Pin name | Functional description | | --- | :---: | --- | | AR21, BB40, BA39, B78, C77, J53, J45, AE21, AG21, AH22, AU23, AT62, P18,
H28, H64, AA69, BA29, AA9, H34, H52, J49, AJ81, BB28, AY10, J51, K44, AU25, AR63, N19,
AF20, AT22, A1, A3, A79, A81, B2, B80, BE1, BE81, BF2, BF80, BG1, BG3, BG79, BG81, C1,
C81 | DNC | Do not connect; do not connect externally. | Last Published: Jan 30, 2026 [Previous Topic Introduction](https://docs.qualcomm.com/bundle/publicresource/80-73417-1/topics/introduction.md) [Next Topic Electrical specifications](https://docs.qualcomm.com/bundle/publicresource/80-73417-1/topics/electrical-specifications.md)