# Electrical specifications
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
This topic defines the device electrical performance specifications, including absolute
maximum ratings, operating conditions, and subsystem (such as memory and connectivity)
parameters, which are useful in deploying the device with optimal processing capabilities and
high efficiency.
## Absolute maximum ratings
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
The absolute maximum ratings shown in the following table reflect the
stress levels that, if exceeded, may cause permanent damage to the device. No functionality is
guaranteed outside the operating specifications. Functionality and reliability are only
guaranteed within the operating conditions described in [Operating conditions](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1).
| Parameter | Parameter | Min | Max | Unit |
| --- | --- | --- | --- | --- |
| ***Power-supply voltages*** | ***Power-supply voltages*** | ***Power-supply voltages*** | ***Power-supply voltages*** | ***Power-supply voltages*** |
| VDD\_APC0 | Power for the cluster 0 Kryo processors | -0.3 | 1.0648 | V |
| VDD\_APC1 | Power for the cluster 1 Kryo processors | -0.3 | 1.0648 | V |
| VDD\_A\_EBI\_0P9 | Power for EBI PHY 0.9 V circuits | -0.3 | 1.0472 | V |
| VDD\_A\_EBI\_PLL | Power for EBI PHY PLL circuits | -0.3 | 1.0472 | V |
| VDD\_CX | Power for digital core circuits | -0.3 | 1.0648 | V |
| VDD\_D\_EBI | Power for EBI digital circuits | -0.3 | 1.0648 | V |
| VDD\_CX\_LPI | Power for Low-power island digital core circuits | -0.3 | 0.9768 | V |
| VDD\_GFX | Power for graphics | -0.3 | 1.0648 | V |
| VDD\_MM | Power for multimedia subsystem circuits | -0.3 | 1.0648 | V |
| VDD\_MX\_A | Power for always-ON memory circuits | -0.3 | 0.979 | V |
| VDD\_MX\_C | Power for collapsible memory circuits | -0.3 | 0.979 | V |
| VDD\_MX\_LPI | Power for Low-power island memory circuit | -0.3 | 0.9768 | V |
| VDD\_NSP\_CX | Power for Hexagon Tensor Processor current sensor | -0.3 | 1.0648 | V |
| VDD\_NSP\_HMX | Power for Hexagon Tensor Processor HMX | -0.3 | 1.0648 | V |
| VDD\_RTSS\_CX | Power for RTSS core circuits | -0.3 | 0.979 | V |
| VDD\_RTSS\_MX | Power for RTSS on-chip memory circuits | -0.3 | 0.979 | V |
| VDD\_A\_CSI\_0\_0P9 | Power for MIPI CSI0 0.9 V analog circuits | -0.3 | 1.012 | V |
| VDD\_A\_CSI\_1\_0P9 | Power for MIPI CSI1 0.9 V analog circuits | -0.3 | 1.012 | V |
| VDD\_A\_DSI\_0\_0P9 | Power for MIPI DSI0 0.9 V analog circuits | -0.3 | 1.012 | V |
| VDD\_A\_DSI\_0\_PLL\_0P9 | Power for MIPI DSI0 PLL 0.9 V | -0.3 | 1.012 | V |
| VDD\_A\_EDP\_0\_CORE | Power for eDP 0 analog circuits | -0.3 | 1.012 | V |
| VDD\_A\_QREFS\_TX1\_0P9 | Reference voltage 0.875V | -0.3 | 1.012 | V |
| VDD\_A\_REFGEN\_0P875\_3 | Reference voltage 0.875V | -0.3 | 1.012 | V |
| VDD\_A\_SGMII\_0\_0P9 | Power for the first Ethernet interface | -0.3 | 1.012 | V |
| VDD\_A\_UFS\_0\_CORE | Power for UFS 0 core circuits | -0.3 | 1.012 | V |
| VDD\_A\_QREFS\_0P875\_0 | Reference voltage for QREFS 0 0.875 V circuits | -0.3 | 1.012 | V |
| VDD\_A\_QREFS\_0P875\_1 | Reference voltage for QREFS 1 0.875 V circuits | -0.3 | 1.012 | V |
| VDD\_A\_RSVD1\_0P9 | Power for reserved1 0.9 V rail | -0.3 | 1.012 | V |
| VDD\_A\_PCIE\_0\_CORE | Power for PCIE 0 core analog circuits | -0.3 | 1.045 | V |
| VDD\_A\_PCIE\_1\_CORE | Power for PCIE 1 core analog circuits | -0.3 | 1.045 | V |
| VDD\_A\_CSI\_0\_1P2 | Power for MIPI CSI0 1.2 V analog circuits | -0.3 | 1.375 | V |
| VDD\_A\_CSI\_1\_1P2 | Power for MIPI CSI1 1.2 V analog circuits | -0.3 | 1.375 | V |
| VDD\_A\_DSI\_0\_1P2 | Power for MIPI DSI0 1.2 V analog circuits | -0.3 | 1.375 | V |
| VDD\_A\_EDP\_0\_1P2 | Power for eDP 0 1.2 V analog circuits | -0.3 | 1.375 | V |
| VDD\_A\_PCIE\_0\_PLL\_1P2 | Power for PCIE 0 PLL 1.2 V analog circuits | -0.3 | 1.375 | V |
| VDD\_A\_PCIE\_1\_PLL\_1P2 | Power for PCIE 1 PLL 1.2 V analog circuits | -0.3 | 1.375 | V |
| VDD\_A\_QREFS\_1P2\_1 | Reference voltage for QREFS 1 1.2 V circuits | -0.3 | 1.375 | V |
| VDD\_A\_REFGEN\_1P2\_3 | Reference voltage 1.2 V | -0.3 | 1.375 | V |
| VDD\_A\_SGMII\_0\_1P2 | Power for the second Ethernet interface | -0.3 | 1.375 | V |
| VDD\_A\_UFS\_0\_1P2 | Power for the UFS 0 1.2 V analog circuits | -0.3 | 1.375 | V |
| VDD\_A\_USBSS\_0\_1P2 | Power for the USB SuperSpeed 0 1.2 V analog circuits | -0.3 | 1.375 | V |
| VDD\_A\_RSVD2\_1P2 | Power for reserved 2 1.2 V rail | -0.3 | 1.375 | V |
| VDD\_A\_RSVD5\_3P1 | Power for reserved 5 3.1 V rail | -0.3 | 3.993 | V |
| VDD\_A\_USBHS\_0\_3P1 | Power for the USB high-speed 0 3.1 V analog circuits | -0.3 | 3.993 | V |
| VDD\_A\_RSVD7\_1P8 | Power for reserved 7 1.8 V rail | -0.3 | 2.178 | V |
| VDD\_A\_USBHS\_0\_1P8 | Power for the USB high-speed 0 1.8 V analog circuits | -0.3 | 2.178 | V |
| VDD\_A\_USBHS\_0\_CORE | Power for the USB high-speed core circuits | -0.3 | 1.012 | V |
| VDD\_A\_USBSS\_0\_CORE | Power for the USB SuperSpeed 0 core circuits | -0.3 | 1.012 | V |
| VDD\_A\_RSVD6\_CORE | Power for reserved 6 Core rail | -0.3 | 1.012 | V |
| VDD\_IO\_EBI\_PHY | Power for EBI PHY circuits | -0.3 | 0.627 | V |
| VDD\_PX9 | Power for pad group 9 | -0.3 | 1.43 | V |
| VDD\_PX1 | Power for pad group 1 | -0.3 | 1.287 | V |
| VDD\_PX11 | Power for pad group 11 | -0.3 | 1.43 | V |
| VDD\_QFPROM | Power for QFPROM | -0.3 | 2.079 | V |
| VDD\_PX0 | Power for pad group 0 | -0.3 | 2.145 | V |
| VDD\_RTSS\_PX11 | Power for RTSS pad group 11 | -0.3 | 2.145 | V |
| VDD\_PX3 | Power for pad group 3 | -0.3 | 2.09 | V |
| VDD\_PX7 | Power for pad group 7 | -0.3 | 2.09 | V |
| VDD\_QFPROM\_RTSS | Power for RTSS QFPROM | -0.3 | 2.09 | V |
| VDD\_RTSS\_PX3 | Power for RTSS pad group 3 | -0.3 | 2.09 | V |
| VDD\_RTSS\_PX0 | Power for RTSS pad group 0 | -0.3 | 2.145 | |
| ***Thermal conditions*** | ***Thermal conditions*** | ***Thermal conditions*** | ***Thermal conditions*** | ***Thermal conditions*** |
| Ts | Storage temperature [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fntarg_1_absolute-maximum-ratings) | -55 | 150 | °C |
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[^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fnsrc_1_absolute-maximum-ratings) The storage temperature range applies when the device is
in the OFF state (the device is not assembled in any platform and is not
electrically connected to any voltage or I/O signals). Damage may occur when the
device is subjected to this temperature for any length of time.
## Operating conditions
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
Operating conditions include parameters such as power supply voltage, power distribution
impedances, and thermal conditions. The QCS8275 chipset meets all
performance specifications listed in the following table when used within the operating
conditions.
| Parameter | Parameter | Min | Max | Unit |
| --- | --- | --- | --- | --- |
| ***Power-supply voltages*** | ***Power-supply voltages*** | ***Power-supply voltages*** | ***Power-supply voltages*** | ***Power-supply voltages*** |
| VDD\_APC0 | Power for the Kryo application processor | 0.312 | 0.968 | V |
| VDD\_APC1 | Power for the Kryo application processor | 0.312 | 0.968 | V |
| VDD\_A\_EBI\_CCPLL\_0P9 | Power for EBI clock PLL 0.9 V circuits | 0.312 | 0.952 | V |
| VDD\_A\_EBI\_PHY | Power for EBI PHY circuits | 0.312 | 0.952 | V |
| VDD\_CX | Power for digital core circuits | 0.312 | 0.968 | V |
| VDD\_D\_EBI | Power for EBI digital circuits | 0.312 | 0.968 | V |
| VDD\_CX\_LPI | Power for LPI digital core circuits | 0.312 | 0.888 | V |
| VDD\_GFX | Power for graphics | 0.312 | 0.968 | V |
| VDD\_MM | Power for multimedia subsystem circuits | 0.312 | 0.968 | V |
| VDD\_MX\_A | Power for memory circuits | 0.504 | 0.888 | V |
| VDD\_MX\_C | Power for memory circuits | 0.504 | 0.888 | V |
| VDD\_MX\_LPI | Power for LPI memory circuit | 0.568 | 0.888 | V |
| VDD\_NSP\_CX | Power for Hexagon Tensor Processor current sensor | 0.312 | 0.968 | V |
| VDD\_NSP\_HMX | Power for Hexagon Tensor Processor HMX | 0.312 | 0.968 | V |
| VDD\_RTSS\_CX | Power for RTSS core circuits | 0.320 | 0.890 | V |
| VDD\_RTSS\_MX | Power for RTSS on-chip memory circuits | 0.560 | 0.890 | V |
| | | | | |
| Parameter[^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fntarg_1_operating-conditions) | Parameter[^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fntarg_1_operating-conditions) | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- | --- |
| ***Power-supply voltages*** | ***Power-supply voltages*** | ***Power-supply voltages*** | ***Power-supply voltages*** | ***Power-supply voltages*** | ***Power-supply voltages*** |
| VDD\_A\_CSI\_0\_0P9 | Power for MIPI CSI0 0.9 V analog circuits | – | 0.88 | – | V |
| VDD\_A\_CSI\_1\_0P9 | Power for MIPI CSI1 0.9 V analog circuits | – | 0.88 | – | V |
| VDD\_A\_DSI\_0\_0P9 | Power for MIPI DSI0 0.9 V analog circuits | – | 0.88 | – | V |
| VDD\_A\_DSI\_0\_PLL\_0P9 | Power for MIPI DSI0 PLL 0.9 V | – | 0.88 | – | V |
| VDD\_A\_EDP\_0\_CORE | Power for eDP 0 analog circuits | – | 0.88 | – | V |
| VDD\_A\_QREFS\_TX1\_0P9 | Reference voltage (0.875 V) | – | 0.88 | – | V |
| VDD\_A\_REFGEN\_0P875\_3 | Reference voltage (0.875 V) | – | 0.88 | – | V |
| VDD\_A\_SGMII\_0\_0P9 | Power for the first Ethernet interface | – | 0.88 | – | V |
| VDD\_A\_UFS\_0\_CORE | Power for UFS 0 core circuits | – | 0.88 | – | V |
| VDD\_A\_QREFS\_0P875\_0 | Reference voltage for QREFS 0 0.875 V circuits | – | 0.88 | – | V |
| VDD\_A\_QREFS\_0P875\_1 | Reference voltage for QREFS 1 0.875 V circuits | – | 0.88 | – | V |
| VDD\_A\_RSVD1\_0P9 | Power for reserved 1 0.9 V rail | – | 0.88 | – | V |
| VDD\_A\_PCIE\_0\_CORE | Power for PCIe 0 core analog circuits | – | 0.910 | – | V |
| VDD\_A\_PCIE\_1\_CORE | Power for PCIe 1 core analog circuits | – | 0.910 | – | V |
| VDD\_A\_CSI\_0\_1P2 | Power for MIPI CSI0 1.2 V analog circuits | – | 1.2 | – | V |
| VDD\_A\_CSI\_1\_1P2 | Power for MIPI CSI1 1.2 V analog circuits | – | 1.2 | – | V |
| VDD\_A\_DSI\_0\_1P2 | Power for MIPI DSI0 1.2 V analog circuits | – | 1.2 | – | V |
| VDD\_A\_EDP\_0\_1P2 | Power for eDP 0 1.2 V analog circuits | – | 1.2 | – | V |
| VDD\_A\_PCIE\_0\_PLL\_1P2 | Power for PCIe 0 PLL 1.2 V analog circuits | – | 1.2 | – | V |
| VDD\_A\_PCIE\_1\_PLL\_1P2 | Power for PCIe 1 PLL 1.2 V analog circuits | – | 1.2 | – | V |
| VDD\_A\_QREFS\_1P2\_1 | Reference voltage for QREFS 1 1.2 V circuits | – | 1.2 | – | V |
| VDD\_A\_REFGEN\_1P2\_3 | Reference voltage (1.2 V) | – | 1.2 | – | V |
| VDD\_A\_SGMII\_0\_1P2 | Power for the second Ethernet interface | – | 1.2 | – | V |
| VDD\_A\_UFS\_0\_1P2 | Power for the UFS 0 1.2 V analog circuits | – | 1.2 | – | V |
| VDD\_A\_USBSS\_0\_1P2 | Power for the USB SuperSpeed 0 1.2 V analog circuits | – | 1.2 | – | V |
| VDD\_A\_RSVD2\_1P2 | Power for reserved 2 1.2 V rail | – | 1.2 | – | V |
| VDD\_A\_RSVD5\_3P1 | Power for reserved 5 3.1 V rail | – | 3.070 | – | V |
| VDD\_A\_USBHS\_0\_3P1 | Power for the USB high-speed 0 3.1 V analog circuits | – | 3.070 | – | V |
| VDD\_A\_RSVD7\_1P8 | Power for reserved 7 1.8 V rail | – | 1.800 | – | V |
| VDD\_A\_USBHS\_0\_1P8 | Power for the USB high-speed 0 1.8 V analog circuits | – | 1.800 | – | V |
| VDD\_A\_USBHS\_0\_CORE | Power for the USB high-speed core circuits | – | 0.880 | – | V |
| VDD\_A\_USBSS\_0\_CORE | Power for the USB SuperSpeed 0 core circuits | – | 0.880 | – | V |
| VDD\_A\_RSVD6\_CORE | Power for reserved 6 core rail | – | 0.880 | – | V |
| VDD\_IO\_EBI\_PHY | Power for EBI PHY circuits | – | 0.500 | – | V |
| VDD\_PX0 | Power for pad group 0 | – | 1.800 | – | V |
| VDD\_PX1 | Power for pad group 1 | – | 1.100 | – | V |
| VDD\_PX11 | Power for pad group 11 | – | 1.200 | – | V |
| VDD\_PX3 | Power for pad group 3 | – | 1.800 | – | V |
| VDD\_PX7 | Power for pad group 7 | – | 1.800 | – | V |
| VDD\_PX9 | Power for pad group 9 | – | 1.200 | – | V |
| VDD\_QFPROM | Power for programming the QFPROM | – | 1.800 | – | V |
| VDD\_QFPROM\_RTSS | Power for programming the QFPROM; RTSS | – | 1.800 | – | V |
| VDD\_RTSS\_PX0 | Power for RTSS pad group 0 | – | 1.800 | – | V |
| VDD\_RTSS\_PX11 | Power for RTSS pad group 11 | – | 1.800 | – | V |
| VDD\_RTSS\_PX3 | Power for RTSS pad group 3 | – | 1.800 | – | V |
| ***Thermal conditions*** | ***Thermal conditions*** | ***Thermal conditions*** | ***Thermal conditions*** | ***Thermal conditions*** | ***Thermal conditions*** |
| T | Device operating temperature | T a = -40 | – | Tj = +125 | °C |
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[^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fnsrc_1_operating-conditions) Parts with voltages outside of the
specified ranges are not guaranteed to operate properly.
## Power distribution network
A detailed power delivery network specification is available in the [QCS8275 Chipset Power Delivery Network Specification
(80-73475-1P)](doc/80-73475-1P/80-73475-1P.xlsm) document.
## Average operating current
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
Detailed current consumption information and details about the operating modes tested are
available in *QCS8275 Current Consumption Data* (to be
released).
## Digital logic characteristics
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
A digital I/O’s performance specification depends on its pad type, its usage, and/or its
supply voltage.
- Some are dedicated for interconnections between the QCS8275 device and
other ICs within the QTI chipset; therefore, specifications are not required.
- Some are defined by existing standards, such as I^2^C and SPI. QTI devices comply
with those standards; therefore, additional specifications are not required.
- All other digital I/Os require performance specifications.
- Back powering protection is not supported in digital pads unless otherwise specified in
the following table. All non-bpp digital pads must be kept at less than 50 mV and with a
maximum of 1 µA current being injected into the pad to avoid potential back-power
scenarios.
Note: Unless otherwise specified, all device characterizations are carried
out across the specified operating temperature and voltage ranges.
Table : Digital I/Os specified in this section
| Pad voltage | Usage | Table |
| :---: | --- | :---: |
| 1.8 V | VDDPX\_0, VDD\_RTSS\_PX\_0, VDDPX\_3, VDD\_RTSS\_PX\_3 | [Table : DC specification of 1.8 V I/Os](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__table_1) |
| 1.2 V | VDDPX\_9/VDDPX\_10 | [Table : Digital I/O characteristics for UFS_RESET and UFS_REF_CLK (VDDPX_9/VDDPX_10)](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__table_4) |
Table : DC specification of 1.8 V I/Os
| Parameter | Description | Min | Max | Unit |
| :---: | --- | :---: | :---: | :---: |
| VIH | High-level input voltage, CMOS/Schmitt (HIHYS\_EN = low) | 0.65 × VDDPX\_x | VDDPX\_x [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__fn_xyv_tlt_hyb_sbannadi_08-01-23-1317-20-899) + 0.3 | V |
| VIL | Low-level input voltage, CMOS/Schmitt (HIHYS\_EN = low) | -0.3 | 0.35 × VDDPX\_x [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__fn_xyv_tlt_hyb_sbannadi_08-01-23-1317-20-899) | V |
| VIH | High-level input voltage, CMOS/Schmitt (HIHYS\_EN = high) | 0.7 × VDDPX\_x | VDDPX\_x [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__fn_xyv_tlt_hyb_sbannadi_08-01-23-1317-20-899) +
0.3 | V |
| VIL | Low-level input voltage, CMOS/Schmitt (HIHYS\_EN = high) | -0.3 | 0.3 × VDDPX\_x [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__fn_xyv_tlt_hyb_sbannadi_08-01-23-1317-20-899) | V |
| VSHYS | Schmitt hysteresis voltage (HIHYS\_EN= low) | 100 | – | mV |
| VSHYS | Schmitt hysteresis voltage (HIHYS\_EN = high) | 300 | – | mV |
| IIH | Input high leakage current [^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__fn_3) | – | 1.0 | µA |
| IIL | Input low leakage current [^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__fn_3) | -1.0 | – | µA |
| RPD | Pull-down resistance | 20k | 60k | Ω |
| RPU | Pull-up resistance | 20k | 60k | Ω |
| RKP | Bus keeper resistor | 20k | 60k | Ω |
| VOH | High-level output voltage, CMOS | VDDPX\_x [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__fn_xyv_tlt_hyb_sbannadi_08-01-23-1317-20-899) -
0.45 | VDDPX\_x [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__fn_xyv_tlt_hyb_sbannadi_08-01-23-1317-20-899) | V |
| VOL | Low-level output voltage, CMOS | 0.0 | 0.45 | V |
^1^ VDDPX\_x can
be VDDPX\_0, VDD\_RTSS\_PX\_0, VDDPX\_3, VDD\_RTSS\_PX\_3 depending on the pad
group.
^2^ IIH and IIL values
are based on nominal PVT (TT/25°C).
Note:
VOL and VOH are measured at IOL and IOH
respectively, with 16 mA current across min/max voltages and operating temperatures. For
more information regarding possible drive strength settings, see [Table : Possible drive strength settings](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__concept_hmf_cdb_nzb_table_j5b_vjs_fgc).
Table : Possible drive strength settings
| BIT configuration | Drive strength (mA) |
| :---: | :---: |
| 000 | 2 |
| 001 | 4 |
| 010 | 6 |
| 011 | 8 |
| 100 | 10 |
| 101 | 12 |
| 110 | 14 |
| 111 | 16 |
Table : Digital I/O characteristics for UFS_RESET and UFS_REF_CLK (VDDPX_9/VDDPX_10)
| Parameter | Description | Min | Max | Unit |
| :---: | --- | :---: | :---: | :---: |
| VOL | Low-level output voltage | 0 | 0.25 × VDDPX\_x | V |
| VOH | High-level output voltage | VDDPX\_x × 0.75 | VDDPX\_x | V |
| RPULL-UP | Pull-up resistance | 20 | – | kΩ |
| RPULL-DOWN | Pull-down resistance | 20 | – | kΩ |
| ILEAK | Standby leakage | -10 | 10 | µA |
Note:
VDDPX\_x can be either VDDPX\_9 or VDDPX\_10.
VOL and VOH are measured at IOL and IOH
respectively, with 4.8 mA current across min/max voltages and operating temperatures.
## Memory support
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
QCS8275 supports four channels up to 32 GB LPDDR5 memory (JESD209-5C)
with maximum speed at 3200 MHz.
## Multimedia
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
Multimedia parameters requiring performance specifications are addressed in this section.
### Camera interfaces
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
The QCS8275 device supports up to four D-PHY or C-PHY camera
interfaces.
Table : Supported MIPI-CSI standards and exceptions
| Applicable standard | Feature exceptions |
| --- | --- |
| MIPI Alliance Specification for CSI-2 v1.3 | RAW7 is not supported; DPCM predictor 2 is not supported. |
| MIPI Alliance Specification for D-PHY v1.2 | None |
| MIPI Alliance Specification for C-PHY v1.2 | None |
### Display support
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
The QCS8275 device supports one D-PHY or C-PHY display.
Table : Supported MIPI-DSI standards and exceptions
| Applicable standard | Feature exceptions |
| --- | --- |
| MIPI Alliance Specification for Display Serial Interface | None |
| MIPI Alliance Specification for D-PHY v1.2 | None |
| MIPI Alliance Specification for C-PHY v1.1 | None |
### DisplayPort (DP)
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
Table : Supported DisplayPort standards and exceptions
| Applicable standard | Feature exceptions |
| --- | --- |
| VESA DisplayPort v1.4 | None |
## Connectivity
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
The connectivity functions supported by the QCS8275 that require
electrical specifications include:
- USB host/slave support with built-in physical layer (PHY)
- Peripheral component interconnect express (PCIe) interfaces
- Universal flash storage (UFS)
- NOR flash storages (OSPI/QSPI)
- Reduced gigabit media independent interface (RGMII)
- High-speed serial gigabit media-independent interface (HSGMII)
- Through proper configuration of 20 main domain (MD) GPIO-based QUP SEs and 5 RTSS domain
RTSS\_IO-based QUP SEs:
- Universal asynchronous receiver/transmitter (UART) ports
- Inter-integrated circuit (I²C) interfaces
- Serial peripheral interface (SPI) ports
- Dedicated I²C interfaces for camera (CCI I²C)
Pertinent specifications for these functions are detailed in the following subsections.
Note: In addition to the following hardware
specifications, see the latest software release notes for software-based performance features
or limitations.
### USB interfaces
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
Table : Supported USB standards and exceptions
| Applicable standard | Feature exceptions |
| :---: | :---: |
| Universal Serial Bus Specification, Revision 3.1 (August 11, 2014 or
later) | None |
| UTMI specification version 1.05, released on 3/29/2001 | None |
| On-The-Go and Embedded Host Supplement to the USB 3.0 Specification (May 10,
2012, Revision 1.1 or later) | Attach detection protocol (ADP), role swap protocol (RSP), session request
protocol (SRP), and host negotiation protocol (HNP) |
| USB Serial Bus Specification, Revision 2.0 (April 27, 2000 or
later) | None |
### PCIe interface
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
| Applicable standard | Feature exceptions |
| --- | --- |
| PCI\_Express\_Base\_Specification\_Revision\_4.0 | Link configure capability |
| PCI\_Express\_Base\_Specification\_Revision\_4.0 | Lane margining at receiver |
| PCI\_Express\_Base\_Specification\_Revision\_4.0 | L0s link state |
| | |
| | |
### UFS interface
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
Table : Supported UFS standards and exceptions
| Applicable standard | Feature exceptions |
| --- | --- |
| Universal Flash Storage (UFS), Version 3.1 | – |
### SGMII interface
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
Table : Supported SGMII standards and exceptions
| Applicable standard | Feature exceptions |
| --- | --- |
| IEEE 802.3 | None |
### Octa-SPI/Quad-SPI interface
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
Figure : Octa-SPI/Quad-SPI SDR timing diagram
Table : Octa-SPI/Quad-SPI interface SDR timing
| Parameter | Comments | Min | Max | Unit |
| --- | --- | :---: | :---: | :---: |
| 1/T | OSPI/QSPI clock frequency | – | 90 | MHz |
| t(mis) | Master input setup time | 1.7 | – | ns |
| t(mih) | Master input hold time | 1.3 | – | ns |
| t(mod) | Master output delay | -2.00 | 2.00 | ns |
Figure : Octa-SPI DDR timing diagram
Table : Octa-SPI interface DDR timing
| Parameter | Comments | Min | Max | Unit |
| :---: | --- | :---: | :---: | :---: |
| 1/T | OSPI clock frequency | – | 166 | MHz |
| t(skew) | DQ to DQS skew | – | 530 | ps |
| t(mod) | Master output delay | -2.00 | 2.00 | ns |
Note: DDR is not supported on Quad-SPI operation.
### RGMII interface
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
Table : Supported RGMII standards and exceptions
| Applicable standard | Feature exceptions |
| --- | --- |
| Reduced Gigabit Media Independent Interface (RGMII) v1.3 and v2.0 | None |
### Audio support
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
The Audio-related interfaces supported with QCS8275 include:
- I²S: [I²S interfaces](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic.dita_3de50955-32a3-4168-a48e-1a6c300bf0c9)
- PCM/TDM: [PCM/TDM interfaces](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#concept_knr_3qc_nzb)
### I²S interfaces
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
Table : Supported I²S standards and exceptions
| Applicable standards | Feature exceptions |
| --- | :---: |
| *Philips I²S Bus Specifications* revised June 5, 1996 | None |
Figure : I²S timing diagram
| Parameter | Parameter | Comments[^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fntarg_1_i2s-interfaces) | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- | --- | --- |
| ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** |
| Frequency | Frequency | | – | – | 24.576 | MHz |
| T | Clock period | | 40.69 | – | – | ns |
| t(HC) | Clock high | | 0.45 × T | – | 0.55 × T | ns |
| t(LC) | Clock low | | 0.45 × T | – | 0.55 × T | ns |
| t(sr) | SD and WS input setup time | | 8.14 | – | – | ns |
| t(hr) | SD and WS input hold time | | 1.5 | – | – | ns |
| t(dtr) | SD and WS output delay | | – | – | 8.14 | ns |
| ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** |
| Frequency | Frequency | | – | – | 24.576 | MHz |
| T | Clock period | | 40.69 | – | – | ns |
| t(HC) | Clock high | | 0.45 × T | – | 0.55 × T | ns |
| t(LC) | Clock low | | 0.45 × T | – | 0.55 × T | ns |
| t(sr) | SD and WS input setup time | | 8.14 | – | – | ns |
| t(hr) | SD and WS input hold time | | 1.5 | – | – | ns |
| t(dtr) | SD and WS output delay | | – | – | 8.14 | ns |
[^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fnsrc_1_i2s-interfaces) Load capacitance is between 10 pF and
40 pF.
| Parameter | Parameter | Comments[^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fntarg_2_i2s-interfaces) | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- | --- | --- |
| ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** |
| | Frequency | | | – | 73.728 | MHz |
| T | Clock period | | 13.56 | – | – | ns |
| t(HC) | Clock high | | 0.45 × T | – | 0.55 × T | ns |
| t(LC) | Clock low | | 0.45 × T | – | 0.55 × T | ns |
| t(sr) | SD and WS input setup time | | 2.71 | – | – | ns |
| t(hr) | SD and WS input hold time | | 1.5 | – | – | ns |
[^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fnsrc_2_i2s-interfaces)
Load capacitance is between 10 pF and 40 pF.
| Parameter | Parameter | Comments[^3^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fntarg_3_i2s-interfaces) | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- | --- | --- |
| ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** |
| | Frequency | | | – | 24.576 | MHz |
| T | Clock period | | 40.69 | – | – | ns |
| t(HC) | Clock high | | 0.45 × T | – | 0.55 × T | ns |
| t(LC) | Clock low | | 0.45 × T | – | 0.55 × T | ns |
| t(dtr) | SD and WS output delay | | – | – | 8.14 | ns |
[^3^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fnsrc_3_i2s-interfaces)
Load capacitance is between 10 pF and 40 pF.
### PCM/TDM interfaces
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
Figure : PCM/TDM audio format with different sync modes
Figure : PCM/TDM timing diagram
| Parameter | Parameter | Comments | Min | Max | Unit |
| --- | --- | --- | --- | --- | --- |
| ***Master mode*** | ***Master mode*** | ***Master mode*** | ***Master mode*** | ***Master mode*** | ***Master mode*** |
| Frequency | Frequency | | – | 24.576 | MHz |
| T | Clock period | | 40.69 | – | ns |
| t(HC) | Clock high | | 0.45× T | 0.55× T | ns |
| t(LC) | Clock low | | 0.45× T | 0.55× T | ns |
| t(sr) | PCM/TDM\_DIN and PCM/TDM\_SYNC setup time | | 8.14 | – | ns |
| t(hr) | PCM/TDM\_DIN and PCM/TDM\_SYNC hold time | | 1.5 | – | ns |
| t(dtr) | PCM/TDM\_DOUT and PCM/TDM\_SYNC output delay | | – | 8.14 | ns |
| ***Slave mode*** | ***Slave mode*** | ***Slave mode*** | ***Slave mode*** | ***Slave mode*** | ***Slave mode*** |
| Frequency | Frequency | | – | 24.576 | MHz |
| T | Clock period | | 40.69 | – | ns |
| t(HC) | Clock high | | 0.45× T | 0.55× T | ns |
| t(LC) | Clock low | | 0.45× T | 0.55× T | ns |
| t(sr) | PCM/TDM\_DIN and PCM/TDM\_SYNC setup time | | 8.14 | – | ns |
| t(hr) | PCM/TDM\_DIN and PCM/TDM\_SYNC hold time | | 1.5 | – | ns |
| t(dtr) | PCM/TDM\_DOUT and PCM/TDM\_SYNC output delay | | – | 8.14 | ns |
^1^ Load
capacitance is between 10 pF to 40 pF.
| Parameter | Parameter | Comments[^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fntarg_2_pcm-tdm-interfaces) | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- | --- | --- |
| ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** |
| | Frequency | | | – | 73.728 | MHz |
| T | Clock period | | 13.56 | – | – | ns |
| t(HC) | Clock high | | 0.45 × T | – | 0.55 × T | ns |
| t(LC) | Clock low | | 0.45 × T | – | 0.55 × T | ns |
| t(sr) | PCM/TDM\_DIN and PCM/TDM\_SYNC setup time | | 2.71 | – | – | ns |
| t(hr) | PCM/TDM\_DIN and PCM/TDM\_SYNC hold time | | 1.5 | – | – | ns |
[^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fnsrc_2_pcm-tdm-interfaces)
Load capacitance is between 10 pF and 40 pF.
| Parameter | Parameter | Comments[^3^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fntarg_3_pcm-tdm-interfaces) | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- | --- | --- |
| ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** |
| | Frequency | | | – | 24.576 | MHz |
| T | Clock period | | 40.69 | – | – | ns |
| t(HC) | Clock high | | 0.45 × T | – | 0.55 × T | ns |
| t(LC) | Clock low | | 0.45 × T | – | 0.55 × T | ns |
| t(dtr) | PCM/TDM\_DOUT and PCM/TDM\_SYNC delay | | – | – | 8.14 | ns |
[^3^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fnsrc_3_pcm-tdm-interfaces)
Load capacitance is between 10 pF and 40 pF.
### I²C interface
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
Table : Supported I²C standards and exceptions
| Applicable standard | Feature exceptions |
| --- | --- |
| I²C Specification, version 3.0 | HS mode, slave mode, multi-master mode, and 10-bit addressing are not
supported. |
### Serial peripheral interface
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
The QCS8275 supports SPI as a master on 24 QUP ports. SPI slave mode is
supported on the eight QUP ports. See the [QCS8275 + PMM8620AU Pin Assignment
and GPIO Configuration Spreadsheet (80-73475-1A)](doc/80-73475-1A/80-73475-1A.xlsm) document for more
details.
Figure : SPI master timing diagram
Note: Depending on the mode configuration (Clock PHA and POL settings), Tx
and Rx sampling edge could differ. The timing diagram above is using mode 1 as an
example
Table : SPI master timing characteristics
| Parameter | Comments | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- | --- |
| T (SPI clock period) | 50 MHz maximum | 20 | – | – | ns |
| t(ch) | Clock high | 8 | – | – | ns |
| t(cl) | Clock low | 8 | – | – | ns |
| t(mov) | Master output valid | -5 | – | 5 | ns |
| t(mis) | Master input setup | 5 | – | – | ns |
| t(mih) | Master input hold | 1 | – | – | ns |
^1^ The minimum clock period includes
1% jitter of maximum frequency.
Figure : SPI slave timing diagram
Table : SPI slave timing characteristics
| Parameter | Comments | Min | Max | Unit |
| --- | --- | --- | --- | --- |
| T (SPI clock period) | 50 MHz maximum | 20.0 | – | ns |
| t(ch) | Clock high | 9 | – | ns |
| t(cl) | Clock low | 9 | – | ns |
| t(sov) | Slave output valid | 2 | 13 | ns |
| t(sis) | Slave input setup | 3 | – | ns |
| t(sih) | Slave input hold | 3 | – | ns |
| S\_TRI\_STATE\_EN [^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic.dita_a678a566-b007-4121-8b9b-f0bd624f07c5__fn_n4s_dk1_3yb_sbannadi_08-02-23-1211-10-42) | Slave tri-state enable | – | 14 | ns |
| S\_TRI\_STATE\_DIS [^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic.dita_a678a566-b007-4121-8b9b-f0bd624f07c5__fn_n4s_dk1_3yb_sbannadi_08-02-23-1211-10-42) | Slave tri-state disable | – | 14 | ns |
^2^ The
total capacitive load must not exceed 30 pF for a single slave system. For each
additional slave, 10 pF should be added to the clock and data lines (not needed for
chip select since it is one-to-one). For example, 40 pF for two slaves, although
most systems have only a single slave. Care must be taken to verify that every slave
can drive the data line fast enough to meet the timing requirement or the system
must use a reduced frequency.
Note: Only SPI slave mode 1 (PHA = 1 and POL = 0) is supported.
## Internal functions
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
Some internal functions require external interfaces to enable their operation. These include
modes and resets, and JTAG functions.
### Modes and resets
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
Mode and reset functions are basic digital I/Os that meet the performance
specifications presented in [Digital logic characteristics](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1).
### JTAG
Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html)
Figure : JTAG interface timing diagram
| Parameter | Parameter | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- | --- |
| t(tckcy) | TCK period | 50 | – | – | ns |
| t(tckh) | TCK pulse width high | 20 | – | – | ns |
| t(tckl) | TCK pulse width low | 20 | – | – | ns |
| t(sutms) | TMS input setup time | 5 | – | – | ns |
| t(htms) | TMS input hold time | 20 | – | – | ns |
| t(sutdi) | TDI input setup time | 5 | – | – | ns |
| t(htdi) | TDI input hold time | 20 | – | – | ns |
| t(do) | TDO data output delay | – | – | 15 | ns |
| t(tckcy) | TCK period | 50 | – | – | ns |
Last Published: Jan 08, 2026
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