# Electrical specifications Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) This topic defines the device electrical performance specifications, including absolute maximum ratings, operating conditions, and subsystem (such as memory and connectivity) parameters, which are useful in deploying the device with optimal processing capabilities and high efficiency. ## Absolute maximum ratings Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) The absolute maximum ratings shown in the following table reflect the stress levels that, if exceeded, may cause permanent damage to the device. No functionality is guaranteed outside the operating specifications. Functionality and reliability are only guaranteed within the operating conditions described in [Operating conditions](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1). | Parameter | Parameter | Min | Max | Unit | | --- | --- | --- | --- | --- | | ***Power-supply voltages*** | ***Power-supply voltages*** | ***Power-supply voltages*** | ***Power-supply voltages*** | ***Power-supply voltages*** | | VDD\_APC0 | Power for the cluster 0 Kryo processors | -0.3 | 1.0648 | V | | VDD\_APC1 | Power for the cluster 1 Kryo processors | -0.3 | 1.0648 | V | | VDD\_A\_EBI\_0P9 | Power for EBI PHY 0.9 V circuits | -0.3 | 1.0472 | V | | VDD\_A\_EBI\_PLL | Power for EBI PHY PLL circuits | -0.3 | 1.0472 | V | | VDD\_CX | Power for digital core circuits | -0.3 | 1.0648 | V | | VDD\_D\_EBI | Power for EBI digital circuits | -0.3 | 1.0648 | V | | VDD\_CX\_LPI | Power for Low-power island digital core circuits | -0.3 | 0.9768 | V | | VDD\_GFX | Power for graphics | -0.3 | 1.0648 | V | | VDD\_MM | Power for multimedia subsystem circuits | -0.3 | 1.0648 | V | | VDD\_MX\_A | Power for always-ON memory circuits | -0.3 | 0.979 | V | | VDD\_MX\_C | Power for collapsible memory circuits | -0.3 | 0.979 | V | | VDD\_MX\_LPI | Power for Low-power island memory circuit | -0.3 | 0.9768 | V | | VDD\_NSP\_CX | Power for Hexagon Tensor Processor current sensor | -0.3 | 1.0648 | V | | VDD\_NSP\_HMX | Power for Hexagon Tensor Processor HMX | -0.3 | 1.0648 | V | | VDD\_RTSS\_CX | Power for RTSS core circuits | -0.3 | 0.979 | V | | VDD\_RTSS\_MX | Power for RTSS on-chip memory circuits | -0.3 | 0.979 | V | | VDD\_A\_CSI\_0\_0P9 | Power for MIPI CSI0 0.9 V analog circuits | -0.3 | 1.012 | V | | VDD\_A\_CSI\_1\_0P9 | Power for MIPI CSI1 0.9 V analog circuits | -0.3 | 1.012 | V | | VDD\_A\_DSI\_0\_0P9 | Power for MIPI DSI0 0.9 V analog circuits | -0.3 | 1.012 | V | | VDD\_A\_DSI\_0\_PLL\_0P9 | Power for MIPI DSI0 PLL 0.9 V | -0.3 | 1.012 | V | | VDD\_A\_EDP\_0\_CORE | Power for eDP 0 analog circuits | -0.3 | 1.012 | V | | VDD\_A\_QREFS\_TX1\_0P9 | Reference voltage 0.875V | -0.3 | 1.012 | V | | VDD\_A\_REFGEN\_0P875\_3 | Reference voltage 0.875V | -0.3 | 1.012 | V | | VDD\_A\_SGMII\_0\_0P9 | Power for the first Ethernet interface | -0.3 | 1.012 | V | | VDD\_A\_UFS\_0\_CORE | Power for UFS 0 core circuits | -0.3 | 1.012 | V | | VDD\_A\_QREFS\_0P875\_0 | Reference voltage for QREFS 0 0.875 V circuits | -0.3 | 1.012 | V | | VDD\_A\_QREFS\_0P875\_1 | Reference voltage for QREFS 1 0.875 V circuits | -0.3 | 1.012 | V | | VDD\_A\_RSVD1\_0P9 | Power for reserved1 0.9 V rail | -0.3 | 1.012 | V | | VDD\_A\_PCIE\_0\_CORE | Power for PCIE 0 core analog circuits | -0.3 | 1.045 | V | | VDD\_A\_PCIE\_1\_CORE | Power for PCIE 1 core analog circuits | -0.3 | 1.045 | V | | VDD\_A\_CSI\_0\_1P2 | Power for MIPI CSI0 1.2 V analog circuits | -0.3 | 1.375 | V | | VDD\_A\_CSI\_1\_1P2 | Power for MIPI CSI1 1.2 V analog circuits | -0.3 | 1.375 | V | | VDD\_A\_DSI\_0\_1P2 | Power for MIPI DSI0 1.2 V analog circuits | -0.3 | 1.375 | V | | VDD\_A\_EDP\_0\_1P2 | Power for eDP 0 1.2 V analog circuits | -0.3 | 1.375 | V | | VDD\_A\_PCIE\_0\_PLL\_1P2 | Power for PCIE 0 PLL 1.2 V analog circuits | -0.3 | 1.375 | V | | VDD\_A\_PCIE\_1\_PLL\_1P2 | Power for PCIE 1 PLL 1.2 V analog circuits | -0.3 | 1.375 | V | | VDD\_A\_QREFS\_1P2\_1 | Reference voltage for QREFS 1 1.2 V circuits | -0.3 | 1.375 | V | | VDD\_A\_REFGEN\_1P2\_3 | Reference voltage 1.2 V | -0.3 | 1.375 | V | | VDD\_A\_SGMII\_0\_1P2 | Power for the second Ethernet interface | -0.3 | 1.375 | V | | VDD\_A\_UFS\_0\_1P2 | Power for the UFS 0 1.2 V analog circuits | -0.3 | 1.375 | V | | VDD\_A\_USBSS\_0\_1P2 | Power for the USB SuperSpeed 0 1.2 V analog circuits | -0.3 | 1.375 | V | | VDD\_A\_RSVD2\_1P2 | Power for reserved 2 1.2 V rail | -0.3 | 1.375 | V | | VDD\_A\_RSVD5\_3P1 | Power for reserved 5 3.1 V rail | -0.3 | 3.993 | V | | VDD\_A\_USBHS\_0\_3P1 | Power for the USB high-speed 0 3.1 V analog circuits | -0.3 | 3.993 | V | | VDD\_A\_RSVD7\_1P8 | Power for reserved 7 1.8 V rail | -0.3 | 2.178 | V | | VDD\_A\_USBHS\_0\_1P8 | Power for the USB high-speed 0 1.8 V analog circuits | -0.3 | 2.178 | V | | VDD\_A\_USBHS\_0\_CORE | Power for the USB high-speed core circuits | -0.3 | 1.012 | V | | VDD\_A\_USBSS\_0\_CORE | Power for the USB SuperSpeed 0 core circuits | -0.3 | 1.012 | V | | VDD\_A\_RSVD6\_CORE | Power for reserved 6 Core rail | -0.3 | 1.012 | V | | VDD\_IO\_EBI\_PHY | Power for EBI PHY circuits | -0.3 | 0.627 | V | | VDD\_PX9 | Power for pad group 9 | -0.3 | 1.43 | V | | VDD\_PX1 | Power for pad group 1 | -0.3 | 1.287 | V | | VDD\_PX11 | Power for pad group 11 | -0.3 | 1.43 | V | | VDD\_QFPROM | Power for QFPROM | -0.3 | 2.079 | V | | VDD\_PX0 | Power for pad group 0 | -0.3 | 2.145 | V | | VDD\_RTSS\_PX11 | Power for RTSS pad group 11 | -0.3 | 2.145 | V | | VDD\_PX3 | Power for pad group 3 | -0.3 | 2.09 | V | | VDD\_PX7 | Power for pad group 7 | -0.3 | 2.09 | V | | VDD\_QFPROM\_RTSS | Power for RTSS QFPROM | -0.3 | 2.09 | V | | VDD\_RTSS\_PX3 | Power for RTSS pad group 3 | -0.3 | 2.09 | V | | VDD\_RTSS\_PX0 | Power for RTSS pad group 0 | -0.3 | 2.145 | | | ***Thermal conditions*** | ***Thermal conditions*** | ***Thermal conditions*** | ***Thermal conditions*** | ***Thermal conditions*** | | Ts | Storage temperature [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fntarg_1_absolute-maximum-ratings) | -55 | 150 | °C | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fnsrc_1_absolute-maximum-ratings) The storage temperature range applies when the device is in the OFF state (the device is not assembled in any platform and is not electrically connected to any voltage or I/O signals). Damage may occur when the device is subjected to this temperature for any length of time. ## Operating conditions Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) Operating conditions include parameters such as power supply voltage, power distribution impedances, and thermal conditions. The QCS8275 chipset meets all performance specifications listed in the following table when used within the operating conditions. | Parameter | Parameter | Min | Max | Unit | | --- | --- | --- | --- | --- | | ***Power-supply voltages*** | ***Power-supply voltages*** | ***Power-supply voltages*** | ***Power-supply voltages*** | ***Power-supply voltages*** | | VDD\_APC0 | Power for the Kryo application processor | 0.312 | 0.968 | V | | VDD\_APC1 | Power for the Kryo application processor | 0.312 | 0.968 | V | | VDD\_A\_EBI\_CCPLL\_0P9 | Power for EBI clock PLL 0.9 V circuits | 0.312 | 0.952 | V | | VDD\_A\_EBI\_PHY | Power for EBI PHY circuits | 0.312 | 0.952 | V | | VDD\_CX | Power for digital core circuits | 0.312 | 0.968 | V | | VDD\_D\_EBI | Power for EBI digital circuits | 0.312 | 0.968 | V | | VDD\_CX\_LPI | Power for LPI digital core circuits | 0.312 | 0.888 | V | | VDD\_GFX | Power for graphics | 0.312 | 0.968 | V | | VDD\_MM | Power for multimedia subsystem circuits | 0.312 | 0.968 | V | | VDD\_MX\_A | Power for memory circuits | 0.504 | 0.888 | V | | VDD\_MX\_C | Power for memory circuits | 0.504 | 0.888 | V | | VDD\_MX\_LPI | Power for LPI memory circuit | 0.568 | 0.888 | V | | VDD\_NSP\_CX | Power for Hexagon Tensor Processor current sensor | 0.312 | 0.968 | V | | VDD\_NSP\_HMX | Power for Hexagon Tensor Processor HMX | 0.312 | 0.968 | V | | VDD\_RTSS\_CX | Power for RTSS core circuits | 0.320 | 0.890 | V | | VDD\_RTSS\_MX | Power for RTSS on-chip memory circuits | 0.560 | 0.890 | V | | | | | | | | Parameter[^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fntarg_1_operating-conditions) | Parameter[^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fntarg_1_operating-conditions) | Min | Typ | Max | Unit | | --- | --- | --- | --- | --- | --- | | ***Power-supply voltages*** | ***Power-supply voltages*** | ***Power-supply voltages*** | ***Power-supply voltages*** | ***Power-supply voltages*** | ***Power-supply voltages*** | | VDD\_A\_CSI\_0\_0P9 | Power for MIPI CSI0 0.9 V analog circuits | 0.83 | 0.88 | 0.92 | V | | VDD\_A\_CSI\_1\_0P9 | Power for MIPI CSI1 0.9 V analog circuits | 0.83 | 0.88 | 0.92 | V | | VDD\_A\_DSI\_0\_0P9 | Power for MIPI DSI0 0.9 V analog circuits | 0.83 | 0.88 | 0.92 | V | | VDD\_A\_DSI\_0\_PLL\_0P9 | Power for MIPI DSI0 PLL 0.9 V | 0.83 | 0.88 | 0.92 | V | | VDD\_A\_EDP\_0\_CORE | Power for eDP 0 analog circuits | 0.83 | 0.88 | 0.92 | V | | VDD\_A\_QREFS\_TX1\_0P9 | Reference voltage (0.875 V) | 0.83 | 0.88 | 0.92 | V | | VDD\_A\_REFGEN\_0P875\_3 | Reference voltage (0.875 V) | 0.83 | 0.88 | 0.92 | V | | VDD\_A\_SGMII\_0\_0P9 | Power for the first Ethernet interface | 0.83 | 0.88 | 0.92 | V | | VDD\_A\_UFS\_0\_CORE | Power for UFS 0 core circuits | 0.83 | 0.88 | 0.92 | V | | VDD\_A\_QREFS\_0P875\_0 | Reference voltage for QREFS0 0.875 V circuits | 0.83 | 0.88 | 0.92 | V | | VDD\_A\_QREFS\_0P875\_1 | Reference voltage for QREFS1 0.875 V circuits | 0.83 | 0.88 | 0.92 | V | | VDD\_A\_RSVD1\_0P9 | Power for reserved 1 0.9 V rail | 0.83 | 0.88 | 0.92 | V | | VDD\_A\_PCIE\_0\_CORE | Power for PCIe 0 core analog circuits | 0.88 | 0.910 | 0.96 | V | | VDD\_A\_PCIE\_1\_CORE | Power for PCIe 1 core analog circuits | 0.88 | 0.910 | 0.96 | V | | VDD\_A\_CSI\_0\_1P2 | Power for MIPI CSI0 1.2 V analog circuits | 1.15 | 1.2 | 1.25 | V | | VDD\_A\_CSI\_1\_1P2 | Power for MIPI CSI1 1.2 V analog circuits | 1.15 | 1.2 | 1.25 | V | | VDD\_A\_DSI\_0\_1P2 | Power for MIPI DSI0 1.2 V analog circuits | 1.15 | 1.2 | 1.25 | V | | VDD\_A\_EDP\_0\_1P2 | Power for eDP 0 1.2 V analog circuits | 1.15 | 1.2 | 1.25 | V | | VDD\_A\_PCIE\_0\_PLL\_1P2 | Power for PCIe 0 PLL 1.2 V analog circuits | 1.15 | 1.2 | 1.25 | V | | VDD\_A\_PCIE\_1\_PLL\_1P2 | Power for PCIe 1 PLL 1.2 V analog circuits | 1.15 | 1.2 | 1.25 | V | | VDD\_A\_QREFS\_1P2\_1 | Reference voltage for QREFS 1 1.2 V circuits | 1.15 | 1.2 | 1.25 | V | | VDD\_A\_REFGEN\_1P2\_3 | Reference voltage (1.2 V) | 1.15 | 1.2 | 1.25 | V | | VDD\_A\_SGMII\_0\_1P2 | Power for the second Ethernet interface | 1.15 | 1.2 | 1.25 | V | | VDD\_A\_UFS\_0\_1P2 | Power for the UFS 0 1.2 V analog circuits | 1.15 | 1.2 | 1.25 | V | | VDD\_A\_USBSS\_0\_1P2 | Power for the USB SuperSpeed 0 1.2 V analog circuits | 1.15 | 1.2 | 1.25 | V | | VDD\_A\_RSVD2\_1P2 | Power for reserved 2 1.2 V rail | 1.15 | 1.2 | 1.25 | V | | VDD\_A\_RSVD5\_3P1 | Power for reserved 5 3.1 V rail | 2.97 | 3.070 | 3.63 | V | | VDD\_A\_USBHS\_0\_3P1 | Power for the USB high-speed 0 3.1 V analog circuits | 2.97 | 3.070 | 3.63 | V | | VDD\_A\_RSVD7\_1P8 | Power for reserved 7 1.8 V rail | 1.62 | 1.800 | 1.98 | V | | VDD\_A\_USBHS\_0\_1P8 | Power for the USB high-speed 0 1.8 V analog circuits | 1.62 | 1.800 | 1.98 | V | | VDD\_A\_USBHS\_0\_CORE | Power for the USB high-speed core circuits | 0.83 | 0.880 | 0.92 | V | | VDD\_A\_USBSS\_0\_CORE | Power for the USB SuperSpeed 0 core circuits | 0.83 | 0.880 | 0.92 | V | | VDD\_A\_RSVD6\_CORE | Power for reserved 6 core rail | 0.83 | 0.880 | 0.92 | V | | VDD\_IO\_EBI\_PHY | Power for EBI PHY circuits | 0.27 | 0.500 | 0.57 | V | | VDD\_PX0 | Power for pad group 0 | 1.65 | 1.800 | 1.95 | V | | VDD\_PX1 | Power for pad group 1 | 1.01 | 1.100 | TBD | V | | VDD\_PX11 | Power for pad group 11 | 1.10 | 1.200 | 1.3 | V | | VDD\_PX3 | Power for pad group 3 | 1.7 | 1.800 | 1.9 | V | | VDD\_PX7 | Power for pad group 7 | 1.7 | 1.800 | 1.9 | V | | VDD\_PX9 | Power for pad group 9 | 1.1 | 1.200 | 1.3 | V | | VDD\_QFPROM | Power for programming the QFPROM | 1.71 | 1.800 | 1.89 | V | | VDD\_QFPROM\_RTSS | Power for programming the QFPROM; RTSS | 1.7 | 1.800 | 1.9 | V | | VDD\_RTSS\_PX0 | Power for RTSS pad group 0 | 1.65 | 1.800 | 1.95 | V | | VDD\_RTSS\_PX11 | Power for RTSS pad group 11 | 1.65 | 1.800 | 1.95 | V | | VDD\_RTSS\_PX3 | Power for RTSS pad group 3 | 1.7 | 1.800 | 1.9 | V | | VDD\_RTSS\_PX8 | Power for RTSS pad group 8 | 1.7 | 1.800 | 1.9 | V | | ***Thermal conditions*** | ***Thermal conditions*** | ***Thermal conditions*** | ***Thermal conditions*** | ***Thermal conditions*** | ***Thermal conditions*** | | T | Device operating temperature | T a = -40 | – | Tj = +125 | °C | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fnsrc_1_operating-conditions) Parts with voltages outside of the specified ranges are not guaranteed to operate properly. ## Power distribution network A detailed power delivery network specification is available in the [QCS8275 Chipset Power Delivery Network Specification (80-73475-1P)](doc/80-73475-1P/80-73475-1P.xlsm) document. ## Average operating current Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) Detailed current consumption information and details about the operating modes tested are available in *QCS8275 Current Consumption Data* (to be released). ## Digital logic characteristics Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) A digital I/O’s performance specification depends on its pad type, its usage, and/or its supply voltage. - Some are dedicated for interconnections between the QCS8275 device and other ICs within the QTI chipset; therefore, specifications are not required. - Some are defined by existing standards, such as I^2^C and SPI. QTI devices comply with those standards; therefore, additional specifications are not required. - All other digital I/Os require performance specifications. - Back powering protection is not supported in digital pads unless otherwise specified in the following table. All non-bpp digital pads must be kept at less than 50 mV and with a maximum of 1 µA current being injected into the pad to avoid potential back-power scenarios. Note: Unless otherwise specified, all device characterizations are carried out across the specified operating temperature and voltage ranges. Table : Digital I/Os specified in this section | Pad voltage | Usage | Table | | :---: | --- | :---: | | 1.8 V | VDDPX\_0, VDD\_RTSS\_PX\_0, VDDPX\_3, VDD\_RTSS\_PX\_3 | [Table : DC specification of 1.8 V I/Os](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__table_1) | | 1.8 V | VDD\_RTSS\_PX\_RGMII | [Table : DC specifications for RGMII 1.8 V mode (VDD_RTSS_PX_RGMII)](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__table_wgf_hmb_nzb_radhikav_11-21-23-1151-55-742) | | 1.2 V | VDDPX\_9/VDDPX\_10 | [Table : Digital I/O characteristics for UFS_RESET and UFS_REF_CLK (VDDPX_9/VDDPX_10)](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__table_4) | Table : DC specification of 1.8 V I/Os | Parameter | Description | Min | Max | Unit | | :---: | --- | :---: | :---: | :---: | | VIH | High-level input voltage, CMOS/Schmitt (HIHYS\_EN = low) | 0.65 × VDDPX\_x | VDDPX\_x [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__fn_xyv_tlt_hyb_sbannadi_08-01-23-1317-20-899) + 0.3 | V | | VIL | Low-level input voltage, CMOS/Schmitt (HIHYS\_EN = low) | -0.3 | 0.35 × VDDPX\_x [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__fn_xyv_tlt_hyb_sbannadi_08-01-23-1317-20-899) | V | | VIH | High-level input voltage, CMOS/Schmitt (HIHYS\_EN = high) | 0.7 × VDDPX\_x | VDDPX\_x [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__fn_xyv_tlt_hyb_sbannadi_08-01-23-1317-20-899) +
0.3 | V | | VIL | Low-level input voltage, CMOS/Schmitt (HIHYS\_EN = high) | -0.3 | 0.3 × VDDPX\_x [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__fn_xyv_tlt_hyb_sbannadi_08-01-23-1317-20-899) | V | | VSHYS | Schmitt hysteresis voltage (HIHYS\_EN= low) | 100 | – | mV | | VSHYS | Schmitt hysteresis voltage (HIHYS\_EN = high) | 300 | – | mV | | IIH | Input high leakage current [^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__fn_3) | – | 1.0 | µA | | IIL | Input low leakage current [^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__fn_3) | -1.0 | – | µA | | RPD | Pull-down resistance | 20k | 60k | Ω | | RPU | Pull-up resistance | 20k | 60k | Ω | | RKP | Bus keeper resistor | 20k | 60k | Ω | | VOH | High-level output voltage, CMOS | VDDPX\_x [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__fn_xyv_tlt_hyb_sbannadi_08-01-23-1317-20-899) -
0.45 | VDDPX\_x [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__fn_xyv_tlt_hyb_sbannadi_08-01-23-1317-20-899) | V | | VOL | Low-level output voltage, CMOS | 0.0 | 0.45 | V | ^1^ VDDPX\_x can be VDDPX\_0, VDD\_RTSS\_PX\_0, VDDPX\_3, VDD\_RTSS\_PX\_3 depending on the pad group. ^2^ IIH and IIL values are based on nominal PVT (TT/25°C). Note: VOL and VOH are measured at IOL and IOH respectively, with 16 mA current across min/max voltages and operating temperatures. For more information regarding possible drive strength settings, see [Table : Possible drive strength settings](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__concept_hmf_cdb_nzb_table_j5b_vjs_fgc). Table : Possible drive strength settings | BIT configuration | Drive strength (mA) | | :---: | :---: | | 000 | 2 | | 001 | 4 | | 010 | 6 | | 011 | 8 | | 100 | 10 | | 101 | 12 | | 110 | 14 | | 111 | 16 | Table : DC specifications for RGMII 1.8 V mode (VDD_RTSS_PX_RGMII) | Parameter | Description | Min | Max | Unit | | :---: | --- | :---: | :---: | :---: | | VOL | Low-level output voltage [^3^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__fn_bk5_mps_fgc) | – | 0.45 | V | | VOH | High-level output voltage [^3^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__fn_bk5_mps_fgc) | VDDPX\_x - 0.45 | – | V | | VIL | Low-level input voltage | -0.3 | 0.35× VDDPX\_x | V | | VIH | High-level input voltage | 0.65× VDDPX\_x | VDDPX\_x+ 0.3 | V | | VHYS | Input Hysteresis | 100 | – | mV | | RPULL-UP | Pull-up resistance | 20 | 50 | kΩ | | RPULL-DOWN | Pull-down resistance | 20 | 50 | kΩ | | RKEEPERUP | Keeper-up resistance | 20 | 50 | kΩ | | RKEEPERDOWN | Keeper-down resistance | 20 | 50 | kΩ | | IIL | Input low leakage current | – | 5 | μA | | IIH | Input high leakage current | -5 | – | μA | ^3^ VOL and VOH are measured at IOL and IOH respectively, with 12 mA current across min and max voltages and operating temperatures. For more information regarding possible drive strength settings, see [Table : Possible drive strength settings](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__concept_hmf_cdb_nzb_table_j5b_vjs_fgc) Table : Possible drive strength | Drive strength | IOL (mA) | IOH (mA) | | :---: | :---: | :---: | | 000 | 1.5 | 1.5 | | 001 | 3.0 | 3.0 | | 010 | 4.5 | 4.5 | | 011 | 6.0 | 6.0 | | 100 | 7.5 | 7.5 | | 101 | 9.0 | 9.0 | | 110 | 10.5 | 10.5 | | 111 | 12.0 | 12.0 | Note: There is no industry-standard specification for a 1.8 V RGMII interface. Therefore, these specifications are based on JESD8‑7A: *“1.8 V ± 0.15 V (normal range) and 1.2 V to 1.95 V (wide range) power supply voltage and interface standard for nonterminated digital integrated circuits.”* Table : Digital I/O characteristics for UFS_RESET and UFS_REF_CLK (VDDPX_9/VDDPX_10) | Parameter | Description | Min | Max | Unit | | :---: | --- | :---: | :---: | :---: | | VOL | Low-level output voltage | 0 | 0.25 × VDDPX\_x | V | | VOH | High-level output voltage | VDDPX\_x × 0.75 | VDDPX\_x | V | | RPULL-UP | Pull-up resistance | 20 | – | kΩ | | RPULL-DOWN | Pull-down resistance | 20 | – | kΩ | | ILEAK | Standby leakage | -10 | 10 | µA | Note: VDDPX\_x can be either VDDPX\_9 or VDDPX\_10. VOL and VOH are measured at IOL and IOH respectively, with 4.8 mA current across min/max voltages and operating temperatures. ## Memory support Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) QCS8275 supports four channels up to 32 GB LPDDR5 memory (JESD209-5C) with maximum speed at 3200 MHz. ## Multimedia Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) Multimedia parameters requiring performance specifications are addressed in this section. ### Camera interfaces Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) The QCS8275 device supports up to four D-PHY or C-PHY camera interfaces. Table : Supported MIPI-CSI standards and exceptions | Applicable standard | Feature exceptions | | --- | --- | | MIPI Alliance Specification for CSI-2 v1.3 | RAW7 is not supported; DPCM predictor 2 is not supported. | | MIPI Alliance Specification for D-PHY v1.2 | None | | MIPI Alliance Specification for C-PHY v1.2 | None | The following tables summarize the electrical and timing characteristics for CSI C‑PHY and D‑PHY interfaces at the SoC pin level. Table : CSI C‑PHY electrical characteristics | Parameter | Condition | Min | Typ | Max | Unit | | --- | :---: | :---: | :---: | :---: | :---: | | Symbol rate per trio | – | – | 4.5 | – | Gsym/s per trio | | Equivalent data rate | Per trio | – | 10.26 | – | Gb/s | | Supported trios | – | 1 | – | 3 | trios | | Single-ended signal swing | HS mode | TBD | 450 | 535 | mVpp | | Common-mode voltage | HS mode | 95 | 225 | 390 | mV | | Intra-trio skew | HS mode | – | – | 5 | ps | | Inter-trio skew | HS mode | – | – | 30 | ps | | HS jitter (total) | at max rate | – | – | 0.55 | UI | | LP input low (VIL) | LP mode | – | – | 550 | mV | | LP input high (VIH) | LP mode | 740 | – | – | mV | Table : CSI D‑PHY electrical characteristics | Parameter | Condition | Min | Typ | Max | Unit | | --- | :---: | :---: | :---: | :---: | :---: | | Data rate per lane | HS mode | – | 2.5 | – | Gb/s | | Supported data lanes | – | 1 | – | 4 | lanes | | HS differential swing | HS mode | 140 | 200 | 270 | mVpp | | HS common-mode voltage | HS mode | 70 | – | 330 | mV | | Receiver sensitivity | HS mode | 40 | – | – | mVpp | | Intra-pair skew (P–N) | HS mode | – | – | 5 | ps | | Lane-to-lane skew | HS mode | – | – | 15 | ps | | HS clock frequency | Dedicated lane | – | 1.25 | – | GHz | | HS clock jitter (total) | at max rate | – | – | 0.5 | UI | | HS eye height | HS mode | 140 | – | – | mV | | LP input high (VIH) | LP mode | – | – | 740 | mV | | LP input low (VIL) | LP mode | 550 | – | – | mV | | Hold time | – | 0.3 | – | 0.5 | UI | | Setup time | – | –0.5 | – | –0.3 | UI | ### Display support Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) The QCS8275 device supports one D-PHY or C-PHY display. Table : Supported MIPI-DSI standards and exceptions | Applicable standard | Feature exceptions | | --- | --- | | MIPI Alliance Specification for Display Serial Interface | None | | MIPI Alliance Specification for D-PHY v1.2 | None | | MIPI Alliance Specification for C-PHY v1.1 | None | The following tables summarize the electrical and timing characteristics for DSI C‑PHY and D‑PHY interfaces at the SoC pin level. Table : DSI C‑PHY electrical characteristics | Parameter | Condition | Min | Typ | Max | Unit | | --- | :---: | :---: | :---: | :---: | :---: | | Symbol rate per trio | – | – | 2.5 | – | Gsym/s per trio | | Equivalent data rate | Per trio | – | 5.7 | – | Gb/s | | Supported trios | – | 1 | – | 3 | trios | | Static common point voltage | HS mode | 175 | – | 310 | mV | | Intra-trio skew [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic.dita_53ebe845-5b96-402a-9d59-65ba13e92b24__fn_umw_nzl_pjc) | HS mode | – | – | 5 | ps | | Inter-trio skew [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic.dita_53ebe845-5b96-402a-9d59-65ba13e92b24__fn_umw_nzl_pjc) | HS mode | – | – | 30 | ps | | HS jitter (total) [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic.dita_53ebe845-5b96-402a-9d59-65ba13e92b24__fn_umw_nzl_pjc) | at max rate | – | – | 0.3 | UI | | HS eye height [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic.dita_53ebe845-5b96-402a-9d59-65ba13e92b24__fn_umw_nzl_pjc) | HS mode | 80 | – | – | mV | | HS eye width [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic.dita_53ebe845-5b96-402a-9d59-65ba13e92b24__fn_umw_nzl_pjc) | HS mode | 0.5 | – | – | UI | | LP output high (VOH) | LP mode | 0.95 | – | 1.3 | V | | LP output low (VOL) | LP mode | -0.05 | – | 0.05 | V | ^1^ Not characterized; guaranteed by design | Parameter | Condition | Min | Typ | Max | Unit | | --- | --- | --- | --- | --- | --- | | Supported data rates | 2.5, 2.1, 1.312 | 2.5, 2.1, 1.312 | 2.5, 2.1, 1.312 | 2.5, 2.1, 1.312 | Gb/s per lane | | Data rate per lane | HS mode | – | – | 2.5 | Gb/s | | Supported data lanes | – | 1 | – | 4 | lanes | | HS differential swing | HS mode | 140 | 200 | 270 | mVpp | | HS common-mode voltage | HS mode | 0.15 | 0.2 | 0.25 | V | | Intra-pair skew (P–N) [^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic.dita_53ebe845-5b96-402a-9d59-65ba13e92b24__fn_xly_ygb_4jc) | HS mode | – | – | 5 | ps | | Lane-to-lane skew [^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic.dita_53ebe845-5b96-402a-9d59-65ba13e92b24__fn_xly_ygb_4jc) | HS mode | – | – | 15 | ps | | HS jitter (total) [^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic.dita_53ebe845-5b96-402a-9d59-65ba13e92b24__fn_xly_ygb_4jc) | at max rate | – | – | 0.3 | UI | | HS eye height [^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic.dita_53ebe845-5b96-402a-9d59-65ba13e92b24__fn_xly_ygb_4jc) | HS mode | 80 | – | – | mV | | HS data rise time | HS mode | – | – | 160 | ps | | HS data fall time | HS mode | – | – | 160 | ps | | HS clock rise time | HS mode | – | – | 160 | ps | | HS clock fall time | HS mode | – | – | 160 | ps | | LP output high (VOH) | LP mode | 0.95 | – | 1.3 | V | | LP output low (VOL) | LP mode | -0.05 | – | 0.05 | V | | LP input high (VIH) | LP mode | 740 | – | – | mV | | LP input low (VIL) | LP mode | – | – | 550 | mV | | LP Tx rise time | LP mode | – | – | 25 | ns | | LP Tx fall time | LP mode | – | – | 25 | ns | ^2^ Not characterized, guaranteed by design. ### DisplayPort (DP) Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) The DisplayPort (DP) interface provides high-speed digital video and audio transmission and complies with industry-standard specifications for interoperability. Table : Supported DisplayPort standards and exceptions | Applicable standard | Feature exceptions | | --- | --- | | VESA DisplayPort v1.4 | None | The following table summarizes the key electrical and link characteristics for the DisplayPort and embedded DisplayPort (eDP) interface. Table : DP/eDP electrical and link characteristics | Parameter | Min | Typ | Max | Unit | | --- | :---: | :---: | :---: | :---: | | Main link lane count | 1 | 2 | 4 | lanes | | Main link per-lane rate (DP 1.4) | 1.612 | – | 8.1 | Gb/s per lane | | Encoding/clocking | – | 8b/10b | – | – | | Total raw bandwidth (4 lanes) | – | – | 32.4 | Gb/s | | AUX channel data rate | – | 1 | – | Mb/s | | AUX differential peak-to-peak voltage (DP) | 0.29 | – | 1.38 | Vpp (diff) | | AUX differential peak-to-peak voltage (eDP) | 0.14 | – | 1.36 | Vpp (diff) | | AUX AC-coupling capacitance | 75 | 100 | 200 | nF | ## Connectivity Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) The connectivity functions supported by the QCS8275 that require electrical specifications include: - USB host/slave support with built-in physical layer (PHY) - Peripheral component interconnect express (PCIe) interfaces - Universal flash storage (UFS) - NOR flash storages (OSPI/QSPI) - Reduced gigabit media independent interface (RGMII) - High-speed serial gigabit media-independent interface (HSGMII) - Through proper configuration of 20 main domain (MD) GPIO-based QUP SEs and 5 RTSS domain RTSS\_IO-based QUP SEs: - Universal asynchronous receiver/transmitter (UART) ports - Inter-integrated circuit (I²C) interfaces - Serial peripheral interface (SPI) ports - Dedicated I²C interfaces for camera (CCI I²C) Pertinent specifications for these functions are detailed in the following subsections. Note: In addition to the following hardware specifications, see the latest software release notes for software-based performance features or limitations. ### USB interfaces Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) The USB interface supports high-speed connectivity and complies with industry-standard specifications for interoperability. Table : Supported USB standards and exceptions | Applicable standard | Feature exceptions | | :---: | :---: | | Universal Serial Bus Specification, Revision 3.1 (August 11, 2014 or
later) | None | | UTMI specification version 1.05, released on 3/29/2001 | None | | On-The-Go and Embedded Host Supplement to the USB 3.0 Specification (May 10,
2012, Revision 1.1 or later) | Attach detection protocol (ADP), role swap protocol (RSP), session request
protocol (SRP), and host negotiation protocol (HNP) | | USB Serial Bus Specification, Revision 2.0 (April 27, 2000 or
later) | None | The following table summarizes the high-speed USB electrical and timing characteristics at the SoC pin level. Table : USB high-speed electrical characteristics | Parameter | Condition | Min | Typ | Max | Unit | | --- | --- | :---: | :---: | :---: | :---: | | Signaling rate | High-speed mode | 479.76 | 480 | 480.24 | Mb/s | | Unit interval (UI) | at 480 Mb/s | – | 2.083 | – | ns | | Differential output voltage (high) | HS driver | 360 | 400 | 440 | mVpp | | Differential output voltage (low) | HS driver | – | – | 10 | mVpp | | Differential interface impedance | Link (cable + termination) | 76.5 | 90 | 103.5 | Ω | | Termination resistance (per line) | HS mode | 40.5 | 45 | 49.5 | Ω | | Differential receiver sensitivity | Receiver | 200 | – | – | mV | | Differential common-mode range | HS signaling | 0.8 | – | 2.5 | V | | Rise time (10–90%) | Signal edge | 0.5 | – | – | ns | | Fall time (10–90%) | Signal edge | 0.5 | – | – | ns | | Chirp K/J width | HS detection | 40 | – | 60 | µs | | Chirp J level (differential) | HS driver | 700 | – | 1100 | mV | | Chirp K level (differential) | HS driver | –900 | – | –500 | mV | | Bus pull-up (upstream port) | – | 1.425 | – | 1.575 | kΩ | | Bus pull-down (downstream port) | – | 14.25 | – | 15.75 | kΩ | Note: - Compliant with the USB 2.0 high-speed specification (480 Mb/s); values reflect SoC pin-level electrical and timing characteristics - High-speed signaling uses bit-stuffed NRZI encoding with differential D+ and D- signaling - High-speed operation requires chirp signaling during reset for speed negotiation with downstream devices - No external reference clock is required; clock is recovered from the data stream - Differential impedance target is 90 Ω ±10%; tight control of D+ and D– skew is recommended for margin - On-die series termination is assumed unless otherwise specified in the hardware design guide - All specifications apply across recommended operating voltage and temperature unless otherwise noted The following table summarizes the SuperSpeed USB electrical and timing characteristics for Gen1 and Gen2 operation at the SoC pin level. Table : USB SuperSpeed electrical characteristics | Parameter | Min | Typ | Max | Unit | | --- | :---: | :---: | :---: | :---: | | Supported generation | – | Gen1, Gen2 | – | – | | Signaling rate (Gen1) | – | 5 | – | Gb/s | | Signaling rate (Gen2) | – | 10 | – | Gb/s | | Unit interval (Gen1) | 199.94 | 200 | 200.065 | ps | | Unit interval (Gen2) | 99.97 | 100 | 100.0325 | ps | | Differential output voltage | 800 | 900 | 1200 | mVpp-diff | | Tx rise / fall time (Gen1) | 20 | – | 80 | ps | | Tx rise / fall time (Gen2) | 10 | – | 50 | ps | | Differential output impedance | 70 | 90 | 110 | Ω | | Intra-pair skew (P–N) | – | – | 5 | ps | | Lane-to-lane skew | – | – | 70 | ps | | Tx total jitter (Gen1) | – | – | 132 | ps | | Tx total jitter (Gen2) | – | – | 67 | ps | | Rx eye height (Gen2) | 0.07 | – | – | mV | | Rx eye height (Gen1) | 0.1 | – | – | mV | Note: - Compliant with USB-IF USB 3.1/USB 3.2 specifications for SuperSpeed operation. - This table applies to SuperSpeed differential pairs (TX/RX); USB 2.0 D+/D− signaling is specified separately. - SuperSpeed signaling uses embedded clocking; an external reference clock is required only for PHY PLL operation. - Differential routing requirement: 90 Ω ±10% impedance, with strict control of intra-pair and inter-pair skew. - AC coupling capacitors are required on Tx SuperSpeed lanes and should be placed near SoC pins. - Supports LFPS-based power management, including U1, U2, and U3 states. - All parameters apply across the recommended voltage and temperature range unless otherwise stated. ### PCIe interface Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) The PCI Express (PCIe) interface supports high-speed serial communication and complies with industry-standard specifications for interoperability. | Applicable standard | Feature exceptions | | --- | --- | | PCI\_Express\_Base\_Specification\_Revision\_4.0 | Link configure capability | | PCI\_Express\_Base\_Specification\_Revision\_4.0 | Lane margining at receiver | | PCI\_Express\_Base\_Specification\_Revision\_4.0 | L0s link state | | | | | | | The following table summarizes the electrical and timing characteristics for the high-speed serial interface operating at Gen4 and Gen3 data rates. The parameters represent SoC pin-level requirements across supported operating conditions. | Parameter | Gen4 | Gen4 | Gen4 | Gen3 | Gen3 | Gen3 | Unit | | --- | --- | --- | --- | --- | --- | --- | --- | | Parameter | Min | Typ | Max | Min | Typ | Max | Unit | | Signaling rate | – | – | 16 | – | – | 8 | GT/s | | Unit interval (UI) | 62.48 | 62.5 | 62.64 | 124.96 | 125 | 125.28 | ps | | Differential voltage (Tx) | 600 | – | 1200 | 800 | – | 1200 | mVpp-diff | | Single-ended swing (Tx) | 300 | – | 600 | 400 | – | 600 | mVpp | | Tx common-mode voltage | 0.7 | – | 0.9 | 0.7 | – | 0.9 | V | | Differential output impedance | 80 | – | 120 | 80 | – | 120 | Ω | | Receiver input sensitivity | 30 | – | – | 85 | – | – | mV | | AC coupling capacitance | 75 | 100 | 200 | 75 | 100 | 200 | nF | | Intra-pair skew (P–N) | – | – | 5 | – | – | 20 | ps | | Lane-to-lane skew | – | – | 20 | – | – | 50 | ps | | Tx total jitter (TJ) | – | – | 15.85 | – | – | 33.83 | ps | | REFCLK frequency | 99.8 | 100 | 100.2 | 99.8 | 100 | 100.2 | MHz | | REFCLK duty cycle | 45 | 50 | 55 | 45 | 50 | 55 | % | | REFCLK RMS jitter (no SSC) | – | – | 1 | – | – | 1 | ps | | REFCLK peak-to-peak jitter | – | – | 10 | – | – | 10 | ps | | Spread spectrum clocking (down spread) | -0.5 | -0.3 | 0 | -0.5 | -0.3 | 0 | % | | PERST# assertion width | 100 | – | – | 100 | – | – | ms | | PERST# deassertion to LTSSM | 2 | – | – | 2 | – | – | ms | | Receiver detect voltage | 200 | – | 600 | 200 | – | 600 | mV | | Receiver detect resistance | 40 | – | 60 | 40 | – | 60 | Ω | | | | | | | | | | ### UFS interface Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) Table : Supported UFS standards and exceptions | Applicable standard | Feature exceptions | | --- | --- | | Universal Flash Storage (UFS), Version 3.1 | – | ### SGMII interface Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) The Serial Gigabit Media Independent Interface (SGMII) provides a serial link between MAC and PHY, enabling Ethernet connectivity over a differential pair with embedded clocking. Table : Supported SGMII standards and exceptions | Applicable standard | Feature exceptions | | --- | --- | | IEEE 802.3 | None | The following tables summarize the SoC pin-level electrical and timing characteristics for SGMII operation at *3.125 Gbps* and *1.25 Gbps*. Table : SGMII characteristics at 3.125 Gbps | Parameter | Min | Typ | Max | Unit | | --- | :---: | :---: | :---: | :---: | | Supported link speed | – | – | 2500 | Mb/s | | Line coding | – | 8b/10b | – | – | | Serial line rate | – | 3.125 | – | Gb/s | | Unit interval (UI) | – | 320 | – | ps | | Tx rise/fall time | 60 | – | 130 | ps | | Intra-pair skew (P–N) | – | – | 15 | ps | | Lane-to-lane skew | – | – | 100 | ps | | Tx total jitter (TJ) | – | – | 0.35 | UI | | Tx random jitter (RJ, RMS) | – | – | 0.18 | UI | | Tx deterministic jitter | – | – | 0.17 | UI | | Tx duty cycle distortion (DCD) | – | – | 2 | % | | Rx eye height | 200 | – | – | mV | | Rx eye width | 0.35 | – | – | UI | Table : SGMII characteristics at 1.25 Gbps | Parameter | Min | Typ | Max | Unit | | --- | :---: | :---: | :---: | :---: | | Supported link speed | – | – | 1000 | Mb/s | | Line coding | – | 8b/10b | – | – | | Serial line rate | – | 1.25 | – | Gb/s | | Unit interval (UI) | – | 800 | – | ps | | Tx rise/fall time | 100 | – | 200 | ps | | Intra-pair skew (P–N) | – | – | 20 | ps | | Lane-to-lane skew | – | – | 100 | ps | | Tx total jitter (TJ) | – | – | 0.30 | UI | | Tx random jitter (RJ, RMS) | – | – | 0.20 | UI | | Tx deterministic jitter | – | – | 0.10 | UI | | Rx eye height | 100 | – | – | mV | | Rx eye width | 0.35 | – | – | UI | Note: - Compliant with SGMII specification and IEEE 802.3 (1000BASE-X PCS/PMA) - Uses 8b/10b encoding with a fixed 1.25 Gb/s serial line rate, independent of negotiated link speed - Clock is embedded in the serial data stream; an optional 25 MHz reference clock may be used for PLL operation, depending on the SoC implementation - Differential routing requires controlled impedance of 100 Ω ± 10% with tight control of intra-pair skew - Auto-negotiation supports 10/100/1000 Mb/s operation over a single differential pair - AC coupling is required on Tx differential signals unless otherwise specified in the platform design - Specifications apply across recommended operating voltage and temperature unless otherwise noted ### Octa-SPI/Quad-SPI interface Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) Figure : Octa-SPI/Quad-SPI SDR timing diagram SDR Input Sheet.117 Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 OSPI_CLK OSPI_CLK Sheet.14 Sheet.15 Tclk Tclk Sheet.16 Tclk/2 Tclk/2 Sheet.17 OSPI_DATA OSPI_DATA Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 Sheet.32 Sheet.34 Sheet.35 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 Sheet.44 Sheet.45 Sheet.46 Sheet.47 Sheet.48 Sheet.49 Sheet.50 Sheet.51 Sheet.52 Sheet.53 Sheet.54 Sheet.55 Sheet.56 Sheet.57 Sheet.58 Sheet.59 Sheet.60 Sheet.61 Sheet.62 Sheet.63 Sheet.64 Sheet.65 Sheet.66 Sheet.67 Sheet.68 Sheet.69 Sheet.70 Sheet.71 Sheet.72 Sheet.73 Sheet.74 Sheet.75 Sheet.76 Sheet.77 Sheet.78 Sheet.79 Sheet.80 Sheet.81 Sheet.82 Sheet.83 Sheet.84 Sheet.85 Sheet.86 Sheet.87 Sheet.88 Input setup time Input setup time Sheet.89 Sheet.90 Sheet.91 Sheet.92 Sheet.93 Sheet.94 Sheet.95 Input hold time Input hold time Sheet.96 Sheet.97 Sheet.98 Sheet.99 Sheet.100 Sheet.101 Sheet.102 Sheet.103 Sheet.104 Sheet.105 Sheet.106 Sheet.107 Sheet.108 Sheet.109 Sheet.110 Sheet.111 Sheet.112 Sheet.113 Sheet.114 Sheet.115 Sheet.116 SDR Output Sheet.206 Sheet.1 Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 OSPI_CLK OSPI_CLK Sheet.12 OSPI_DATA OSPI_DATA Sheet.13 Sheet.14 Sheet.15 Sheet.46 Sheet.47 Sheet.48 Sheet.49 Sheet.50 Sheet.51 Sheet.52 Sheet.53 Sheet.54 Sheet.55 Sheet.56 Sheet.57 Sheet.58 Sheet.59 Sheet.60 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.28 Sheet.29 Sheet.30 Sheet.16 Sheet.17 Sheet.31 Sheet.32 Sheet.33 Sheet.34 Sheet.35 Sheet.36 Tclk Tclk Sheet.37 Tclk/2 Tclk/2 Sheet.42 Maximum output delay Maximum output delay Sheet.43 Minimum output delay Minimum output delay Sheet.102 Sheet.103 Sheet.104 Sheet.105 Sheet.106 Sheet.107 Sheet.108 Sheet.109 Sheet.110 Sheet.111 Sheet.184 Sheet.185 Sheet.186 Sheet.187 Sheet.200 Sheet.201 Sheet.188 Sheet.189 Sheet.190 Sheet.191 Sheet.192 Sheet.193 Sheet.194 Sheet.195 Sheet.196 Sheet.197 Sheet.198 Sheet.199 Sheet.202 Sheet.203 Sheet.204 Sheet.205 Table : Octa-SPI/Quad-SPI interface SDR timing | Parameter | Comments | Min | Max | Unit | | --- | --- | :---: | :---: | :---: | | 1/T | OSPI/QSPI clock frequency | – | 90 | MHz | | t(mis) | Master input setup time | 1.7 | – | ns | | t(mih) | Master input hold time | 1.3 | – | ns | | t(mod) | Master output delay | -2.00 | 2.00 | ns | Figure : Octa-SPI DDR timing diagram Page-1 Sheet.94 Sheet.1 Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 OSPI_CLK OSPI_CLK Sheet.13 Sheet.14 Sheet.15 Sheet.16 Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.45 Sheet.46 Sheet.47 Sheet.48 Sheet.49 Sheet.50 Sheet.51 Sheet.52 Sheet.53 Sheet.54 Sheet.55 Tclk Tclk Sheet.56 Tclk/2 Tclk/2 Sheet.57 Maximum output delay Maximum output delay Sheet.58 Minimum output delay Minimum output delay Sheet.31 Sheet.32 Sheet.33 Sheet.34 Sheet.35 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 Sheet.44 Sheet.60 Sheet.62 Sheet.63 Sheet.64 Sheet.65 Sheet.66 Sheet.67 Sheet.68 Sheet.69 Sheet.70 Sheet.71 Sheet.72 Sheet.73 Sheet.74 Sheet.75 Sheet.76 Sheet.77 Sheet.78 Sheet.79 Sheet.80 Sheet.81 Sheet.82 Sheet.83 Sheet.84 Sheet.85 Sheet.86 Sheet.87 Sheet.88 Sheet.89 Sheet.90 Sheet.91 Sheet.92 Sheet.93 OSPI_DATA OSPI_DATA Table : Octa-SPI interface DDR timing | Parameter | Comments | Min | Max | Unit | | :---: | --- | :---: | :---: | :---: | | 1/T | OSPI clock frequency | – | 166 | MHz | | t(skew) | DQ to DQS skew | – | 530 | ps | | t(mod) | Master output delay | -2.00 | 2.00 | ns | Note: DDR is not supported on Quad-SPI operation. ### RGMII interface Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) Table : Supported RGMII standards and exceptions | Applicable standard | Feature exceptions | | --- | :---: | | *Reduced Gigabit Media Independent Interface (RGMII) v1.3 and v2.0* | None | | Parameter | Min | Typ | Max | Unit | | --- | --- | --- | --- | --- | | Supported speeds | 10/100/1000 | 10/100/1000 | 10/100/1000 | Mb/s | | Reference clock (TXC/RXC) | 2.5/25/125 | 2.5/25/125 | 2.5/25/125 | MHz | | Data transfer | DDR at 1000 Mbps only | DDR at 1000 Mbps only | DDR at 1000 Mbps only | DDR at 1000 Mbps only | | **Signal electrical levels (CMOS)** | **Signal electrical levels (CMOS)** | **Signal electrical levels (CMOS)** | **Signal electrical levels (CMOS)** | **Signal electrical levels (CMOS)** | | I/O supply voltage (VDDIO) | 1.7 | 1.8 | 1.9 | V | | Input high voltage (VIH) | 0.65 × VDD\_PXx | — | VDD\_PXx + 0.3 | V | | Input low voltage (VIL) | -0.3 | — | 0.35 × VDD\_PXx | V | | Output high voltage (VOH) | VDD\_PXx - 0.45 | — | — | V | | Output low voltage (VOL) | — | — | 0.45 | V | | **Timing (1000BASE‑T)** | **Timing (1000BASE‑T)** | **Timing (1000BASE‑T)** | **Timing (1000BASE‑T)** | **Timing (1000BASE‑T)** | | TXD setup time | 1.2 | — | — | ns | | TXD hold time | 1.2 | — | — | ns | | RXD setup time | 1 | — | — | ns | | RXD hold time | 1 | — | — | ns | | Clock duty cycle | 45 | 50 | 55 | % | | **Management interface (MDIO/MDC)** | **Management interface (MDIO/MDC)** | **Management interface (MDIO/MDC)** | **Management interface (MDIO/MDC)** | **Management interface (MDIO/MDC)** | | MDC clock frequency | — | 2.5 | | MHz | | Input high voltage (VIH) | 0.65 × VDD\_PXx | — | VDD\_PXx + 0.3 | | | Input low voltage (VIL) | -0.3 | — | 0.35 × VDD\_PXx | | | Output high voltage (VOH) | VDD\_PXx - 0.45 | — | — | V | | Output low voltage (VOL) | — | — | 0.45 | V | When the MDIO signal is sourced by the PHY, it is sampled by the SoC synchronous to the rising edge of MDC. The clock-to-output delay from the PHY shall be a minimum of 0 ns and a maximum of 300 ns. Figure : MDIO sourced by PHY Page-1 Sheet.1 When the SoC sources the MDIO signal, it shall provide a minimum setup time of 10 ns and a minimum hold time of 10 ns, referenced to the rising edge of MDC. Figure : MDIO sourced by SoC Page-1 Sheet.1 Figure : RGMII Tx and Rx timing Page-1 Sheet.1 ### Audio support Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) The Audio-related interfaces supported with QCS8275 include: - I²S: [I²S interfaces](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic.dita_3de50955-32a3-4168-a48e-1a6c300bf0c9) - PCM/TDM: [PCM/TDM interfaces](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#concept_knr_3qc_nzb) ### I²S interfaces Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) Table : Supported I²S standards and exceptions | Applicable standards | Feature exceptions | | --- | :---: | | *Philips I²S Bus Specifications* revised June 5, 1996 | None | Figure : I²S timing diagram Page-1 Sheet.1 Sheet.2 High-level I2S timing High-level I2S timing Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 Sheet.12 Sheet.13 Sheet.14 Sheet.15 Sheet.16 Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 Sheet.32 Sheet.33 Sheet.34 Sheet.35 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 Sheet.44 Sheet.45 SCK SCK Sheet.46 Sheet.47 Sheet.48 Sheet.49 Sheet.50 Sheet.51 Sheet.52 Sheet.53 Sheet.54 Sheet.55 Sheet.56 Sheet.57 Sheet.58 WS WS Sheet.59 Sheet.60 Sheet.61 Sheet.62 Sheet.63 Sheet.64 Sheet.65 Sheet.66 Sheet.67 Sheet.68 Sheet.69 Sheet.70 Sheet.71 Sheet.72 Sheet.73 SD SD Sheet.74 Sheet.75 Sheet.76 Sheet.77 Sheet.78 Sheet.79 Sheet.80 Sheet.81 Sheet.82 Sheet.83 Sheet.84 Sheet.85 Sheet.86 Sheet.87 Sheet.88 LSB LSB Sheet.89 MSB MSB Sheet.90 Sheet.91 Sheet.92 Sheet.93 Sheet.94 Sheet.95 Sheet.96 Sheet.97 Sheet.98 Sheet.99 Sheet.100 Sheet.101 Sheet.102 Sheet.103 Sheet.104 LSB LSB Sheet.105 MSB MSB Sheet.106 Sheet.107 Sheet.108 Sheet.109 Sheet.110 Sheet.111 Sheet.112 Sheet.113 Sheet.114 Sheet.115 Sheet.116 Word (n – 1) right channel Word (n – right channel Sheet.117 Word (n) left channel Word (n) left channel Sheet.118 Word (n + 1) right channel Word (n + 1) right channel Sheet.119 Sheet.120 Sheet.121 Sheet.122 Sheet.123 Sheet.124 Sheet.125 Sheet.126 Sheet.127 Sheet.128 Sheet.129 Sheet.130 SCK SCK Sheet.131 SD or WS transmitter SD or WS transmitter Sheet.132 T T Sheet.133 Sheet.134 Sheet.135 Sheet.136 Sheet.137 t(HC) t(HC) Sheet.138 Sheet.139 Sheet.140 Sheet.141 Sheet.142 Sheet.143 Sheet.144 Sheet.145 Sheet.146 Sheet.147 Sheet.151 Sheet.152 Sheet.153 Sheet.166 Sheet.167 Sheet.168 Sheet.178 Sheet.179 Sheet.180 t(LC) t(LC) Sheet.196 Sheet.197 t(dtr) t(dtr) Sheet.198 Sheet.199 Sheet.209 Sheet.214 SD or WS receiver SD or WS receiver Sheet.215 Sheet.216 Sheet.217 Sheet.218 Sheet.219 Sheet.220 Sheet.221 Sheet.222 Sheet.236 Sheet.237 Sheet.238 t(sr) t(sr) Sheet.239 Sheet.240 Sheet.255 Sheet.256 Sheet.257 Sheet.258 Sheet.259 Sheet.260 t(hr) t(hr) Sheet.261 I2S timing details – Tx and Rx I2S timing details – Tx and Rx Sheet.262 Sheet.263 Sheet.154 Sheet.163 Sheet.164 Sheet.165 Sheet.160 Sheet.161 Sheet.162 Sheet.190 Sheet.191 Sheet.192 Sheet.187 Sheet.188 Sheet.189 Sheet.157 Sheet.158 Sheet.159 Sheet.241 Sheet.242 Sheet.243 Sheet.250 Sheet.251 Sheet.252 | Parameter | Parameter | Comments[^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fntarg_1_i2s-interfaces) | Min | Typ | Max | Unit | | --- | --- | --- | --- | --- | --- | --- | | ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** | | Frequency | Frequency | | – | – | 24.576 | MHz | | T | Clock period | | 40.69 | – | – | ns | | t(HC) | Clock high | | 0.45 × T | – | 0.55 × T | ns | | t(LC) | Clock low | | 0.45 × T | – | 0.55 × T | ns | | t(sr) | SD and WS input setup time | | 8.14 | – | – | ns | | t(hr) | SD and WS input hold time | | 1.5 | – | – | ns | | t(dtr) | SD and WS output delay | | – | – | 8.14 | ns | | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | | Frequency | Frequency | | – | – | 24.576 | MHz | | T | Clock period | | 40.69 | – | – | ns | | t(HC) | Clock high | | 0.45 × T | – | 0.55 × T | ns | | t(LC) | Clock low | | 0.45 × T | – | 0.55 × T | ns | | t(sr) | SD and WS input setup time | | 8.14 | – | – | ns | | t(hr) | SD and WS input hold time | | 1.5 | – | – | ns | | t(dtr) | SD and WS output delay | | – | – | 8.14 | ns | [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fnsrc_1_i2s-interfaces) Load capacitance is between 10 pF and 40 pF. | Parameter | Parameter | Comments[^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fntarg_2_i2s-interfaces) | Min | Typ | Max | Unit | | --- | --- | --- | --- | --- | --- | --- | | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | | | Frequency | | | – | 73.728 | MHz | | T | Clock period | | 13.56 | – | – | ns | | t(HC) | Clock high | | 0.45 × T | – | 0.55 × T | ns | | t(LC) | Clock low | | 0.45 × T | – | 0.55 × T | ns | | t(sr) | SD and WS input setup time | | 2.71 | – | – | ns | | t(hr) | SD and WS input hold time | | 1.5 | – | – | ns | [^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fnsrc_2_i2s-interfaces) Load capacitance is between 10 pF and 40 pF. | Parameter | Parameter | Comments[^3^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fntarg_3_i2s-interfaces) | Min | Typ | Max | Unit | | --- | --- | --- | --- | --- | --- | --- | | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | | | Frequency | | | – | 24.576 | MHz | | T | Clock period | | 40.69 | – | – | ns | | t(HC) | Clock high | | 0.45 × T | – | 0.55 × T | ns | | t(LC) | Clock low | | 0.45 × T | – | 0.55 × T | ns | | t(dtr) | SD and WS output delay | | – | – | 8.14 | ns | [^3^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fnsrc_3_i2s-interfaces) Load capacitance is between 10 pF and 40 pF. ### PCM/TDM interfaces Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) Figure : PCM/TDM audio format with different sync modes PCM/TDM format Sheet.302 Valid Bus.66 MSB MSB Sheet.17 PCM5/TDM_SYNC2, 3 (short) PCM5/TDM_SYNC2, 3(short) Sheet.20 PCM5/TDM_SYNC2, 3 (long) PCM5/TDM_SYNC2, 3 (long) Sheet.21 Rate: (1 to 512 bits/frame) Rate: (1 to 512 bits/frame) Sheet.25 1 to 32 bits/slot 1 to 32 bits/slot Sheet.1 16 active Tx and Rx slots 16 active Tx and Rx slots Sheet.2 TDM_SYNC2, 3 (one slot) TDM_SYNC2, 3 (one slot) Sheet.77 PCM5/TDM_CLK1 PCM5/TDM_CLK1 Sheet.78 Sheet.115 Sheet.117 Sheet.118 Sheet.120 Sheet.121 Sheet.139 Sheet.140 Sheet.141 Sheet.143 Sheet.144 Sheet.145 Sheet.146 Sheet.147 Sheet.149 Sheet.150 Sheet.151 Sheet.152 Sheet.153 Sheet.154 Sheet.155 Sheet.158 Sheet.157 Sheet.176 Sheet.156 Sheet.159 Sheet.18 PCM5/TDM_DOUT4 PCM5/TDM_DOUT4 Valid Bus.124 D30 D30 Valid Bus.125 D29 D29 Break.134 Sheet.135 Sheet.136 Sheet.137 open valid.138 D1 D1 open valid.165 D28 D28 Sheet.126 Valid Bus.129 MSB MSB Valid Bus.130 D30 D30 Valid Bus.131 D29 D29 Break.132 Sheet.133 Sheet.166 Sheet.171 open valid.173 D28 D28 Sheet.172 Sheet.174 Sheet.175 Valid Bus.170 LSB LSB Sheet.182 Sheet.183 Sheet.160 Break.167 Sheet.168 Sheet.169 Sheet.181 Sheet.179 Channel 0 Channel 0 Valid Bus.19 MSB MSB Valid Bus.24 D30 D30 Valid Bus.184 D29 D29 open valid.190 D28 D28 Sheet.191 Sheet.192 Sheet.193 Valid Bus.194 LSB LSB Break.197 Sheet.198 Sheet.199 Sheet.200 Sheet.22 Channel 1 to channel 7 Channel 1 to channel 7 Sheet.185 Valid Bus.177 MSB MSB Valid Bus.186 D30 D30 Valid Bus.187 D29 D29 open valid.188 D28 D28 Sheet.189 Sheet.201 Sheet.202 Break.204 Sheet.205 Sheet.206 Sheet.207 Sheet.208 Channel 8 to channel 15 Channel 8 to channel 15 Break.209 Sheet.210 Sheet.211 Sheet.212 open valid.213 D1 D1 Valid Bus.214 LSB LSB Sheet.215 Sheet.216 Break.217 Sheet.218 Sheet.219 Sheet.220 Sheet.180 Sheet.203 Sheet.221 Sheet.222 Sheet.223 Sheet.119 Sheet.225 Sheet.148 Valid Bus.226 MSB MSB Sheet.294 PCM5/TDM_DIN PCM5/TDM_DIN Sheet.16 Valid Bus.296 D30 D30 Sheet.297 Sheet.298 Valid Bus.299 D29 D29 Valid Bus.300 D28 D28 Sheet.301 Valid Bus.4 LSB LSB Sheet.5 Sheet.6 Break.7 Sheet.8 Sheet.9 Sheet.10 Sheet.13 Sheet.12 Sheet.30 Sheet.31 Sheet.26 D1 D1 Break.14 Sheet.27 Sheet.28 Sheet.29 Valid Bus.33 MSB MSB Valid Bus.35 D30 D30 Sheet.36 Sheet.37 Valid Bus.38 D29 D29 Valid Bus.39 D28 D28 Sheet.40 Sheet.43 Sheet.56 Valid Bus.41 MSB MSB Sheet.42 Valid Bus.44 D30 D30 Sheet.45 Sheet.46 Valid Bus.47 D29 D29 Valid Bus.48 D28 D28 Sheet.51 Sheet.52 Break.53 Sheet.54 Sheet.55 Sheet.58 Sheet.59 Valid Bus.60 LSB LSB Sheet.61 Sheet.62 D1 D1 Break.63 Sheet.64 Sheet.65 Sheet.66 Sheet.34 Valid Bus.67 MSB MSB Sheet.68 Valid Bus.69 D30 D30 Sheet.70 Sheet.71 Valid Bus.72 D29 D29 Sheet.74 Sheet.49 Break.50 Sheet.57 Sheet.73 Sheet.75 Sheet.79 Sheet.80 LSB LSB Break.81 Sheet.82 Sheet.84 Sheet.85 Sheet.76 Sheet.83 Sheet.86 Sheet.87 Sheet.88 Sheet.89 Channel 0 Channel 0 Sheet.90 Sheet.91 Sheet.92 Sheet.93 Channel 1 to channel 7 Channel 1 to channel 7 Sheet.94 Sheet.95 Sheet.96 Sheet.97 Channel 8 to channel 15 Channel 8 to channel 15 Sheet.3 Sheet.15 Sheet.23 Notes: 1. Internal clock can also be inverted (180 degrees ou... Notes:1. Internal clock can also be inverted (180 degrees out of phase) relative to the external clock.2. Frame sync signal can also be inverted. 3. Supports 0 to 2 cycle delays between the frame sync pulse edge and PCM_DOUT/DIN data. 4. PCM data per slot can be smaller or equal to the slot size: ● If data size < slot size, remaining data bits are padded with zeroes. ● If data size > slot size, extra data bits will be ignored.5. PCM audio interface: ● Supports only mono channel. ● Does not support one-slot mode. ● PCM_SYNC period is equivalent to 1 frame. Sheet.32 32 bits/slot; 512 bits/frame; 0 frame sync delay; 16 active T... 32 bits/slot; 512 bits/frame; 0 frame sync delay; 16 active Tx and Rx slots (TDM interface) or mono channel (PCM interface) Sheet.98 Sheet.99 Sheet.100 Sheet.101 Figure : PCM/TDM timing diagram Page-1 Sheet.1 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 Sheet.12 Sheet.13 Sheet.14 PCM/TDM_CLK PCM/TDM_CLK Sheet.15 PCM/TDM_DOUT and PCM/TDM_SYNC PCM/TDM_DOUT and PCM/TDM_SYNC Sheet.16 T T Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 T(LC) T(LC) Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.35 Sheet.155 Sheet.156 Sheet.157 Sheet.161 Sheet.162 Sheet.163 Sheet.164 Sheet.165 Sheet.166 Sheet.167 Sheet.168 Sheet.169 Sheet.173 Sheet.174 Sheet.175 Sheet.180 Sheet.181 Sheet.182 Sheet.183 Sheet.184 T(HC) T(HC) Sheet.185 Sheet.191 Sheet.192 Sheet.193 Sheet.194 Sheet.195 Sheet.196 Sheet.200 Sheet.201 Sheet.202 Sheet.203 Sheet.204 t(dtr) t(dtr) Sheet.205 Sheet.206 Sheet.221 PCM/TDM_DIN and PCM/TDM_SYNC PCM/TDM_DIN and PCM/TDM_SYNC Sheet.222 Sheet.223 Sheet.224 Sheet.225 Sheet.226 Sheet.227 Sheet.228 Sheet.229 Sheet.230 Sheet.231 Sheet.232 Sheet.233 Sheet.234 Sheet.235 Sheet.236 Sheet.237 Sheet.238 Sheet.239 Sheet.240 Sheet.241 Sheet.242 Sheet.243 Sheet.244 Sheet.245 t(sr) t(sr) Sheet.246 Sheet.247 Sheet.248 Sheet.249 Sheet.250 Sheet.251 Sheet.252 Sheet.253 Sheet.254 Sheet.255 Sheet.256 Sheet.257 Sheet.258 Sheet.259 Sheet.262 Sheet.263 Sheet.266 Sheet.267 Sheet.268 t(hr) t(hr) Sheet.269 PCM/TDM timing details PCM/TDM timing details Sheet.270 | Parameter | Parameter | Comments | Min | Max | Unit | | --- | --- | --- | --- | --- | --- | | ***Master mode*** | ***Master mode*** | ***Master mode*** | ***Master mode*** | ***Master mode*** | ***Master mode*** | | Frequency | Frequency | | – | 24.576 | MHz | | T | Clock period | | 40.69 | – | ns | | t(HC) | Clock high | | 0.45× T | 0.55× T | ns | | t(LC) | Clock low | | 0.45× T | 0.55× T | ns | | t(sr) | PCM/TDM\_DIN and PCM/TDM\_SYNC setup time | | 8.14 | – | ns | | t(hr) | PCM/TDM\_DIN and PCM/TDM\_SYNC hold time | | 1.5 | – | ns | | t(dtr) | PCM/TDM\_DOUT and PCM/TDM\_SYNC output delay | | – | 8.14 | ns | | ***Slave mode*** | ***Slave mode*** | ***Slave mode*** | ***Slave mode*** | ***Slave mode*** | ***Slave mode*** | | Frequency | Frequency | | – | 24.576 | MHz | | T | Clock period | | 40.69 | – | ns | | t(HC) | Clock high | | 0.45× T | 0.55× T | ns | | t(LC) | Clock low | | 0.45× T | 0.55× T | ns | | t(sr) | PCM/TDM\_DIN and PCM/TDM\_SYNC setup time | | 8.14 | – | ns | | t(hr) | PCM/TDM\_DIN and PCM/TDM\_SYNC hold time | | 1.5 | – | ns | | t(dtr) | PCM/TDM\_DOUT and PCM/TDM\_SYNC output delay | | – | 8.14 | ns | ^1^ Load capacitance is between 10 pF to 40 pF. | Parameter | Parameter | Comments[^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fntarg_2_pcm-tdm-interfaces) | Min | Typ | Max | Unit | | --- | --- | --- | --- | --- | --- | --- | | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | | | Frequency | | | – | 73.728 | MHz | | T | Clock period | | 13.56 | – | – | ns | | t(HC) | Clock high | | 0.45 × T | – | 0.55 × T | ns | | t(LC) | Clock low | | 0.45 × T | – | 0.55 × T | ns | | t(sr) | PCM/TDM\_DIN and PCM/TDM\_SYNC setup time | | 2.71 | – | – | ns | | t(hr) | PCM/TDM\_DIN and PCM/TDM\_SYNC hold time | | 1.5 | – | – | ns | [^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fnsrc_2_pcm-tdm-interfaces) Load capacitance is between 10 pF and 40 pF. | Parameter | Parameter | Comments[^3^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fntarg_3_pcm-tdm-interfaces) | Min | Typ | Max | Unit | | --- | --- | --- | --- | --- | --- | --- | | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | | | Frequency | | | – | 24.576 | MHz | | T | Clock period | | 40.69 | – | – | ns | | t(HC) | Clock high | | 0.45 × T | – | 0.55 × T | ns | | t(LC) | Clock low | | 0.45 × T | – | 0.55 × T | ns | | t(dtr) | PCM/TDM\_DOUT and PCM/TDM\_SYNC delay | | – | – | 8.14 | ns | [^3^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#fnsrc_3_pcm-tdm-interfaces) Load capacitance is between 10 pF and 40 pF. ### I²C interface Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) Table : Supported I²C standards and exceptions | Applicable standard | Feature exceptions | | --- | --- | | I²C Specification, version 3.0 | HS mode, slave mode, multi-master mode, and 10-bit addressing are not
supported. | ### Serial peripheral interface Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) The QCS8275 supports SPI as a master on 24 QUP ports. SPI slave mode is supported on the eight  QUP ports. See the [QCS8275 + PMM8620AU Pin Assignment and GPIO Configuration Spreadsheet (80-73475-1A)](doc/80-73475-1A/80-73475-1A.xlsm) document for more details. Figure : SPI master timing diagram Page-1 Sheet.309 Sheet.223 Sheet.224 Sheet.228 Sheet.222 Sheet.241 Sheet.242 Sheet.246 50% clock duty cycle is shown, but is not a requirement. 50% clock duty cycle is shown, but is not a requirement. Sheet.247 SPI_CLK SPI_CLK Sheet.248 SPI_DATA_MOSI SPI_DATA_MOSI Sheet.249 T T Sheet.251 Sheet.252 t(mov) t(mov) Sheet.264 Sheet.265 Sheet.268 Sheet.271 Sheet.1 Sheet.2 Sheet.3 Sheet.8 Sheet.9 Sheet.10 Sheet.11 Sheet.12 Sheet.13 Sheet.14 Sheet.15 Sheet.16 Sheet.17 Sheet.19 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.30 Sheet.31 Sheet.32 Sheet.33 Sheet.34 Sheet.35 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 Sheet.44 Sheet.45 Sheet.46 SPI_DATA_MISO SPI_DATA_MISO Sheet.48 Sheet.49 t(mis) t(mis) Sheet.50 Sheet.53 Sheet.54 t(mih) t(mih) Sheet.55 Sheet.294 t(mov) value is positive if after clock transition (shown); n... t(mov) value is positive if after clock transition (shown); negative if before. Sheet.250 Sheet.306 SPI_CS_N SPI_CS_N Sheet.307 SPI_CS_N to SPI_CLK timing is fixed at 1 clock period. SPI_CS_N to SPI_CLK timing is fixed at 1 clock period. Sheet.18 Sheet.47 Sheet.52 Sheet.56 Sheet.57 Sheet.58 Sheet.59 Sheet.60 Sheet.61 Sheet.62 Sheet.63 Sheet.64 T T Sheet.28 Sheet.29 Sheet.65 Sheet.66 Sheet.67 Sheet.68 Sheet.69 Sheet.70 Sheet.71 Sheet.72 Sheet.308 Note: Depending on the mode configuration (Clock PHA and POL settings), Tx and Rx sampling edge could differ. The timing diagram above is using mode 1 as an example Table : SPI master timing characteristics | Parameter | Comments | Min | Typ | Max | Unit | | --- | --- | --- | --- | --- | --- | | T (SPI clock period) | 50 MHz maximum | 20 | – | – | ns | | t(ch) | Clock high | 8 | – | – | ns | | t(cl) | Clock low | 8 | – | – | ns | | t(mov) | Master output valid | -5 | – | 5 | ns | | t(mis) | Master input setup | 5 | – | – | ns | | t(mih) | Master input hold | 1 | – | – | ns | ^1^ The minimum clock period includes 1% jitter of maximum frequency. Figure : SPI slave timing diagram Page-1 Sheet.223 Sheet.224 Sheet.228 Sheet.222 Sheet.241 Sheet.242 Sheet.246 50% clock duty cycle is shown, but is not a requirement. 50% clock duty cycle is shown, but is not a requirement. Sheet.247 SPI_CLK SPI_CLK Sheet.248 SPI_DATA_MOSI SPI_DATA_MOSI Sheet.249 T T Sheet.251 Sheet.252 t(sov) t(sov) Sheet.264 Sheet.265 Sheet.268 Sheet.271 Sheet.1 Sheet.2 Sheet.3 Sheet.8 Sheet.9 Sheet.10 Sheet.11 Sheet.6 Sheet.7 Sheet.30 Sheet.31 Sheet.32 Sheet.33 Sheet.34 Sheet.35 Sheet.36 Sheet.37 Sheet.46 SPI_DATA_MISO SPI_DATA_MISO Sheet.49 t(sis) t(sis) Sheet.50 Sheet.51 Sheet.53 Sheet.54 t(sih) t(sih) Sheet.55 Sheet.250 Sheet.306 SPI_CS_N SPI_CS_N Sheet.56 Sheet.57 Sheet.58 Sheet.59 Sheet.60 Sheet.61 Sheet.62 Sheet.63 Sheet.28 Sheet.29 Sheet.65 Sheet.66 Sheet.69 Sheet.70 Sheet.72 Sheet.308 Sheet.309 Sheet.320 Sheet.321 Sheet.323 Sheet.327 Sheet.329 Sheet.330 Sheet.331 Sheet.333 S_TRI_STATE_EN S_TRI_STATE_EN Sheet.334 Sheet.335 Sheet.336 Sheet.337 Sheet.338 Sheet.339 Sheet.340 Sheet.341 Sheet.342 Sheet.343 Sheet.344 Sheet.345 Sheet.346 Sheet.347 Sheet.348 Sheet.349 Sheet.350 Sheet.351 Sheet.352 Sheet.353 Sheet.354 Sheet.369 Sheet.370 Sheet.371 Sheet.372 Sheet.373 Sheet.374 Sheet.375 Sheet.376 Sheet.377 Sheet.378 Sheet.379 Sheet.380 Sheet.388 Sheet.389 Sheet.391 Sheet.392 Sheet.393 Sheet.394 Sheet.395 S_TRI_STATE_DIS S_TRI_STATE_DIS Sheet.404 Sheet.401 Sheet.402 Sheet.405 Sheet.406 Sheet.407 Sheet.408 Sheet.409 Sheet.410 Sheet.411 Sheet.412 Sheet.413 Sheet.414 Sheet.415 Sheet.416 Sheet.417 Sheet.423 Sheet.424 Sheet.425 Sheet.426 Sheet.427 Sheet.428 Sheet.429 Sheet.430 Sheet.431 Sheet.433 Sheet.434 Sheet.435 Sheet.436 Sheet.437 Sheet.438 Sheet.439 Sheet.440 Sheet.441 Sheet.442 Sheet.443 Sheet.444 Sheet.445 Table : SPI slave timing characteristics | Parameter | Comments | Min | Max | Unit | | --- | --- | --- | --- | --- | | T (SPI clock period) | 50 MHz maximum | 20.0 | – | ns | | t(ch) | Clock high | 9 | – | ns | | t(cl) | Clock low | 9 | – | ns | | t(sov) | Slave output valid | 2 | 13 | ns | | t(sis) | Slave input setup | 3 | – | ns | | t(sih) | Slave input hold | 3 | – | ns | | S\_TRI\_STATE\_EN [^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic.dita_a678a566-b007-4121-8b9b-f0bd624f07c5__fn_n4s_dk1_3yb_sbannadi_08-02-23-1211-10-42) | Slave tri-state enable | – | 14 | ns | | S\_TRI\_STATE\_DIS [^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic.dita_a678a566-b007-4121-8b9b-f0bd624f07c5__fn_n4s_dk1_3yb_sbannadi_08-02-23-1211-10-42) | Slave tri-state disable | – | 14 | ns | ^2^ The total capacitive load must not exceed 30 pF for a single slave system. For each additional slave, 10 pF should be added to the clock and data lines (not needed for chip select since it is one-to-one). For example, 40 pF for two slaves, although most systems have only a single slave. Care must be taken to verify that every slave can drive the data line fast enough to meet the timing requirement or the system must use a reduced frequency. Note: Only SPI slave mode 1 (PHA = 1 and POL = 0) is supported. ### CAN-FD-interface Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) QCS8275 supports up to four CAN-FD interfaces multiplexed through RTSS\_IOs in the RTSS domain. For voltage characteristics, see [Table : DC specification of 1.8 V I/Os](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1__table_1). CAN-FD supports data rates up to 10 Mbps. For information about supported lower data rates, contact QTI. Table : Supported CAN-FD standards and exceptions | Applicable standard | Feature exception | | --- | :---: | | *ISO 11898-1: 2015, Road vehicles, Controller area network (CAN)* | None | | *ISO 11898-4, Road vehicles, Controller area network (CAN)* | None | ### Secured digital interfaces Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) The supported secure digital (SD) interface standards and their exceptions are listed here. Table : Supported SD standards and exceptions | Applicable standard | Feature exceptions | | :---: | :---: | | *MultiMediaCard Host Specification version 5.1* | None | | *Secure Digital: Physical Layer Specification version 3.0* | None | | *SDIO Card Specification version 3.0* | None | | Function | Bits | I/O voltage | Vector name | Frequency | | --- | --- | --- | --- | --- | | eMMC | 8 | 1.8 V | HS400 | 192 MHz | | eMMC | 8 | 1.8 V | HS200 | 192 MHz | | eMMC | 8 | 1.8 V | HSSDR (SDR25) | 52 MHz | | eMMC | 8 | 1.8 V | HSDDR (DDR50) | 52 MHz | | SD | 4 | 1.8 V | SDR50 | 100 MHz | | | | | | | | | | | | | | | | | | | Figure : Single data rate – SDR mode Page-1 Sheet.1 Figure : Double data rate – DDR mode Page-1 Sheet.1 Figure : HS400 mode input timing Page-1 Sheet.1 Figure : HS400 mode output timing Page-1 Sheet.1 | SDCC modes | Frequency | Parameter | Description | Minimum (ns) | Maximum (ns) | | --- | --- | --- | --- | --- | --- | | HS400



(DDR 200 MHz) | 192 MHz | Tclhigh | Clock high time | 2.3437 | 2.8646 | | HS400



(DDR 200 MHz) | 192 MHz | tRQ | DQS to DQ valid setup | 0.4 | – | | HS400



(DDR 200 MHz) | 192 MHz | tRQH | DQS to DQ valid hold | 0.4 | – | | HS400



(DDR 200 MHz) | 192 MHz | tCIDV | Command input valid window | 2.4 | – | | HS400



(DDR 200 MHz) | 192 MHz | tCODLY | Command output delay | -1.45 | 0.85 | | HS400



(DDR 200 MHz) | 192 MHz | tIDV | Data input valid window | 1.7 | – | | HS400



(DDR 200 MHz) | 192 MHz | tODLY | Data output delay | 0.4 | 1.85 | | HS200



(SDR 200 MHz) | 192 MHz | Tclhigh | Clock high time | 2.3437 | 2.8646 | | HS200



(SDR 200 MHz) | 192 MHz | tCIDV | Command input valid window | 2.4 | – | | HS200



(SDR 200 MHz) | 192 MHz | tCODLY | Command output delay | -1.45 | 0.85 | | HS200



(SDR 200 MHz) | 192 MHz | tIDV | Data input valid window | 1.7 | – | | HS200



(SDR 200 MHz) | 192 MHz | tODLY | Data output delay | -1.45 | 0.85 | | HSDDR



(DDR 50) | 52 MHz | Tclhigh | Clock high time | 9 | 11 | | HSDDR



(DDR 50) | 52 MHz | tCIS | Command input setup | 6.3 | – | | HSDDR



(DDR 50) | 52 MHz | tCIH | Command input hold | 1.5 | – | | HSDDR



(DDR 50) | 52 MHz | tCODLY | Command output delay | -8.2 | 3 | | HSDDR



(DDR 50) | 52 MHz | tIS | Data input setup | 2 | – | | HSDDR



(DDR 50) | 52 MHz | tIH | Data input hold | 1.5 | – | | HSDDR



(DDR 50) | 52 MHz | tODLY | Data output delay | 0.8 | 6 | | HSSDR



(SDR25) | 52 MHz | Tclhigh | Clock high time | 9 | 11 | | HSSDR



(SDR25) | 52 MHz | tCIS | Command input setup | 6.3 | – | | HSSDR



(SDR25) | 52 MHz | tCIH | Command input hold | 1.5 | – | | HSSDR



(SDR25) | 52 MHz | tCODLY | Command output delay | -8.2 | 3 | | HSSDR



(SDR25) | 52 MHz | tIS | Data input setup | 2 | – | | HSSDR



(SDR25) | 52 MHz | tIH | Data input hold | 1.5 | – | | HSSDR



(SDR25) | 52 MHz | tODLY | Data output delay | -3.7 | 1.5 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SDCC modes | Frequency | Parameter | Description | Minimum (ns) | Maximum (ns) | | --- | --- | --- | --- | --- | --- | | SDR 50 | 100 MHz | Tclhigh | Clock high time | T\*0.45 | T\*0.45 | | SDR 50 | 100 MHz | tCIS | Command input setup | 2.5 | – | | SDR 50 | 100 MHz | tCIH | Command input hold | 1.5 | – | | SDR 50 | 100 MHz | tCODLY | Command output delay | -3.7 | 1.5 | | SDR 50 | 100 MHz | tIS | Data input setup | 2.5 | – | | SDR 50 | 100 MHz | tIH | Data input hold | 1.5 | – | | SDR 50 | 100 MHz | tODLY | Data output delay | -3.7 | 1.5 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ## Internal functions Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) Some internal functions require external interfaces to enable their operation. These include modes and resets, and JTAG functions. ### Modes and resets Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) Mode and reset functions are basic digital I/Os that meet the performance specifications presented in [Digital logic characteristics](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html#topic_1). ### JTAG Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73475-1/topic/electrical-specifications.html) Figure : JTAG interface timing diagram Page-1 Sheet.104 Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.10 Sheet.11 Sheet.12 Sheet.13 Sheet.14 Sheet.15 Sheet.16 Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 Sheet.34 Sheet.35 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 Sheet.44 Sheet.45 Sheet.46 Sheet.47 Sheet.48 Sheet.49 Sheet.50 Sheet.51 Sheet.52 Sheet.53 Sheet.54 Sheet.55 Sheet.56 Sheet.57 Sheet.58 Sheet.59 Sheet.60 Sheet.61 Sheet.62 Sheet.63 Sheet.64 Sheet.65 Sheet.66 Sheet.67 Sheet.68 Sheet.69 Sheet.70 Sheet.71 Sheet.72 Sheet.73 Sheet.74 Sheet.75 Sheet.76 Sheet.77 Sheet.78 Sheet.79 Sheet.80 Sheet.81 Sheet.82 Sheet.83 Sheet.84 Sheet.85 Sheet.86 Sheet.87 Sheet.88 Sheet.89 t(do) t(do) Sheet.90 t(htdi) t(htdi) Sheet.91 t(sutdi) t(sutdi) Sheet.92 t(htms) t(htms) Sheet.93 t(sutms) t(sutms) Sheet.96 t(tckl) t(tckl) Sheet.98 t(tckh) t(tckh) Sheet.99 t(tckcy) t(tckcy) Sheet.100 TCK TCK Sheet.101 TMS TMS Sheet.102 TDI TDI Sheet.103 TDO TDO | Parameter | Parameter | Min | Typ | Max | Unit | | --- | --- | --- | --- | --- | --- | | t(tckcy) | TCK period | 50 | – | – | ns | | t(tckh) | TCK pulse width high | 20 | – | – | ns | | t(tckl) | TCK pulse width low | 20 | – | – | ns | | t(sutms) | TMS input setup time | 5 | – | – | ns | | t(htms) | TMS input hold time | 20 | – | – | ns | | t(sutdi) | TDI input setup time | 5 | – | – | ns | | t(htdi) | TDI input hold time | 20 | – | – | ns | | t(do) | TDO data output delay | – | – | 15 | ns | | t(tckcy) | TCK period | 50 | – | – | ns | Last Published: Jun 29, 2026 [Previous Topic Pin definitions](https://docs.qualcomm.com/bundle/publicresource/80-73475-1/topics/pin-definitions.md) [Next Topic Mechanical information](https://docs.qualcomm.com/bundle/publicresource/80-73475-1/topics/mechanical-information.md)