IVI

# Introduction Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-73475-1/topic/introduction.html) This topic provides the functional block diagram and the device features. Note: Unless otherwise specified, QCS8275 refers to the QCS8275-AA and QCS8275-AC throughout this document. Wherever appropriate, exceptions are specified. ## Functional block diagram Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-73475-1/topic/introduction.html) This functional block diagram shows the overall representation of the subsystems on this chipset. Figure : QCS8275 functional block diagram Note: Only 2 × PMIC (2 × PMM8620AU) is supported, 4 × PMIC support will be available later. Note: - RTSS\_IO (×68): Only the RTSS\_IO\_52 pin is reserved for internal use. - HS-I²S (×3): Two out of the three HS-I²S interfaces are muxed behind the I²S interfaces. - LS-I²S/PCM/TDM (×8): Among the eight LS-I²S interfaces, five are dedicated LS-I²S, two are muxed with HS-I²S, and one dedicated HS-I²S interface reconfigured as an LS-I²S interface. - eMMC and UFS: Cannot co-exist, either eMMC or UFS can be used. ## QCS8275 features Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-73475-1/topic/introduction.html) This table lists the comprehensive features of the QCS8275 chipset and its capabilities. Note: Some of the hardware features integrated within the QCS8275 must be enabled by software. See the latest revision of the applicable software release notes to identify the enabled QCS8275 features. Table : QCS8275 variant feature set comparison | Feature | QCS8275-AA | QCS8275-AC | | --- | --- | --- | | Kryo Prime | 2 × 2.35 GHz | 2 × 2.05 GHz | | Kryo Gold | 2 × 2.1 GHz | 2 × 1.9 GHz | | Kryo Silver | 4 × 1.95 GHz | 4 × 1.8 GHz | | GPU | A623 at 877 MHz | A623 at 599 MHz | | HMX/HVX | 1.2 GHz/1.5 GHz [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/introduction.html#fntarg_1_features) | 672 MHz/960 MHz | [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/introduction.html#fnsrc_1_features) To support HMX/HVX maximum specification, 4 × PMIC configuration is required. ### Processors | Function | Description | | :---: | :---: | | CPU | Kryo Gen 6 CPU subsystem

Dual Kryo Prime cores with 256 kB L2 cache per core targeting up to 2.35 GHz

Dual Kryo Gold cores with 256 kB L2 cache per core targeting up to 2.1 GHz

1 MB shared L3 cache per cluster for Prime cluster and Gold cluster

Quad Kryo Silver cores with 64 kB L2 cache per core targeting up to 1.95 GHz

512 kB shared L3 cache for Silver cluster

| | Digital signal processing | Hexagon Tensor Processor is integrated with Qualcomm Hexagon DSP, quad Hexagon
vector eXtensions (quad-HVX), and dual Hexagon matrix eXtensions (HMX)
co-processors

Common AI processing architecture for machine learning use cases

Matrix co-processors (one HMX-Integer and one HMX-float per Hexagon Tensor
Processor) for deep neural network acceleration

Audio Hexagon DSP dedicated to audio subsystem, targeting up to 1.344 GHz and
with a 2 MB L2/TCM

One general-purpose Hexagon DSP (GPDSP) targeting up to 1.708 GHz and with a 1 MB
L2 cache for advanced audio processing and other use cases

All Hexagon DSPs are cache-based processors with full access to DDR memory | | Real time subsystem |

A subsystem integrated with quad Cortex-R52 CPU

Separated clock and reset input

Dedicated logic/memory voltage domain

Independent booting capability through OSPI interface

| | Always-on system |

Always-on subsystem with always-on processor

Hardware-based resource and power management (RPMh) with hardware accelerators
for voltage control and regulation, clock management, and resource
communication

Four-channel high-speed memory – 3200 MHz LPDDR5 SDRAM (4 × 16‑bit) and
supports up to 32 GB (8 GB per channel)

NOTE: Tested only for 12 GB (2 × 6 GB)

1 MB system cache

| | Other internal memory |

256 kB IMEM

1.5 MB GMEM for graphics

1 MB L2 cache and 8 MB Vector-TCM (vTCM) for each Hexagon Tensor
Processor

| ### External memory | Function | Description | | :---: | :---: | | Via UFS | One UFS 3.1 gear 4 – two lanes for on-board memory (Main domain boot
up device) | | Via eMMC | eMMC interface (Main domain boot up device)

**NOTE**: Either UFS or eMMC can be the primary (Main domain) boot
interface | | Via OSPI/QSPI | NOR flash memory running up to 166 MHz as RTSS domain boot up device | | Via PCIe | NVMe (non-bootable) | ### Multimedia | Function | Description | | --- | --- | | Display | Adreno display processing unit (DPU) 1199 | | Display interface/performance | One 4-lane MIPI DSI with VESA DSC v1.2

D-PHY v1.2: 2.5 Gbps/lane on four lanes per port, 10 Gbps total

C-PHY v1.1: 5.7 Gbps/trio on three trios per port, 17 Gbps total

One DisplayPort (DP) v1.4 at 8.1 Gbps/lane, 32.4 Gbps/port, MST, and VESA DSC
v1.2a and forward error correction (FEC) | | Image processing | Destination scaler, fetch exclusion rectangle, inline rotation, 17 × 17 × 17 3D
LUT (ViG/DSPP), HDR10 improvements WCG, rounded-corner, CCCS to fixed-point | | Compression | UBWC 4.0, DSC v1.2 | | Camera | Qualcomm Spectra 692 ISP | | Performance |

Pixel processing: 2 × IFE + 5 × IFE_L

Data format inputs: 24‑bit HDR RGGB/RCCB/RYYCy/RGBIR, RCCG, YUV
Data format
outputs: 12/10/8 bit Y, 10/8 bit UV; RGB8 in planar or interleaved order

| | Camera interface | Processing features: 24b HDR bayer processing, lens distortion correction,
advanced tone mapping, offset correction, lens roll off correction, bad pixel
correction, directional scalers, color LUTs, color space transform, noise reduction

Three MIPI CSI interfaces are configurable as D-PHY or C-PHY mode

D-PHY v1.2: 2.5 Gbps/lane on four lanes per port, 10 Gbps/port, up to 30 Gbps
total. Each 4-lane port can also be configured as 1-lane + 2-lane ports or
1-lane +1-lane ports

C-PHY v1.2: 10.2 Gbps/trio on three trios per port, 31 Gbps/port, up to
93 Gbps total. Each 3-trio port can also be configured as 1-trio + 2-trio ports,
or three 1-trio ports

| | Video |

Adreno video processing unit (VPU) 623 – fifth-generation UHD video processing
unit

Video decode up to 4k135 (2x 4K at 60 fps or 4x 4K at 30 fps or 8x 1080p at
60 fps or 16x 1080p at 30 fps)

Video encode up to 4k85 (1x 4K at 60 fps or 2x 4K at 30 fps or 4x 1080p at
60 fps or 8x 1080p at 30 fps)

Concurrent UHD60D + UHD30E or 2x (UHD30 decode + UHD30 encode)

Native decode support for AV1, HEVC, H.264, H.265, VP9, MPEG-2 codecs

Native encode support for HEVC, H.264 and H.265

Embedded video analytics (EVA) for optical flow processing and stereo
disparity

| | Graphics |

Adreno graphic processing unit (GPU) 623 targeting up to 877 MHz

Graphics APIs: Vulkan 1.2, OpenGL ES 3.2

Compute APIs: Vulkan 1.2, OpenCL 2.0 FP, Adreno NN direct

| | Low-power audio subsystem (LPASS) |

Dedicated audio LPASS Hexagon DSP with a 2 MB L2/TCM

AI processor (eNPU) to accelerate neural networking use cases

Hardware linear echo cancellation accelerator

One general purpose DSP (GPDSP) to offload audio high-performance use
cases

Up to 8 (5 + 2 + 1)
^² interfaces (pin multiplexed with PCM/TDM interfaces): seven (4 + 2 + 1)
^²
interfaces with two data lanes each; one interface with four data lanes for a
total of 18 (12 + 4 + 2) ^²
data lanes

Three MCLKs up to 512 × 48 kHz (24.576 MHz); clock master or slave independent
of the source of frame sync/word select

Supports two channels of 32‑bit sample up to 384 kHz sample rate, for each
data line

| | PCM/TDM (muxed with LS-I^2^S pins) |

Multi-lane TDM (master and slave capable)

Up to 10 (7 + 3*) interfaces (pin multiplexed with I²S): nine (6 +
3*) interfaces with two data lanes each; one interface with four data lanes

Short, long, and one-slot sync mode

Maximum clock frequency of 24.576 MHz
- Up to 512 bits/frame, 32 bits/slot, 16 slots/interface with 48 kHz sample
  rate

Support TDM interfaces grouping for data synchronization

| | HS-I^2^S |

Three high-speed (up to 73.728 MHz) receive interfaces; two of them are muxed
behind LS-I²S interfaces; all of them can be configured as
LS-I²S interfaces if needed

Two receive-only data lanes per interface; clock and word select in slave
mode

**NOTE**: The additional LS-I^2^S interfaces (muxed with PCM/TDM
pins) are configured from the three dedicated HS-I^2^S interfaces. | ^2^ Five dedicated LS-I^2^S, two muxed with HS-I^2^S, and one dedicated HS-I^2^S reconfigured as LS-I^2^S interface ### Physical interfaces | Interface | Description | | :---: | :---: | | Qualcomm universal peripheral (QUP) serial engines |

17 main domain (MD) GPIO-based QUP SEs: multiplexed serial interface
functions

5 bits for QUP1_SE_2 and 4 bits for each of the other 15 QUP SEs; multiplexed
serial interface functions

Five RTSS domain GPIO-based QUP SEs: 5 bits for QUP0_SE_4 and 4 bits for each
of the other four QUP SEs; multiplexed serial interface functions

| | UART (up to 4 MHz) | UART (64 B FIFO) interface available on all MD and RTSS domains QUP SEs, except
MD QUP0\_SE\_2/3, QUP1\_SE\_2/3 and RTSS QUP0\_SE\_2/3, which also support HS-UART
(128 B FIFO) | | I²C master (up to 1 MHz) | I²C interface available on QUP SEs of MD and RTSS domains, dedicated controller
for each port | | SPI master (up to 50 MHz) | SPI master interfaces are available on all QUP SEs of MD and RTSS
domains except for MD QUP0\_SE\_7 and MD QUP1\_SE\_3 | | SPI slave (up to 50 MHz) | SPI slave interface available on MD QUP0\_SE\_4/5, QUP1\_SE\_4/5, and
RTSS QUP0\_SE\_0/1 | | QSPI | QSPI (up to 100 MHz): QSPI interface is available GPIO [10] – GPIO
[16] | | CCI I²C | Six dedicated I²C interfaces for devices using CSI ports | | USB | Two total USB interfaces

One USB 3.1 Gen 2 – USB0 (HS + SS, support device and host modes)

One USB 2.0 – USB 2 (HS, support device and host modes)

| | PCIe |

One 2-lane PCIe Gen4: PCIe0 (RC + EP)

One 4-lane PCIe Gen4: PCIe1 (RC + EP)

| | RGMII | One RTSS domain RGMII interface with MDIO for Ethernet | | CAN-FD | Four CAN-FD interfaces located in the RTSS domain, each of them supports up to
12 Mbps | | SGMII | One SGMII interface supporting up to 2.5 GbE | ### Configurable GPIOs | Function | Description | | :---: | :---: | | Number of main domain GPIO ports | 133 – GPIO\_0 to GPIO\_132 | | Number of RTSS domain GPIO ports | 68 – RTSS\_IO\_0 to RTSS\_IO\_67 | | Input configurations | Pull-up, pull-down, keeper, or no pull | | Output configurations | Programmable drive current up to 16 mA | | Top-level mode multiplexer | Provides a convenient way to program groups of GPIOs | ### Internal functions | Function | Description | | :---: | :---: | | Security | Crypto: Hardware ECC and RSA (Elliptic-Curve Cryptography), ICE, Crypto engine v5
(CE5), FIPS/CAVP certifiable, RNG (random number generation)

QFPROM: Fuse bits available for OEM use

Access control: Programmable security domain protection and sand-boxing

Secure boot and tools: Secure boot with Sectools 5.4; easy to use tool set

Storage security: Secure file system (SFS); fast trusted storage

TrustZone: Qualcomm® Trusted Execution Environment (QTEE v5.3)

QTEE services: SHE emulation in TEE

ICEMEM: An inline encryption/decryption engine used to protect the
confidentiality of external RAM

Debug: JTAG

Others: Thermal sensors; modes and resets; peripheral subsystem | | PLLs and clocks |

Multiple clock regimes; watchdog and sleep timers

Dedicated 19.2 MHz RTSS_CXO for real time subsystem

19.2 MHz CXO_0 and CXO_1 as clock sources for main domain of the chip

General-purpose outputs: M/N counter and PDM