# Pin definitions Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html) This topic explains the pin assignments of the QCS8275 chipsets. The figure and table within this topic provide details on pinouts, pad attributes, and their corresponding definitions. ## I/O parameter definitions Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html) | Symbol | Description | | --- | --- | | ***Pad type*** | ***Pad type*** | | AI | Analog input (does not include pad circuitry) | | AO | Analog output (does not include pad circuitry) | | B | Bidirectional digital with CMOS input | | DI | Digital input (CMOS) | | DO | Digital output (CMOS) | | H | High-voltage tolerant | | S | Schmitt trigger input | | Z | High impedance (Hi-Z) output | | ***Padpull details for digital I/Os*** | ***Padpull details for digital I/Os*** | | nppdpukp | Programmable pull resistor. The default pull direction is indicated using capital
letters and is a prefix to other programmable options:



NP: pdpukp = default no-pull with programmable options following the colon (:)



PD: nppukp = default pull-down with programmable options following the colon (:)



PU: nppdkp = default pull-up with programmable options following the colon (:)



KP: nppdpu = default keeper with programmable options following the colon (:) | | KP | Contains an internal weak keeper device (keepers cannot drive external
buses) | | NP | Contains no internal pull | | PU | Contains an internal pull-up device | | PD | Contains an internal pull-down device | | ***Pad voltage groupings for baseband circuits*** | ***Pad voltage groupings for baseband circuits*** | | PX\_0 | Pad group 0 for main domain (control signals); 1.8 V | | PX\_1 | Pad group 1 (EBI I/O); 1.1 V | | RTSS\_PX\_0 | Pad group 0 for RTSS domain (control signals); 1.8 V | | PX\_3 | Pad group 3 (most peripherals); 1.8 V | | PX\_7 | Pad group 7 (SDC1- eMMC); 1.8 V | | RTSS\_PX\_3 | Pad group 3 for RTSS domain (most peripherals); 1.8 V | | PX\_9 | Pad group 9 (UFS0\_REF\_CLK and UFS0\_RESET); 1.2 V | | PX\_10 | Pad group 10 (RESERVED); 1.2 V | | PX\_11 | Pad group 11 (CXO); 1.2 V | | RTSS\_PX\_11 | Pad group 11 for RTSS domain (CXO); 1.8 V | ## Pin map Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html) The QCS8275 chipset is available in the FCBGA1326+HS package. A high-level view of the pin assignments is shown in the following figure. For more information on package details and to create printed circuit board (PCB) footprint, see [Mechanical information](https://docs.qualcomm.com/doc/80-73475-1/topic/mechanical-information.html). The [QCS8275 Pin Assignment and GPIO Configuration Spreadsheet (80-73475-1A)](https://docs.qualcomm.com/bundle/80-73475-1A/resource/80-73475-1A.xlsm) lists all QCS8275 pad numbers (in alphanumeric order), pad names, pad voltages, pad types, and functional descriptions. Figure : QCS8275 pin assignments Page-1 Sheet.2 Sheet.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 A NC NC GND EBI1_WC K0_C EBI1_DQ6 EBI1_CA5 GND EBI1_CK_ C EBI1_CA1 EBI1_DQ1 4 GND EBI1_WC K1_T EBI1_DQ1 1 GND EBI2_DQ 3 EBI2_WC K0_T GND EBI2_DQ 7 EBI2_CA 6 GND EBI2_CK _C EBI2_CA1 EBI2_DQ1 4 EBI2_WC K1_C GND NC NC A B NC EBI1_DQ3 EBI1_WC K0_T GND GND EBI1_CA3 EBI1_CK_ T GND GND EBI1_DQ1 5 EBI1_WC K1_C GND EBI1_DQ1 0 EBI2_DQ 2 GND EBI2_WC K0_C GND GND EBI2_CA 3 EBI2_CK _T GND GND GND EBI2_WC K1_T EBI2_DQ1 1 NC B C NC EBI1_DQ1 GND GND EBI1_DQ7 EBI1_DQ5 GND EBI1_CS0 EBI1_CA0 GND GND GND EBI1_DQ9 GND EBI2_DQ1 GND GND EBI2_DQ 6 EBI2_CA 5 GND EBI2_CS 0 EBI2_DQ1 3 EBI2_DQ1 5 GND GND EBI2_DQ 9 NC C Legend D GND GND EBI1_RD QS0_C GND GND EBI1_CA4 EBI1_CA2 GND EBI1_DQ1 3 EBI1_DQ1 2 EBI1_RD QS1_C GND EBI1_DQ8 EBI2_DQ 0 GND EBI2_RD QS0_C EBI2_DQ 4 EBI2_DQ 5 EBI2_CA 4 EBI2_CA 2 EBI2_CS1 GND GND EBI2_RD QS1_C GND GND D Color Net Group E EBI1_DQ0 EBI1_DQ2 EBI1_RD QS0_T EBI1_DMI 0 EBI1_DQ4 EBI1_CA6 GND EBI1_CS1 GND GND EBI1_DMI1 EBI1_RD QS1_T GND GND GND EBI2_RD QS0_T EBI2_DMI 0 GND GND GND GND EBI2_CA 0 EBI2_DQ1 2 EBI2_DMI 1 EBI2_RD QS1_T EBI2_DQ1 0 EBI2_DQ 8 E EBI F GND GND GND GND GND EBI0_CA1 GND EBI0_CA 3 GND GND GND EBI0_DQ1 1 EBI0_DQ 8 EBI3_DQ 0 EBI3_DQ 3 GND GND GND EBI3_CA1 GND EBI3_CA 3 GND GND GND GND GND F PCIE G EBI0_DQ 2 EBI0_DQ 3 EBI0_RD QS0_C EBI0_DQ 7 EBI0_DMI 0 GND EBI0_CS 0 EBI0_CK _C EBI0_CA 5 EBI0_DMI 1 EBI0_DQ1 5 GND GND GND GND GND EBI3_DQ 7 EBI3_DMI 0 EBI3_CA 0 EBI3_CS 0 EBI3_CK _C EBI3_CA 5 EBI3_DMI 1 EBI3_DQ1 5 EBI3_RD QS1_C EBI3_DQ1 1 EBI3_DQ1 0 G USB H GND EBI0_RD QS0_T GND GND EBI0_DQ 5 EBI0_CS1 EBI0_CK _T GND GND GND GND EBI0_RD QS1_T EBI0_DQ 9 EBI3_DQ1 EBI3_RD QS0_T GND GND EBI3_DQ 5 EBI3_CS1 EBI3_CK _T GND GND GND GND EBI3_RD QS1_T GND H GPIO J EBI0_DQ 0 GND GND EBI0_WC K0_C GND GND GND GND EBI0_CA 6 EBI0_DQ1 4 EBI0_WC K1_C EBI0_RD QS1_C EBI0_DQ1 0 GND EBI3_DQ 2 EBI3_RD QS0_C EBI3_WC K0_C GND GND GND GND EBI3_CA 6 EBI3_DQ1 4 EBI3_WC K1_C GND GND EBI3_DQ 8 J Power K GND EBI0_DQ1 EBI0_WC K0_T EBI0_DQ 4 EBI0_DQ 6 EBI0_CA 0 EBI0_CA 2 EBI0_CA 4 EBI0_DQ1 3 EBI0_DQ1 2 EBI0_WC K1_T GND GND GND GND EBI3_WC K0_T EBI3_DQ 4 EBI3_DQ 6 GND EBI3_CA 2 EBI3_CA 4 EBI3_DQ1 3 EBI3_DQ1 2 EBI3_WC K1_T EBI3_DQ 9 GND K GND L REFGEN_ REXT2 GND GND GND EBI01_CA L GND DNC GND GND GND GND VDD_IO_ EBI_PHY VDD_PX1 VDD_PX1 GND VDD_IO_ EBI_PHY VDD_PX1 VDD_PX1 GND GND DNC GND GND EBI23_C AL GND GND DDR_RE SET_N L CSI M USB0_S S_RX_P GND CXO_1 DNC GND VDD_PX1 1 GND VDD_IO_ EBI_PHY VDD_IO_ EBI_PHY VDD_IO_ EBI_PHY VDD_IO_ EBI_PHY VDD_IO_ EBI_PHY VDD_IO_ EBI_PHY VDD_IO_ EBI_PHY VDD_IO_ EBI_PHY VDD_IO_ EBI_PHY VDD_IO_ EBI_PHY VDD_IO_ EBI_PHY VDD_IO_ EBI_PHY GND GND GND GND GND GND GND M DSI N USB0_S S_RX_M GND USB0_S S_TX_P GPIO_7 GPIO_8 VDD_PX 3 VDD_A_ QREFS_T X1_0P9 GND GND GND VDD_A_E BI_PHY GND GND GND VDD_A_E BI_PHY GND GND GND VDD_A_E BI_PHY GND GND GND GND GND GND GND GND N UFS P GND USB0_S S_TX_M GPIO_53 GPIO_2 GND GND GND VDD_A_E BI_PHY VDD_A_E BI_PHY VDD_A_E BI_PHY VDD_A_E BI_PHY VDD_A_E BI_PHY VDD_A_E BI_PHY VDD_A_E BI_PHY VDD_A_E BI_PHY VDD_A_E BI_PHY VDD_A_E BI_PHY VDD_A_E BI_PHY VDD_A_E BI_PHY GND GND GND GND GND UFS0_TX 1_P GND P SDC R USB0_H S_DP GND GND GPIO_1 GPIO_0 DNC VDD_A_E BI_PHY GND GND GND GND VDD_A_E BI_CCPL L_0P9 VDD_A_E BI_CCPL L_0P9 GND GND VDD_A_E BI_CCPL L_0P9 VDD_A_E BI_CCPL L_0P9 GND GND GND UFS0_RX 1_P GND GND UFS0_TX 1_M GND R OTHER T USB0_H S_DM GND GPIO_78 GPIO_79 GND GND DNC GND VDD_D_E BI VDD_D_E BI VDD_D_E BI GND VDD_D_E BI VDD_D_E BI VDD_D_E BI GND VDD_D_E BI VDD_D_E BI VDD_D_E BI GND GND GND UFS0_RX 1_M GND UFS0_TX 0_P UFS0_TX 0_M T U USB1_HS _DM USB1_HS _DP GND GND GND VDD_A_ USBHS_1 _3P1 VDD_A_ USBSS_ 0_CORE GND VDD_NS P_HMX GND VDD_NS P_HMX GND VDD_D_E BI GND GND VDD_D_E BI VDD_D_E BI GND VDD_AP C0 VDD_AP C0 GND GND UFS0_RX 0_P UFS0_RX 0_M GND GND GND U V GND GND PCIE1_TX 3_P PCIE1_TX 3_M VDD_A_ USBHS_1 _CORE VDD_A_ USBSS_ 0_1P2 VDD_NS P_HMX VDD_NS P_HMX VDD_NS P_HMX GND VDD_NS P_HMX VDD_NS P_HMX GND GND VDD_AP C0 VDD_AP C0 THERM_ P GND GND GND EDP0_TX 0_P GND V W GND GND GND PCIE1_TX 2_M GND VDD_A_ USBHS_1 _1P8 VDD_A_ QREFS_1 P2_1 VDD_NS P_HMX GND VDD_MM VDD_MM VDD_CX VDD_AP C0 GND THERM_ M DNC GND GND GND EDP0_TX 0_M GND W Y PCIE1_TX 1_P PCIE1_TX 1_M PCIE1_TX 2_P GND VDD_A_ USBHS_ 0_3P1 GND GND VDD_NS P_HMX VDD_NS P_HMX VDD_MM GND VDD_AP C0 VDD_AP C0 GND DNC GND CXO_0 EDP0_TX 1_M EDP0_TX 1_P Y AA GND PCIE1_TX 0_M GND GND GND VDD_A_ USBHS_ 0_CORE VDD_A_ QREFS_0 P875_1 VDD_NS P_HMX VDD_NS P_HMX GND VDD_CX VDD_CX VDD_AP C0 VDD_AP C0 GND DNC GND UFS0_RE FCLK GND EDP0_TX 2_P GND AA AB GND PCIE1_TX 0_P GND PCIE1_RX 3_M VDD_A_ USBHS_ 0_1P8 GND GND GND VDD_NS P_HMX VDD_MM VDD_CX GND VDD_AP C1 GND GND GND DNC GND UFS0_RE SET_N EDP0_TX 2_M GND AB AC GND GND GND PCIE1_RX 3_P GND VDD_A_ PCIE_1_C ORE VDD_A_ PCIE_1_P LL_1P2 VDD_NS P_HMX VDD_NS P_HMX VDD_NS P_HMX VDD_NS P_HMX GND VDD_MX _C GND VDD_AP C1 VDD_AP C1 GND VDD_AP C0 GND DNC GND DS_EN GND GND GND AC AD PCIE1_RX 1_M GND PCIE1_RX 2_P PCIE1_RX 2_M GND GND VDD_NS P_CX VDD_NS P_CX GND VDD_NS P_HMX VDD_MX _C VDD_MM VDD_AP C1 VDD_AP C0 VDD_AP C0 VDD_A_ UFS_0_C ORE DNC GND SPMI_DA TA EDP0_TX 3_M EDP0_TX 3_P AD AE GND PCIE1_RX 1_P GND PCIE1_RE FCLK_M GND VDD_A_ PCIE_1_C ORE GND GND VDD_MX _C VDD_CX VDD_MX _A GND GND GND VDD_PX 9 SPMI_CL K GND EDP0_AU X_P GND AE AF PCIE1_RX 0_P PCIE1_RX 0_M GND PCIE1_RE FCLK_P VDD_A_ PCIE_1_C ORE VDD_A_ PCIE_1_C ORE VDD_NS P_CX VDD_NS P_CX VDD_MX _C VDD_AP C1 VDD_AP C0 GND VDD_AP C0 VDD_AP C0 VDD_A_ UFS_0_1 P2 GND VDD_A_ QREFS_0 P875_0 PS_HOL D GND EDP0_AU X_M AF AG GND GND GND GND GND GND VDD_NS P_CX VDD_NS P_CX VDD_MX _A VDD_MX _A VDD_MX _A VDD_CX _LPI GND GND VDD_A_E DP_0_C ORE VDD_PX1 1 RESIN_N RESOUT _N GND GND AG AH PCIE0_R X0_M GND PCIE0_T X0_P PCIE0_T X0_M GND GND VDD_NS P_CX VDD_NS P_CX GND VDD_NS P_CX VDD_NS P_CX GND GND GND VDD_CX _LPI GND VDD_CX _LPI VDD_A_E DP_0_1P 2 GND GND SLEEP_C LK GPIO_98 GPIO_97 AH AJ GND PCIE0_R X0_P GND PCIE0_T X1_M GND VDD_A_ PCIE_0_ CORE VDD_A_ PCIE_0_ CORE VDD_NS P_CX GND VDD_NS P_CX GND VDD_CX VDD_MX _A VDD_MX _LPI VDD_CX _LPI GND VDD_CX _LPI GND VDD_PX1 GND GPIO_10 2 GPIO_101 GPIO_10 0 GPIO_99 AJ AK PCIE0_R X1_M PCIE0_R X1_P GND PCIE0_T X1_P GND GND GND VDD_CX VDD_CX VDD_CX VDD_CX VDD_MX _C VDD_MX _C VDD_MX _C VDD_MX _C VDD_MX _LPI VDD_MX _LPI GND VDD_PX 0 GND GND GPIO_10 5 GPIO_10 4 GPIO_10 3 AK AL GND GND GND PCIE0_R EFCLK_P PCIE0_R EFCLK_M VDD_A_ PCIE_0_ CORE VDD_A_ PCIE_0_ PLL_1P2 DNC GND VDD_RT SS_MX VDD_RT SS_MX GND VDD_GF X GND VDD_GF X VDD_MX _C GND VDD_MM VDD_MM GND GND VDD_PX 3 GND GPIO_10 8 GPIO_10 7 GPIO_10 6 GND AL AM GND GND GND GND GND GND DNC VDD_RT SS_MX VDD_RT SS_MX GND VDD_RT SS_MX VDD_MX _C GND GND VDD_MM GND GND GND GND GPIO_111 GPIO_110 GPIO_10 9 AM AN SGMII0_T X_P SGMII0_T X_M SDC1_CM D SDC1_CL K GND GND VDD_A_ SGMII_0_ 0P9 DNC VDD_RT SS_MX VDD_RT SS_MX VDD_RT SS_CX VDD_RT SS_CX VDD_GF X VDD_MM VDD_MM VDD_MM GND GND GND GPIO_115 GPIO_114 GPIO_113 GPIO_112 AN AP SGMII0_R X_P GND SDC1_DA TA_4 GND VDD_PX 7 VDD_A_ SGMII_0_ 1P2 DNC VDD_RT SS_CX GND VDD_RT SS_CX GND VDD_RT SS_CX GND VDD_MM GND VDD_MM GND GND GND GPIO_118 GPIO_117 GPIO_116 AP AR SGMII0_R X_M GND SDC1_DA TA_1 SDC1_RC LK VDD_PX 3 VDD_RT SS_PX3 GND VDD_RT SS_CX VDD_RT SS_CX GND VDD_RT SS_CX VDD_RT SS_CX VDD_GF X GND VDD_GF X VDD_MM VDD_MM GND VDD_MM VDD_MM GND VDD_PX 3 GND GPIO_121 GPIO_12 0 GPIO_119 GND AR AT GND SDC1_DA TA_6 SDC1_DA TA_7 GND VDD_QF PROM_R TSS GND GND GND VDD_RT SS_CX VDD_RT SS_CX GND GND VDD_GF X VDD_GF X GND GND VDD_MM VDD_MM GND GND GND GND GND GPIO_12 4 GPIO_12 3 GPIO_12 2 AT AU SDC1_DA TA_0 SDC1_DA TA_3 SDC1_DA TA_2 SDC1_DA TA_5 GND GND GND VDD_RT SS_CX VDD_RT SS_CX GND GND VDD_RT SS_CX GND GND GND VDD_MM VDD_MM VDD_MM GND VDD_MM GND GND GND GPIO_12 8 GPIO_12 7 GPIO_12 6 GPIO_12 5 AU AV GPIO_16 GPIO_15 GPIO_14 DNC GND GND GND VDD_RT SS_CX GND VDD_RT SS_CX VDD_RT SS_CX VDD_RT SS_CX VDD_GF X VDD_GF X GND VDD_MM GND VDD_MM GND VDD_MM GND GND GND GPIO_131 GPIO_13 0 GPIO_12 9 AV AW GND GPIO_13 GPIO_12 GPIO_11 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GPIO_13 2 GPIO_96 GPIO_95 GND AW AY GPIO_10 GPIO_6 GPIO_5 DNC GND GND GND GND DNC DNC DNC VDD_A_ CSI_0_0 P9 VDD_A_ CSI_1_0P 9 VDD_A_ CSI_2_0 P9 VDD_A_ DSI_0_P LL_0P9 VDD_A_ DSI_0_1P 2 GND GND GND GND GND GND GND GPIO_17 GPIO_18 GPIO_19 AY BA GPIO_4 RTSS_JT AG_TDO RTSS_JT AG_TDI RTSS_JT AG_TMS GND GND GND GND DNC DNC DNC GND VDD_A_ CSI_0_1P 2 VDD_A_ CSI_1_1P 2 VDD_A_ CSI_2_1P 2 VDD_A_ DSI_0_0 P9 GND GND GND GND GND GND GND GPIO_20 GPIO_39 GPIO_38 GPIO_37 BA BB RTSS_JT AG_TCK RTSS_JT AG_TRS T_N RTSS_JT AG_SRS T_N GND GND GND GND GND VDD_QF PROM GND VDD_QF PROM GND GND GND GND GND GND VDD_PX 3 GND VDD_PX 3 GND GND GND GPIO_40 GPIO_77 GPIO_3 BB BC GND RTSS_IO _67 RTSS_IO _66 RTSS_IO _65 GND GND GND VDD_RT SS_PX11 VDD_RT SS_PX3 GND VDD_RT SS_PX3 VDD_RT SS_PX0 GND GND GND GND GND GND GND GND GND GND GND GPIO_9 GPIO_56 GPIO_93 GND BC BD RTSS_IO _64 RTSS_IO _63 RTSS_IO _62 GND GND GND GND VDD_PX 3 GND VDD_PX 3 GND GND GND VDD_A_ REFGEN_ 0P875_3 VDD_A_ REFGEN_ 1P2_3 GND GND GND GND GND GND GND GND GPIO_67 GPIO_68 GPIO_69 BD BE RTSS_IO _61 RTSS_IO _60 RTSS_IO _59 RTSS_IO _57 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GPIO_43 GPIO_44 GPIO_23 GPIO_21 BE BF RTSS_IO _56 RTSS_IO _29 RTSS_IO _35 RTSS_IO _6 GND GND GND GND DNC RTSS_P S_HOLD GPIO_60 GPIO_58 GPIO_65 DNC GPIO_71 GPIO_36 GPIO_92 GPIO_89 GPIO_30 DNC GPIO_45 GPIO_86 GPIO_52 GPIO_22 GPIO_24 GPIO_76 BF BG GND RTSS_IO _28 RTSS_IO _33 RTSS_IO _34 RTSS_IO _2 RTSS_IO _15 RTSS_IO _42 RTSS_IO _48 RTSS_IO _55 RTSS_M ODE_0 RTSS_RE SIN_N GPIO_59 GPIO_75 GPIO_64 GPIO_72 GPIO_62 GPIO_34 GPIO_90 GPIO_31 GPIO_42 GPIO_47 GPIO_87 GPIO_84 GPIO_50 GPIO_66 GPIO_94 GND BG BH RTSS_IO _26 RTSS_IO _27 RTSS_IO _32 RTSS_IO _7 RTSS_IO _18 RTSS_IO _38 RTSS_IO _45 RTSS_IO _54 RTSS_IO _19 RTSS_RE SOUT_N MD_PS_ HOLD GPIO_57 GPIO_73 GPIO_63 GPIO_70 GPIO_35 GPIO_91 GPIO_32 GPIO_29 GPIO_48 GPIO_88 GPIO_85 GPIO_51 GPIO_25 GPIO_54 GPIO_55 BH BJ RTSS_IO _25 RTSS_IO _24 RTSS_IO _30 RTSS_IO _31 RTSS_IO _3 RTSS_IO _16 RTSS_IO _41 RTSS_IO _47 RTSS_IO _58 RTSS_M ODE_1 GND GND GPIO_74 GND GND GPIO_61 GPIO_33 GND GND GPIO_41 GPIO_46 GND GND GPIO_49 GPIO_26 GPIO_27 GPIO_28 BJ BK RTSS_IO _23 RTSS_IO _22 RTSS_IO _21 RTSS_IO _10 RTSS_IO _0 RTSS_IO _37 RTSS_IO _44 RTSS_IO _50 RTSS_IO _20 GND CSI0_B1_ LN1_M GND CSI0_NC _CLK_P CSI1_B2_ LN3_P GND GND GND CSI2_B1_ LN1_M REFGEN_ REXT3 GND GND DSI0_C1_ CLK_M GND GND GPIO_81 GPIO_80 BK BL NC RTSS_IO _36 RTSS_IO _9 RTSS_IO _12 RTSS_IO _4 RTSS_IO _17 RTSS_IO _40 RTSS_IO _46 RTSS_IO _51 GND CSI0_A2 _LN2_M CSI0_A1_ LN1_P CSI0_B0 _LN0_P CSI1_C2_ LN3_M CSI1_C1_ LN2_P GND CSI1_NC_ CLK_P CSI2_A2 _LN2_M CSI2_A1_ LN1_P GND CSI2_A0 _CLK_M DSI0_B2 _LN2_M DSI0_B1_ CLK_P DSI0_C0 _LN1_P GND GPIO_82 NC BL BM NC RTSS_C XO RTSS_IO _13 RTSS_IO _11 RTSS_IO _1 RTSS_IO _14 RTSS_IO _43 RTSS_IO _49 RTSS_IO _52 CSI0_C2 _LN3_M CSI0_C1_ LN2_P CSI0_C0 _LN0_M CSI0_A0 _CLK_M CSI1_A2_ LN2_M CSI1_A1_ LN1_P CSI1_B0_ LN0_P CSI2_C2 _LN3_M CSI2_C1_ LN2_P GND CSI2_B0 _LN0_P DSI0_NC _LN3_M DSI0_A2 _LN2_P DSI0_A1_ LN1_M DSI0_A0 _LN0_P GPIO_83 NC BM BN NC NC RTSS_IO _8 GND RTSS_IO _5 GND RTSS_IO _39 GND RTSS_IO _53 GND CSI0_B2 _LN3_P GND GND GND CSI1_B1_ LN1_M CSI1_C0_ LN0_M CSI1_A0_ CLK_M CSI2_B2 _LN3_P GND CSI2_C0 _LN0_M CSI2_NC _CLK_P DSI0_C2 _LN3_P GND DSI0_B0 _LN0_M GND NC NC BN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 ## Pin descriptions Source: [https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html) The following table describes the pin functions, pin pull types, and pin voltages. It also provides a mapping of pin numbers and pin names for all the pins on the device. These include general pins, GPIO pins, and power pins. | Pin number | Pin name | Pad characteristics[^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#fntarg_1_pin-descriptions) | Pad characteristics[^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#fntarg_1_pin-descriptions) | Functional description | | --- | --- | --- | --- | --- | | Pin number | Pin name | Voltage | Type | Functional description | | BM26 | CSI0\_A0\_CLK\_M | CSI | AI | MIPI CSI0 (D-PHY), differential clock – minus | | BM26 | CSI0\_A0\_CLK\_M | CSI | AI | MIPI CSI0 (C-PHY), trio lane 0 – A | | BL23 | CSI0\_A1\_LN1\_P | CSI | AI | MIPI CSI0 (D-PHY), differential lane 1 – plus | | BL23 | CSI0\_A1\_LN1\_P | CSI | AI | MIPI CSI0 (C-PHY), trio lane 1 – A | | BL21 | CSI0\_A2\_LN2\_M | CSI | AI | MIPI CSI0 (D-PHY), differential lane 2 – minus | | BL21 | CSI0\_A2\_LN2\_M | CSI | AI | MIPI CSI0 (C-PHY), trio lane 2 – A | | BL25 | CSI0\_B0\_LN0\_P | CSI | AI | MIPI CSI0 (D-PHY), differential lane 0 – plus | | BL25 | CSI0\_B0\_LN0\_P | CSI | AI | MIPI CSI0 (C-PHY), trio lane 0 – B | | BK22 | CSI0\_B1\_LN1\_M | CSI | AI | MIPI CSI0 (D-PHY), differential lane 1 – minus | | BK22 | CSI0\_B1\_LN1\_M | CSI | AI | MIPI CSI0 (C-PHY), trio lane 1 – B | | BN21 | CSI0\_B2\_LN3\_P | CSI | AI | MIPI CSI0 (D-PHY), differential lane 3 – plus | | BN21 | CSI0\_B2\_LN3\_P | CSI | AI | MIPI CSI0 (C-PHY), trio lane 2 – B | | BM24 | CSI0\_C0\_LN0\_M | CSI | AI | MIPI CSI0 (D-PHY), differential lane 0 – minus | | BM24 | CSI0\_C0\_LN0\_M | CSI | AI | MIPI CSI0 (C-PHY), trio lane 0 – C | | BM22 | CSI0\_C1\_LN2\_P | CSI | AI | MIPI CSI0 (D-PHY), differential lane 2 – plus | | BM22 | CSI0\_C1\_LN2\_P | CSI | AI | MIPI CSI0 (C-PHY), trio lane 1 – C | | BM20 | CSI0\_C2\_LN3\_M | CSI | AI | MIPI CSI0 (D-PHY), differential lane 3 – minus | | BM20 | CSI0\_C2\_LN3\_M | CSI | AI | MIPI CSI0 (C-PHY), trio lane 2 – C | | BK26 | CSI0\_NC\_CLK\_P | CSI | AI | MIPI CSI0 (D-PHY), differential clock – plus | | BK26 | CSI0\_NC\_CLK\_P | CSI | AI | MIPI CSI0 (C-PHY), no connect | | BN33 | CSI1\_A0\_CLK\_M | CSI | AI | MIPI CSI1 (D-PHY), differential clock – minus | | BN33 | CSI1\_A0\_CLK\_M | CSI | AI | MIPI CSI0 (C-PHY), no connect | | BM30 | CSI1\_A1\_LN1\_P | CSI | AI | MIPI CSI1 (D-PHY), differential lane 1 – plus | | BM30 | CSI1\_A1\_LN1\_P | CSI | AI | MIPI CSI1 (C-PHY), trio lane 1 – A | | BM28 | CSI1\_A2\_LN2\_M | CSI | AI | MIPI CSI1 (D-PHY), differential lane 2 – minus | | BM28 | CSI1\_A2\_LN2\_M | CSI | AI | MIPI CSI1 (C-PHY), trio lane 2 – A | | BM32 | CSI1\_B0\_LN0\_P | CSI | AI | MIPI CSI1 (D-PHY), differential lane 0 – plus | | BM32 | CSI1\_B0\_LN0\_P | CSI | AI | MIPI CSI1 (C-PHY), trio lane 0 – B | | BN29 | CSI1\_B1\_LN1\_M | CSI | AI | MIPI CSI1 (D-PHY), differential lane 1 – minus | | BN29 | CSI1\_B1\_LN1\_M | CSI | AI | MIPI CSI1 (C-PHY), trio lane 1 – B | | BK28 | CSI1\_B2\_LN3\_P | CSI | AI | MIPI CSI1 (D-PHY), differential lane 3 – plus | | BK28 | CSI1\_B2\_LN3\_P | CSI | AI | MIPI CSI1 (C-PHY), trio lane 2 – B | | BN31 | CSI1\_C0\_LN0\_M | CSI | AI | MIPI CSI1 (D-PHY), differential lane 0 – minus | | BN31 | CSI1\_C0\_LN0\_M | CSI | AI | MIPI CSI1 (C-PHY), trio lane 0 – C | | BL29 | CSI1\_C1\_LN2\_P | CSI | AI | MIPI CSI1 (D-PHY), differential lane 2 – plus | | BL29 | CSI1\_C1\_LN2\_P | CSI | AI | MIPI CSI1 (C-PHY), trio lane 1 – C | | BL27 | CSI1\_C2\_LN3\_M | CSI | AI | MIPI CSI1 (D-PHY), differential lane 3 – minus | | BL27 | CSI1\_C2\_LN3\_M | CSI | AI | MIPI CSI1 (C-PHY), trio lane 2 – C | | BL33 | CSI1\_NC\_CLK\_P | CSI | AI | MIPI CSI1 (D-PHY), differential clock – plus | | BL33 | CSI1\_NC\_CLK\_P | CSI | AI | MIPI CSI1 (C-PHY), no connect | | BL41 | CSI2\_A0\_CLK\_M | CSI | AI | MIPI CSI2 (D-PHY), differential clock – minus | | BL41 | CSI2\_A0\_CLK\_M | CSI | AI | MIPI CSI2 (C-PHY), trio lane 0 – A | | BL37 | CSI2\_A1\_LN1\_P | CSI | AI | MIPI CSI2 (D-PHY), differential lane 1 – plus | | BL37 | CSI2\_A1\_LN1\_P | CSI | AI | MIPI CSI2 (C-PHY), trio lane 1 – A | | BL35 | CSI2\_A2\_LN2\_M | CSI | AI | MIPI CSI2 (D-PHY), differential lane 2 – minus | | BL35 | CSI2\_A2\_LN2\_M | CSI | AI | MIPI CSI2 (C-PHY), trio lane 2 – A | | BM40 | CSI2\_B0\_LN0\_P | CSI | AI | MIPI CSI2 (D-PHY), differential lane 0 – plus | | BM40 | CSI2\_B0\_LN0\_P | CSI | AI | MIPI CSI2 (C-PHY), trio lane 0 – B | | BK36 | CSI2\_B1\_LN1\_M | CSI | AI | MIPI CSI2 (D-PHY), differential lane 1 – minus | | BK36 | CSI2\_B1\_LN1\_M | CSI | AI | MIPI CSI2 (C-PHY), trio lane 1 – B | | BN35 | CSI2\_B2\_LN3\_P | CSI | AI | MIPI CSI2 (D-PHY), differential lane 3 – plus | | BN35 | CSI2\_B2\_LN3\_P | CSI | AI | MIPI CSI2 (C-PHY), trio lane 2 – B | | BN39 | CSI2\_C0\_LN0\_M | CSI | AI | MIPI CSI2 (D-PHY), differential lane 0 – minus | | BN39 | CSI2\_C0\_LN0\_M | CSI | AI | MIPI CSI2 (C-PHY), trio lane 0 – C | | BM36 | CSI2\_C1\_LN2\_P | CSI | AI | MIPI CSI2 (D-PHY), differential lane 2 – plus | | BM36 | CSI2\_C1\_LN2\_P | CSI | AI | MIPI CSI2 (C-PHY), trio lane 1 – C | | BM34 | CSI2\_C2\_LN3\_M | CSI | AI | MIPI CSI2 (D-PHY), differential lane 3 – minus | | BM34 | CSI2\_C2\_LN3\_M | CSI | AI | MIPI CSI2 (C-PHY), trio lane 2 – C | | BN41 | CSI2\_NC\_CLK\_P | CSI | AI | MIPI CSI2 (D-PHY), differential clock – plus | | BN41 | CSI2\_NC\_CLK\_P | CSI | AI | MIPI CSI2 (C-PHY), no connect | | Y48 | CXO\_0 | PX\_11 | DI | Core crystal oscillator 0 | | M6 | CXO\_1 | PX\_11 | DI | Core crystal oscillator 1 | | L53 | DDR\_RESET\_N | PX\_1 | DO | LPDDR5 reset (shared by EBIs) | | BM48 | DSI0\_A0\_LN0\_P | DSI | AO | MIPI DSI0 (D-PHY), differential lane 0 – plus | | BM48 | DSI0\_A0\_LN0\_P | DSI | AO | MIPI DSI0 (C-PHY), trio lane 0 – A | | BM46 | DSI0\_A1\_LN1\_M | DSI | AO | MIPI DSI0 (D-PHY), differential lane 1 – minus | | BM46 | DSI0\_A1\_LN1\_M | DSI | AO | MIPI DSI0 (C-PHY), trio lane 1 – A | | BM44 | DSI0\_A2\_LN2\_P | DSI | AO | MIPI DSI0 (D-PHY), differential lane 2 – plus | | BM44 | DSI0\_A2\_LN2\_P | DSI | AO | MIPI DSI0 (C-PHY), trio lane 2 – A | | BN47 | DSI0\_B0\_LN0\_M | DSI | AO | MIPI DSI0 (D-PHY), differential lane 0 – minus | | BN47 | DSI0\_B0\_LN0\_M | DSI | AO | MIPI DSI0 (C-PHY), trio lane 0 – B | | BL45 | DSI0\_B1\_CLK\_P | DSI | AO | MIPI DSI0 (D-PHY), differential clock – plus | | BL45 | DSI0\_B1\_CLK\_P | DSI | AO | MIPI DSI0 (C-PHY), trio lane 1 – B | | BL43 | DSI0\_B2\_LN2\_M | DSI | AO | MIPI DSI0 (D-PHY), differential lane 2 – minus | | BL43 | DSI0\_B2\_LN2\_M | DSI | AO | MIPI DSI0 (C-PHY), trio lane 2 – B | | BL47 | DSI0\_C0\_LN1\_P | DSI | AO | MIPI DSI0 (D-PHY), differential lane 1 – plus | | BL47 | DSI0\_C0\_LN1\_P | DSI | AO | MIPI DSI0 (C-PHY), trio lane 0 – C | | BK44 | DSI0\_C1\_CLK\_M | DSI | AO | MIPI DSI0 (D-PHY), differential clock – minus | | BK44 | DSI0\_C1\_CLK\_M | DSI | AO | MIPI DSI0 (C-PHY), trio lane 1 – C | | BN43 | DSI0\_C2\_LN3\_P | DSI | AO | MIPI DSI0 (D-PHY), differential lane 3 – plus | | BN43 | DSI0\_C2\_LN3\_P | DSI | AO | MIPI DSI0 (C-PHY), trio lane 2 – C | | BM42 | DSI0\_NC\_LN3\_M | DSI | AO | MIPI DSI0 (D-PHY), differential lane 3 – minus | | BM42 | DSI0\_NC\_LN3\_M | DSI | AO | MIPI DSI0 (C-PHY), no connect | | AC47 | DS\_EN | PX\_0 | DI | Deep sleep signal | | L9 | EBI01\_CAL | EBI | DO | EBI01 calibration resistor | | K12 | EBI0\_CA0 | EBI | DO | EBI0 LPDDR5 command/address bit 0 | | F12 | EBI0\_CA1 | EBI | DO | EBI0 LPDDR5 command/address bit 1 | | K14 | EBI0\_CA2 | EBI | DO | EBI0 LPDDR5 command/address bit 2 | | F16 | EBI0\_CA3 | EBI | DO | EBI0 LPDDR5 command/address bit 3 | | K16 | EBI0\_CA4 | EBI | DO | EBI0 LPDDR5 command/address bit 4 | | G17 | EBI0\_CA5 | EBI | DO | EBI0 LPDDR5 command/address bit 5 | | J17 | EBI0\_CA6 | EBI | DO | EBI0 LPDDR5 command/address bit 6 | | G15 | EBI0\_CK\_C | EBI | DO | EBI0 LPDDR5 differential clock (C) | | H14 | EBI0\_CK\_T | EBI | DO | EBI0 LPDDR5 differential clock (T) | | G13 | EBI0\_CS0 | EBI | DO | EBI0 LPDDR5 chip-select 0 | | H12 | EBI0\_CS1 | EBI | DO | EBI0 LPDDR5 chip-select 1 | | G9 | EBI0\_DMI0 | EBI | B | EBI0 LPDDR5 data mask for byte 0 | | G19 | EBI0\_DMI1 | EBI | B | EBI0 LPDDR5 data mask for byte 1 | | J1 | EBI0\_DQ0 | EBI | B | EBI0 LPDDR5 data bit 0 | | K4 | EBI0\_DQ1 | EBI | B | EBI0 LPDDR5 data bit 1 | | J25 | EBI0\_DQ10 | EBI | B | EBI0 LPDDR5 data bit 10 | | F24 | EBI0\_DQ11 | EBI | B | EBI0 LPDDR5 data bit 11 | | K20 | EBI0\_DQ12 | EBI | B | EBI0 LPDDR5 data bit 12 | | K18 | EBI0\_DQ13 | EBI | B | EBI0 LPDDR5 data bit 13 | | J19 | EBI0\_DQ14 | EBI | B | EBI0 LPDDR5 data bit 14 | | G21 | EBI0\_DQ15 | EBI | B | EBI0 LPDDR5 data bit 15 | | G1 | EBI0\_DQ2 | EBI | B | EBI0 LPDDR5 data bit 2 | | G3 | EBI0\_DQ3 | EBI | B | EBI0 LPDDR5 data bit 3 | | K8 | EBI0\_DQ4 | EBI | B | EBI0 LPDDR5 data bit 4 | | H10 | EBI0\_DQ5 | EBI | B | EBI0 LPDDR5 data bit 5 | | K10 | EBI0\_DQ6 | EBI | B | EBI0 LPDDR5 data bit 6 | | G7 | EBI0\_DQ7 | EBI | B | EBI0 LPDDR5 data bit 7 | | F26 | EBI0\_DQ8 | EBI | B | EBI0 LPDDR5 data bit 8 | | H26 | EBI0\_DQ9 | EBI | B | EBI0 LPDDR5 data bit 9 | | G5 | EBI0\_RDQS0\_C | EBI | B | EBI0 LPDDR5 differential read data strobe for byte 0 (C) | | H4 | EBI0\_RDQS0\_T | EBI | B | EBI0 LPDDR5 differential read data strobe for byte 0 (T) | | J23 | EBI0\_RDQS1\_C | EBI | B | EBI0 LPDDR5 differential read data strobe for byte 1 (C) | | H24 | EBI0\_RDQS1\_T | EBI | B | EBI0 LPDDR5 differential read data strobe for byte 1 (T) | | J7 | EBI0\_WCK0\_C | EBI | DO | EBI0 LPDDR5 differential data clock for byte 0 (C) | | K6 | EBI0\_WCK0\_T | EBI | DO | EBI0 LPDDR5 differential data clock for byte 0 (T) | | J21 | EBI0\_WCK1\_C | EBI | DO | EBI0 LPDDR5 differential data clock for byte 1 (C) | | K22 | EBI0\_WCK1\_T | EBI | DO | EBI0 LPDDR5 differential data clock for byte 1 (T) | | C17 | EBI1\_CA0 | EBI | DO | EBI1 LPDDR5 command/address bit 0 | | A17 | EBI1\_CA1 | EBI | DO | EBI1 LPDDR5 command/address bit 1 | | D14 | EBI1\_CA2 | EBI | DO | EBI1 LPDDR5 command/address bit 2 | | B12 | EBI1\_CA3 | EBI | DO | EBI1 LPDDR5 command/address bit 3 | | D12 | EBI1\_CA4 | EBI | DO | EBI1 LPDDR5 command/address bit 4 | | A11 | EBI1\_CA5 | EBI | DO | EBI1 LPDDR5 command/address bit 5 | | E11 | EBI1\_CA6 | EBI | DO | EBI1 LPDDR5 command/address bit 6 | | A15 | EBI1\_CK\_C | EBI | DO | EBI1 LPDDR5 differential clock (C) | | B14 | EBI1\_CK\_T | EBI | DO | EBI1 LPDDR5 differential clock (T) | | C15 | EBI1\_CS0 | EBI | DO | EBI1 LPDDR5 chip-select 0 | | E15 | EBI1\_CS1 | EBI | DO | EBI1 LPDDR5 chip-select 1 | | E7 | EBI1\_DMI0 | EBI | B | EBI1 LPDDR5 data mask for byte 0 | | E21 | EBI1\_DMI1 | EBI | B | EBI1 LPDDR5 data mask for byte 1 | | E1 | EBI1\_DQ0 | EBI | B | EBI1 LPDDR5 data bit 0 | | C3 | EBI1\_DQ1 | EBI | B | EBI1 LPDDR5 data bit 1 | | B26 | EBI1\_DQ10 | EBI | B | EBI1 LPDDR5 data bit 10 | | A25 | EBI1\_DQ11 | EBI | B | EBI1 LPDDR5 data bit 11 | | D20 | EBI1\_DQ12 | EBI | B | EBI1 LPDDR5 data bit 12 | | D18 | EBI1\_DQ13 | EBI | B | EBI1 LPDDR5 data bit 13 | | A19 | EBI1\_DQ14 | EBI | B | EBI1 LPDDR5 data bit 14 | | B20 | EBI1\_DQ15 | EBI | B | EBI1 LPDDR5 data bit 15 | | E3 | EBI1\_DQ2 | EBI | B | EBI1 LPDDR5 data bit 2 | | B4 | EBI1\_DQ3 | EBI | B | EBI1 LPDDR5 data bit 3 | | E9 | EBI1\_DQ4 | EBI | B | EBI1 LPDDR5 data bit 4 | | C11 | EBI1\_DQ5 | EBI | B | EBI1 LPDDR5 data bit 5 | | A9 | EBI1\_DQ6 | EBI | B | EBI1 LPDDR5 data bit 6 | | C9 | EBI1\_DQ7 | EBI | B | EBI1 LPDDR5 data bit 7 | | D26 | EBI1\_DQ8 | EBI | B | EBI1 LPDDR5 data bit 8 | | C25 | EBI1\_DQ9 | EBI | B | EBI1 LPDDR5 data bit 9 | | D6 | EBI1\_RDQS0\_C | EBI | B | EBI1 LPDDR5 differential read data strobe for byte 0 (C) | | E5 | EBI1\_RDQS0\_T | EBI | B | EBI1 LPDDR5 differential read data strobe for byte 0 (T) | | D22 | EBI1\_RDQS1\_C | EBI | B | EBI1 LPDDR5 differential read data strobe for byte 1 (C) | | E23 | EBI1\_RDQS1\_T | EBI | B | EBI1 LPDDR5 differential read data strobe for byte 1 (T) | | A7 | EBI1\_WCK0\_C | EBI | DO | EBI1 LPDDR5 differential data clock for byte 0 (C) | | B6 | EBI1\_WCK0\_T | EBI | DO | EBI1 LPDDR5 differential data clock for byte 0 (T) | | B22 | EBI1\_WCK1\_C | EBI | DO | EBI1 LPDDR5 differential data clock for byte 1 (C) | | A23 | EBI1\_WCK1\_T | EBI | DO | EBI1 LPDDR5 differential data clock for byte 1 (T) | | L47 | EBI23\_CAL | EBI | DO | EBI23 calibration resistor | | E43 | EBI2\_CA0 | EBI | DO | EBI2 LPDDR5 command/address bit 0 | | A43 | EBI2\_CA1 | EBI | DO | EBI2 LPDDR5 command/address bit 1 | | D40 | EBI2\_CA2 | EBI | DO | EBI2 LPDDR5 command/address bit 2 | | B38 | EBI2\_CA3 | EBI | DO | EBI2 LPDDR5 command/address bit 3 | | D38 | EBI2\_CA4 | EBI | DO | EBI2 LPDDR5 command/address bit 4 | | C37 | EBI2\_CA5 | EBI | DO | EBI2 LPDDR5 command/address bit 5 | | A37 | EBI2\_CA6 | EBI | DO | EBI2 LPDDR5 command/address bit 6 | | A41 | EBI2\_CK\_C | EBI | DO | EBI2 LPDDR5 differential clock (C) | | B40 | EBI2\_CK\_T | EBI | DO | EBI2 LPDDR5 differential clock (T) | | C41 | EBI2\_CS0 | EBI | DO | EBI2 LPDDR5 chip-select 0 | | D42 | EBI2\_CS1 | EBI | DO | EBI2 LPDDR5 chip-select 1 | | E33 | EBI2\_DMI0 | EBI | B | EBI2 LPDDR5 data mask for byte 0 | | E47 | EBI2\_DMI1 | EBI | B | EBI2 LPDDR) data mask for byte 1 | | D28 | EBI2\_DQ0 | EBI | B | EBI2 LPDDR5 data bit 0 | | C29 | EBI2\_DQ1 | EBI | B | EBI2 LPDDR5 data bit 1 | | E51 | EBI2\_DQ10 | EBI | B | EBI2 LPDDR5 data bit 10 | | B50 | EBI2\_DQ11 | EBI | B | EBI2 LPDDR5 data bit 11 | | E45 | EBI2\_DQ12 | EBI | B | EBI2 LPDDR5 data bit 12 | | C43 | EBI2\_DQ13 | EBI | B | EBI2 LPDDR5 data bit 13 | | A45 | EBI2\_DQ14 | EBI | B | EBI2 LPDDR5 data bit 14 | | C45 | EBI2\_DQ15 | EBI | B | EBI2 LPDDR5 data bit 15 | | B28 | EBI2\_DQ2 | EBI | B | EBI2 LPDDR5 data bit 2 | | A29 | EBI2\_DQ3 | EBI | B | EBI2 LPDDR5 data bit 3 | | D34 | EBI2\_DQ4 | EBI | B | EBI2 LPDDR5 data bit 4 | | D36 | EBI2\_DQ5 | EBI | B | EBI2 LPDDR5 data bit 5 | | C35 | EBI2\_DQ6 | EBI | B | EBI2 LPDDR5 data bit 6 | | A35 | EBI2\_DQ7 | EBI | B | EBI2 LPDDR5 data bit 7 | | E53 | EBI2\_DQ8 | EBI | B | EBI2 LPDDR5 data bit 8 | | C51 | EBI2\_DQ9 | EBI | B | EBI2 LPDDR5 data bit 9 | | D32 | EBI2\_RDQS0\_C | EBI | B | EBI2 LPDDR5 differential read data strobe for byte 0 (C) | | E31 | EBI2\_RDQS0\_T | EBI | B | EBI2 LPDDR5 differential read data strobe for byte 0 (T) | | D48 | EBI2\_RDQS1\_C | EBI | B | EBI2 LPDDR5 differential read data strobe for byte 1 (C) | | E49 | EBI2\_RDQS1\_T | EBI | B | EBI2 LPDDR5 differential read data strobe for byte 1 (T) | | B32 | EBI2\_WCK0\_C | EBI | DO | EBI2 LPDDR5 differential data clock for byte 0 (C) | | A31 | EBI2\_WCK0\_T | EBI | DO | EBI2 LPDDR5 differential data clock for byte 0 (T) | | A47 | EBI2\_WCK1\_C | EBI | DO | EBI2 LPDDR5 differential data clock for byte 1 (C) | | B48 | EBI2\_WCK1\_T | EBI | DO | EBI2 LPDDR5 differential data clock for byte 1 (T) | | G37 | EBI3\_CA0 | EBI | DO | EBI3 LPDDR5 command/address bit 0 | | F38 | EBI3\_CA1 | EBI | DO | EBI3 LPDDR5 command/address bit 1 | | K40 | EBI3\_CA2 | EBI | DO | EBI3 LPDDR5 command/address bit 2 | | F42 | EBI3\_CA3 | EBI | DO | EBI3 LPDDR5 command/address bit 3 | | K42 | EBI3\_CA4 | EBI | DO | EBI3 LPDDR5 command/address bit 4 | | G43 | EBI3\_CA5 | EBI | DO | EBI3 LPDDR5 command/address bit 5 | | J43 | EBI3\_CA6 | EBI | DO | EBI3 LPDDR5 command/address bit 6 | | G41 | EBI3\_CK\_C | EBI | DO | EBI3 LPDDR5 differential clock (C) | | H40 | EBI3\_CK\_T | EBI | DO | EBI3 LPDDR5 differential clock (T) | | G39 | EBI3\_CS0 | EBI | DO | EBI3 LPDDR5 chip-select 0 | | H38 | EBI3\_CS1 | EBI | DO | EBI3 LPDDR5 chip-select 1 | | G35 | EBI3\_DMI0 | EBI | B | EBI3 LPDDR5 data mask for byte 0 | | G45 | EBI3\_DMI1 | EBI | B | EBI3 LPDDR5 data mask for byte 1 | | F28 | EBI3\_DQ0 | EBI | B | EBI3 LPDDR5 data bit 0 | | H28 | EBI3\_DQ1 | EBI | B | EBI3 LPDDR5 data bit 1 | | G53 | EBI3\_DQ10 | EBI | B | EBI3 LPDDR5 data bit 10 | | G51 | EBI3\_DQ11 | EBI | B | EBI3 LPDDR5 data bit 11 | | K46 | EBI3\_DQ12 | EBI | B | EBI3 LPDDR5 data bit 12 | | K44 | EBI3\_DQ13 | EBI | B | EBI3 LPDDR5 data bit 13 | | J45 | EBI3\_DQ14 | EBI | B | EBI3 LPDDR5 data bit 14 | | G47 | EBI3\_DQ15 | EBI | B | EBI3 LPDDR5 data bit 15 | | J29 | EBI3\_DQ2 | EBI | B | EBI3 LPDDR5 data bit 2 | | F30 | EBI3\_DQ3 | EBI | B | EBI3 LPDDR5 data bit 3 | | K34 | EBI3\_DQ4 | EBI | B | EBI3 LPDDR5 data bit 4 | | H36 | EBI3\_DQ5 | EBI | B | EBI3 LPDDR5 data bit 5 | | K36 | EBI3\_DQ6 | EBI | B | EBI3 LPDDR5 data bit 6 | | G33 | EBI3\_DQ7 | EBI | B | EBI3 LPDDR5 data bit 7 | | J53 | EBI3\_DQ8 | EBI | B | EBI3 LPDDR5 data bit 8 | | K50 | EBI3\_DQ9 | EBI | B | EBI3 LPDDR5 data bit 9 | | J31 | EBI3\_RDQS0\_C | EBI | B | EBI3 LPDDR5 differential read data strobe for byte 0 (C) | | H30 | EBI3\_RDQS0\_T | EBI | B | EBI3 LPDDR5 differential read data strobe for byte 0 (T) | | G49 | EBI3\_RDQS1\_C | EBI | B | EBI3 LPDDR5 differential read data strobe for byte 1 (C) | | H50 | EBI3\_RDQS1\_T | EBI | B | EBI3 LPDDR5 differential read data strobe for byte 1 (T) | | J33 | EBI3\_WCK0\_C | EBI | DO | EBI3 LPDDR5 differential data clock for byte 0 (C) | | K32 | EBI3\_WCK0\_T | EBI | DO | EBI3 LPDDR5 differential data clock for byte 0 (T) | | J47 | EBI3\_WCK1\_C | EBI | DO | EBI3 LPDDR5 differential data clock for byte 1 (C) | | K48 | EBI3\_WCK1\_T | EBI | DO | EBI3 LPDDR5 differential data clock for byte 1 (T) | | AF52 | EDP0\_AUX\_M | EBI | AO | eDP 0 auxiliary channel | | AE51 | EDP0\_AUX\_P | – | AO | eDP 0 auxiliary channel | | W51 | EDP0\_TX0\_M | – | AO | eDP 0 transmit channel 0 – minus | | V50 | EDP0\_TX0\_P | – | AO | eDP 0 transmit channel 0 – plus | | Y50 | EDP0\_TX1\_M | – | AO | eDP 0 transmit channel 1 – minus | | Y52 | EDP0\_TX1\_P | – | AO | eDP 0 transmit channel 1 – plus | | AB50 | EDP0\_TX2\_M | – | AO | eDP 0 transmit channel 2 – minus | | AA51 | EDP0\_TX2\_P | – | AO | eDP 0 transmit channel 2 – plus | | AD50 | EDP0\_TX3\_M | – | AO | eDP 0 transmit channel 3 – minus | | AD52 | EDP0\_TX3\_P | – | AO | eDP 0 transmit channel 3 – plus | | BH22 | MD\_PS\_HOLD | PX\_3 | DI | The main domain PS\_HOLD is an input and must be connected externally to the SoC
PS\_HOLD signal. | | AL9 | PCIE0\_REFCLK\_M | – | AO | PCIe 0 Gen 3 reference clock – minus | | AL7 | PCIE0\_REFCLK\_P | – | AO | PCIe 0 Gen 3 reference clock – plus | | AH2 | PCIE0\_RX0\_M | – | AI | PCIe 0 Gen 3 receive 0 – minus | | AJ3 | PCIE0\_RX0\_P | – | AI | PCIe 0 Gen 3 receive 0 – plus | | AK2 | PCIE0\_RX1\_M | – | AI | PCIe 0 Gen 3 receive 1 – minus | | AK4 | PCIE0\_RX1\_P | – | AI | PCIe 0 Gen 3 receive 1 – plus | | AH8 | PCIE0\_TX0\_M | – | AO | PCIe 0 Gen 3 transmit 0 – minus | | AH6 | PCIE0\_TX0\_P | – | AO | PCIe 0 Gen 3 transmit 0 – plus | | AJ7 | PCIE0\_TX1\_M | – | AO | PCIe 0 Gen 3 transmit 1 – minus | | AK8 | PCIE0\_TX1\_P | – | AO | PCIe 0 Gen 3 transmit 1 – plus | | AE7 | PCIE1\_REFCLK\_M | – | AO | PCIe 1 Gen 3 reference clock – minus | | AF8 | PCIE1\_REFCLK\_P | – | AO | PCIe 1 Gen 3 reference clock – plus | | AF4 | PCIE1\_RX0\_M | – | AI | PCIe 1 Gen 3 receive 0 – minus | | AF2 | PCIE1\_RX0\_P | – | AI | PCIe 1 Gen 3 receive 0 – plus | | AD2 | PCIE1\_RX1\_M | – | AI | PCIe 1 Gen 3 receive 1 – minus | | AE3 | PCIE1\_RX1\_P | – | AI | PCIe 1 Gen 3 receive 1 – plus | | AD8 | PCIE1\_RX2\_M | – | AI | PCIe 1 Gen 3 receive 2 – minus | | AD6 | PCIE1\_RX2\_P | – | AI | PCIe 1 Gen 3 receive 2 – plus | | AB8 | PCIE1\_RX3\_M | – | AI | PCIe 1 Gen 3 receive 3 – minus | | AC7 | PCIE1\_RX3\_P | – | AI | PCIe 1 Gen 3 receive 3 – plus | | AA3 | PCIE1\_TX0\_M | – | AO | PCIe 1 Gen 3 transmit 0 – minus | | AB4 | PCIE1\_TX0\_P | – | AO | PCIe 1 Gen 3 transmit 0 – plus | | Y4 | PCIE1\_TX1\_M | – | AO | PCIe 1 Gen 3 transmit 1 – minus | | Y2 | PCIE1\_TX1\_P | – | AO | PCIe 1 Gen 3 transmit 1 – plus | | W7 | PCIE1\_TX2\_M | – | AO | PCIe 1 Gen 3 transmit 2 – minus | | Y6 | PCIE1\_TX2\_P | – | AO | PCIe 1 Gen 3 transmit 2 – plus | | V8 | PCIE1\_TX3\_M | – | AO | PCIe 1 Gen 3 transmit 3 – minus | | V6 | PCIE1\_TX3\_P | – | AO | PCIe 1 Gen 3 transmit 3 – plus | | AF48 | PS\_HOLD | PX\_3 | DO-Z | The Power Supply HOLD (PS\_HOLD) signal is driven by the SoC to the PMIC. It is
active HIGH and has an internal pull-down by default. During boot, PS\_HOLD is set HIGH
(logic 1) to indicate a successful boot and to request that the PMIC keep the power
supplies enabled. During shutdown, watchdog expiry, thermal trip, or certain error
conditions, software or hardware clears PS\_HOLD to LOW (logic 0) to instruct the PMIC
to shut down or reset the system. | | L1 | REFGEN\_REXT2 | – | AI | High-speed interface – external resistor 2 | | BK38 | REFGEN\_REXT3 | – | AI | High-speed interface – external resistor 3 | | AG47 | RESIN\_N | PX\_0 | DI | The main domain hardware reset input to the SoC is provided by the PMIC.



This is an active-low reset pin.





If the SoC does not assert PS\_HOLD HIGH within a certain period after RESIN\_N goes
HIGH, the PMIC will trigger a reset.



RESIN\_N connects to the PON\_RESET\_N pin on the PMIC side. | | AG49 | RESOUT\_N | PX\_3 | DO | The main domain active-low reset output follows RESIN\_N with a short delay. It
can be used to reset external circuitry. This signal is asserted or released a few
clock cycles after a change on RESIN\_N or after a watchdog expiration. | | BM4 | RTSS\_CXO | PX\_11 | DI | RTSS subsystem crystal oscillator | | BB6 | RTSS\_JTAG\_SRST\_N | PX\_3 | DI | RTSS subsystem JTAG reset for debug | | BB2 | RTSS\_JTAG\_TCK | PX\_3 | DI | RTSS subsystem JTAG clock input | | BA5 | RTSS\_JTAG\_TDI | PX\_3 | DI | RTSS subsystem JTAG data input | | BA3 | RTSS\_JTAG\_TDO | PX\_3 | DO-Z | RTSS subsystem JTAG data output | | BA7 | RTSS\_JTAG\_TMS | PX\_3 | B | RTSS subsystem JTAG mode select input | | BB4 | RTSS\_JTAG\_TRST\_N | PX\_3 | DI | RTSS subsystem JTAG reset | | BG19 | RTSS\_MODE\_0 | PX\_3 | DI | RTSS subsystem mode control bit 0 | | BJ19 | RTSS\_MODE\_1 | PX\_3 | DI | RTSS subsystem mode control bit 1 | | BF20 | RTSS\_PS\_HOLD | PX\_3 | DO | When the RTSS domain is active, this signal will be HIGH. For debugging purposes,
a test point can be added to this signal. RTSS temperature fatal events, power
sequence watchdog expiration, MD PMIC fault indications, or software faults can cause
this signal to go LOW. | | BG21 | RTSS\_RESIN\_N | PX\_0 | DI | The RTSS domain hardware reset input to the SoC is provided by the PMIC. This
input should be connected to the main domain RESIN\_N signal. | | BH20 | RTSS\_RESOUT\_N | PX\_3 | DO | The RTSS domain active-low reset output follows RTSS\_RESIN\_N with a short delay.
It can be used to reset external circuitry. This signal is asserted or released a few
clock cycles after a change on RTSS\_RESIN\_N or based on watchdog expire
status. | | AN7 | SDC1\_CLK | PX\_7 | DO | Secure digital controller 1 clock | | AN5 | SDC1\_CMD | PX\_7 | B | Secure digital controller 1 command | | AU1 | SDC1\_DATA\_0 | PX\_7 | B | Secure digital controller 1 data bit 0 | | AR5 | SDC1\_DATA\_1 | PX\_7 | B | Secure digital controller 1 data bit 1 | | AU5 | SDC1\_DATA\_2 | PX\_7 | B | Secure digital controller 1 data bit 2 | | AU3 | SDC1\_DATA\_3 | PX\_7 | B | Secure digital controller 1 data bit 3 | | AP6 | SDC1\_DATA\_4 | PX\_7 | B | Secure digital controller 1 data bit 4 | | AU7 | SDC1\_DATA\_5 | PX\_7 | B | Secure digital controller 1 data bit 5 | | AT4 | SDC1\_DATA\_6 | PX\_7 | B | Secure digital controller 1 data bit 6 | | AT6 | SDC1\_DATA\_7 | PX\_7 | B | Secure digital controller 1 data bit 7 | | AR7 | SDC1\_RCLK | PX\_7 | DI | Secure digital controller 1 return clock | | AR1 | SGMII0\_RX\_M | – | AI, AO | SGMII 0 receive M – minus | | AP2 | SGMII0\_RX\_P | – | AI, AO | SGMII 0 receive P – plus | | AN3 | SGMII0\_TX\_M | – | AI, AO | SGMII interface 0 serial data Tx – minus | | AN1 | SGMII0\_TX\_P | – | AI, AO | SGMII interface 0 serial data Tx – plus | | AH48 | SLEEP\_CLK | PX\_3 | DI | Sleep clock | | AE47 | SPMI\_CLK | PX\_0 | B | Slave and PBUS interface for PMICs – clock | | AD48 | SPMI\_DATA | PX\_0 | B | Slave and PBUS interface for PMICs – data | | AA47 | UFS0\_REFCLK | PX\_9 | DO | UFS0 reference clock | | AB48 | UFS0\_RESET\_N | PX\_9 | DO | UFS0 reset | | U47 | UFS0\_RX0\_M | – | AI | UFS0 receive 0 – minus | | U45 | UFS0\_RX0\_P | – | AI | UFS0 receive 0 – plus | | T46 | UFS0\_RX1\_M | – | AI | UFS0 receive 1 – minus | | R45 | UFS0\_RX1\_P | – | AI | UFS0 receive 1 – plus | | T52 | UFS0\_TX0\_M | – | AO | UFS0 transmit 0 – minus | | T50 | UFS0\_TX0\_P | – | AO | UFS0 transmit 0 – plus | | R51 | UFS0\_TX1\_M | – | AO | UFS0 transmit 1 – minus | | P50 | UFS0\_TX1\_P | – | AO | UFS0 transmit 1 – plus | | T2 | USB0\_HS\_DM | – | AI, AO | USB0 high-speed data – minus | | R1 | USB0\_HS\_DP | – | AI, AO | USB0 high-speed data – plus | | N1 | USB0\_SS\_RX\_M | – | AI | USB0 SuperSpeed receive 0 – minus | | M2 | USB0\_SS\_RX\_P | – | AI | USB0 SuperSpeed receive 0 – plus | | P4 | USB0\_SS\_TX\_M | – | AO | USB0 SuperSpeed transmit 0 – minus | | N5 | USB0\_SS\_TX\_P | – | AO | USB0 SuperSpeed transmit 0 – plus | | U1 | USB1\_HS\_DM | – | AI, AO | USB1 high-speed data – minus | | U3 | USB1\_HS\_DP | – | AI, AO | USB1 high-speed data – plus | | | | | | | [^1^](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#fnsrc_1_pin-descriptions) For parameter and acronym definitions, see [I/O parameter definitions](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_0e123156-7709-4fda-8838-d52533a739b6). GPIO pins can support multiple functions. To assign GPIOs to particular functions (such as the options listed in the preceding table), identify all their application’s requirements and map each GPIO to its function. See the following table for a list of all supported functions for each GPIO. Some GPIOs can wake up the SoC from sleep. For more information, see [Table : Pin descriptions – general-purpose input/output ports](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_uxn_dql_5sb). To avoid excessive current leakage, examine each GPIO external connection and programmed configuration. Ensure control of the following factors: - GPIO configuration - Input vs. output - Pull-up or pull-down - External connections - Unused inputs - Connections to high-impedance (tri-state) outputs - Connections to external devices that may not be attached For GPIO assignments, see the [QCS8275 Pin Assignment and GPIO Configuration Spreadsheet (80-73475-1A)](https://docs.qualcomm.com/bundle/80-73475-1A/resource/80-73475-1A.xlsm). It lists all pad names and/or functions for QCS8275 GPIOs (in numeric order), pad numbers, pad voltages, pull states, and available configurations. | Pin number | Pin name | Configurable function | Pad characteristics[^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#fntarg_2_pin-descriptions) | Pad characteristics[^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#fntarg_2_pin-descriptions) | Functional description | Wakeup | | --- | --- | --- | --- | --- | --- | --- | | Pin number | Pin name | Configurable function | Voltage | Type | Functional description | Wakeup | | R9 | GPIO\_0 | PCIE0\_WAKE\_N | PX\_3 | PD:nppukp | Configurable I/O | Y | | R7 | GPIO\_1 | | PX\_3 | PU:nppdkp | Configurable I/O | Y | | R7 | GPIO\_1 | PCIE0\_CLKREQ\_N | PX\_3 | PU:nppdkp | PCIE0 clock request | Y | | P8 | GPIO\_2 | PCIE0\_RST\_N | PX\_3 | PD:nppukp | Configurable I/O | Y | | BB52 | GPIO\_3 | START\_DS | PX\_3 | PD:nppukp | Configurable I/O | Y | | BA1 | GPIO\_4 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BA1 | GPIO\_4 | SGMII\_PHY\_INTR0\_N | PX\_3 | PD:nppukp | SGMII 0 PHY interrupt | Y | | AY6 | GPIO\_5 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AY6 | GPIO\_5 | EMAC0\_MDC | PX\_3 | PD:nppukp | EMAC 0 management interface clock | N | | AY4 | GPIO\_6 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AY4 | GPIO\_6 | EMAC0\_MDIO | PX\_3 | PD:nppukp | EMAC 0 management interface I/O | N | | N7 | GPIO\_7 | | PX\_3 | PD:nppukp | Configurable I/O | N | | N7 | GPIO\_7 | USB2PHY\_AC\_EN0 | PX\_3 | PD:nppukp | USB AC coupling 0 control | N | | N7 | GPIO\_7 | BOOT\_CONFIG[12] | PX\_3 | PD:nppukp | Boot configuration bit 12 | N | | N9 | GPIO\_8 | | PX\_3 | PD:nppukp | Configurable I/O | N | | N9 | GPIO\_8 | USB2PHY\_AC\_EN2 | PX\_3 | PD:nppukp | USB AC coupling 2 control | N | | N9 | GPIO\_8 | BOOT\_CONFIG[14] | PX\_3 | PD:nppukp | Boot configuration bit 14 | N | | BC47 | GPIO\_9 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AY2 | GPIO\_10 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AY2 | GPIO\_10 | QSPI\_DATA[1] | PX\_3 | PD:nppukp | QSPI\_DATA[1] | Y | | AY2 | GPIO\_10 | EMAC0\_MCG\_PST\_TRIG\_LW[0] | PX\_3 | PD:nppukp | EMAC0 trigger input 0 for media clock generation | Y | | AW7 | GPIO\_11 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AW7 | GPIO\_11 | QSPI\_DATA[0] | PX\_3 | PD:nppukp | QSPI\_DATA[0] | Y | | AW7 | GPIO\_11 | EMAC0\_MCG\_PST\_TRIG\_LW[1] | PX\_3 | PD:nppukp | EMAC0 trigger input 1 for media clock generation | Y | | AW5 | GPIO\_12 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AW5 | GPIO\_12 | QSPI\_CLK | PX\_3 | PD:nppukp | QSPI\_CLK | N | | AW3 | GPIO\_13 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AW3 | GPIO\_13 | QSPI\_CS | PX\_3 | PD:nppukp | QSPI\_CS | Y | | AV6 | GPIO\_14 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AV6 | GPIO\_14 | QSPI\_DATA[2] | PX\_3 | PD:nppukp | QSPI\_DATA[2] | N | | AV4 | GPIO\_15 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AV4 | GPIO\_15 | QSPI\_DATA[3] | PX\_3 | PD:nppukp | QSPI\_DATA[3] | N | | AV2 | GPIO\_16 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AV2 | GPIO\_16 | QSPI\_INT | PX\_3 | PD:nppukp | QSPI\_INT | Y | | AV2 | GPIO\_16 | GP\_PDM\_MIRA[2] | PX\_3 | PD:nppukp | General-purpose PDM output 2 A | Y | | AY48 | GPIO\_17 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AY48 | GPIO\_17 | QUP0\_SE0\_L0 | PX\_3 | PD:nppukp | QUP 0 SE 0 lane 0: I2C\_SDA/SPI\_MISO/UART\_CTS | Y | | AY48 | GPIO\_17 | QUP0\_SE1\_L2 | PX\_3 | PD:nppukp | QUP 0 SE 1 lane 2: SPI\_SCLK/UART\_TX | Y | | AY48 | GPIO\_17 | IBI\_I3C\_QUP0\_SE0\_SDA | PX\_3 | PD:nppukp | QUP0 In-band interrupt I3C SE clock 0 | Y | | AY48 | GPIO\_17 | GP\_PDM\_MIRB[1] | PX\_3 | PD:nppukp | General-purpose PDM output 1 B | Y | | AY50 | GPIO\_18 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AY50 | GPIO\_18 | QUP0\_SE0\_L1 | PX\_3 | PD:nppukp | QUP 0 SE 0 lane 1: I2C\_SCL/SPI\_MOSI/UART\_RFR | Y | | AY50 | GPIO\_18 | QUP0\_SE1\_L3 | PX\_3 | PD:nppukp | QUP 0 SE 1 lane 3: SPI\_CS\_0/UART\_RX | Y | | AY50 | GPIO\_18 | IBI\_I3C\_QUP0\_SE0\_SCL | PX\_3 | PD:nppukp | QUP0 In-Band interrupt I3C SE data 0 | Y | | AY52 | GPIO\_19 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AY52 | GPIO\_19 | QUP0\_SE1\_L0 | PX\_3 | PD:nppukp | QUP 0 SE 1 lane 0: I2C\_SDA/SPI\_MISO/UART\_CTS | Y | | AY52 | GPIO\_19 | QUP0\_SE0\_L2 | PX\_3 | PD:nppukp | QUP 0 SE 0 lane 2: SPI\_SCLK/UART\_TX | Y | | AY52 | GPIO\_19 | CCI\_TIMER5 | PX\_3 | PD:nppukp | Camera control interface timer 5 | Y | | AY52 | GPIO\_19 | IBI\_I3C\_QUP0\_SE1\_SDA | PX\_3 | PD:nppukp | QUP0 In-Band interrupt I3C SE clock 0 | Y | | AY52 | GPIO\_19 | GP\_PDM\_MIRB[2] | PX\_3 | PD:nppukp | General-purpose PDM output 2 B | Y | | BA47 | GPIO\_20 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BA47 | GPIO\_20 | QUP0\_SE1\_L1 | PX\_3 | PD:nppukp | QUP 0 SE 1 lane 1: I2C\_SCL/SPI\_MOSI/UART\_RFR | Y | | BA47 | GPIO\_20 | QUP0\_SE0\_L3 | PX\_3 | PD:nppukp | QUP 0 SE 0 lane 3: SPI\_CS\_0/UART\_RX | Y | | BA47 | GPIO\_20 | CCI\_TIMER6 | PX\_3 | PD:nppukp | Camera control interface timer 6 | Y | | BA47 | GPIO\_20 | IBI\_I3C\_QUP0\_SE1\_SCL | PX\_3 | PD:nppukp | QUP0 In-Band interrupt I3C SE data 0 | Y | | BA47 | GPIO\_20 | GP\_PDM\_MIRA[1] | PX\_3 | PD:nppukp | General-purpose PDM output 1 A | Y | | BE53 | GPIO\_21 | PCIE1\_WAKE\_N | PX\_3 | PD:nppukp | Configurable I/O | Y | | BE53 | GPIO\_21 | QUP0\_SE5\_L0 | PX\_3 | PD:nppukp | QUP 0 SE 5 lane 0: I2C-SDA/SPI\_MISO/SPI-S\_MISO/UART\_CTS | Y | | BE53 | GPIO\_21 | CCI\_TIMER7 | PX\_3 | PD:nppukp | Camera control interface timer 7 | Y | | BF48 | GPIO\_22 | | PX\_3 | PU:nppdkp | Configurable I/O | Y | | BF48 | GPIO\_22 | PCIE1\_CLKREQ\_N | PX\_3 | PU:nppdkp | PCIe1 clock request | Y | | BF48 | GPIO\_22 | QUP0\_SE5\_L1 | PX\_3 | PU:nppdkp | QUP 0 SE 5 lane 1: I2C\_SCL/SPI\_MOSI/SPI-S\_MOSI/UART\_RFR | Y | | BF48 | GPIO\_22 | CCI\_TIMER8 | PX\_3 | PU:nppdkp | Camera control interface timer 8 | Y | | BE51 | GPIO\_23 | PCIE1\_RST\_N | PX\_3 | PD:nppukp | Configurable I/O | Y | | BE51 | GPIO\_23 | QUP0\_SE5\_L2 | PX\_3 | PD:nppukp | QUP 0 SE 5 lane 2: SPI\_SCLK/SPI-S\_SCLK/UART\_TX | Y | | BE51 | GPIO\_23 | CCI\_TIMER9 | PX\_3 | PD:nppukp | Camera control interface timer 9 | Y | | BF50 | GPIO\_24 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BF50 | GPIO\_24 | QUP0\_SE5\_L3 | PX\_3 | PD:nppukp | QUP 0 SE 5 lane 3: SPI\_CS\_0/SPI-S\_CS/UART\_RX | Y | | BF50 | GPIO\_24 | EMAC0\_PTP\_AUX\_TS\_I\_2 | PX\_3 | PD:nppukp | EMAC 0 trigger 2 A for auxiliary snapshot | Y | | BF50 | GPIO\_24 | EMAC0\_PTP\_PPS\_O\_2 | PX\_3 | PD:nppukp | EMAC 0 configurable PPS output 2 | Y | | BF50 | GPIO\_24 | EMAC0\_MCG\_PST\_TRIG\_LW[2] | PX\_3 | PD:nppukp | EMAC0 trigger input 2 for media clock generation | Y | | BH48 | GPIO\_25 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BH48 | GPIO\_25 | QUP0\_SE3\_L0 | PX\_3 | PD:nppukp | QUP 0 SE 3 lane 0: I2C\_SDA/SPI\_MISO/UART\_CTS/HS-UART\_CTS | N | | BJ49 | GPIO\_26 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BJ49 | GPIO\_26 | QUP0\_SE3\_L1 | PX\_3 | PD:nppukp | QUP 0 SE 3 lane 1: I2C\_SCL/SPI\_MOSI/UART\_RFR/HS-UART\_RFR | N | | BJ51 | GPIO\_27 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BJ51 | GPIO\_27 | QUP0\_SE3\_L2 | PX\_3 | PD:nppukp | QUP 0 SE 3 lane 2: SPI\_SCLK/UART\_TX/HS-UART\_TX | N | | BJ53 | GPIO\_28 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BJ53 | GPIO\_28 | QUP0\_SE3\_L3 | PX\_3 | PD:nppukp | QUP 0 SE 3 lane 3: SPI\_CS\_0/UART\_RX/HS-UART\_RX | Y | | BH38 | GPIO\_29 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BH38 | GPIO\_29 | QUP0\_SE4\_L0 | PX\_3 | PD:nppukp | QUP 0 SE 4 lane 0: I2C\_SDA/SPI\_MISO/SPI-S\_MISO/UART\_CTS | Y | | BH38 | GPIO\_29 | CCI\_I2C\_SDA1 | PX\_3 | PD:nppukp | Camera I²C data 1 | Y | | BH38 | GPIO\_29 | CCI\_ASYNC\_IN3 | PX\_3 | PD:nppukp | Camera control interface async 3 | Y | | BH38 | GPIO\_29 | EMAC0\_PTP\_PPS\_O\_0 | PX\_3 | PD:nppukp | EMAC 0 configurable PPS output 0 | Y | | BF38 | GPIO\_30 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BF38 | GPIO\_30 | QUP0\_SE4\_L1 | PX\_3 | PD:nppukp | QUP 0 SE 4 lane 1: I2C\_SCL/SPI\_MOSI/SPI-S\_MOSI/UART\_RFR | N | | BF38 | GPIO\_30 | CCI\_I2C\_SCL1 | PX\_3 | PD:nppukp | Camera I²C clock 1 | N | | BF38 | GPIO\_30 | CCI\_ASYNC\_IN4 | PX\_3 | PD:nppukp | Camera control interface async 4 | N | | BF38 | GPIO\_30 | EMAC0\_PTP\_PPS\_O\_1 | PX\_3 | PD:nppukp | EMAC 0 configurable PPS output 1 | N | | BG37 | GPIO\_31 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BG37 | GPIO\_31 | QUP0\_SE4\_L2 | PX\_3 | PD:nppukp | QUP 0 SE 4 lane 2: I2C\_SCL/SPI\_MOSI/SPI-S\_MOSI | Y | | BG37 | GPIO\_31 | CCI\_I2C\_SDA3 | PX\_3 | PD:nppukp | Camera I²C data 3 | Y | | BG37 | GPIO\_31 | CCI\_ASYNC\_IN5 | PX\_3 | PD:nppukp | Camera control interface async 5 | Y | | BG37 | GPIO\_31 | EMAC0\_PTP\_AUX\_TS\_I\_0 | PX\_3 | PD:nppukp | EMAC 0 trigger 0 A for auxiliary snapshot | Y | | BH36 | GPIO\_32 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BH36 | GPIO\_32 | QUP0\_SE4\_L3 | PX\_3 | PD:nppukp | QUP 0 SE 4 lane 3: SPI\_CS\_0/SPI-S\_CS/UART\_RX | Y | | BH36 | GPIO\_32 | CCI\_I2C\_SCL3 | PX\_3 | PD:nppukp | Camera I²C clock 3 | Y | | BH36 | GPIO\_32 | EMAC0\_PTP\_AUX\_TS\_I\_1 | PX\_3 | PD:nppukp | EMAC 0 trigger 1 A for auxiliary snapshot | Y | | BH36 | GPIO\_32 | MDP\_VSYNC\_S | PX\_3 | PD:nppukp | MDP vertical sync – secondary | Y | | BH36 | GPIO\_32 | GP\_MN | PX\_3 | PD:nppukp | General-purpose M/N:D counter output | Y | | BJ33 | GPIO\_33 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BJ33 | GPIO\_33 | QUP0\_SE2\_L0 | PX\_3 | PD:nppukp | QUP 0 SE 2 lane 0: I2C\_SDA/SPI\_MISO/UART\_CTS/HS-UART\_CTS | N | | BG33 | GPIO\_34 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BG33 | GPIO\_34 | QUP0\_SE2\_L1 | PX\_3 | PD:nppukp | QUP 0 SE 2 lane 1: I2C\_SCL/SPI\_MOSI/UART\_RFR/HS-UART\_RFR | N | | BH32 | GPIO\_35 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BH32 | GPIO\_35 | QUP0\_SE2\_L2 | PX\_3 | PD:nppukp | QUP 0 SE 2 lane 2: SPI\_SCLK/UART\_TX/HS-UART\_TX | N | | BH32 | GPIO\_35 | GCC\_GP1\_CLK\_MIRB | PX\_3 | PD:nppukp | General-purpose clock 1 B | N | | BF32 | GPIO\_36 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BF32 | GPIO\_36 | QUP0\_SE2\_L3 | PX\_3 | PD:nppukp | QUP 0 SE 2 lane 3: SPI\_CS\_0/UART\_RX/HS-UART\_RX | Y | | BF32 | GPIO\_36 | GCC\_GP2\_CLK\_MIRB | PX\_3 | PD:nppukp | General-purpose clock 2 B | Y | | BA53 | GPIO\_37 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BA53 | GPIO\_37 | QUP1\_SE0\_L0 | PX\_3 | PD:nppukp | QUP 1 SE 0 lane 0: I2C\_SDA/SPI\_MISO/UART\_CTS | Y | | BA53 | GPIO\_37 | IBI\_I3C\_QUP1\_SE0\_SDA | PX\_3 | PD:nppukp | QUP1 In-Band interrupt I3C SE clock 1 | Y | | BA53 | GPIO\_37 | QUP1\_SE1\_L2 | PX\_3 | PD:nppukp | QUP 1 SE 1 lane 2: SPI\_SCLK/UART\_TX | Y | | BA51 | GPIO\_38 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BA51 | GPIO\_38 | QUP1\_SE0\_L1 | PX\_3 | PD:nppukp | QUP 1 SE 0 lane 1: I2C\_SCL/SPI\_MOSI/UART\_RFR | Y | | BA51 | GPIO\_38 | IBI\_I3C\_QUP1\_SE0\_SCL | PX\_3 | PD:nppukp | QUP1 In-Band interrupt I3C SE data 1 | Y | | BA51 | GPIO\_38 | QUP1\_SE1\_L3 | PX\_3 | PD:nppukp | QUP 1 SE 1 lane 3: SPI\_CS\_0/UART\_RX | Y | | BA49 | GPIO\_39 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BA49 | GPIO\_39 | QUP1\_SE1\_L0 | PX\_3 | PD:nppukp | QUP 1 SE 1 lane 0: I2C\_SDA/SPI\_MISO/UART\_CTS | Y | | BA49 | GPIO\_39 | IBI\_I3C\_QUP1\_SE1\_SDA | PX\_3 | PD:nppukp | QUP1 In-Band interrupt I3C SE clock 1 | Y | | BA49 | GPIO\_39 | QUP1\_SE0\_L2 | PX\_3 | PD:nppukp | QUP 1 SE 0 lane 2: SPI\_SCLK/UART\_TX | Y | | BB48 | GPIO\_40 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BB48 | GPIO\_40 | QUP1\_SE1\_L1 | PX\_3 | PD:nppukp | QUP 1 SE 1 lane 1: I2C\_SCL/SPI\_MOSI/UART\_RFR | Y | | BB48 | GPIO\_40 | IBI\_I3C\_QUP1\_SE1\_SCL | PX\_3 | PD:nppukp | QUP1 In-Band interrupt I3C SE data 1 | Y | | BB48 | GPIO\_40 | QUP1\_SE0\_L3 | PX\_3 | PD:nppukp | QUP 1 SE 0 lane 3: SPI\_CS\_0/UART\_RX | Y | | BJ39 | GPIO\_41 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BJ39 | GPIO\_41 | QUP1\_SE3\_L2 | PX\_3 | PD:nppukp | QUP 1 SE 3 lane 2: UART\_TX/HS-UART\_TX | N | | BJ39 | GPIO\_41 | QUP1\_SE3\_L0 | PX\_3 | PD:nppukp | QUP 1 SE 3 lane 0: UART\_CTS/HS-UART\_CTS | N | | BJ39 | GPIO\_41 | BOOT\_CONFIG[9] | PX\_3 | PD:nppukp | Boot configuration bit 9 | N | | BG39 | GPIO\_42 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BG39 | GPIO\_42 | QUP1\_SE3\_L3 | PX\_3 | PD:nppukp | QUP 1 SE 3 lane 3: UART\_RX/HS-UART\_RX | Y | | BG39 | GPIO\_42 | QUP1\_SE3\_L1 | PX\_3 | PD:nppukp | QUP 1 SE 3 lane 1: UART\_RFR/HS-UART\_RFR | Y | | BG39 | GPIO\_42 | MDP\_VSYNC\_E | PX\_3 | PD:nppukp | MDP vertical sync – external | Y | | BE47 | GPIO\_43 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BE47 | GPIO\_43 | QUP0\_SE7\_L2 | PX\_3 | PD:nppukp | QUP 0 SE 7 lane 2: UART\_TX | N | | BE47 | GPIO\_43 | QUP0\_SE7\_L0 | PX\_3 | PD:nppukp | QUP 0 SE 7 lane 0: I2C\_SDA/UART\_CTS | N | | BE49 | GPIO\_44 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BE49 | GPIO\_44 | QUP0\_SE7\_L3 | PX\_3 | PD:nppukp | QUP 0 SE 7 lane 3: UART\_RX | Y | | BE49 | GPIO\_44 | QUP0\_SE7\_L1 | PX\_3 | PD:nppukp | QUP 0 SE 7 lane 1: I2C\_SCL/UART\_RFR | Y | | BF42 | GPIO\_45 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BF42 | GPIO\_45 | QUP1\_SE4\_L0 | PX\_3 | PD:nppukp | QUP 1 SE 4 lane 0: I2C\_SDA/SPI\_MISO/SPI-S\_MISO/UART\_CTS | Y | | BJ41 | GPIO\_46 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BJ41 | GPIO\_46 | QUP1\_SE4\_L1 | PX\_3 | PD:nppukp | QUP 1 SE 4 lane 1: I2C\_SCL/SPI\_MOSI/SPI\_MOSI/UART\_RFR | N | | BG41 | GPIO\_47 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BG41 | GPIO\_47 | QUP1\_SE4\_L2 | PX\_3 | PD:nppukp | QUP 1 SE 4 lane 2: SPI\_SCLK/SPI-S\_SCLK/UART\_TX | N | | BH40 | GPIO\_48 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BH40 | GPIO\_48 | QUP1\_SE4\_L3 | PX\_3 | PD:nppukp | QUP 1 SE 4 lane 3: SPI\_CS\_0/SPI\_CS/UART\_RX | Y | | BJ47 | GPIO\_49 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BJ47 | GPIO\_49 | QUP1\_SE5\_L0 | PX\_3 | PD:nppukp | QUP 1 SE 5 lane 0: I2C\_SDA/SPI\_MISO/SPI-S\_MISO/UART\_CTS | N | | BJ47 | GPIO\_49 | CCI\_TIMER3 | PX\_3 | PD:nppukp | Camera control interface timer 3 | N | | BJ47 | GPIO\_49 | BOOT\_CONFIG[6] | PX\_3 | PD:nppukp | Boot configuration bit 6 | N | | BG47 | GPIO\_50 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BG47 | GPIO\_50 | QUP1\_SE5\_L1 | PX\_3 | PD:nppukp | QUP 1 SE 5 lane 1: I2C\_SCL/SPI\_MOSI/SPI-S\_MOSI | N | | BG47 | GPIO\_50 | CCI\_TIMER4 | PX\_3 | PD:nppukp | Camera control interface timer 4 | N | | BH46 | GPIO\_51 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BH46 | GPIO\_51 | QUP1\_SE5\_L2 | PX\_3 | PD:nppukp | QUP 1 SE 5 lane 2 | Y | | BH46 | GPIO\_51 | BOOT\_CONFIG[7] | PX\_3 | PD:nppukp | Boot configuration bit 7 | Y | | BF46 | GPIO\_52 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BF46 | GPIO\_52 | QUP1\_SE5\_L3 | PX\_3 | PD:nppukp | QUP 1 SE 5 lane 3 SPI\_CS\_0/SPI-S\_CS/UART\_RX | Y | | BF46 | GPIO\_52 | MDP\_VSYNC\_P | PX\_3 | PD:nppukp | MDP vertical sync - primary | Y | | BF46 | GPIO\_52 | FORCED\_USB\_BOOT | PX\_3 | PD:nppukp | Forced USB boot | Y | | P6 | GPIO\_53 | HST\_SW\_CTRL | PX\_3 | PD:nppukp | Configurable I/O | Y | | P6 | GPIO\_53 | BOOT\_CONFIG[11] | PX\_3 | PD:nppukp | Boot configuration bit 11 | Y | | BH50 | GPIO\_54 | WLAN\_EN | PX\_3 | PD:nppukp | Configurable I/O | N | | BH50 | GPIO\_54 | CCI\_I2C\_SDA5 | PX\_3 | PD:nppukp | Camera I²C data 5 | N | | BH52 | GPIO\_55 | BT\_EN | PX\_3 | PD:nppukp | Configurable I/O | N | | BH52 | GPIO\_55 | CCI\_I2C\_SCL5 | PX\_3 | PD:nppukp | Camera I²C clock 5 | N | | BC49 | GPIO\_56 | STR\_WAKE | PX\_3 | PD:nppukp | Configurable I/O | Y | | BH24 | GPIO\_57 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BH24 | GPIO\_57 | CCI\_I2C\_SDA0 | PX\_3 | PD:nppukp | Camera I²C data 0 | N | | BF24 | GPIO\_58 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BF24 | GPIO\_58 | CCI\_I2C\_SCL0 | PX\_3 | PD:nppukp | Camera I²C clock 0 | N | | BG23 | GPIO\_59 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BG23 | GPIO\_59 | CCI\_I2C\_SDA2 | PX\_3 | PD:nppukp | Camera I²C data 2 | N | | BF22 | GPIO\_60 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BF22 | GPIO\_60 | CCI\_I2C\_SCL2 | PX\_3 | PD:nppukp | Camera I²C clock 2 | N | | BF22 | GPIO\_60 | EDL\_INDICATOR | PX\_3 | PD:nppukp | EDL indicator | N | | BJ31 | GPIO\_61 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BJ31 | GPIO\_61 | CCI\_I2C\_SDA4 | PX\_3 | PD:nppukp | Camera I²C data 4 | N | | BG31 | GPIO\_62 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BG31 | GPIO\_62 | CCI\_I2C\_SCL4 | PX\_3 | PD:nppukp | Camera I²C clock 4 | N | | BH28 | GPIO\_63 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BH28 | GPIO\_63 | CCI\_TIMER0 | PX\_3 | PD:nppukp | Camera control interface timer 0 | N | | BH28 | GPIO\_63 | CCI\_ASYNC\_IN0 | PX\_3 | PD:nppukp | Camera control interface async 0 | N | | BG27 | GPIO\_64 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BG27 | GPIO\_64 | CCI\_TIMER1 | PX\_3 | PD:nppukp | Camera control interface timer 1 | N | | BG27 | GPIO\_64 | CCI\_ASYNC\_IN1 | PX\_3 | PD:nppukp | Camera control interface async 1 | N | | BF26 | GPIO\_65 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BF26 | GPIO\_65 | CCI\_TIMER2 | PX\_3 | PD:nppukp | Camera control interface timer 2 | N | | BF26 | GPIO\_65 | CCI\_ASYNC\_IN2 | PX\_3 | PD:nppukp | Camera control interface async 2 | N | | BG49 | GPIO\_66 | DISP\_RST | PX\_3 | PD:nppukp | Configurable I/O | Y | | BG49 | GPIO\_66 | BOOT\_CONFIG[13] | PX\_3 | PD:nppukp | Boot configuration bit 13 | Y | | BD48 | GPIO\_67 | CCI\_ERR0 | PX\_3 | PD:nppukp | Configurable I/O | Y | | BD48 | GPIO\_67 | CAM\_MCLK0 | PX\_3 | PD:nppukp | Camera 0 MCLK | Y | | BD50 | GPIO\_68 | CCI\_ERR1 | PX\_3 | PD:nppukp | Configurable I/O | Y | | BD50 | GPIO\_68 | CAM\_MCLK1 | PX\_3 | PD:nppukp | Camera 1 MCLK | Y | | BD50 | GPIO\_68 | GCC\_GP4\_CLK\_MIRB | PX\_3 | PD:nppukp | General-purpose clock 4 B | Y | | BD52 | GPIO\_69 | CCI\_ERR2 | PX\_3 | PD:nppukp | Configurable I/O | Y | | BD52 | GPIO\_69 | CAM\_MCLK2 | PX\_3 | PD:nppukp | Camera 2 MCLK | Y | | BD52 | GPIO\_69 | GCC\_GP3\_CLK\_MIRB | PX\_3 | PD:nppukp | General-purpose clock 3 B | Y | | BH30 | GPIO\_70 | CAM\_0\_LOCK | PX\_3 | PD:nppukp | Configurable I/O | Y | | BF30 | GPIO\_71 | CAM\_1\_LOCK | PX\_3 | PD:nppukp | Configurable I/O | Y | | BG29 | GPIO\_72 | CAM\_2\_LOCK | PX\_3 | PD:nppukp | Configurable I/O | Y | | BH26 | GPIO\_73 | CAM0\_EN | PX\_3 | PD:nppukp | Configurable I/O | Y | | BH26 | GPIO\_73 | GP\_PDM\_MIRA[0] | PX\_3 | PD:nppukp | General-purpose PDM output 0 A | Y | | BJ25 | GPIO\_74 | CAM1\_EN | PX\_3 | PD:nppukp | Configurable I/O | Y | | BG25 | GPIO\_75 | CAM2\_EN | PX\_3 | PD:nppukp | Configurable I/O | Y | | BG25 | GPIO\_75 | GP\_PDM\_MIRB[0] | PX\_3 | PD:nppukp | General-purpose PDM output 0 B | Y | | BF52 | GPIO\_76 | GNSS\_INT\_N | PX\_3 | PD:nppukp | Configurable I/O | Y | | BF52 | GPIO\_76 | GCC\_GP5\_CLK\_MIRA | PX\_3 | PD:nppukp | General-purpose clock 5 A | Y | | BF52 | GPIO\_76 | BOOT\_CONFIG[1] | PX\_3 | PD:nppukp | Boot configuration bit 1 | Y | | BB50 | GPIO\_77 | GNSS\_EN | PX\_3 | PD:nppukp | Configurable I/O | Y | | BB50 | GPIO\_77 | GCC\_GP5\_CLK\_MIRB | PX\_3 | PD:nppukp | General-purpose clock 5 B | Y | | T6 | GPIO\_78 | GNSS\_RESET | PX\_3 | PD:nppukp | Configurable I/O | Y | | T8 | GPIO\_79 | GNSS\_BOOT\_MODE | PX\_3 | PD:nppukp | Configurable I/O | Y | | T8 | GPIO\_79 | EMAC0\_PTP\_AUX\_TS\_I\_3 | PX\_3 | PD:nppukp | EMAC 0 trigger 3 A for auxiliary snapshot | Y | | T8 | GPIO\_79 | EMAC0\_PTP\_PPS\_O\_3 | PX\_3 | PD:nppukp | EMAC 0 configurable PPS output 3 | Y | | T8 | GPIO\_79 | EMAC0\_MCG\_PST\_TRIG\_LW[3] | PX\_3 | PD:nppukp | EMAC0 trigger input 3 for media clock generation | Y | | BK52 | GPIO\_80 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BK52 | GPIO\_80 | QUP0\_SE6\_L0 | PX\_3 | PD:nppukp | QUP 0 SE 6 lane 0: I2C\_SDA/SPI\_MISO/UART\_CTS | N | | BK52 | GPIO\_80 | MDP0\_VSYNC6\_OUT | PX\_3 | PD:nppukp | MDP 0 vertical sync 6 output | N | | BK50 | GPIO\_81 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BK50 | GPIO\_81 | QUP0\_SE6\_L1 | PX\_3 | PD:nppukp | QUP 0 SE 6 lane 1: I2C\_SCL/SPI\_MOSI/UART\_RFR | N | | BK50 | GPIO\_81 | MDP0\_VSYNC7\_OUT | PX\_3 | PD:nppukp | MDP 0 vertical sync 7 output | N | | BK50 | GPIO\_81 | GCC\_GP2\_CLK\_MIRA | PX\_3 | PD:nppukp | General-purpose clock 2 A | N | | BL51 | GPIO\_82 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BL51 | GPIO\_82 | QUP0\_SE6\_L2 | PX\_3 | PD:nppukp | QUP 0 SE 6 lane 2: SPI\_SCLK/UART\_TX | N | | BL51 | GPIO\_82 | GCC\_GP3\_CLK\_MIRA | PX\_3 | PD:nppukp | General-purpose clock 3 A | N | | BL51 | GPIO\_82 | BOOT\_CONFIG[10] | PX\_3 | PD:nppukp | Boot configuration bit 10 | N | | BM50 | GPIO\_83 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BM50 | GPIO\_83 | QUP0\_SE6\_L3 | PX\_3 | PD:nppukp | QUP 0 SE 6 lane 3: SPI\_CS\_0/UART\_RX | Y | | BM50 | GPIO\_83 | GCC\_GP4\_CLK\_MIRA | PX\_3 | PD:nppukp | General-purpose clock 4 A | Y | | BG45 | GPIO\_84 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BG45 | GPIO\_84 | QUP1\_SE2\_L0 | PX\_3 | PD:nppukp | QUP 1 SE 2 lane 0: I2C\_SDA/SPI\_MISO/UART\_CTS/HS-UART\_CTS | Y | | BG45 | GPIO\_84 | GCC\_GP1\_CLK\_MIRA | PX\_3 | PD:nppukp | General-purpose clock 1 A | Y | | BH44 | GPIO\_85 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BH44 | GPIO\_85 | QUP1\_SE2\_L1 | PX\_3 | PD:nppukp | QUP 1 SE 2 lane 1: I2C\_SCL/SPI\_MOSI/UART\_RFR/HS-UART\_RFR | N | | BF44 | GPIO\_86 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BF44 | GPIO\_86 | QUP1\_SE2\_L2 | PX\_3 | PD:nppukp | QUP 1 SE 2 lane 2: SPI\_SCLK/UART\_TX/HS-UART\_TX | N | | BG43 | GPIO\_87 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BG43 | GPIO\_87 | QUP1\_SE2\_L3 | PX\_3 | PD:nppukp | QUP 1 SE 2 lane 3: SPI\_CS\_0/UART\_RX/HS-UART\_RX | Y | | BH42 | GPIO\_88 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BH42 | GPIO\_88 | QUP1\_SE2\_L4 | PX\_3 | PD:nppukp | QUP 1 SE 2 lane 4: SPI\_CS\_1 | N | | BF36 | GPIO\_89 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BF36 | GPIO\_89 | QUP1\_SE6\_L0 | PX\_3 | PD:nppukp | QUP 1 SE 6 lane 0: I2C\_SDA/SPI\_MISO/UART\_CTS | Y | | BF36 | GPIO\_89 | QUP1\_SE7\_L2 | PX\_3 | PD:nppukp | QUP 1 SE 7 lane 2: SPI\_SCLK/UART\_TX | Y | | BF36 | GPIO\_89 | MDP0\_VSYNC0\_OUT | PX\_3 | PD:nppukp | MDP 0 vertical sync 0 output | Y | | BG35 | GPIO\_90 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BG35 | GPIO\_90 | QUP1\_SE6\_L1 | PX\_3 | PD:nppukp | QUP 1 SE 6 lane 1: I2C\_SCL/SPI\_MOSI/UART\_RFR | Y | | BG35 | GPIO\_90 | QUP1\_SE7\_L3 | PX\_3 | PD:nppukp | QUP 1 SE 7 lane 3: SPI\_CS\_0/UART\_RX | Y | | BG35 | GPIO\_90 | MDP0\_VSYNC1\_OUT | PX\_3 | PD:nppukp | MDP 0 vertical sync 1 output | Y | | BH34 | GPIO\_91 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BH34 | GPIO\_91 | QUP1\_SE7\_L0 | PX\_3 | PD:nppukp | QUP 1 SE 7 lane 0: I2C\_SDA/SPI\_MISO/UART\_CTS | Y | | BH34 | GPIO\_91 | QUP1\_SE6\_L2 | PX\_3 | PD:nppukp | QUP 1 SE 6 lane 2: SPI\_SCLK/UART\_TX | Y | | BH34 | GPIO\_91 | MDP0\_VSYNC3\_OUT | PX\_3 | PD:nppukp | MDP 0 vertical sync 3 output | Y | | BH34 | GPIO\_91 | BOOT\_CONFIG[0] | PX\_3 | PD:nppukp | Boot configuration bit 0 | Y | | BF34 | GPIO\_92 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BF34 | GPIO\_92 | QUP1\_SE7\_L1 | PX\_3 | PD:nppukp | QUP 1 SE 7 lane 1: I2C\_SCL/SPI\_MOSI/UART\_RFR | Y | | BF34 | GPIO\_92 | QUP1\_SE6\_L3 | PX\_3 | PD:nppukp | QUP 1 SE 6 lane 3: SPI\_CS\_0/UART\_RX | Y | | BC51 | GPIO\_93 | DISP\_INT | PX\_3 | PD:nppukp | Configurable I/O | Y | | BC51 | GPIO\_93 | TIC\_SEL\_MD | PX\_3 | PD:nppukp | | Y | | BG51 | GPIO\_94 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BG51 | GPIO\_94 | EDP0\_HOT\_PLUG\_DETECT | PX\_3 | PD:nppukp | Enhanced DisplayPort 0 hot plug detect | Y | | AW51 | GPIO\_95 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AW49 | GPIO\_96 | MERC\_RST\_N | PX\_3 | PD:nppukp | Configurable I/O | N | | AW49 | GPIO\_96 | BOOT\_CONFIG[8] | PX\_3 | PD:nppukp | Boot configuration bit 8 | N | | AH52 | GPIO\_97 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AH52 | GPIO\_97 | MI2S\_MCLK0 | PX\_3 | PD:nppukp | External Master Clock 0 | Y | | AH52 | GPIO\_97 | BOOT\_CONFIG[2] | PX\_3 | PD:nppukp | Boot configuration bit 2 | Y | | AH50 | GPIO\_98 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AH50 | GPIO\_98 | MI2S1\_SCK\_OR\_HS3\_MI2S\_SCK | PX\_3 | PD:nppukp | MI^2^S 1 clock or high-speed 3 MI^2^S clock | Y | | AH50 | GPIO\_98 | BOOT\_CONFIG[3] | PX\_3 | PD:nppukp | Boot configuration bit 3 | Y | | AJ53 | GPIO\_99 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AJ53 | GPIO\_99 | MI2S1\_WS\_OR\_HS3\_MI2S\_WS | PX\_3 | PD:nppukp | MI^2^S 1 word select or high-speed 3 MI^2^S word select and synchronization | Y | | AJ51 | GPIO\_100 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AJ51 | GPIO\_100 | MI2S1\_DATA0\_OR\_HS3\_MI2S\_DATA0 | PX\_3 | PD:nppukp | MI^2^S 1 serial data channel 0 or high speed 3 MI^2^S serial data channel 0 | Y | | AJ49 | GPIO\_101 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AJ49 | GPIO\_101 | MI2S1\_DATA1\_OR\_HS3\_MI2S\_DATA1 | PX\_3 | PD:nppukp | MI^2^S 1 serial data channel 1 or high speed 3 MI^2^S serial data channel 1 | Y | | AJ47 | GPIO\_102 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AJ47 | GPIO\_102 | MI2S2\_SCK\_OR\_HS4\_MI2S\_SCK | PX\_3 | PD:nppukp | MI^2^S 2 clock or high-speed 4 MI^2^S clock | Y | | AJ47 | GPIO\_102 | BOOT\_CONFIG[4] | PX\_3 | PD:nppukp | Boot configuration bit 4 | Y | | AK52 | GPIO\_103 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AK52 | GPIO\_103 | MI2S2\_WS\_OR\_HS4\_MI2S\_WS | PX\_3 | PD:nppukp | MI^2^S 2 word select or high-speed 4 MI^2^S word select and synchronization | Y | | AK52 | GPIO\_103 | BOOT\_CONFIG[5] | PX\_3 | PD:nppukp | Boot configuration bit 5 | Y | | AK50 | GPIO\_104 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AK50 | GPIO\_104 | MI2S2\_DATA0\_OR\_HS4\_MI2S\_DATA0 | PX\_3 | PD:nppukp | MI^2^S 2 serial data channel 0 or high speed 4 MI^2^S serial data channel 0 | Y | | AK48 | GPIO\_105 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AK48 | GPIO\_105 | MI2S2\_DATA1\_OR\_HS4\_MI2S\_DATA1 | PX\_3 | PD:nppukp | MI^2^S 2 serial data channel 1 or high speed 4 MI2S serial data channel 1 | Y | | AK48 | GPIO\_105 | AUDIO\_REF\_CLK | PX\_3 | PD:nppukp | Audio reference clock | Y | | AL51 | GPIO\_106 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AL51 | GPIO\_106 | HS\_I2S0\_SCK | PX\_3 | PD:nppukp | High-speed 0 MI^2^S clock | N | | AL49 | GPIO\_107 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AL49 | GPIO\_107 | HS\_I2S0\_WS | PX\_3 | PD:nppukp | High-speed 0 MI^2^S word select | N | | AL47 | GPIO\_108 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AL47 | GPIO\_108 | HS\_I2S0\_DATA0 | PX\_3 | PD:nppukp | High-speed 0 MI^2^S data 0 | N | | AM52 | GPIO\_109 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AM52 | GPIO\_109 | HS\_I2S0\_DATA1 | PX\_3 | PD:nppukp | High-speed 0 MI^2^S data 1 | N | | AM52 | GPIO\_109 | MI2S\_MCLK1 | PX\_3 | PD:nppukp | External master clock 1 | N | | AM50 | GPIO\_110 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AM50 | GPIO\_110 | LPASS\_0 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | N | | AM48 | GPIO\_111 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AM48 | GPIO\_111 | LPASS\_1 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | N | | AN53 | GPIO\_112 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AN53 | GPIO\_112 | LPASS\_2 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | N | | AN51 | GPIO\_113 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AN51 | GPIO\_113 | LPASS\_3 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | | | AN49 | GPIO\_114 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AN49 | GPIO\_114 | LPASS\_4 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | N | | AN47 | GPIO\_115 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AN47 | GPIO\_115 | LPASS\_5 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | N | | AP52 | GPIO\_116 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AP52 | GPIO\_116 | LPASS\_6 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | N | | AP50 | GPIO\_117 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AP50 | GPIO\_117 | LPASS\_7 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | N | | AP48 | GPIO\_118 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AP48 | GPIO\_118 | LPASS\_8 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | N | | AR51 | GPIO\_119 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AR51 | GPIO\_119 | LPASS\_9 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | N | | AR49 | GPIO\_120 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AR49 | GPIO\_120 | LPASS\_10 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | N | | AR47 | GPIO\_121 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AR47 | GPIO\_121 | LPASS\_11 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | N | | AT52 | GPIO\_122 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AT52 | GPIO\_122 | LPASS\_15 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | N | | AT50 | GPIO\_123 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AT50 | GPIO\_123 | LPASS\_16 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | N | | AT48 | GPIO\_124 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AT48 | GPIO\_124 | LPASS\_14 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | N | | AU53 | GPIO\_125 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AU53 | GPIO\_125 | LPASS\_12 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | N | | AU51 | GPIO\_126 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AU51 | GPIO\_126 | LPASS\_13 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | N | | AU49 | GPIO\_127 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AU49 | GPIO\_127 | LPASS\_17 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | N | | AU47 | GPIO\_128 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AU47 | GPIO\_128 | LPASS\_18 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | N | | AV52 | GPIO\_129 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AV52 | GPIO\_129 | LPASS\_19 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | Y | | AV50 | GPIO\_130 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | AV50 | GPIO\_130 | LPASS\_20 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | Y | | AV48 | GPIO\_131 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AV48 | GPIO\_131 | LPASS\_21 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | | | AW47 | GPIO\_132 | | PX\_3 | PD:nppukp | Configurable I/O | N | | AW47 | GPIO\_132 | LPASS\_22 | PX\_3 | PD:nppukp | See [Table : Pin descriptions – MD_LPASS](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_e0c70b29-04cd-48b2-ab88-a07687a9c1ed__table_w4l_cfd_vsb) for details | N | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [^2^](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#fnsrc_2_pin-descriptions) For parameter and acronym definitions, see [I/O parameter definitions](https://docs.qualcomm.com/doc/80-73475-1/topic/pin-definitions.html#topic.dita_0e123156-7709-4fda-8838-d52533a739b6). | Pin number | RTSS I/O | Alternate functions | Pad voltage | Pad type | Functional description | Wakeup function | | --- | --- | --- | --- | --- | --- | --- | | BK10 | RTSS\_IO\_0 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BK10 | RTSS\_IO\_0 | RTSS\_QUP0\_SE0\_L0 | PX\_3 | PD:nppukp | RTSS QUP0 SE0 lane 0 | N | | BM10 | RTSS\_IO\_1 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BM10 | RTSS\_IO\_1 | RTSS\_QUP0\_SE0\_L1 | PX\_3 | PD:nppukp | RTSS QUP0 SE0 lane 1 | N | | BG9 | RTSS\_IO\_2 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BG9 | RTSS\_IO\_2 | RTSS\_QUP0\_SE0\_L2 | PX\_3 | PD:nppukp | RTSS QUP0 SE0 lane 2 | N | | BJ9 | RTSS\_IO\_3 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BJ9 | RTSS\_IO\_3 | RTSS\_QUP0\_SE0\_L3 | PX\_3 | PD:nppukp | RTSS QUP0 SE0 lane 3 | Y | | BL9 | RTSS\_IO\_4 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BL9 | RTSS\_IO\_4 | RTSS\_QUP0\_SE1\_L0 | PX\_3 | PD:nppukp | RTSS QUP0 SE1 lane 0 | N | | BN9 | RTSS\_IO\_5 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BN9 | RTSS\_IO\_5 | RTSS\_QUP0\_SE1\_L1 | PX\_3 | PD:nppukp | RTSS QUP0 SE1 lane 2 | N | | BF8 | RTSS\_IO\_6 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BF8 | RTSS\_IO\_6 | RTSS\_QUP0\_SE1\_L2 | PX\_3 | PD:nppukp | RTSS QUP0 SE1 lane 2 | N | | BF8 | RTSS\_IO\_6 | RTSS\_BOOT\_CONFIG[13] | PX\_3 | PD:nppukp | RTSS boot configuration bit 13 | N | | BH8 | RTSS\_IO\_7 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BH8 | RTSS\_IO\_7 | RTSS\_QUP0\_SE1\_L3 | PX\_3 | PD:nppukp | RTSS QUP0 SE1 lane 3 | Y | | BH8 | RTSS\_IO\_7 | RTSS\_BOOT\_CONFIG[14] | PX\_3 | PD:nppukp | RTSS boot configuration bit 14 | Y | | BN5 | RTSS\_IO\_8 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BN5 | RTSS\_IO\_8 | RTSS\_QUP0\_SE2\_L2 | PX\_3 | PD:nppukp | RTSS QUP0 SE2 lane 2 | N | | BL5 | RTSS\_IO\_9 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BL5 | RTSS\_IO\_9 | RTSS\_QUP0\_SE2\_L3 | PX\_3 | PD:nppukp | RTSS QUP0 SE2 lane 3 | | | BK8 | RTSS\_IO\_10 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BK8 | RTSS\_IO\_10 | RTSS\_QUP0\_SE3\_L0 | PX\_3 | PD:nppukp | RTSS QUP0 SE3 lane 0 | N | | BK8 | RTSS\_IO\_10 | RTSS\_BOOT\_CONFIG[1] | PX\_3 | PD:nppukp | RTSS boot configuration bit 1 | N | | BM8 | RTSS\_IO\_11 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BM8 | RTSS\_IO\_11 | RTSS\_QUP0\_SE3\_L1 | PX\_3 | PD:nppukp | RTSS QUP0 SE3 lane 1 | N | | BM8 | RTSS\_IO\_11 | RTSS\_BOOT\_CONFIG[2] | PX\_3 | PD:nppukp | RTSS boot configuration bit 2 | N | | BL7 | RTSS\_IO\_12 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BL7 | RTSS\_IO\_12 | RTSS\_QUP0\_SE3\_L2 | PX\_3 | PD:nppukp | RTSS QUP0 SE3 lane 2 | N | | BL7 | RTSS\_IO\_12 | RTSS\_QUP0\_SE2\_L0 | PX\_3 | PD:nppukp | RTSS QUP0 SE2 lane 0 | N | | BL7 | RTSS\_IO\_12 | RTSS\_BOOT\_CONFIG[3] | PX\_3 | PD:nppukp | RTSS boot configuration bit 3 | N | | BM6 | RTSS\_IO\_13 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BM6 | RTSS\_IO\_13 | RTSS\_QUP0\_SE3\_L3 | PX\_3 | | RTSS QUP0 SE3 lane 3 | Y | | BM6 | RTSS\_IO\_13 | RTSS\_QUP0\_SE2\_L1 | PX\_3 | | RTSS QUP0 SE2 lane 1 | Y | | BM12 | RTSS\_IO\_14 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BM12 | RTSS\_IO\_14 | RTSS\_QUP0\_SE4\_L0 | PX\_3 | PD:nppukp | RTSS QUP0 SE4 lane 0 | N | | BM12 | RTSS\_IO\_14 | RTSS\_BOOT\_CONFIG[4] | PX\_3 | PD:nppukp | RTSS boot configuration bit 4 | N | | BG11 | RTSS\_IO\_15 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BG11 | RTSS\_IO\_15 | RTSS\_QUP0\_SE4\_L1 | PX\_3 | PD:nppukp | RTSS QUP0 SE4 lane 2 | N | | BG11 | RTSS\_IO\_15 | RTSS\_BOOT\_CONFIG[5] | PX\_3 | PD:nppukp | RTSS boot configuration bit 5 | N | | BJ11 | RTSS\_IO\_16 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BJ11 | RTSS\_IO\_16 | RTSS\_QUP0\_SE4\_L2 | PX\_3 | PD:nppukp | RTSS QUP0 SE4 lane 2 | N | | BJ11 | RTSS\_IO\_16 | RTSS\_BOOT\_CONFIG[11] | PX\_3 | PD:nppukp | RTSS boot configuration bit 11 | N | | BL11 | RTSS\_IO\_17 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BL11 | RTSS\_IO\_17 | RTSS\_QUP0\_SE4\_L3 | PX\_3 | PD:nppukp | RTSS QUP0 SE4 lane 3 | Y | | BL11 | RTSS\_IO\_17 | RTSS\_BOOT\_CONFIG[12] | PX\_3 | PD:nppukp | RTSS boot configuration bit 12 | Y | | BH10 | RTSS\_IO\_18 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BH10 | RTSS\_IO\_18 | RTSS\_QUP0\_SE4\_L4 | PX\_3 | PD:nppukp | RTSS QUP0 SE4 lane 4 | N | | BH10 | RTSS\_IO\_18 | RTSS\_BOOT\_CONFIG[6] | PX\_3 | PD:nppukp | RTSS boot configuration bit 6 | N | | BH18 | RTSS\_IO\_19 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BH18 | RTSS\_IO\_19 | RTSS\_ERR1 | PX\_3 | PD:nppukp | | N | | BK18 | RTSS\_IO\_20 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BK18 | RTSS\_IO\_20 | RTSS\_ERR2 | PX\_3 | PD:nppukp | | N | | BK6 | RTSS\_IO\_21 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BK6 | RTSS\_IO\_21 | RTSS\_EMAC0\_PHY\_INTR\_N | PX\_3 | PD:nppukp | RTSS Ethernet interrupt 0 | Y | | BK6 | RTSS\_IO\_21 | RTSS\_RGMII\_VOL\_SEL | PX\_3 | PD:nppukp | Voltage selection pin for RTSS RGMII interface | Y | | BK4 | RTSS\_IO\_22 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BK4 | RTSS\_IO\_22 | RTSS\_RGMII0\_MDC | PX\_3 | PD:nppukp | RTSS RGMII 0 management interface clock | N | | BK2 | RTSS\_IO\_23 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BK2 | RTSS\_IO\_23 | RTSS\_RGMII0\_MDIO | PX\_3 | PD:nppukp | RTSS RGMII0 management interface I/O | N | | BJ3 | RTSS\_IO\_24 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BJ3 | RTSS\_IO\_24 | RTSS\_RGMII0\_RXC | PX\_3 | PD:nppukp | RTSS RGMII 0 receive clock signal | N | | BJ1 | RTSS\_IO\_25 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BJ1 | RTSS\_IO\_25 | RTSS\_RGMII0\_RX\_CTL | PX\_3 | PD:nppukp | RTSS RGMII 0 receive control | N | | BH2 | RTSS\_IO\_26 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BH2 | RTSS\_IO\_26 | RTSS\_RGMII0\_RXD0 | PX\_3 | PD:nppukp | RTSS RGMII 0 receive data 0 | N | | BH4 | RTSS\_IO\_27 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BH4 | RTSS\_IO\_27 | RTSS\_RGMII0\_RXD1 | PX\_3 | PD:nppukp | RTSS RGMII 0 receive data 1 | N | | BG3 | RTSS\_IO\_28 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BG3 | RTSS\_IO\_28 | RTSS\_RGMII0\_RXD2 | PX\_3 | PD:nppukp | RTSS RGMII 0 receive data 2 | N | | BF4 | RTSS\_IO\_29 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BF4 | RTSS\_IO\_29 | RTSS\_RGMII0\_RXD3 | PX\_3 | PD:nppukp | RTSS RGMII 0 receive data 3 | N | | BJ5 | RTSS\_IO\_30 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BJ5 | RTSS\_IO\_30 | RTSS\_RGMII0\_TXC | PX\_3 | PD:nppukp | RTSS RGMII 0 transmit clock signal | N | | BJ7 | RTSS\_IO\_31 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BJ7 | RTSS\_IO\_31 | RTSS\_RGMII0\_TX\_CTL | PX\_3 | PD:nppukp | RTSS RGMII 0 transmit control | N | | BH6 | RTSS\_IO\_32 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BH6 | RTSS\_IO\_32 | RTSS\_RGMII0\_TXD0 | PX\_3 | PD:nppukp | RTSS RGMII 0 transmit data 0 | N | | BG5 | RTSS\_IO\_33 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BG5 | RTSS\_IO\_33 | RTSS\_RGMII0\_TXD1 | PX\_3 | PD:nppukp | RTSS RGMII 0 transmit data 1 | N | | BG7 | RTSS\_IO\_34 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BG7 | RTSS\_IO\_34 | RTSS\_RGMII0\_TXD2 | PX\_3 | PD:nppukp | RTSS RGMII 0 transmit data 2 | N | | BF6 | RTSS\_IO\_35 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BF6 | RTSS\_IO\_35 | RTSS\_RGMII0\_TXD3 | PX\_3 | PD:nppukp | RTSS RGMII 0 transmit data 3 | N | | BL3 | RTSS\_IO\_36 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BK12 | RTSS\_IO\_37 | | PX\_3 | PU:nppdkp | Configurable I/O | N | | BK12 | RTSS\_IO\_37 | RTSS\_CAN0\_TX | PX\_3 | PU:nppdkp | RTSS CAN 0 transmit | N | | BH12 | RTSS\_IO\_38 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BH12 | RTSS\_IO\_38 | RTSS\_CAN0\_RX | PX\_3 | PD:nppukp | RTSS CAN 0 receive | Y | | BH12 | RTSS\_IO\_38 | RTSS\_CC\_GP4\_CLK\_MIRB | PX\_3 | PD:nppukp | RTSS global general-purpose clock 4 B | Y | | BN13 | RTSS\_IO\_39 | | PX\_3 | PU:nppdkp | Configurable I/O | N | | BN13 | RTSS\_IO\_39 | RTSS\_CAN1\_TX | PX\_3 | PU:nppdkp | RTSS CAN 1 transmit | N | | BN13 | RTSS\_IO\_39 | RTSS\_CC\_GP5\_CLK\_MIRA | PX\_3 | PU:nppdkp | RTSS global general-purpose clock 5 A | N | | BL13 | RTSS\_IO\_40 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BL13 | RTSS\_IO\_40 | RTSS\_CAN1\_RX | PX\_3 | PD:nppukp | RTSS CAN 1 receive | | | BL13 | RTSS\_IO\_40 | RTSS\_CC\_GP5\_CLK\_MIRB | PX\_3 | PD:nppukp | RTSS global general-purpose clock 5 B | | | BJ13 | RTSS\_IO\_41 | | PX\_3 | PU:nppdkp | Configurable I/O | N | | BJ13 | RTSS\_IO\_41 | RTSS\_CAN2\_TX | PX\_3 | PU:nppdkp | RTSS CAN 2 transmit | N | | BJ13 | RTSS\_IO\_41 | RTSS\_EMAC0\_PTP\_PPS\_O\_1\_MIRA | PX\_3 | PU:nppdkp | RTSS EMAC0 configurable PPS output 1 A | N | | BJ13 | RTSS\_IO\_41 | RTSS\_EMAC0\_PTP\_AUX\_TS\_I\_0\_MIRA | PX\_3 | PU:nppdkp | RTSS EMAC0 trigger 0 A for auxiliary snapshot | N | | BJ13 | RTSS\_IO\_41 | RTSS\_CC\_GP1\_CLK\_MIRA | PX\_3 | PU:nppdkp | RTSS global general-purpose clock 1 A | N | | BG13 | RTSS\_IO\_42 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BG13 | RTSS\_IO\_42 | RTSS\_CAN2\_RX | PX\_3 | PD:nppukp | RTSS CAN 2 receive | Y | | BG13 | RTSS\_IO\_42 | RTSS\_EMAC0\_PTP\_PPS\_O\_0\_MIRA | PX\_3 | PD:nppukp | RTSS EMAC0 configurable PPS output 0 A | Y | | BG13 | RTSS\_IO\_42 | RTSS\_CC\_GP2\_CLK\_MIRA | PX\_3 | PD:nppukp | RTSS global general-purpose clock 2 A | Y | | BM14 | RTSS\_IO\_43 | | PX\_3 | PU:nppdkp | Configurable I/O | N | | BM14 | RTSS\_IO\_43 | RTSS\_CAN3\_TX | PX\_3 | PU:nppdkp | RTSS CAN 3 transmit | N | | BM14 | RTSS\_IO\_43 | RTSS\_EMAC0\_PTP\_PPS\_O\_0\_MIRB | PX\_3 | PU:nppdkp | RTSS EMAC0 configurable PPS output 0 B | N | | BM14 | RTSS\_IO\_43 | RTSS\_CC\_GP2\_CLK\_MIRB | PX\_3 | PU:nppdkp | RTSS global general-purpose clock 2 B | N | | BK14 | RTSS\_IO\_44 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BK14 | RTSS\_IO\_44 | RTSS\_CAN3\_RX | PX\_3 | PD:nppukp | RTSS CAN 3 receive | Y | | BK14 | RTSS\_IO\_44 | RTSS\_EMAC0\_PTP\_PPS\_O\_1\_MIRB | PX\_3 | PD:nppukp | RTSS EMAC0 configurable PPS output 1 B | Y | | BK14 | RTSS\_IO\_44 | RTSS\_CC\_GP3\_CLK\_MIRA | PX\_3 | PD:nppukp | RTSS global general-purpose clock 3 A | Y | | BH14 | RTSS\_IO\_45 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BH14 | RTSS\_IO\_45 | RTSS\_CAN0\_CTL | PX\_3 | PD:nppukp | RTSS CAN0 control | Y | | BH14 | RTSS\_IO\_45 | RTSS\_EMAC0\_PTP\_PPS\_O\_2 | PX\_3 | PD:nppukp | RTSS EMAC0 configurable PPS output 2 | Y | | BH14 | RTSS\_IO\_45 | RTSS\_CC\_GP3\_CLK\_MIRB | PX\_3 | PD:nppukp | RTSS global general-purpose clock 3 B | Y | | BL15 | RTSS\_IO\_46 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BL15 | RTSS\_IO\_46 | RTSS\_CAN1\_CTL | PX\_3 | PD:nppukp | RTSS CAN1 control | Y | | BL15 | RTSS\_IO\_46 | RTSS\_EMAC0\_PTP\_AUX\_TS\_I\_0\_MIRB | PX\_3 | PD:nppukp | RTSS EMAC0 trigger 0 B for auxiliary snapshot | Y | | BL15 | RTSS\_IO\_46 | RTSS\_EMAC0\_PTP\_PPS\_O\_3 | PX\_3 | PD:nppukp | RTSS EMAC0 configurable PPS output 3 | Y | | BL15 | RTSS\_IO\_46 | RTSS\_CC\_GP1\_CLK\_MIRB | PX\_3 | PD:nppukp | RTSS global general-purpose clock 1 B | Y | | BJ15 | RTSS\_IO\_47 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BJ15 | RTSS\_IO\_47 | RTSS\_CAN2\_CTL | PX\_3 | PD:nppukp | RTSS CAN2 control | Y | | BJ15 | RTSS\_IO\_47 | RTSS\_EMAC0\_MCG\_PST\_TRIG\_LW[0] | PX\_3 | PD:nppukp | RTSS EMAC0 trigger input 0 for media clock generation | Y | | BJ15 | RTSS\_IO\_47 | RTSS\_CC\_GP4\_CLK\_MIRA | PX\_3 | PD:nppukp | RTSS global general-purpose clock 4 A | Y | | BG15 | RTSS\_IO\_48 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BG15 | RTSS\_IO\_48 | RTSS\_CAN3\_CTL | PX\_3 | PD:nppukp | RTSS CAN3 control | Y | | BG15 | RTSS\_IO\_48 | RTSS\_EMAC0\_MCG\_PST\_TRIG\_LW[1] | PX\_3 | PD:nppukp | RTSS EMAC0 trigger input 1 for media clock generation | Y | | BM16 | RTSS\_IO\_49 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BM16 | RTSS\_IO\_49 | RTSS\_CAN4\_CTL | PX\_3 | PD:nppukp | RTSS CAN4 control | Y | | BM16 | RTSS\_IO\_49 | RTSS\_EMAC0\_MCG\_PST\_TRIG\_LW[2] | PX\_3 | PD:nppukp | RTSS EMAC0 trigger input 2 for media clock generation | Y | | BK16 | RTSS\_IO\_50 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BK16 | RTSS\_IO\_50 | RTSS\_CAN5\_CTL | PX\_3 | PD:nppukp | RTSS CAN5 control | Y | | BK16 | RTSS\_IO\_50 | RTSS\_EMAC0\_MCG\_PST\_TRIG\_LW[3] | PX\_3 | PD:nppukp | RTSS EMAC0 trigger input 3 for media clock generation | Y | | BL17 | RTSS\_IO\_51 | RTSS\_INT | PX\_3 | PD:nppukp | Configurable I/O | Y | | BL17 | RTSS\_IO\_51 | RTSS\_BOOT\_CONFIG[0] | PX\_3 | PD:nppukp | RTSS boot configuration bit 0 | Y | | BM18 | RTSS\_IO\_52 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BM18 | RTSS\_IO\_52 | PRTSS\_ERR\_N | PX\_3 | PD:nppukp | PMIC RTSS domain error signal active low (internally pulled up to 1.8 V) | Y | | BN17 | RTSS\_IO\_53 | RTSS\_PMIC\_INT\_N | PX\_3 | PD:nppukp | Configurable I/O | Y | | BH16 | RTSS\_IO\_54 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BG17 | RTSS\_IO\_55 | | PX\_3 | PD:nppukp | Configurable I/O | Y | | BG17 | RTSS\_IO\_55 | RTSS\_SLP\_EN | PX\_3 | PD:nppukp | RTSS sleep enable | Y | | BF2 | RTSS\_IO\_56 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BF2 | RTSS\_IO\_56 | RTSS\_QSPI0\_CS\_N\_0 | PX\_3 | PD:nppukp | RTSS QSPI0 chip-select 0 | N | | BE7 | RTSS\_IO\_57 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BE7 | RTSS\_IO\_57 | RTSS\_QSPI0\_DQS | PX\_3 | PD:nppukp | RTSS QSPI0 differential data strobe | N | | BJ17 | RTSS\_IO\_58 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BJ17 | RTSS\_IO\_58 | RTSS\_FORCED\_USB\_BOOT | PX\_3 | PD:nppukp | Bootstrap to enter USB0 emergency download mode for RTSS domain | N | | BE5 | RTSS\_IO\_59 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BE5 | RTSS\_IO\_59 | RTSS\_QSPI0\_CLK | PX\_3 | PD:nppukp | RTSS QSPI0 clock | N | | BE3 | RTSS\_IO\_60 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BE3 | RTSS\_IO\_60 | RTSS\_QSPI0\_DATA[0] | PX\_3 | PD:nppukp | RTSS QSPI0 data 0 | N | | BE1 | RTSS\_IO\_61 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BE1 | RTSS\_IO\_61 | RTSS\_QSPI0\_DATA[1] | PX\_3 | PD:nppukp | RTSS QSPI0 data 1 | N | | BD6 | RTSS\_IO\_62 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BD6 | RTSS\_IO\_62 | RTSS\_QSPI0\_DATA[2] | PX\_3 | PD:nppukp | RTSS QSPI0 data 2 | N | | BD4 | RTSS\_IO\_63 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BD4 | RTSS\_IO\_63 | RTSS\_QSPI0\_DATA[3] | PX\_3 | PD:nppukp | RTSS QSPI0 data 3 | N | | BD2 | RTSS\_IO\_64 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BD2 | RTSS\_IO\_64 | RTSS\_QSPI0\_DATA[4] | PX\_3 | PD:nppukp | RTSS QSPI0 data 4 | N | | BC7 | RTSS\_IO\_65 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BC7 | RTSS\_IO\_65 | RTSS\_QSPI0\_DATA[5] | PX\_3 | PD:nppukp | RTSS QSPI0 data 5 | N | | BC5 | RTSS\_IO\_66 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BC5 | RTSS\_IO\_66 | RTSS\_QSPI0\_DATA[6] | PX\_3 | PD:nppukp | RTSS QSPI0 data 6 | N | | BC3 | RTSS\_IO\_67 | | PX\_3 | PD:nppukp | Configurable I/O | N | | BC3 | RTSS\_IO\_67 | RTSS\_QSPI0\_DATA[7] | PX\_3 | PD:nppukp | RTSS QSPI0 data 7 | N | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LPASS I/O | Configurable function | Functional description | | --- | --- | --- | | LPASS\_0 | | (GPIO\_110) | | LPASS\_0 | LPI\_QUA\_MI2S\_SCK | LPI quad I²S clock | | LPASS\_1 | | (GPIO\_111) | | LPASS\_1 | LPI\_QUA\_MI2S\_WS | LPI quad I²S word select | | LPASS\_2 | | (GPIO\_112) | | LPASS\_2 | LPI\_QUA\_MI2S\_DATA0 | LPI quad I²S serial channel 0 | | LPASS\_3 | | (GPIO\_113) | | LPASS\_3 | LPI\_QUA\_MI2S\_DATA1 | LPI quad I²S serial channel 1 | | LPASS\_4 | | (GPIO\_114) | | LPASS\_4 | LPI\_QUA\_MI2S\_DATA2 | LPI quad I²S serial channel 2 | | LPASS\_5 | | (GPIO\_115) | | LPASS\_5 | LPI\_QUA\_MI2S\_DATA3 | LPI quad I²S serial channel 3 | | LPASS\_5 | EXT\_MCLK1\_C | MI2S external MCLK1 C | | LPASS\_6 | | (GPIO\_116) | | LPASS\_6 | LPI\_I2S1\_CLK | LPI I²S 1 clock | | LPASS\_7 | | (GPIO\_117) | | LPASS\_7 | LPI\_I2S1\_WS | LPI I²S 1 word select | | LPASS\_8 | | (GPIO\_118) | | LPASS\_8 | LPI\_I2S1\_DATA0 | LPI I²S 1 serial channel 0 | | LPASS\_9 | | (GPIO\_119) | | LPASS\_9 | LPI\_I2S1\_DATA1 | LPI I²S 1 data | | LPASS\_10 | | (GPIO\_120) | | LPASS\_10 | LPI\_I2S2\_CLK | LPI I²S 2 clock | | LPASS\_11 | | (GPIO\_121) | | LPASS\_11 | LPI\_I2S2\_WS | LPI I²S 2 word select | | LPASS\_12 | | (GPIO\_125) | | LPASS\_12 | LPI\_I2S4\_CLK | LPI I²S 4 clock | | LPASS\_13 | | (GPIO\_126) | | LPASS\_13 | LPI\_I2S4\_WS | LPI I²S 4 word select | | LPASS\_13 | EXT\_MCLK1\_A | MI²S external MCLK1 A | | LPASS\_14 | | (GPIO\_124) | | LPASS\_14 | EXT\_MCLK1\_D | MI²S external MCLK1 D | | LPASS\_15 | | (GPIO\_122) | | LPASS\_15 | LPI\_I2S2\_DATA0 | LPI I²S 2 serial channel 0 | | LPASS\_16 | | (GPIO\_123) | | LPASS\_16 | LPI\_I2S2\_DATA1 | LPI I²S 2 serial channel 1 | | LPASS\_17 | | (GPIO\_127) | | LPASS\_17 | LPI\_I2S4\_DATA0 | LPI I²S 4 serial channel 0 | | LPASS\_18 | | (GPIO\_128) | | LPASS\_18 | LPI\_I2S4\_DATA1 | LPI I²S 4 serial channel 1 | | LPASS\_19 | | (GPIO\_129) | | LPASS\_19 | LPI\_I2S3\_CLK | LPI I²S 3 clock | | LPASS\_20 | | (GPIO\_130) | | LPASS\_20 | LPI\_I2S3\_WS | LPI I²S 3 word select | | LPASS\_21 | | (GPIO\_131) | | LPASS\_21 | LPI\_I2S3\_DATA0 | LPI I²S 3 serial channel 0 | | LPASS\_22 | | (GPIO\_132) | | LPASS\_22 | LPI\_I2S3\_DATA1 | LPI I²S 3 serial channel 1 | | LPASS\_22 | EXT\_MCLK1\_E | MI2S external MCLK1 E | | | | | | | | | Table : Pin descriptions – power supply pins | Pin number | Pin name | Functional description | | --- | --- | --- | | AA33, AA39, AC39, AD38, AD40, AF34, AF38, AF40, U37, U39, V38, V40, W33, Y38,
Y40 | VDD\_APC0 | Power for the Kryo application processor | | AB32, AC29, AC31, AD32, AF32 | VDD\_APC1 | Power for the Kryo application processor | | AY24 | VDD\_A\_CSI\_0\_0P9 | Power for MIPI CSI0 0.9 V analog circuits | | BA25 | VDD\_A\_CSI\_0\_1P2 | Power for MIPI CSI0 1.2 V analog circuits | | AY26 | VDD\_A\_CSI\_1\_0P9 | Power for MIPI CSI1 0.9 V analog circuits | | BA27 | VDD\_A\_CSI\_1\_1P2 | Power for MIPI CSI1 1.2 V analog circuits | | AY28 | VDD\_A\_CSI\_2\_0P9 | Power for MIPI CSI2 0.9 V analog circuits | | BA29 | VDD\_A\_CSI\_2\_1P2 | Power for MIPI CSI2 1.2 V analog circuits | | BA31 | VDD\_A\_DSI\_0\_0P9 | Power for MIPI DSI0 0.9 V analog circuits | | AY32 | VDD\_A\_DSI\_0\_1P2 | Power for MIPI DSI0 1.2 V analog circuits | | AY30 | VDD\_A\_DSI\_0\_PLL\_0P9 | Power for MIPI DSI0 PLL 0.9 V | | R25, R27, R33, R35 | VDD\_A\_EBI\_CCPLL\_0P9 | Power for EBI clock PLL 0.9 V circuits | | N21, N29, N37, P16, P18, P20, P22, P24, P26, P28, P30, P32, P34, P36, P38,
R15 | VDD\_A\_EBI\_PHY | Power for EBI PHY circuits | | AH42 | VDD\_A\_EDP\_0\_1P2 | Power for eDP 0 1.2 V analog circuits | | AG43 | VDD\_A\_EDP\_0\_CORE | Power for eDP 0 analog circuits | | AJ11, AJ13, AL11 | VDD\_A\_PCIE\_0\_CORE | Power for PCIe 0 core analog circuits | | AL13 | VDD\_A\_PCIE\_0\_PLL\_1P2 | Power for PCIe 0 PLL 1.2 V analog circuits | | AC11, AE15, AF10, AF14 | VDD\_A\_PCIE\_1\_CORE | Power for PCIe 1 core analog circuits | | AC13 | VDD\_A\_PCIE\_1\_PLL\_1P2 | Power for PCIe 1 PLL 1.2 V analog circuits | | AF46 | VDD\_A\_QREFS\_0P875\_0 | Reference voltage for QREFS 0 0.875 V circuits | | AA13 | VDD\_A\_QREFS\_0P875\_1 | Reference voltage for QREFS 1 0.875 V circuits | | W13 | VDD\_A\_QREFS\_1P2\_1 | Reference voltage for QREFS 1 1.2 V circuits | | N13 | VDD\_A\_QREFS\_TX1\_0P9 | Reference voltage 0.88 V | | BD28 | VDD\_A\_REFGEN\_0P875\_3 | Reference voltage 0.875 V | | BD30 | VDD\_A\_REFGEN\_1P2\_3 | Reference voltage 1.2 V | | AN13 | VDD\_A\_SGMII\_0\_0P9 | Power for the first Ethernet interface | | AP12 | VDD\_A\_SGMII\_0\_1P2 | Power for the second Ethernet interface | | AF42 | VDD\_A\_UFS\_0\_1P2 | Power for the UFS 0 1.2 V analog circuits | | AD42 | VDD\_A\_UFS\_0\_CORE | Power for UFS 0 core circuits | | AB10 | VDD\_A\_USBHS\_0\_1P8 | Power for the USB high-speed 0 1.8 V analog circuits | | Y10 | VDD\_A\_USBHS\_0\_3P1 | Power for the USB high-speed 0 3.1 V analog circuits | | AA11 | VDD\_A\_USBHS\_0\_CORE | Power for the USB high-speed core circuits | | W11 | VDD\_A\_USBHS\_1\_1P8 | Power for the USB high-speed 1 1.8 V analog circuits | | U11 | VDD\_A\_USBHS\_1\_3P1 | Power for the USB high-speed 1 3.1 V analog circuits | | V10 | VDD\_A\_USBHS\_1\_CORE | Power for the USB high-speed 1 core circuits | | V12 | VDD\_A\_USBSS\_0\_1P2 | Power for the USB SuperSpeed 0 1.2 V analog circuits | | U13 | VDD\_A\_USBSS\_0\_CORE | Power for the USB SuperSpeed 0 core circuits | | AA27, AA31, AB28, AE27, AJ23, AK16, AK18, AK20, AK22, W31 | VDD\_CX | Power for digital core circuits | | AG37, AH36, AH40, AJ35, AJ39 | VDD\_CX\_LPI | Power for LPI digital core circuits | | T18, T20, T22, T26, T28, T30, T34, T36, T38, U25, U31, U33 | VDD\_D\_EBI | Power for EBI digital circuits | | AL25, AL29, AN29, AR25, AR29, AT26, AT28, AV26, AV28 | VDD\_GFX | Power for graphics | | L23, L31, M16, M18, M20, M22, M24, M26, M28, M30, M32, M34, M36, M38 | VDD\_IO\_EBI\_PHY | Power for EBI PHY circuits | | AB26, AD26, AL35, AL37, AM38, AN31, AN37, AN39, AP36, AP40, AR31, AR33, AR37,
AR39, AT34, AT36, AU31, AU33, AU35, AU39, AV32, AV36, AV40, W25, W27, Y26 | VDD\_MM | Power for multimedia subsystem circuits | | AE33, AG31, AG33, AG35, AJ31 | VDD\_MX\_A | Power for memory circuits | | AC25, AD24, AE25, AF24, AK24, AK26, AK32, AK34, AL31, AM24 | VDD\_MX\_C | Power for memory circuits | | AJ33, AK36, AK38 | VDD\_MX\_LPI | Power for LPI memory circuit | | AD16, AD18, AF16, AF18, AG17, AG23, AH14, AH16, AH20, AH22, AJ15, AJ19 | VDD\_NSP\_CX | Power for HTP current sensor | | AA15, AA17, AB24, AC15, AC17, AC19, AC21, AD22, U17, U21, V14, V16, V18, V22,
V24, W15, Y16, Y24 | VDD\_NSP\_HMX | Power for HTP HMX | | AK42 | VDD\_PX0 | Power for pad group 0 | | AJ43, L25, L27, L33, L35 | VDD\_PX1 | Power for pad group 1 | | AG45, M12 | VDD\_PX11 | Power for pad group 11 | | AL43, AR43, AR9, BB36, BB40, BD16, BD20, N11 | VDD\_PX3 | Power for pad group 3 | | AP10 | VDD\_PX7 | Power for pad group 7 | | AE45 | VDD\_PX9 | Power for pad group 9 | | BB18, BB22 | VDD\_QFPROM | Power for programming the QFPROM | | AT10 | VDD\_QFPROM\_RTSS | Power for programming the QFPROM; RTSS | | AN21, AN23, AP16, AP20, AP24, AR15, AR17, AR21, AR23, AT18, AT20, AU15, AU17,
AU23, AV16, AV20, AV22, AV24 | VDD\_RTSS\_CX | Power for RTSS core circuits | | AL19, AL21, AM16, AM18, AM22, AN17, AN19 | VDD\_RTSS\_MX | Power for RTSS on-chip memory circuits | | BC23 | VDD\_RTSS\_PX0 | Power for RTSS pad group 0 | | BC15 | VDD\_RTSS\_PX11 | Power for RTSS pad group 11 | | AR11, BC17, BC21 | VDD\_RTSS\_PX3 | Power for RTSS pad group 3 | Table : Pin descriptions – ground pins | Pin number | Pin name | Functional description | | --- | :---: | --- | | A13, A21, A27, A33, A39, A49, A5, AA1, AA25, AA41, AA45, AA49, AA5, AA53, AA7, AA9, AB12, AB14, AB16, AB2, AB30, AB38, AB40, AB42, AB46, AB52, AB6, AC1, AC23, AC27, AC3, AC33, AC41, AC45, AC49, AC5, AC51, AC53, AC9, AD10, AD14, AD20, AD4, AD46, AE1, AE17, AE23, AE39, AE41, AE43, AE49, AE5, AE53, AE9, AF36, AF44, AF50, AF6, AG1, AG15, AG3, AG39, AG41, AG5, AG51, AG53, AG7, AG9, AH10, AH12, AH18, AH24, AH32, AH34, AH38, AH4, AH44, AH46, AJ1, AJ17, AJ21, AJ37, AJ41, AJ45, AJ5, AJ9, AK10, AK12, AK14, AK40, AK44, AK46, AK6, AL1, AL17, AL23, AL27, AL3, AL33, AL39, AL41, AL45, AL5, AL53, AM10, AM12, AM2, AM20, AM30, AM36, AM4, AM40, AM42, AM44, AM46, AM6, AM8, AN11, AN41, AN43, AN45, AN9, AP18, AP22, AP30, AP38, AP4, AP42, AP44, AP46, AP8, AR13, AR19, AR27, AR3, AR35, AR41, AR45, AR53, AT12, AT14, AT16, AT2, AT22, AT24, AT30, AT32, AT38, AT40, AT42, AT44, AT46, AT8, AU11, AU13, AU19, AU21, AU25, AU27, AU29, AU37, AU41, AU43, AU45, AU9, AV10, AV12, AV14, AV18, AV30, AV34, AV38, AV42, AV44, AV46, AW1, AW13, AW15, AW17, AW19, AW21, AW23, AW25, AW27, AW29, AW31, AW33, AW35, AW37, AW39, AW41, AW43, AW45, AW53, AW9, AY10, AY12, AY14, AY16, AY34, AY36, AY38, AY40, AY42, AY44, AY46, B10, B16, B18, B24, B30, B34, B36, B42, B44, B46, B8, BA11, BA13, BA15, BA23, BA33, BA35, BA37, BA39, BA41, BA43, BA45, BA9, BB10, BB12, BB14, BB16, BB20, BB24, BB26, BB28, BB30, BB32, BB34, BB38, BB42, BB44, BB46, BB8, BC1, BC11, BC13, BC19, BC25, BC27, BC29, BC31, BC33, BC35, BC37, BC39, BC41, BC43, BC45, BC53, BC9, BD10, BD12, BD14, BD18, BD22, BD24, BD26, BD32, BD34, BD36, BD38, BD40, BD42, BD44, BD46, BD8, BE11, BE13, BE15, BE17, BE19, BE21, BE23, BE25, BE27, BE29, BE31, BE33, BE35, BE37, BE39, BE41, BE43, BE45, BE9, BF10, BF12, BF14, BF16, BG1, BG53, BJ21, BJ23, BJ27, BJ29, BJ35, BJ37, BJ43, BJ45, BK20, BK24, BK30, BK32, BK34, BK40, BK42, BK46, BK48, BL19, BL31, BL39, BL49, BM38, BN11, BN15, BN19, BN23, BN25, BN27, BN37, BN45, BN49, BN7, C13, C19, C21, C23, C27, C31, C33, C39, C47, C49, C5, C7, D10, D16, D2, D24, D30, D4, D44, D46, D50, D52, D8, E13, E17, E19, E25, E27, E29, E35, E37, E39, E41, F10, F14, F18, F2, F20, F22, F32, F34, F36, F4, F40, F44, F46, F48, F50, F52, F6, F8, G11, G23, G25, G27, G29, G31, H16, H18, H2, H20, H22, H32, H34, H42, H44, H46, H48, H52, H6, H8, J11, J13, J15, J27, J3, J35, J37, J39, J41, J49, J5, J51, J9, K2, K24, K26, K28, K30, K38, K52, L11, L15, L17, L19, L21, L29, L3, L37, L39, L43, L45, L49, L5, L51, L7, M10, M14, M4, M40, M42, M44, M46, M48, M50, M52, N15, N17, N19, N23, N25, N27, N3, N31, N33, N35, N39, N41, N43, N45, N47, N49, N51, N53, P10, P12, P14, P2, P40, P42, P44, P46, P48, P52, R17, R19, R21, R23, R29, R3, R31, R37, R39, R43, R47, R49, R5, R53, T10, T12, T16, T24, T32, T4, T40, T42, T44, T48, U15, U19, U23, U27, U29, U35, U41, U43, U49, U5, U51, U53, U7, U9, V2, V20, V26, V32, V4, V44, V46, V48, V52, W1, W17, W3, W39, W45, W47, W49, W5, W53, W9, Y12, Y14, Y32, Y42, Y46, Y8 | GND | Ground | Table : Pin descriptions – NC and DNC pins | Pin number | Pin name | Functional description | | --- | :---: | --- | | A1, A3, A51, A53, B2, B52, BL1, BL53, BM2, BM52, BN1, BN3, BN51, BN53, C1, C53 | NC | No connect; not connected internally. | | AY8, AV8, AD44, Y44, BA21, AB44, AP14, AL15, T14, BA19, BA17, L13, L41, BF28, M8,
BF40, BF18, AC43, W43, AY22, AA43, AN15, AM14, R13, AY20, AY18, W41, V42 | DNC | Do not connect; connected internally, do not connect externally. | Last Published: Jan 08, 2026 [Previous Topic Introduction](https://docs.qualcomm.com/bundle/publicresource/80-73475-1/topics/introduction.md) [Next Topic Electrical specifications](https://docs.qualcomm.com/bundle/publicresource/80-73475-1/topics/electrical-specifications.md)