# References
This section includes the following references:
- Low-speed and high-speed expansion connector locations, GPIOs, and pin numbers
- DIP switch locations and functions
- How to interface a custom camera sensor
- Reference designs and related documents
- Acronyms and terms
## Low-speed and high-speed expansion connectors
All regular GPIOs and Qualcomm universal peripherals (QUPs) are 1.8 V logic unless otherwise specified.
The following image shows the location of the low-speed and high-speed expansion connectors on the mainboard.
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### Low-speed expansion connector 1 (LS1)
The LS1 connector has the following functionalities:
- UART (x2)
- I2C (x2)
- SPI
- PCM
- GPIOs (x12)
- DC power
- Ground
The GPIOs labeled QUP have additional low-speed interface capabilities (UART, SPI, I2C).
You can also use low-speed interfaces to control various peripherals, such as audio functions.
| Wake-up function | GPIO | Signal | Pin number | Pin number | Signal | GPIO | Wake-up function |
| --- | --- | --- | --- | --- | --- | --- | --- |
| – | – | GND | 1 | 2 | GND | – | – |
| Yes | 16 | UART0\_CTS | 3 | 4 | PWR\_BTN\_N | KPD\_PWR\_N | – |
| Yes | 18 | UART0\_TXD | 5 | 6 | RST\_BTN\_N | PM\_RESIN\_N | – |
| Yes | 19 | UART0\_RXD | 7 | 8 | SPI0\_SCLK | 46 | – |
| – | 17 | UART0\_RTS | 9 | 10 | SPI0\_MISO | 44 | Yes |
| – | 22 | UART1\_TXD | 11 | 12 | SPI0\_CS | 47 | Yes |
| Yes | 23 | UART1\_RXD | 13 | 14 | SPI0\_MOSI | 45 | Yes |
| – | 9 | I2C0\_SCL | 15 | 16 | PCM\_FS/I2S0\_WS | 100 | – |
| Yes | 8 | I2C0\_SDA | 17 | 18 | PCM\_CLK/I2S0\_CLK | 97 | – |
| – | 5 | I2C1\_SCL | 19 | 20 | PCM\_DO/I2S0\_D1 | 99 | – |
| Yes | 4 | I2C1\_SDA | 21 | 22 | PCM\_DI/I2S0\_D0 | 98 | – |
| Yes | 36 | GPIO-A/QUP-A0 | 23 | 24 | GPIO-B | 96 | Yes |
| – | 37 | GPIO-C/QUP-A1 | 25 | 26 | GPIO-D/QUP-A3 | 39 | Yes |
| – | 38 | GPIO-E/QUP-A2 | 27 | 28 | GPIO-F\* | 124 | – |
| Yes | 80 | GPIO-G\* | 29 | 30 | GPIO-H\* | 123 | Yes |
| Yes | 20 | GPIO-I\* | 31 | 32 | GPIO-J\* | 109 | – |
| Yes | 21 | GPIO-K\* | 33 | 34 | GPIO-L\* | 136 | Yes |
| – | – | 1.8 V-A | 35 | 36 | SYS\_DCIN | – | – |
| – | – | 5V | 37 | 38 | SYS\_DCIN | – | – |
| – | – | GND | 39 | 40 | GND | – | – |
### Low-speed expansion connector 2 (LS2)
The LS2 connector has the following functionalities:
- Three pairs of DMICs
- Additional 4‑bit I2S audio interface
- CAN-FD interface
- 2x camera CCI I2C
- PMIC PWM and ADC pins
- Configurable interface available for SPI/I2C and UART
- Spare GPIOs
- Battery ID/therm
You can also use low-speed interfaces to control various peripherals, such as audio functions.
| Wake-up function | GPIO | Signal | Pin number | Pin number | Signal | GPIO | Wake-up function |
| --- | --- | --- | --- | --- | --- | --- | --- |
| Yes | 78 | GPIO-U | 1 | 2 | GPIO-Z | 149 | Yes |
| Yes | 150 | DMIC CLK1/AMIC1\_P | 3 | 4 | CAN\_H | – | – |
| Yes | 151 | DMIC DATA1/AMIC1\_M | 5 | 6 | CAN\_L | – | – |
| Yes | 148 | GPIO-V/I2S1\_DATA2 | 7 | 8 | 1.8V-A | VREG\_SYS\_1P8 | – |
| – | 152 | DMIC CLK2/AMIC3\_P | 9 | 10 | GND | – | – |
| Yes | 153 | DMIC DATA2/AMIC3\_M | 11 | 12 | PM\_GPIO-A (PWM output) | – | – |
| – | 110 | GPIO-W/I2S1\_DATA3 (CAM5\_RST\_N) | 13 | 14 | PM\_GPIO-B (PWM output) | – | – |
| Yes | 156 | DMIC CLK3/HS\_MIC\_P | 15 | 16 | GPIO-M/QUP-B0 | 32 | Yes |
| Yes | 157 | DMIC DATA3/HS\_MIC\_M | 17 | 18 | GPIO-N/QUP-B1 | 33 | – |
| – | – | PM\_GPIO-F | 19 | 20 | GPIO-O/QUP-B2 (also PWM) | 34 | Yes |
| – | 74 | CCI\_I2C\_SCL2 | 21 | 22 | GPIO-P/QUP-B3 | 35 | Yes |
| – | 73 | CCI\_I2C\_SDA2 | 23 | 24 | GPIO-Q/I2S1\_WS | 145 | Yes |
| – | 76 | CCI\_I2C\_SCL3 | 25 | 26 | GPIO-R/I2S1\_CLK | 144 | – |
| – | – | SPK0\_P | 27 | 28 | GPIO-S/I2S1\_DATA0 | 146 | – |
| – | – | SKP0\_M | 29 | 30 | GPIO-T/I2S1\_DATA1 | 147 | – |
| – | – | SPK1\_P | 31 | 32 | PM\_GPIO-C (ADC IN) | PM\_B\_AMUX2 (PM7325) | – |
| – | – | SPK1\_M | 33 | 34 | PM\_GPIO-D (ADC IN) | PM\_B\_AMUX4 (PM7325) | – |
| Yes | 75 | CCI\_I2C\_SDA3 | 35 | 36 | BATT\_THERM | PM7250B BATT\_THERM | – |
| – | – | PM\_GPIO-E | 37 | 38 | BATT\_ID | PM7250B BATT\_ID | – |
| – | – | VBAT | 39 | 40 | USB\_VBUS | – | – |
| – | – | GND | 41 | 42 | GND | – | – |
| Yes | 6 | GPIO-X | 43 | 44 | GPIO-AA | 25 | Yes |
| – | 137 | GPIO-Y | 45 | 46 | GPIO-BB | 120 | – |
### Low-speed expansion connector 3 (LS3)
The LS3 connector has the following functionalities:
- Four Qualcomm sensor core QUP interfaces
- Interrupts signals for sensors
- Additional GPIOs and power supplies
The GPIOs labeled QUP have additional low-speed interface capabilities (UART, SPI, I2C). Several GPIOs can be used to wake up the application processor.
| Wake-up function | GPIO | Signal | Pin number | Pin number | Signal | GPIO | Wake-up function |
| --- | --- | --- | --- | --- | --- | --- | --- |
| – | 68 | GPIO-KK | 1 | 2 | GPIO-TT | 90 | – |
| – | PMIC | SLEEP\_CLK | 3 | 4 | CLK | PMIC | – |
| Yes | 119 | GPIO-LL | 5 | 6 | GPIO-UU | 83 | Yes |
| Yes | 40 | GPIO-MM | 7 | 8 | QCA\_GPIO-D GPIO-YY | 112 | – |
| Yes | 41 | GPIO-NN | 9 | 10 | QCA\_GPIO-E GPIO-ZZ | 113 | – |
| – | 42 | GPIO-OO | 11 | 12 | GPIO-VV | 114 | Yes |
| – | 111 | QCA\_GPIO-A GPIO-AAA | 13 | 14 | GPIO-WW | 115 | Yes |
| – | 116 | QCA\_GPIO-B GPIO-BBB | 15 | 16 | SPI3\_MISO | 48 | Yes |
| – | 117 | QCA\_GPIO-C GPIO-CCC | 17 | 18 | SPI3\_MOSI | 49 | – |
| Yes | 43 | GPIO-PP | 19 | 20 | SPI3\_CLK | 50 | – |
| – | 129 | GPIO-QQ | 21 | 22 | SPI3\_CS | 51 | Yes |
| Yes | 165 | SPI2\_CLK (on SSC\*) | 23 | 24 | PS\_INT | 104 | Yes |
| – | 164 | SPI2\_MOSI (on SSC\*) | 25 | 26 | ACCEL\_INT | 103 | Yes |
| Yes | 163 | SPI2\_MISO (on SSC\*) | 27 | 28 | GYRO\_INT | 102 | Yes |
| Yes | 166 | SPI2\_ACCEL\_CS (on SSC\*) | 29 | 30 | MAG\_INT | 142 | Yes |
| – | 161 | SPI2\_CS1 (on SSC\*) | 31 | 32 | MAG\_DRDY\_INT | 81 | Yes |
| Yes | 55 | SPI3\_CS1 (on SSC\*) | 33 | 34 | I2C4\_SDA (on SSC\*) | 159 | – |
| – | VREG\_L8C\_1P8 | 1.8 V-B | 35 | 36 | I2C4\_SCL (on SSC\*) | 160 | – |
| – | – | 5V | 37 | 38 | 1.8 V-C | VREG\_L2C\_1P8 | – |
| – | – | VBAT | 39 | 40 | GND | – | – |
| – | – | GND | 41 | 42 | GND | – | – |
| Yes | 130 | GPIO-RR | 43 | 44 | SPI3\_CS2 | 54 | Yes |
| Yes | 52 | GPIO-SS | 45 | 46 | GPIO-XX | 53 | – |
\* SSC is the sensor core running on DSP.
### High-speed expansion connector 1 (HS1)
The HS1 connector has the following functionalities:
- GPIOs
- Display serial interface (DSI)
- Camera serial interfaces (CSI) (x2)
- Camera MClk
- Camera control interface (CCI) I2C
- USB DP/DM
| Wake-up function | GPIO | Signal | Pin number | Pin number | Signal | GPIO | Wake-up function |
| --- | --- | --- | --- | --- | --- | --- | --- |
| – | 61 | GPIO | 1 | 2 | CSI0\_C\_P | – | – |
| – | 118 | GPIO | 3 | 4 | CSI0\_C\_M | – | – |
| – | 138 | GPIO | 5 | 6 | GND | – | – |
| – | 63 | GPIO | 7 | 8 | CSI0\_D0\_P | – | – |
| – | 62 | GPIO | 9 | 10 | CSI0\_D0\_M | – | – |
| – | 60 | GPIO | 11 | 12 | GND | – | – |
| – | – | GND | 13 | 14 | CSI0\_D1\_P | – | – |
| – | 64 | CLK0/CSI0\_MCLK | 15 | 16 | CSI0\_D1\_M | – | – |
| – | 67 | CLK3/CSI3\_MCLK | 17 | 18 | GND | – | – |
| – | – | GND | 19 | 20 | CSI0\_D2\_P | – | – |
| – | – | DSI0\_CLK\_P | 21 | 22 | CSI0\_D2\_M | – | – |
| – | – | DSI0\_CLK\_M | 23 | 24 | GND | – | – |
| – | – | GND | 25 | 26 | CSI0\_D3\_P | – | – |
| – | – | DSI0\_D0\_P | 27 | 28 | CSI0\_D3\_M | – | – |
| – | – | DSI0\_D0\_M | 29 | 30 | GND | – | – |
| – | – | GND | 31 | 32 | CCI\_I2C\_SCL0 | 70 | – |
| – | – | DSI0\_D1\_P | 33 | 34 | CCI\_I2C\_SDA0 | 69 | – |
| – | – | DSI0\_D1\_M | 35 | 36 | CCI\_I2C\_SCL1 | 72 | Yes |
| – | – | GND | 37 | 38 | CCI\_I2C\_SDA1 | 71 | – |
| – | – | DSI0\_D2\_P | 39 | 40 | GND | – | – |
| – | – | DSI0\_D2\_M | 41 | 42 | CSI3\_D0\_P | – | – |
| – | – | GND | 43 | 44 | CSI3\_D0\_M | – | – |
| – | – | DSI0\_D3\_P | 45 | 46 | GND | – | – |
| – | – | DSI0\_D3\_M | 47 | 48 | CSI3\_D1\_P | – | – |
| – | – | GND | 49 | 50 | CSI3\_D1\_M | – | – |
| – | – | USB0\_DP | 51 | 52 | GND | – | – |
| – | – | USB0\_DM | 53 | 54 | CSI3\_C\_P | – | – |
| – | – | GND | 55 | 56 | CSI3\_C\_M | – | – |
| – | – | USB1\_DP / NC | 57 | 58 | GND | – | – |
| – | – | USB1\_DM / NC | 59 | 60 | Reserved | – | – |
### High-speed expansion connector 2 (HS2)
The HS2 connector has the following functionalities:
- PCIe interface and control signals
- CSI (x2)
- SPI/QUP interface
- Camera MClk (x2)
- Additional GPIOs
- SS USB signals
| Wake-up function | GPIO | Signal | Pin number | Pin number | Signal | GPIO | Wake-up function |
| --- | --- | --- | --- | --- | --- | --- | --- |
| – | – | PCIE1\_REFCLK\_M | 1 | 2 | CSI1\_C\_P | – | – |
| – | – | PCIE1\_REFCLK\_P | 3 | 4 | CSI1\_C\_M | – | – |
| – | – | PCIE1\_RX\_M | 5 | 6 | GND | – | – |
| – | – | PCIE1\_RX\_P | 7 | 8 | CSI1\_D0\_P | – | – |
| – | – | PCIE1\_TX\_M | 9 | 10 | CSI1\_D0\_M | – | – |
| – | – | PCIE1\_TX\_P | 11 | 12 | GND | – | – |
| – | 87 | GPIO-CC | 13 | 14 | CSI1\_D1\_P | – | – |
| Yes | 88 | GPIO-DD | 15 | 16 | CSI1\_D1\_M | – | – |
| Yes | 89 | GPIO-EE | 17 | 18 | GND | – | – |
| – | 2 | GPIO-FF | 19 | 20 | CSI1\_D2\_P | – | – |
| Yes | 79 | GPIO-GG | 21 | 22 | CSI1\_D2\_M | – | – |
| Yes | 3 | GPIO-HH | 23 | 24 | GND | – | – |
| – | – | GND | 25 | 26 | CSI1\_D3\_P | – | – |
| – | 65 | CLK1/CSI1\_MCLK | 27 | 28 | CSI1\_D3\_M | – | – |
| – | 66 | CLK2/CSI2\_MCLK | 29 | 30 | GND | – | – |
| – | – | GND | 31 | 32 | SPI1\_CLK | 58 | – |
| – | – | CSI2\_C\_P | 33 | 34 | SPI1\_CS | 59 | Yes |
| – | – | CSI2\_C\_M | 35 | 36 | SPI1\_MOSI | 57 | – |
| – | – | GND | 37 | 38 | SPI1\_MISO | 56 | Yes |
| – | – | CSI2\_D0\_P | 39 | 40 | GPIO-AA/CSI4\_MCLK | 68 | Yes |
| – | – | CSI2\_D0\_M | 41 | 42 | GPIO-BB/CSI5\_MCLK | 93 | Yes |
| – | – | GND | 43 | 44 | GPIO-II | 77 | Yes |
| – | – | CSI2\_D1\_P | 45 | 46 | GPIO-JJ | 122 | – |
| – | – | CSI2\_D1\_M | 47 | 48 | PMIC SPMI CLK | PMK\_7325 GPIO\_01 | – |
| – | – | GND | 49 | 50 | PMIC SPMI DATA | PMK\_7325\_GPIO\_02 | – |
| – | – | CSI2\_D2\_P | 51 | 52 | GND | – | – |
| – | – | CSI2\_D2\_M | 53 | 54 | USB0\_SS\_TX0\_P | – | – |
| – | – | GND | 55 | 56 | USB0\_SS\_TX0\_M | – | – |
| – | – | CSI2\_D3\_P | 57 | 58 | USB0\_SS\_RX0\_P | – | – |
| – | – | CSI2\_D3\_M | 59 | 60 | USB0\_SS\_RX0\_M | – | – |
High-speed expansion connector 3 (HS3)
The HS3 connector has the following functionalities:
- Additional PCIe interface
- Additional camera CSI interface
- Additional display DSI interface
- Additional clock signals
| Wake-up function | GPIO | Signal | Pin number | Pin number | Signal | GPIO | Wake-up function |
| --- | --- | --- | --- | --- | --- | --- | --- |
| – | – | CSI4\_C\_P | 1 | 2 | GND | – | – |
| – | – | CSI4\_C\_M | 3 | 4 | PCIE1\_RX1\_M | – | – |
| – | – | CSI4\_D0\_P | 5 | 6 | PCIE1\_RX1\_P | – | – |
| – | – | CSI4\_D0\_M | 7 | 8 | PCIE1\_TX1\_M | – | – |
| – | – | GND | 9 | 10 | PCIE1\_TX1\_P | – | – |
| – | – | CSI4\_D1\_P | 11 | 12 | GND | – | – |
| – | – | CSI4\_D1\_M | 13 | 14 | PCIE2\_REFCLK\_M | – | – |
| – | – | CSI4\_D2\_P | 15 | 16 | PCIE2\_REFCLK\_P | – | – |
| – | – | CSI4\_D2\_M | 17 | 18 | PCIE2\_RX0\_M | – | – |
| – | – | CSI4\_D3\_P | 19 | 20 | PCIE2\_RX0\_P | – | – |
| – | – | CSI4\_D3\_M | 21 | 22 | PCIE2\_RX1\_M (not used) | – | – |
| – | – | GND | 23 | 24 | PCIE2\_RX1\_P (not used) | – | – |
| – | – | CSI3\_D2\_P | 25 | 26 | PCIE2\_TX0\_M | – | – |
| – | – | CSI3\_D2\_M | 27 | 28 | PCIE2\_TX0\_P | – | – |
| – | – | CSI3\_D3\_P | 29 | 30 | PCIE2\_TX1\_M (not used) | – | – |
| – | – | CSI3\_D3\_M | 31 | 32 | PCIE2\_TX1\_P (not used) | – | – |
| – | – | GND | 33 | 34 | GND | – | – |
| – | – | CSI5\_C\_P | 35 | 36 | DSI1\_CLK\_P | – | – |
| – | – | CSI5\_C\_M | 37 | 38 | DSI1\_CLK\_M | – | – |
| – | – | CSI5\_D0\_P | 39 | 40 | DSI1\_D0\_P | – | – |
| – | – | CSI5\_D0\_M | 41 | 42 | DSI1\_D0\_M | – | – |
| – | – | CSI5\_D1\_P | 43 | 44 | DSI1\_D1\_P | – | – |
| – | – | CSI5\_D1\_M | 45 | 46 | DSI1\_D1\_M | – | – |
| – | – | CSI5\_D2\_P | 47 | 48 | GND | – | – |
| – | – | CSI5\_D2\_M | 49 | 50 | DSI1\_D2\_P | – | – |
| – | – | CSI5\_D3\_P | 51 | 52 | DSI1\_D2\_M | – | – |
| – | – | CSI5\_D3\_M | 53 | 54 | DSI1\_D3\_P | – | – |
| – | – | GND | 55 | 56 | DSI1\_D3\_M | – | – |
| – | – | PMK8002\_RF\_CLK1 | 57 | 58 | GND | – | – |
| – | LNBBCLK2 | PMK8002\_RF\_CLK2 | 59 | 60 | GPIO-DDD | PM\_A\_GPIO\_05 (PM7250B) | – |
## DIP switches
The following image shows the location of the DIP switches on the mainboard and interposer.
DIP switches are on the front, underside of the mainboard and interposer board. They’re near the front, on the top side of the vision mezzanine board.
A tool similar to a dental pick is provided to help access switches that might be difficult to reach.
### Mainboard DIP switches
DIP\_SW\_0 contains six switches and is present on the bottom side of the mainboard. DIP\_SW\_1 is inactive. Use the pick included in the kit to help access switches that might be difficult to reach. The following table lists the switches and their functionalities.
DIP switch selection
| DIP\_SW\_0 | Name | Details | Default |
| --- | --- | --- | --- |
| 1 | Mic switch | ON: on-board DMIC
OFF: off-board DMIC (LS2 connector) | ON |
| 2 | Debug UART | ON: enable serial log (debug UART)
OFF: disable serial log (off-board UART) | ON |
| 3 | N/A | – | – |
| 4 | HDMI switch | ON: HDMI disabled
OFF: HDMI enabled | OFF |
| 5 | Sensor IMU toggle | ON: on-board IMU disabled
OFF: on-board IMU enabled | OFF |
| 6 | IMU external clock | ON: external clock to IMU
OFF: no external clock to IMU | OFF |
The following flowcharts show how the DIP switch settings on the mainboard control the routing of signals from/to connectors and components. Refer to the [block diagram](https://docs.qualcomm.com/doc/80-80015-251/topic/rb3_hardware_overview.html#mainboard-interposer-block-diagram) to see the signals, switches, and connectors in context.
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> **Circuits controlled by DIP switches on the mainboard**
### Interposer DIP switches
The following image shows the location of the interposer DIP switches.
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> **DIP switches on the interposer**
The interposer board has three boot configuration DIP switches. The following table lists the interposer DIP switches along with their functionalities:
| DIP\_SW\_2 | Name | Details | Default |
| --- | --- | --- | --- |
| 1 | BOOT\_CONFIG\_1 [GPIO\_120] | Selects external boot devices | OFF |
| 2 | BOOT\_CONFIG\_2 [GPIO\_122] | Selects external boot devices | OFF |
| 3 | BOOT\_CONFIG\_3 [GPIO\_124] | Selects external boot devices | OFF |
| 4 | BOOT\_CONFIG\_0 [GPIO\_118] | ON: disables watchdog
OFF: enables watchdog | OFF |
| | | | |
| | | | |
Interposer DIP switch selection (DIP_SW_3)
| DIP\_SW\_3 | Name | Details | Default |
| --- | --- | --- | --- |
| 1 | DIP\_CSI3\_SW | OFF: CSI3 input from Vision mezzanine CAM3 (IMX577)
ON: CSI3 input from Vision mezzanine CAM5 (GMSL) | OFF |
| 2 | PCIE\_DIP\_SW | ON: QPS 1 Lane PCIe goes to mainboard 500 pin (HS expansion PCIE2)
OFF: QPS 1 Lane PCIe goes to PCIE2USB (uPD) | OFF |
Interposer DIP switch selection (DIP_SW_4)
| DIP\_SW\_4 | Name | Details | Default |
| --- | --- | --- | --- |
| 1 | CSI1\_DIP\_SW | ON: CSI1 input from interposer CPHY CAM1
OFF: CSI1 input from Vision mezzanine CAM1 | OFF |
| 2 | CSI2\_DIP\_SW | ON: CSI2 input from interposer CPHY CAM2
OFF: CSI2 input from Vision mezzanine CAM2 | OFF |
| 3 | QSPI\_CAN\_DIP\_SW | ON: not supported
OFF: SPI to CAN interface on mainboard | OFF |
| 4 | QSPI\_GPIO\_DIP\_SW | ON: not supported
OFF: SPI to CAN interface on mainboard | OFF |
The following flowcharts show how the DIP switch settings on the interposer control the routing of signals from/to connectors and components. Refer to the [block diagram](https://docs.qualcomm.com/doc/80-80015-251/topic/rb3_hardware_overview.html#mainboard-interposer-block-diagram) to see the signals, switches, and connectors in context.
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> **Circuits controlled by DIP switches on the interposer**
### Vision mezzanine DIP switches
The following image shows the location of the DIP switches on the Vision mezzanine.
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> **Vision mezzanine DIP switches**
Vision mezzanine DIP switches (DIP1)
| DIP1 | Name | Details | Default |
| --- | --- | --- | --- |
| 1 | SENSOR\_SPI\_PASSTHRU | ON: Snapdragon sensor core (SSC) sensor SPI routed to IMU\_SPI\_SELECT switch
OFF: IMU sensor SPI passthrough | OFF |
| 2 | APPS\_SPI\_PASSTHRU | ON: Application processor SPI routed to IMU\_SPI\_SELECT switch
OFF: passthrough | OFF |
| 3 | CAM2\_APPS\_SPI\_PASSTHRU | ON: SPI to CAM2 connector
OFF: passthrough | OFF |
| 4 | PRESS\_SENS\_DISCONNECT | ON: on-board
OFF: disconnected | ON |
| 5 | MAG\_SENSOR\_DISCONNECT | ON: on-board
OFF: disconnected | ON |
| 6 | UART0\_PASSTHRU | ON: on-board
OFF: passthrough | OFF |
Vision mezzanine DIP switches (DIP2)
| DIP2 | Name | Details | Default |
| --- | --- | --- | --- |
| 1 | DIP\_CSI0A\_B\_SWITCH | ON: CSI0 all 4 lanes to CAM0A
OFF: CSI0 2 lanes to CAM0A, 1 lane to CAM0B | OFF |
| 2 | MIC\_DISCONNECT | ON: DMIC 2/3 connects to on-board mics
OFF: DMIC 2/3 passthrough | ON |
| 3 | IMU\_SPI\_SELECT | ON: connects IMU to APPS SPI – only if DIP 1:2 is ON
OFF: connects IMU to SSC SPI – only if DIP 1:1 is ON | OFF |
| 4 | IMU\_INT\_1\_2\_SELECT\_LOGIC1 | ON: IMU INT1 to GYRO\_INT, IMU INT2 to PMIC clock
OFF: IMU INT1 and 2 connected to IMU sensor switch | OFF |
| 5 | IMU\_INT\_1\_2\_SELECT\_LOGIC2 | ON: IMU INT1 to ACCEL\_INT, IMU INT2 to GYRO\_INT
OFF: IMU INT 1 and 2 disconnected | OFF |
| 6 | PRESSURE\_COMPASS\_SELECT | ON: Pressure/Compass connected to APPS I2C
OFF: Pressure/Compass connected to sensor core I2C | OFF |
The following flowcharts show how the DIP switch settings on the Vision mezzanine control the routing of signals from/to connectors and components. Refer to the [block diagram](https://docs.qualcomm.com/doc/80-80015-251/topic/rb3_hardware_overview.html#mainboard-interposer-block-diagram) as necessary to see the signals, switches, and connectors in context.
**Circuits controlled by DIP switches on the Vision mezzanine**
## Connect a custom camera sensor
If your camera sensor’s connector matches the RB3 Gen 2 board, you can use it directly. See [Design Package, RB5/RB5GEN2/RB3GEN2 Navigation Mezzanine](https://www.qualcomm.com/search?query=DP25-PV086-43#q=DP25-PV086-43&tab=all) for connector details.
**Vision mezzanine camera connectors**
Otherwise, create an interface PCB to convert the pinout from the Vision mezzanine to match your camera sensor signals. The example below assumes a “fisheye camera” to be tested with RB3 Gen 2. Two different flex cables (Flex\_A and Flex\_B) would also be needed.
**Vision mezzanine with interface PCB**
A custom-vision-mezzanine board can also be designed to host more than one camera connector. See [Design Package, RBx Generic Mezz Card Schematic and Layout, IOT](https://www.qualcomm.com/search?query=DP25-63340-1#q=DP25-63340-1&tab=all).
### Connectors on RB3 Gen 2
The CAM1 and CAM2 connectors on the interposer (*see below*) are C/D-PHY. The connectors on the [Vision Mezzanine](https://docs.qualcomm.com/doc/80-80015-251/topic/references.html#vision-mezz-connectors) are D-PHY only.
**Interposer camera connectors**
The following images show details for the CAM1 and CAM2 connectors on the interposer.
### Vision Mezzanine pinouts
The following table lists the pinout locations on the Vision Mezzanine.
|
RB5 4 Lane MIPI CSI Connectors |
RB5 4 Lane MIPI CSI Connectors |
RB5 4 Lane MIPI CSI Connectors |
RB5 4 Lane MIPI CSI Connectors |
RB5 4 Lane MIPI CSI Connectors |
RB5 4 Lane MIPI CSI Connectors |
| --- | --- | --- | --- | --- | --- |
| Pin | CAM0A | CAM1 | CAM2 | CAM3 | Notes |
| 1 | Strobe (GPIO) | Strobe (GPIO) | Strobe (GPIO) | Strobe (GPIO) | strobe not typically used by most modules |
| 2 | Spare (GPIO) | Spare (GPIO) | Spare (GPIO), Optionally SPI\_CLK | Spare (GPIO) | spare not typically used by most modules |
| 3 | 2V8 | 2V8 | 2V8 | 2V8 or 5V | |
| 4 | GND | GND | Optionally SPI\_MOSI | GND | |
| 5 | Reset (GPIO) | Reset (GPIO) | Reset (GPIO) | Reset (GPIO) | Key GPIO |
| 6 | GND | GND | GND, For CAM2, this pin can be remapped to a 32kHz SLEEP\_CLK. GND is the default. | GND | |
| 7 | CSI\_D2\_P | CSI\_D2\_P | CSI\_D2\_P | CSI\_D2\_P | |
| 8 | CSI\_D2\_M | CSI\_D2\_M | CSI\_D2\_M | CSI\_D2\_M | |
| 9 | GND | GND | GND | GND | |
| 10 | CSI\_D0\_P | CSI\_D0\_P | CSI\_D0\_P | CSI\_D0\_P | |
| 11 | CSI\_D0\_M | CSI\_D0\_M | CSI\_D0\_M | CSI\_D0\_M | |
| 12 | GND | GND | GND | GND | |
| 13 | CSI\_D3\_P | CSI\_D3\_P | CSI\_D3\_P | CSI\_D3\_P | |
| 14 | CSI\_D3\_M | CSI\_D3\_M | CSI\_D3\_M | CSI\_D3\_M | |
| 15 | CAM\_PWR\_SWITCH | CAM\_PWR\_SWITCH | CAM\_PWR\_SWITCH | CAM\_PWR\_SWITCH | Controls 1V1 or 1V2 selection on pin 30. Pull low to GND for 1.1V, pull high to 1V8 rail on the flex for 1V2. |
| 16 | 0R to GND | 0R to GND | 0R to GND | CAM\_PWR\_SWITCH2 | CAM3 Only: Pull low to GND for normal operation (1V1/1V2, 1V8, 2V8). Pull high to Pin 28 for 5V on all three power pins. |
| 17 | CSI\_D1\_M | CSI\_D1\_M | CSI\_D1\_M | CSI\_D1\_M | |
| 18 | CSI\_D1\_P | CSI\_D1\_P | CSI\_D1\_P | CSI\_D1\_P | |
| 19 | GND | GND | GND | GND | |
| 20 | CSI\_C\_M | CSI\_C\_M | CSI\_C\_M | CSI\_C\_M | |
| 21 | CSI\_C\_P | CSI\_C\_P | CSI\_C\_P | CSI\_C\_P | |
| 22 | GND | GND | GND | GND | |
| 23 | MCLK | MCLK | MCLK | MCLK | Key GPIO |
| 24 | GND | GND | GND | GND | |
| 25 | SCL | SCL | SCL | SCL | Key GPIO |
| 26 | SDA | SDA | SDA | SDA | Key GPIO |
| 27 | PWDN/Sync to CAM0B | PWDN | Optionally SPI\_CS | PWDN | PWDN not typically used by most modules |
| 28 | 1V8 | 1V8 | 1V8 | 1V8 or 5V | |
| 29 | GND | GND | Optionally SPI\_MISO | GND | |
| 30 | 1V1 or 1V2 | 1V1 or 1V2 | 1V1 or 1V2 | 1V2 or 5V | |
| - General Notes:
- Only Camera interfaces with 4 D-PHY lanes are shown. QC software only uses RST and MCLK. The other GPIO pins can be used for other purposes as they are not nominally routed to anything in the software. CAM0A and CAM0B can be synchronized via pin 27. Optional SPI bus on CAM2 is connected to the apps processor block, not the DSP block. | - General Notes:
- Only Camera interfaces with 4 D-PHY lanes are shown. QC software only uses RST and MCLK. The other GPIO pins can be used for other purposes as they are not nominally routed to anything in the software. CAM0A and CAM0B can be synchronized via pin 27. Optional SPI bus on CAM2 is connected to the apps processor block, not the DSP block. | - General Notes:
- Only Camera interfaces with 4 D-PHY lanes are shown. QC software only uses RST and MCLK. The other GPIO pins can be used for other purposes as they are not nominally routed to anything in the software. CAM0A and CAM0B can be synchronized via pin 27. Optional SPI bus on CAM2 is connected to the apps processor block, not the DSP block. | - General Notes:
- Only Camera interfaces with 4 D-PHY lanes are shown. QC software only uses RST and MCLK. The other GPIO pins can be used for other purposes as they are not nominally routed to anything in the software. CAM0A and CAM0B can be synchronized via pin 27. Optional SPI bus on CAM2 is connected to the apps processor block, not the DSP block. | - General Notes:
- Only Camera interfaces with 4 D-PHY lanes are shown. QC software only uses RST and MCLK. The other GPIO pins can be used for other purposes as they are not nominally routed to anything in the software. CAM0A and CAM0B can be synchronized via pin 27. Optional SPI bus on CAM2 is connected to the apps processor block, not the DSP block. | - General Notes:
- Only Camera interfaces with 4 D-PHY lanes are shown. QC software only uses RST and MCLK. The other GPIO pins can be used for other purposes as they are not nominally routed to anything in the software. CAM0A and CAM0B can be synchronized via pin 27. Optional SPI bus on CAM2 is connected to the apps processor block, not the DSP block. |
**RB3 Gen 2**
## Reference designs and related documents
List of reference designs, schematics, and related documents.
- [RB3 Gen 2 Quick Start Guide](https://docs.qualcomm.com/doc/80-80015-253/topic/qsg-landing-page.html)
- [Design Package, RB3 Gen 2 SOM and Interposer](https://www.qualcomm.com/search?query=DP25-20659-5#q=DP25-20659-5&tab=all)
- [Design Package, RB3G2 Vision Kit, Mechanical 3D Model, IOT](https://www.qualcomm.com/search?query=DP25-55695-1#q=DP25-55695-1&tab=all)
- [Design Package, RBx Generic Mezz Card Schematic and Layout, IOT](https://www.qualcomm.com/search?query=DP25-63340-1#q=DP25-63340-1&tab=all)
- [Design Package, RB5/RB5GEN2/RB3GEN2 Main Board](https://www.qualcomm.com/search?query=DP25-PV086-42#q=DP25-PV086-42&tab=all)
- [Design Package, RB5/RB5GEN2/RB3GEN2 Navigation Mezzanine](https://www.qualcomm.com/search?query=DP25-PV086-43#q=DP25-PV086-43&tab=all)
- [Design Package, RB3GEN2 Industrial Mezzanine](https://www.qualcomm.com/search?query=DP25-PV086-44#q=DP25-PV086-44&tab=all)
## Acronyms and terms
List of acronyms and terms used in this document.
| Term | Description |
| --- | --- |
| DMIC | Digital microphone interface |
| EDL/QDL | Emergency download mode or Qualcomm download mode |
| GMSL | Gigabit multimedia serial links |
| GNSS | Global navigation satellite system |
| GPIO | General-purpose input/output |
| QUP | Qualcomm universal peripheral |
| SoC | System-on-chip |
| SoM | System-on-module |
| UART | Universal asynchronous receiver/transmitter |
Last Published: Dec 08, 2025
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Development regulatory notice](https://docs.qualcomm.com/bundle/publicresource/80-80015-251/topics/develop_device_regulatory_notice.md)
Source: [https://docs.qualcomm.com/doc/80-80015-251/topic/references.html](https://docs.qualcomm.com/doc/80-80015-251/topic/references.html)