# Enable SDHCI using kernel configuration

The following table lists the default values of kernel configuration to enable SD card functionality.

SDHC kernel configuration

| Configuration | Enabled by default (yes/no) | Comments |
| --- | --- | --- |
| `CONFIG_MMC` | Yes | Enables MMC driver |
| `CONFIG_MMC_DEBUG` | No | Enables driver debug messages |
| `CONFIG_MMC_SDHCI` | Yes | Detects SDHCI driver |
| `CONFIG_MMC_CQHCI` | Yes | Enables Command Queue Host Control Interface |
| `CONFIG_MMC_SDHCI_MSM` | Yes | Enables MSM SDHCI driver |
| `CONFIG_MMC_BLOCK` | Yes | Enables MMC block driver |
| `CONFIG_MMC_CRYPTO` | Yes | Enables support for the MMC Crypto Engine<br><br><br>Note<br><br><br>`CONFIG_MMC_CRYPTO` is not enabled by default on Dragonwing IQ-615. |

# Configure SDHCI (eMMC and SD card internal) Linux kernel device tree

The SoC DTSI node specifies register address space, clocks, interrupts, and reset information. The platform DTSI node specifies power supply, voltage, and current levels.
The `sdhc_2: mmc@8804000` node describes the on-chip SDHC host controller and is typically within the SoC DTSI file. For example, `<workspace_root_path>/sources/kernel/kernel_platform/kernel/arch/arm64/boot/dts/qcom/sc7280.dtsi` file.

Note

These parameters are only for information purposes. Don’t modify them.

| Property | Description |
| --- | --- |
| `Compatible` | Specify compatible strings such as `qcom,sc7280-sdhci`, `qcom,sdhci-msm-v5`. |
| `Pinctrl-names` | Defines name of the pin control states. |
| `Pinctrl-0 &amp;1` | Points to pin control settings. This is an array defines pin  control settings for multiple states. |
| `Interrupts` | Interrupt mapping for SDHC IRQ. |
| `Interrupt-names` | Lists the names corresponding to each interrupt defined in the `interrupts` property. |
| `reg` | SDHC host registers address mapping. |
| `iommus` | `Iommus` specifies the IOMMU node and stream ID. |
| `clock-names` | List of clock input name strings. |
| `clocks` | List of phandle and clock specifier pairs. |
| `interconnects` | Defines the interconnect paths for the device. |
| `interrupt-names` | Lists the names to each interconnect path defined in `interconnects` property. |
| `power-domains` | Specifies the power domain used by the SDHC. |
| `bus-width` | Specifies the number of data lines used for communication. |
| `dma-coherent` | Specifies that the SDHCI and CPU maintain cache coherency. |
| `qcom,dll-config` | Platform specific settings for `DLL_CONFIG` reg. |
| `resets` | Reset node register. |
| `sdhc2_opp_table` | This table defines various operating points supported by the SDHCI. |

# Enable eMMC using device tree properties

To enable eMMC, add the following lines in the `&sdhc_1` node in the SoC-specific DTSI file.

&sdhc_1 {
    status = "okay";
    pinctrl-names = "default", "sleep";
    pinctrl-0 = <&sdc1_on>;
    pinctrl-1 = <&sdc1_off>;
    vmmc-supply = <&vreg_l19a_2p9>;
    vqmmc-supply = <&vreg_l12a_1p8>;
    };
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Update the following files as per the SoC device tree path `/kernel_platform/kernel/arch/arm64/boot/dts/qcom/`:

- `qcs6490-addons-rb3gen2.dts`
- `qcs6490-rb3gen2.dts`
- `qcs6490-addons-rb3gen2.dtsi`
- `qcs6490-addons-rb3gen2-ia-mezz.dts`
- `qcs6490-addons-rb3gen2-ptz-mezz.dts`
- `qcs6490-addons-rb3gen2-video-mezz.dts`
- `qcs6490-addons-rb3gen2-vision-mezz.dts`
- `qcs6490-addons-rb3gen2-vision-mezz-hsp.dts`

Last Published: Mar 12, 2026

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