# Display overview
The Qualcomm^®^ Adreno™ Display Processing Unit (DPU) provides hardware-accelerated
image processing. The DPU retrieves pixel data from memory and sends
it to the display peripherals through standard interfaces.
**Figure: DPU architecture**
The DPU provides the following image processing and interface
capabilities:
- **Image processing** includes the following:
- **Composition**: blends individual layers into a single frame and sends it to the display panel
- **Scaling**: supports upscale and downscale of the source image to
match the panel resolution
- **Color format conversion**: converts colors from one color format
to another (from YUV to RGB)
- **Color space conversion**: converts colors from one color space
to another (sRGB, P3, and BT2020)
- **Color processing**: enhances the colors for better visual
quality
- **Interfaces**: Connects with various panels using the mobile industry
processor interface display serial interface (MIPI DSI) and TV or
monitor with the DisplayPort interface
- **MIPI DSI**: defines the protocols between a host processor and
peripheral devices that adhere to the MIPI Alliance specifications
for mobile device interfaces
- **DisplayPort**: serves as a digital display interface, primarily
connecting video sources to display devices such as computer
monitors, and can also transmit audio, USB, and other data forms
The [Qualcomm^®^ Intelligent Multimedia SDK (IM SDK)](https://docs.qualcomm.com/bundle/publicresource/topics/80-80022-50/overview.html) and the `libdrm` APIs expose the hardware capabilities of the Adreno DPU engines.
Note
See [Hardware SoCs](https://docs.qualcomm.com/bundle/publicresource/topics/80-80022-115/soc.html) that are supported on Qualcomm^®^ Linux^®^.
## Display architecture
This information explains the primary components within the hardware and the software architecture of the Qualcomm Linux display subsystem.
### Display hardware architecture
The hardware architecture includes components for source and destination
processing, layer mixing, compression, and display interfaces.
**Figure: DPU hardware architecture block diagram**
The following table lists the components of the display hardware architecture.
Table: Display hardware architecture components
| Component | Description |
| --- | --- |
| Bus interface | Fetches data from memory for processing |
| Source surface processing | Reads RGB and YUV surfaces from games and video applications
Performs format conversion and quality improvements for the source |
| Blending | Blends and mixes the source surfaces together |
| Destination surface processing | Converts, corrects, and adjusts the data based on panel characteristics |
| Compression | Reduces bandwidth and power consumption by sending compressed display buffers to the display |
| Display interface | Generates timings for the connected display peripherals |
Detailed information on the display hardware architecture is available
to licensed developers with authorized access. For more information, see [Qualcomm Linux Display
Guide -
Addendum](https://docs.qualcomm.com/bundle/resource/topics/80-80022-18A/architecture.html#high-level-display-hardware-architecture).
### Display software architecture
The display subsystem consists of Wayland, a display server protocol,
and its compositors, such as Weston. Wayland uses a client-server model where the client application interacts with the Wayland server.
**Figure: Display software architecture block diagram**
The components of the display software architecture are as follows:
>
>
> Table: Display software architecture components
>
>
> | Component | Description |
> | --- | --- |
> | Wayland sink | The Wayland sink plug-in communicates with the Weston subsystem to render the display. |
> | Wayland compositor (Weston) | The Wayland compositor uses the Wayland protocol as a display server. The compositor handles the composition and rendering requirements at the system level and runs as a separate process in the system. Weston serves as the reference implementation of a Wayland compositor. |
> | Direct rendering manager (DRM) backend | The DRM backend software framework manages the Qualcomm Adreno DPU hardware resources. It selects the optimal composition strategy for each connected display and allocates display processor hardware resources for the layer stack received from the client. |
> | `libdrm` | The `libdrm` library provides APIs for accessing DRM I/O control (IOCTL). |
> | DRM/KMS framework | The DRM/KMS framework offers kernel and user-space level interface, with the help of `libdrm` libraries to access the related hardware features, configuration, and hardware acceleration. |
> | Adreno DPU driver | The Adreno DPU driver manages all the pixel data paths to different panel interfaces. |
> | Adreno DPU | The Adreno DPU is a hardware-accelerated engine that performs image processing and interfacing with minimal power consumption. |
#### Software APIs
>
>
> Qualcomm Linux provides the following display APIs:
>
> - Weston API: facilitates interactions with the DRM compositor. For the Weston APIs, see [Wayland client APIs](https://wayland.freedesktop.org/docs/html/apb.html) and [Wayland server APIs](https://wayland.freedesktop.org/docs/html/apc.html).
> - `libdrm` API: facilitates interactions with the DRM/KMS framework. For the APIs, see [libdrm](https://dri.freedesktop.org/docs/drm/gpu/drm-uapi.html).
>
>
>
> Qualcomm provides the GStreamer-based plugins. You can add the Waylandsink plugin to your media pipeline from [IM SDK plugins](https://docs.qualcomm.com/bundle/publicresource/topics/80-80022-50/qim-sdk-plugins.html).
>
>
> For more information, see [GStreamer application development and pipeline creation](https://gstreamer.freedesktop.org/documentation/application-development/basics/index.html).
## Next steps
- [Enable display](https://docs.qualcomm.com/doc/80-80022-18/topic/enable_the_display.html#set-up-hdmi)
- [Run sample test applications](https://docs.qualcomm.com/doc/80-80022-18/topic/enable_the_display.html#run-the-weston-simple-egl-client-application)
- [Display specifications](https://docs.qualcomm.com/doc/80-80022-18/topic/display_specifications.html#display-specifications)
Last Published: May 13, 2026
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