# Configure UART in kernel
Source: [https://docs.qualcomm.com/doc/80-88500-1/topic/19_Configure_UART_in_kernel.html](https://docs.qualcomm.com/doc/80-88500-1/topic/19_Configure_UART_in_kernel.html)
## Before you begin
The following files are required to
configure UART in the kernel:
| File type | Location |
| --- | --- |
| Device tree source | Linux Ubuntu:
\kernel\msm-5.4\arch\arm64\boot\dts\qcom\kona-qupv3.dtsi
Linux Embedded:
\kernel\msm-5.15\arch\arm64\boot\dts\qcom\kona-qupv3.dtsi |
| Pin control settings | Linux Ubuntu:
\kernel\msm-5.4\arch\arm64\boot\dts\qcom\kona-pinctrl.dtsi
Linux Embedded:
\kernel\msm-5.15\arch\arm64\boot\dts\qcom\kona-pinctrl.dtsi |
| TrustZone settings | \trustzone\_images\core\settings\buses\qup\_accesscontrol\qupv3\config\kona\QUPAC\_Access.c |
## About this task
The low-speed UART driver supports small data transfers at slower rates, for example, for console debugging or IrDA transfers. The high-speed UART must be used when a large amount of data is transferred or for instances where a high-speed transfer is required.
To configure a high-speed UART in the kernel, do the following:
## Procedure
1. Create a device tree node.
1. To map QUP interfaces, see [QUP configuration with 20 QUPs for GPIO](https://docs.qualcomm.com/doc/80-88500-1/topic/16_Qualcomm_universal_peripheral__QUP_.html#Qualcomm_universal_peripheral__QUP__16__table_1). The table provides the
pin-mapping information of serial interfaces supported by each QUP serial engine.
2. Open kona-qupv3.dtsi file and add a device tree node as shown in the following
examples.
The kona-qupv3.dtsi file is available at:
- Linux Ubuntu:
\kernel\msm-5.4\arch\arm64\boot\dts\qcom\kona-qupv3.dtsi
- Linux Embedded:
\kernel\msm-5.15\arch\arm64\boot\dts\qcom\kona-qupv3.dtsi
**4-wire UART configuration**
qupv3_se6_4uart: qcom,qup_uart@ 0X998000
{
compatible = "qcom,msm-geni-serial-hs", "qcom,msm-geni-uart";
//Manufacturer model of serial driver
reg = <0x998000 0x4000>; //SE address and size
reg-names = "se_phys"; //resource name
clock-names = "se-clk", "m-ahb", "s-ahb"; //clocks name
/*Clocks for SE */
clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>,
<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
/* Using pinctrl setting */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_4uart_active>;
pinctrl-1 = <&qupv3_se6_4uart_sleep>;
interrupts-extended = <&intc GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>, <&tlmm 19 0>;
status = "disabled"; // uart is disabled, status OK enables it
qcom,wakeup-byte = <0xFD>; //Wake up byte is used for resume.
qcom,wrapper-core = <&qupv3_0>;
};Copy to clipboard
**2-wire UART configuration**
qupv3_se18_2uart: qcom,qup_uart@890000 {
compatible = "qcom,msm-geni-serial-hs";
reg = <0x890000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&clock_gcc GCC_QUPV3_WRAP2_S4_CLK>, <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se18_rx>, <&qupv3_se18_tx>;
pinctrl-1 = <&qupv3_se18_rx>, <&qupv3_se18_tx>;
interrupts-extended = <&intc GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>, <&tlmm 59 0>;
status = "disabled"; // uart is disabled, status OK enables it
qcom,wakeup-byte = <0xFD>;
qcom,wrapper-core = <&qupv3_2>;
}; };Copy to clipboard
For more information, see the device tree documentation:
- Linux Ubuntu:
\kernel\msm-5.4\Documentation\devicetree\bindings
- Linux Embedded:
\kernel\msm-5.15\Documentation\devicetree\bindings
2. See the following example and update the pin settings in the pin control file:
- Linux Ubuntu:
\kernel\msm-5.4\arch\arm64\boot\dts\qcom\kona-pinctrl.dtsi
- Linux Embedded:
\kernel\msm-5.15\arch\arm64\boot\dts\qcom\kona-pinctrl.dtsi
qupv3_se6_4uart_pins: qupv3_se6_4uart_pins {
qupv3_se6_default_cts:
qupv3_se6_default_cts {
mux {
pins = "gpio16";
function = "gpio";
};
config {
pins = "gpio16";
drive-strength = <2>;
bias-disable;
};
};
qupv3_se6_default_rtsrx:
qupv3_se6_default_rtsrx {
mux {
pins = "gpio17", "gpio19";
function = "gpio";
};
config {
pins = "gpio17", "gpio19";
drive-strength = <2>;
bias-pull-down;
};
};
qupv3_se6_default_tx:
qupv3_se6_default_tx {
mux {
pins = "gpio18";
function = "gpio";
};
config {
pins = "gpio18";
drive-strength = <2>;
bias-pull-up;
};
};
qupv3_se6_ctsrx: qupv3_se6_ctsrx {
mux {
pins = "gpio16", "gpio19";
function = "qup6";
};
config {
pins = "gpio16", "gpio19";
drive-strength = <2>;
bias-disable;
};
};
qupv3_se6_rts: qupv3_se6_rts {
mux {
pins = "gpio17";
function = "qup6";
};
config {
pins = "gpio17";
drive-strength = <2>;
bias-pull-down;
};
};
qupv3_se6_tx: qupv3_se6_tx {
mux {
pins = "gpio18";
function = "qup6";
};
config {
pins = "gpio18";
drive-strength = <2>;
bias-pull-up;
};
};
};Copy to clipboard
3. In the \trustzone\_images\core\settings\buses\qup\_accesscontrol\qupv3\config\kona\QUPAC\_Access.c file, add the UART instance as following:
const QUPv3_se_security_permissions_type qupv3_perms_default[] =
{
----
----
{ QUPV3_0_SE6, QUPV3_PROTOCOL_UART_4W, QUPV3_MODE_FIFO, AC_HLOS, TRUE, TRUE, FALSE },
----
----
};Copy to clipboard
**Parent Topic:** [UART in QUP](https://docs.qualcomm.com/doc/80-88500-1/topic/29_UART_in_QUP_v3.html)
Last Published: Aug 18, 2023
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