# Configure SPI in kernel 

Source: [https://docs.qualcomm.com/doc/80-88500-1/topic/31_Configure_SPI_in_kernel_.html](https://docs.qualcomm.com/doc/80-88500-1/topic/31_Configure_SPI_in_kernel_.html)

## Before you begin
The following table lists the files required to configure the QUP core as SPI in the kernel:

| File type | Location |
| --- | --- |
| Device tree source | Linux Ubuntu:<br>                    \kernel\msm-5.4\arch\arm64\boot\dts\qcom\kona-qupv3.dtsi<br><br><br>                <br>Linux Embedded:<br>                    \kernel\msm-5.15\arch\arm64\boot\dts\qcom\kona-qupv3.dtsi |
| Pin control settings | Linux Ubuntu:<br>                    \kernel\msm-5.4\arch\arm64\boot\dts\qcom\kona-pinctrl.dtsi<br><br><br>                <br>Linux Embedded:<br>                    \kernel\msm-5.15\arch\arm64\boot\dts\qcom\kona-pinctrl.dtsi |
| TrustZone settings | \trustzone\_images\core\settings\buses\qup\_accesscontrol\qupv3\config\kona\QUPAC\_Access.c |

## About this task

To configure and use a QUP core as an SPI master, do the following:

## Procedure

1. Create a device tree node for the SPI master.
2. In one of the file, add a device tree node. 
        
- Linux Ubuntu:
                \kernel\msm-5.4\arch\arm64\boot\dts\qcom\kona-qupv3.dtsi
    - Linux Embedded:
                \kernel\msm-5.15\arch\arm64\boot\dts\qcom\kona-qupv3.dtsi

Following is an example device tree node: 

        aliases{
           spi5 = & qupv3_se5_spi;
        };
        
            qupv3_se5_spi: spi@894000 {
                compatible = "qcom,spi-geni";//Manufacturer model of serial driver
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0x894000 0x4000>;//SE address and size
                reg-names = "se_phys";
                clock-names = "se-clk", "m-ahb", "s-ahb";//clocks name
        
                /*clocks for SE*/
                clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>,
                    <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
                    <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
                pinctrl-names = "default", "sleep";
                pinctrl-0 = <&qupv3_se5_spi_active>;
                pinctrl-1 = <&qupv3_se5_spi_sleep>;
                interrupts = <GIC_SPI 606 0>;
                spi-max-frequency = <50000000>;
                qcom,wrapper-core = <&qupv3_0>;
                status = "disabled";// SPI is disabled, status OK enables it
            };Copy to clipboard

For more information, see the device tree available at
              /kernel/Documentation/devicetree/bindings/.
3. Configure the SPI master GPIOs using the pin control settings.
    1. For the QUP GPIO configuration details, see [QUP configuration with 20 QUPs for GPIO](https://docs.qualcomm.com/doc/80-88500-1/topic/16_Qualcomm_universal_peripheral__QUP_.html#Qualcomm_universal_peripheral__QUP__16__table_1) and chipset software interface.
    2. See the following examples and modify the pin control settings in the file: 
            
- Linux Ubuntu:
                    \kernel\msm-5.4\arch\arm64\boot\dts\qcom\kona-pinctrl.dtsi
        - Linux Embedded:
                    \kernel\msm-5.15\arch\arm64\boot\dts\qcom\kona-pinctrl.dtsi

qupv3_se5_spi_pins: qupv3_se5_spi_pins {
                        qupv3_se5_spi_active: qupv3_se5_spi_active {
                            mux {
                                pins = "gpio85", "gpio86", "gpio87",
                                            "gpio88";
                                function = "qup5";
                            };
                            config {
                                pins = "gpio85", "gpio86", "gpio87",
                                            "gpio88";
                                drive-strength = <6>;
                                bias-disable;
                            };
                        };
            
                        qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
                            mux {
                                pins = "gpio85", "gpio86", "gpio87",
                                            "gpio88";
                                function = "gpio";
                            };
                            config {
                                pins = "gpio85", "gpio86", "gpio87",
                                            "gpio88";
                                drive-strength = <6>;
                                bias-disable;
                            };
                        };
                    };Copy to clipboard

For more information, see the pin control documentation
                  /kernel/Documentation/devicetree/bindings/pinctrl/msm-pinctrl.txt.
4. To verify the configuration settings, run the following commands:
        
adb shellCopy to clipboard

        cd /sys/class/spi_master to list all the spi masterCopy to clipboard

        root@android:/sys/class/spi_master # lsCopy to clipboard

Sample output:

<samp class="ph systemoutput">ls</samp>

<samp class="ph systemoutput">spi0</samp>

<samp class="ph systemoutput">spi6</samp>

<samp class="ph systemoutput">spi7</samp>

If all the information is correctly entered, the SPI bus is registered under /sys/class/spi\_master/spi#, where the cell-index matches the bus number.

**Parent Topic:** [SPI in QUP](https://docs.qualcomm.com/doc/80-88500-1/topic/30_SPI_in_QUP_v3.html)

Last Published: Aug 18, 2023

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