# I2C in QUP

Source: [https://docs.qualcomm.com/doc/80-88500-1/topic/41_I2C_in_QUP_v3.html](https://docs.qualcomm.com/doc/80-88500-1/topic/41_I2C_in_QUP_v3.html)

The I^2^C core supports the following:

- Multi-Master mode
- 10‑bit slave address and 10‑bit extend address
        
    Example: Any slave device should not use the 1111 0XX address listed in the I^2^C specification.
- High-Speed mode with 3.4 MHz clock frequency

## I^2^C bus driver structure

All non-HLOS peripheral drivers are present in the following directory structure and the APIs are exposed through `ddixxx.h` files as shown in the directory structure:

    +---buses
    |   |   
    |   +---api
    |   |   +---i2c
    |   |   |       ddii2c.h
    |   |   |       ....
    |   |   |       
    |   |   +---spi
    |   |   |       ddispi.h
    |   |   |       ....
    |   |   |       
    |   |   +---uart_lite
    |   |           uart.h
    |   |           ....
    |   |          
    |   +---build
    |   |       
    |   +---i2c
    |   |                   
    |   +---icb
    |   |               
    |   +---uart_lite
    |   |                   
    |   +---spiCopy to clipboard

- **Configure I2C in kernel**
- **Configure I2C in UEFI**
- **Enable I2C bus in UEFI**
- **Configure I2C in sensor core as sensor low-power island (SLPI) processor**
- **Enable I2C bus in sensor low-power island (SLPI)**
- **Update QUP serial engine firmware for I2C**
- **Configure GPI as I2C**
- **Enable I2C bus in TrustZone**
- **Enable I2C bus in aDSP**
- **Debug I2C in kernel**
- **Debug I2C in sensor core**

**Parent Topic:** Qualcomm universal peripheral (QUP)

Last Published: Aug 18, 2023

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