# GPIO configurations

Source: [https://docs.qualcomm.com/doc/80-88500-3/topic/6_Configure_GPIO_direction_and_value.html](https://docs.qualcomm.com/doc/80-88500-3/topic/6_Configure_GPIO_direction_and_value.html)

The GPIOs must be configured before updating the direction and value parameters. The GPIO direction and value can be updated through the `sysfs` interface.
      
- QRB5165 supports 180 (146 + 34) GPIO pins
    - Normal GPIOs – 146
    - Extended GPIOs (eGPIO) – 34. eGPIO allows the Qualcomm® Snapdragon™ Sensor Core or LPASS I/Os to be reused as a regular GPIO

To configure the GPIO and identify the GPIO base number, perform the following steps.

1. Use the following command to determine the `gpiochip0` details.

        cat /sys/kernel/debug/gpioCopy to clipboard

    The `gpiochip0` value is `gpiochip0: GPIOs 328-511`.
2. To identify the node for the `sysfs` interface, use the following formula.
        
    GPIO base number + GPIO number

    The GPIO base number is used by the `sysfs` interface to create a node for accessing from the user space.

    Example: From `gpiochip0: GPIOs 328-511`, the GPIO base number is 328. For GPIO 47, the node is 328 + 47 = 375.

    - `cd /sys/class/gpio/`contains the following files.
        - `export`– User space notifies the kernel to export control of a GPIO to user space by writing its number to this file.
            - Example: Use the following command to create a `gpio375` node for GPIO\_47 when the kernel code requests it.

                    echo 375 > exportCopy to clipboard
        - `unexport`– Reverses the effect of exporting to user space.
            - Example – Use the following command to remove the `gpio375` node exported using the `export` file.

                    echo 375 > unexportCopy to clipboard

After the GPIO is exported, the GPIO signals have paths similar to sys/class/gpio/gpio375/ (for GPIO\_47).

- Use the following commands to read and configure the direction.
    - Read the current direction:

            /sys/class/gpio/gpioN/directionCopy to clipboard
    - Configure the direction:
        - `gpioN` as output pin

                echo "out" > /sys/class/gpio/gpioN/directionCopy to clipboard
        - `gpioN` as input pin

                echo "in" > /sys/class/gpio/gpioN/directionCopy to clipboard
- Use the following commands to read and configure the value.
    - Read the value of `gpioN`:

            echo > /sys/class/gpio/gpioN/valueCopy to clipboard
    - Configure the value:
        - Write <kbd class="ph userinput">1</kbd> to `gpioN`

                echo 1 > /sys/class/gpio/gpioN/valueCopy to clipboard

Note: Any nonzero value is treated as high.
        - Write <kbd class="ph userinput">0</kbd> to `gpioN`

                echo 0 > /sys/class/gpio/gpioN/valueCopy to clipboard

Read the GPIO configuration register (example GPIO `config0`) through ADB and
      modify the configurations. Ensure that CONFIG\_DEVMEM kernel configuration is enabled.

Note: CONFIG\_DEVMEM kernel configuration is
      enabled by default on Linux Ubuntu-based systems.

1. Use the following command after the network (`eth0` or `wlan0` interface) is connected.

        apt-get updateCopy to clipboard

        This command updates the package index files on the system, which contain information about available packages and their versions. It downloads the most recent package information from the sources listed in the  /etc/apt/sources.list file.
2. Install the `devmem2` tool.

        apt-get install devmem2Copy to clipboard

        devmem2Copy to clipboard

        The following output is displayed. 
    <samp class="ph systemoutput"> Usage: devmem2 { address } [ type [
            data ] ] address : memory address to act upon type : access operation type : [b]yte,
            [h]alfword, [w]ord data : data to be written</samp>

    - `devmem2` tool is supported on the Linux Ubuntu-based systems.
    - `devmem2` tool is not supported on the Linux Embedded systems.
3. Read the GPIO\_CFG0 register.

        devmem2 0x0F500000Copy to clipboard

        The following output is displayed.
        
    <samp class="ph systemoutput">Memory mapped at address 0x7fb7274000. Value at address 0xF500000 (0x7fb7274000): 0x1</samp>
Where,
    - `devmem2` is a program to read or write from or to any location in memory
    - `0x0F500000` is the actual memory to run `devmem2`
    - `0x7fb7274000` is the virtual address of 0x0F500000
    - `0x1` is the value read
4. Write the GENI initial CFG revision register.

        devmem2 0x00984000 w 0x9Copy to clipboard

        The following output is displayed.
        
    <samp class="ph systemoutput">/dev/mem opened. Memory mapped at address 0x7fa494e000. Value at address 0xF500000 (0x7fa494e000): 0x1 Written 0x3; readback 0x3</samp>

    - Where,
        - `0x0F500000` is GPIO\_CFG0 register
        - `0x00984000` is QUPV3\_0\_SE1\_GENI\_INIT\_CFG\_REVISION (GENI initial CFG revision register)
        - `/dev/mem opened.` opens the `/dev/mem` to perform a memory operation
        - `Memory mapped at address 0x7fa494e000.` maps to virtual address
        - `Value at address 0xF500000 (0x7fa494e000): 0x1` shows the current value in the address location by read operation
        - `Written 0x3; readback 0x3` writes `0x3` value in the memory location

Note:
- Location of the QUPAC\_Access file in TrustZone: /core/settings/buses/qup\_accesscontrol/qupv3/config/8250/QUPAC\_Access.c
- All serial engines for the QRB5165 device are listed in `qupv3_perms_qrb`. Only available serial engines can be accessed by any subsystem. The design is flexible enough to list only available serial engines on a particular platform.
- The QUPAC\_Access.c file can be modified to suit the board design.
            `qupv3_perms_qrb` specifies the resource owners of the serial engines. It
          is initially populated according to system I/O GPIO allocation. After the
            QUPAC\_Access.c file is updated, ensure to flash
            devcfg.mbn.

For more information on customizing QUPs, see <cite class="cite">Qualcomm Robotics RB5 Platform Software Porting Guide</cite> (80-88500-1).

**Parent Topic:** [QUP and GPIO configurations](https://docs.qualcomm.com/doc/80-88500-3/topic/4_Configure_QUP_and_GPIO_settings.html)

Last Published: Sep 26, 2023

[Previous Topic
About QUP ports](https://docs.qualcomm.com/bundle/publicresource/80-88500-3/topics/5_About_QUP_ports.md) [Next Topic
Configure multimedia settings](https://docs.qualcomm.com/bundle/publicresource/80-88500-3/topics/7_Configure_multimedia_settings.md)