# Clock

Source: [https://docs.qualcomm.com/doc/80-88500-4/topic/13_Clock.html](https://docs.qualcomm.com/doc/80-88500-4/topic/13_Clock.html)

A mandatory core crystal oscillator (CXO) is supported at the oscillation frequency of
    38.4 MHz. During Retention or Low-power mode, the CXO runs at a frequency of 19.2 MHz. The CXO
    is the source for all the clocks.

A phased lock loop (PLL) generates an output signal for a phase that is related to the phase
      of an input signal. The CXO drives the phase-locked loops (PLL), which then drive the clock
      distribution.

The PLLs are partitioned into subsystems. The core that owns each PLL configures and uses
      it.

The QRB5165 SoC supports subsystems such as applications processor subsystem or CPU subsystem
      (APSS or CPUSS), low-power audio subsystem (LPASS), multimedia subsystem (MMSS), compute
      subsystem (CSS), Qualcomm^®^ Snapdragon™ processor sensor core, resource power
      manager (RPM), and memory interfaces like double data rate (DDR) and internal memory (IMEM).
      There is a network-on-a-chip (NoC) interface bus, which interconnects all the subsystems and
      memory interfaces with clocks.

The following table lists the PLL output frequencies for all the supported subsystems:

Table : PLL output frequencies for subsystems

| PLL | Output frequency (MHz) | Subsystem |
| --- | --- | --- |
| AOSSPLL0 | 600.00 | Always-on subsystem (AOSS) |
| AOSSPLL1 | 38.40 | AOSS |
| APSSPLL0 | – | Applications processor subsystem (APSS) |
| APSSPLL1 | – | APSS |
| APSSPLL2 | – | APSS |
| APSSPLL3 | – | APSS |
| CAMPLL0 | 1200.00 | Camera |
| CAMPLL1 | 600.00 950.00 1050.00 1400.00 | Camera |
| CAMPLL2 | 1440.00 | Camera |
| CAMPLL3 | 700.00<br><br><br>              <br>950.00<br><br><br>              <br>1152.00<br><br><br>              <br>1360.00 | Camera |
| CAMPLL4 | 700.00<br><br><br>              <br>950.00<br><br><br>              <br>1152.00<br><br><br>              <br>1360.00 | Camera |
| DDR4CCPLL0 | – | Double data rate (DDR) |
| DDR4CCPLL1 | – | DDR |
| DDR5CCPLL0 | – | DDR |
| DDR5CCPLL1 | – | DDR |
| DISPPLL0 | 1380.00 | Multimedia Display subsystem (MDSS) |
| DISPPLL1 | 600.00 | MDSS |
| GPLL0 | 600.00 | Top level |
| GPLL1 | 1066.00 | Top level |
| GPLL10 | 1020.00 | Top level |
| GPLL11 |  | Top level |
| GPLL2 | 400.00 451.20 547.20 | Top level |
| GPLL3 | 400.00 451.20 547.20 | Top level |
| GPLL4 | 806.00 | Top level |
| GPLL5 | 933.00 | Top level |
| GPLL6 | 880.00 | Top level |
| GPLL7 | 1036.00 | Top level |
| GPLL8 | 700.00 | Top level |
| GPLL9 | 808.00 | Top level |
| GPUPLL0 | 390.00 610.00 800.00 883.20 980.00 1050.00 1174.00 1340.00<br><br><br>              <br>1400.00 1450.00 | Multimedia subsystem (MMSS) |
| GPUPLL1 | 500.00 | MMSS |
| LPAAONPLL0 | 614.40 | Low-power audio subsystem (LPASS) |
| LPAAONPLL1 | 38.40 | LPASS |
| LPAAONPLL2 | 384.00 576.00 768.00 940.80 1171.20 1324.80 1401.60 | LPASS |
| LPAPLL0 | 1128.96 | LPASS |
| LPAPLL1 | 614.40 | LPASS |
| NPUPLL0 | 600.00<br><br><br>              <br>812.00 1066.00<br><br><br>              <br>1460.00 1840.00 2000.00 | Top level |
| NPUPLL1 | 1500.00 | Top level |
| NPUPLL2 | 300.00 400.00 500.00 660.00 800.00 | Top level |
| SSCPLL0 | 600.00 | Sensors |
| SSCPLL1 | 269.00 384.00 499.00 634.00 806.00 922.00 998.00 | Sensors |
| CSSPLL0 | 403.20 537.60 652.8 825.60 | Compute subsystem (CSS) |
| CSSPLL1 | 614.40 | CSS |
| CSSPLL2 | 525.00 | CSS |
| CSSPLL3 | 364.80 576.00 768.00 960.00 1171.20 1324.80 1401.60 1497.60 | CSS |
| VIDEOPLL0 | 720.00 1014.00 1098.00 1332.00 | Video |
| VIDEOPLL1 | 840.00 1098.00 1332.00 | Video |

Note: A separate sleep crystal is not supported. The sleep clock is used
      as the source for the time tick with an oscillation frequency of 32.7645 kHz and is generated
      from the CXO using a divisor of 586.

- **[NoC (bus) configuration](https://docs.qualcomm.com/doc/80-88500-4/topic/16_NoC__bus__configuration.html)**  

The network-on-chip (NoC) facilitates and controls the data flow using a bus interface.     The NoC configuration can be done for various system and memory cores.
- **[Subsystem performance levels](https://docs.qualcomm.com/doc/80-88500-4/topic/17_Subsystem_performance_levels.html)**  

The subsystem performance levels provide the frequency at which the source PLLs drive     the clocks of the SoC.

**Parent Topic:** [System](https://docs.qualcomm.com/doc/80-88500-4/topic/7_System.html)

Last Published: Aug 18, 2023

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