# Qualcomm® Hexagon™ Tensor Accelerator
Source: [https://docs.qualcomm.com/doc/80-88500-4/topic/147_HTA.html](https://docs.qualcomm.com/doc/80-88500-4/topic/147_HTA.html)
The Qualcomm® Hexagon™ Tensor Accelerator (HTA) is a dedicated, scalable,
power-efficient, programmable hardware accelerator for fixed-point deep convolutional neural
networks (DCNN) models.
HTA is a part of the Hexagon processor that can offload neural network inference tasks to the
HTA or cDSP or HVX.
HTA offers high-level programming access through the Qualcomm Neural Processing SDK and the
Hexagon-HTA-NN (also known as Direct HTA) API in the Hexagon SDK as well as the Google Android
NN-API in Android NDK to developers.
Table : HTA features
| Feature | Description |
| --- | --- |
| Network execution engine | - 8-bit and 16-bit fixed-point math—scalable for AI compute
- Generates complex address patterns to fetch data for MACs
|
| Tightly coupled memory | Built-in support for the NPU-centric load/store operations + synchronization with the DMA |
| 3D DMA controller | Supports 3D data structure movement, streaming DMA, gather/scatter, padding/cropping in any dimension |
| Control plane processor | Dedicated CPU and cache to allow AI workloads to process in parallel without interaction with an application processor CPU or DRAM |
Figure : HTA 230 hardware block diagram
Table : HTA 130 vs. HTA 230 hardware specifications
| Specification | HTA 130 | HTA 230 |
| --- | --- | --- |
| Number of cores | 1 | 2 |
| Deep learning bandwidth compression (DLBC) | No | Yes |
| Control processor cache | No | L2 cache (256 kB) |
| Core tightly coupled memory | 128 kB | 2 ´ 128 kB |
| Data compression (DLBC) | No | Yes |
| MACs | - 1024 – 8-bit fixed point
- 512 – 16-bit fixed point
| - 4096 – 8-bit fixed point
- 1024 – 16-bit fixed point
|
| TOPs | - ~1.8 TOPs (8 bit)
- ~0.9 TOPs (16 bit)
| - ~8 TOPs (8 bit)
- ~2 TOPs (16 bit)
|
| Maximum core clock | 908 MHz | 1000 MHz |
Table : HTA 130 vs. HTA 230 core hardware clock frequency plan
| Clock | HTA 130 | HTA 230 |
| --- | --- | --- |
| Low\_SVS | 300 MHz | 300 MHz |
| SVS | 400 MHz | 466 MHz |
| SVS\_L1 | 487 MHz | 533 MHz |
| Nominal | 652 MHz | 850 MHz |
| Turbo | 811 MHz | 1000 MHz |
| Turbo\_L1 | 908 MHz | – |
- **[HTA software](https://docs.qualcomm.com/doc/80-88500-4/topic/150_HTA_software.html)**
The HTA neural network software uses Qualcomm^®^ Neural Processing SDK environment. The HTA can honor execution requests from both the CPU and the DSP without coordination.
- **[DLBC](https://docs.qualcomm.com/doc/80-88500-4/topic/149_DLBC.html)**
The deep learning bandwidth compression (DLBC) is an internal compression for private Qualcomm^®^ Hexagon™ Tensor Accelerator (HTA) data and is not visible to any SoC cores outside the HTA.
- **[Inception v3 performance](https://docs.qualcomm.com/doc/80-88500-4/topic/151_Inception_v3_performance.html)**
Inception v3 is a neural network model for image analysis and object detection.
- **[HTA dual cores – batch processing](https://docs.qualcomm.com/doc/80-88500-4/topic/148_HTA_230_features.html)**
The HTA dual cores can be used to perform batch processing for multiple images using the Inception v3 neural network architecture.
**Parent Topic:** [Artificial intelligence/Machine learning](https://docs.qualcomm.com/doc/80-88500-4/topic/143_AI_ML.html)
Last Published: Aug 18, 2023
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