# PM8250
Source: [https://docs.qualcomm.com/doc/80-88500-4/topic/43_PM8250.html](https://docs.qualcomm.com/doc/80-88500-4/topic/43_PM8250.html)
PM8250 is the core PMIC for core power or options with lighting.
Figure : Functional block diagram for PM8250
## Input power management
Coin-cell charging is enabled through software control and powered from Vbatt. The on-chip
charger is implemented using a programmable voltage source and a programmable series
resistor. The modem integrated circuit (IC) reads the coin-cell voltage through the analog
multiplexer of PMIC to monitor charging.
## Output power management
The output power management circuits include the following:
- Bandgap voltage reference circuit
- Fast-transient switched-mode power supply (FTS510) circuits
- High-frequency switched-mode power supply (HFS510) circuits
- Internal voltage-regulator connections
- LDO linear (LDO510) regulators
The PM8150/PM8250 device is supplemented by the PM8150L device to provide all the regulated
voltages needed for most wireless handset applications. Independent regulated power sources
are required for various electronic functions to avoid signal corruption between diverse
circuits to support power-management sequencing, and to meet different voltage-level
requirements.
A total of 28 programmable voltage regulators are provided by the PM8150/PM8250 device,
with all outputs derived from a common bandgap reference circuit. Each regulator can be set
to a low-power mode for power savings.
The PM8150/PM8250 device eliminates the need to have local load capacitors for certain LDOs
(600 mA and under).
An LDO implements its low-power mode by reducing the current of its feedback loop. During
low-power operation, the regulator performance is degraded, for example, lower PSRR and less
output current capability. If the load is greater than 10 mA, the output voltage is likely
to be out of specification during LPM.
## Subregulation
Subregulation implements a two-stage regulation scheme, the first stage uses a buck
converter, and the second stage uses a linear regulator.
Rather than dropping a large voltage across an LDO (such as 3.6 V to 1.05 V), the buck
converter efficiently creates an intermediate voltage (1.3 V), which is used by several LDOs
to create the anticipated outputs. The intermediate voltage (1.3 V, for example) can also be
used to power other circuits. Low LDO headroom provides greatly reduced power
dissipation.
Subregulation allows fewer SMPS circuits, resulting in reduction of the die area, PWB area,
and BOM cost. Subregulation provides sufficient suppression of buck noise and spurs to
enable the Auto mode in buck converter. The Auto mode yields better buck efficiency when the
load is below 100 mA to 150 mA.
Subregulation also reduces the supply ripple and noise, resulting in improved circuit
performance. The RFIC supplies use subregulation to improve noise and ripple. Dedicated LDOs
for different circuits provide isolation between those circuits.
Figure : Subregulation scheme in PM8250
## General housekeeping
The PMIC includes several circuits that support handset-level housekeeping functions, that
is, various tasks that must be performed to keep the handset in order. Integration of these
functions reduces the external parts count and the associated size and cost. Housekeeping
functions include an analog switch matrix, multiplexers, and voltage scaling; a housekeeping
crystal oscillator (HK/XO) analog-to-digital converter (ADC) circuit; system clock circuits;
a real-time clock (RTC) for time and alarm functions; and overtemperature protection.
## Analog multiplexer and scaling circuits
A set of analog switches, analog multiplexers, and voltage-scaling circuits select and
condition a single analog signal for routing to the on-chip HK/XO ADC.
Table : Analog multiplexer and scaling functions in PM8250
| Channel number (hexadecimal) | Description | Source | Scaling | Internal pull-up | Input range (V) |
| --- | --- | --- | --- | --- | --- |
| 0 | REF\_GND | Pin: REF\_GND | 1/1 | Open | 0 to 1.875 |
| 1 | 1.25VREF | Internal: MBG | 1/1 | Open | 0 to 1.875 |
| 2 | VREF\_VADC | Internal: VADC LDO | 1/1 | Open | 0 to 1.875 |
| 83 | VPH\_PWR | Pin: VPH\_PWR | 1/3 | Open | 0 to 5 |
| 85 | VCOIN | Pin: VCOIN | 1/3 | Open | 0 to 3.6 |
| 6 | DIE\_TEMP | Internal: TEMP\_ALARM | 1/1 | Open | 0 to 1.875 |
| C | XO\_THERM | Pin: XO\_THERM | 1/1 | Open | 0 to 1.875 |
| D | AMUX\_THM1 | Pin: AMUX\_1 | 1/1 | Open | 0 to 1.875 |
| E | AMUX\_THM2 | Pin: AMUX\_2 | 1/1 | Open | 0 to 1.875 |
| 12 | AMUX1\_GPIO | Pin: GPIO3 (LV) | 1/1 | Open | 0 to 1.875 |
| 13 | AMUX2\_GPIO | Pin: GPIO4 (LV) | 1/1 | Open | 0 to 1.875 |
| 14 | AMUX3\_GPIO | Pin: GPIO5 (MV) | 1/1 | Open | 0 to 1.875 |
| 15 | AMUX4\_GPIO | Pin: GPIO2 (LV) | 1/1 | Open | 0 to 1.875 |
| 2C | XO\_THERM | Pin: XO\_THERM | 1/1 | 30 k | 0 to 1.875 |
| 2D | AMUX\_THM1 | Pin: AMUX\_1 | 1/1 | 30 k | 0 to 1.875 |
| 2E | AMUX\_THM2 | Pin: AMUX\_2 | 1/1 | 30 k | 0 to 1.875 |
| 32 | AMUX1\_GPIO | Pin: GPIO3 (LV) | 1/1 | 30 k | 0 to 1.875 |
| 33 | AMUX2\_GPIO | Pin: GPIO4 (LV) | 1/1 | 30 k | 0 to 1.875 |
| 34 | AMUX3\_GPIO | Pin: GPIO5 (MV) | 1/1 | 30 k | 0 to 1.875 |
| 35 | AMUX4\_GPIO | Pin: GPIO2 (LV) | 1/1 | 30 k | 0 to 1.875 |
| 4C | XO\_THERM | Pin: XO\_THERM | 1/1 | 100 k | 0 to 1.875 |
| 4D | AMUX\_THM1 | Pin: AMUX\_1 | 1/1 | 100 k | 0 to 1.875 |
| 4E | AMUX\_THM2 | Pin: AMUX\_2 | 1/1 | 100 k | 0 to 1.875 |
| 52 | AMUX1\_GPIO | Pin: GPIO3 (LV) | 1/1 | 100 k | 0 to 1.875 |
| 53 | AMUX2\_GPIO | Pin: GPIO4 (LV) | 1/1 | 100 k | 0 to 1.875 |
| 54 | AMUX3\_GPIO | Pin: GPIO5 (MV) | 1/1 | 100 k | 0 to 1.875 |
| 55 | AMUX4\_GPIO | Pin: GPIO2 (LV) | 1/1 | 100 k | 0 to 1.875 |
| 6C | XO\_THERM | Pin: XO\_THERM | 1/1 | 400 k | 0 to 1.875 |
| 6D | AMUX\_THM1 | Pin: AMUX\_1 | 1/1 | 400 k | 0 to 1.875 |
| 6E | AMUX\_THM2 | Pin: AMUX\_2 | 1/1 | 400 k | 0 to 1.875 |
| 72 | AMUX1\_GPIO | Pin: GPIO3 (LV) | 1/1 | 400 k | 0 to 1.875 |
| 73 | AMUX2\_GPIO | Pin: GPIO4 (LV) | 1/1 | 400 k | 0 to 1.875 |
| 74 | AMUX3\_GPIO | Pin: GPIO5 (MV) | 1/1 | 400 k | 0 to 1.875 |
| 75 | AMUX4\_GPIO | Pin: GPIO2 (LV) | 1/1 | 400 k | 0 to 1.875 |
| 83 | VPH\_PWR | Pin: VPH\_PWR | 1/3 | Open | 0 to 5 |
| 85 | VCOIN | Pin: VCOIN | 1/3 | Open | 0 to 3.6 |
| 94 | AMUX3\_GPIO | Pin: GPIO5 (MV) | 1/3 | Open | 0 to 5 |
| . | . | – | – | – | – |
| FF | All channels off | – | – | – | – |
## System clocks
The PMIC includes several clock circuits whose outputs are used for general housekeeping
functions and elsewhere within the handset system. These circuits include a 19.2 MHz XO with
multiple controllers and buffers, an MP3 clock output, an RC oscillator, and sleep-clock
outputs.
Figure : Clock interfaces in PM8250
- 38.4 MHz XO circuits – An external crystal is supplemented by on-chip circuits to
generate the intended 38.4 MHz reference signal. Using an external thermistor network, the
on-chip ADC and advanced temperature compensation software, the PMIC eliminates the large
and expensive VCTCXO module required by previous-generation chipsets. The XO circuits
initialize and maintain valid pulse waveforms and measure time intervals for higher-level
handset functions.
- Multiple controllers manage the XO and signal buffering and generate the intended clock
outputs (all derived from one source):
- RF\_CLKx and LN\_BB\_CLKx low-noise outputs – enabled internally, or can be enabled via
properly configured GPIOs (RF\_CLKx is 38.4 MHz while LN\_BB\_CLKx is 19.2 MHz)
- LN\_BB\_CLK1\_EN low-noise output – enabled by the dedicated control pin; this output
is used as the clock signal for modem IC
- Since the different controllers and outputs are independent, circuits other than those
needed for the WAN can operate even while the modem IC is asleep, and its RF circuits are
powered down. The XTAL\_IN and XTAL\_OUT pins are incapable of driving a load; the
oscillator will be disrupted if either pin is externally loaded.
- Sleep clock – Generated using the 38.4 MHz XO circuit and dividing its output by 1172 to
create a 32.7645 kHz signal. The PMIC sleep-clock output is routed to the modem IC via
SLEEP\_CLK. It is also available for other applications using properly configured
GPIOs.
## Real-time clock (RTC)
The RTC functions are implemented by a 32‑bit real-time counter and one 32‑bit alarm; both
are configurable in one second increments. The primary input to the RTC circuits is the
selected sleep-clock source (calibrated low-frequency oscillator or divided-down 38.4 MHz
XO). Even when the device is off, the selected oscillator and RTC continue to run off the
main battery.
If only the main battery is present and an SMPL event occurs, the RTC contents are
corrupted. The device must reacquire system time from the network to resume the usual RTC
accuracy. Similarly, if the main battery is not present and the voltage at VCOIN drops too
much, the RTC contents are again corrupted. In either case, the RTC reset interrupt is
generated. If the oscillator stops, a different interrupt is generated, which also causes
RTC errors.
If the RTC support is needed when the battery is removed, a qualified coin-cell or super
capacitor is required on the VCOIN pin of the PMIC. If only the SMPL support is needed when
the battery is removed, a 47-µF capacitor with at least 10 µF effective capacitance at 3 V
is required on the VCOIN pin of the PMIC.
## Overtemperature protection (smart thermal control)
The PMIC includes overtemperature protection in stages, depending on the urgency as the die
temperature rises:
1. Stage 0 – normal operating conditions (less than 95°C)
2. Stage 1 – 95 to 115°C; an interrupt is sent to the modem IC
3. Stage 2 – 115 to 145°C; an interrupt is sent to the modem IC
4. Stage 3 – greater than 145°C; an interrupt is sent to the modem IC, and the PMIC is shut
down
Temperature hysteresis is incorporated, such that the die temperature must cool
significantly before the device can be powered on again. If any start signals are present
while at Stage 3, they are ignored until Stage 0 is reached. When the device cools enough to
reach Stage 0 and a start signal is present, the PMIC powers up immediately.
## Configurable I/Os
The 10 GPIO ports are digital I/Os that can be programmed for various configurations. Most
GPIOs default to digital input with 10 µA pull-down at power-on. Before they can be used for
their intended purposes, they must be configured for use.
The PM8150/PM8250 device includes two GPIOs (GPIO\_2 and GPIO\_5) that are used for the
option pins (OPT [2:1]); the settings of these two pins define or influence the device
parameters.
The OPT pins must be set correctly for their application; the reference design uses the
settings OPT [2:1] = Hi-Z, Hi-Z.
Table : Pin options in PM8150
| OPT\_1
(GPIO\_5) | Configuration | OPT\_2
(GPIO\_2) | Configuration |
| --- | --- | --- | --- |
| GND | Default power on (PON) | GND | – |
| Hi-Z | Legacy PON | Hi-Z | – |
| VPH\_PWR | Reserved | VREG\_IO | Reserved |
Table : Pin options in PM8250
| OPT\_1
(GPIO\_5) | Configuration | OPT\_2
(GPIO\_2) | Configuration |
| --- | --- | --- | --- |
| GND | Reserved | GND | LPDDR4 support |
| Hi-Z | Default PON | Hi-Z | Reserved |
| VPH\_PWR | Reserved | VREG\_IO | LPDDR5 support |
## IC-level interfaces
Figure : PON circuits hardware architecture in PM8250
The Qualcomm PMIC has a PON module responsible for the following roles:
- Power on (PON)
- Power off (POFF)
- Reset of the PMIC peripherals and complete system
- Reset triggers – internal and external triggers are routed to the PON module; the PON
module determines the actions to take in response to these triggers (for example, OTST3,
KPD\_PWR\_N, and PS\_HOLD)
- Reset types – describes the behavior of the PMIC during a reset or shutdown event (for
example, warm reset or hard reset event); the configuration registers in the PON module
determine the type of reset event
- Reset stages occur via the following configurable timers and in this order:
- Software configurable bark
- Software configurable reset
- Failsafe reset
- Reset timer stages:
- Stage 1 – for each trigger, an interrupt is sent to the SDM to warn it about the
shutdown; the amount of time (S1\_Timer) the debounced trigger must be held before a
bark is sent to the SDM and can be configured using the PON\_XXX\_RESET\_S1\_TIMER
register
- Stage 2 – after the interrupt is sent to the SDM, the PMIC awaits reply for the
S2\_TIMER period before it does the shutdown; the amount of time the debounced trigger
must wait can be configured using the PON\_XXX\_RESET\_S2\_TIMER register
- Stage 3 – this stage is independent of S1 and S2; if a trigger is held for an
extended period (default is 64 seconds), force xVdd shutdown occurs, that is, it does
not follow a graceful shutdown procedure and results in an abrupt power-down; it
guarantees a way out for unexpected hang-ups and resets all the PMIC registers
Figure : PON state machine in PM8250
**Parent Topic:** [PMIC](https://docs.qualcomm.com/doc/80-88500-4/topic/42_PMIC.html)
Last Published: Aug 18, 2023
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