# Erroneous transaction on bus (error and timeout)

Source: [https://docs.qualcomm.com/doc/80-88500-4/topic/72_Erroneous_transaction_on_bus__error_and_timeout_.html](https://docs.qualcomm.com/doc/80-88500-4/topic/72_Erroneous_transaction_on_bus__error_and_timeout_.html)

Errors and timeouts on the bus can happen due to invalid bus access or when there is a
    bus hang. A bus hang occurs when a bus master (processor or nonprocessor) accesses a slave that
    may have one of the key clocks off such that an access to this slave waits indefinitely and
    never returns.

If the access that hung was from a processor, the processor waits indefinitely, and the
      processor can recover by restarting the system through watchdog.

To monitor and control such scenarios, the network-on-chip (NOC) time monitor and advanced
      high-performance bus (AHB) time monitor are bus hang monitors implemented in all the buses in
      the system.

To overcome the challenge of having invalid access to DDR from unintended master without
      permission, external protection unit (XPU) and translation buffer unit (TBU), a system memory
      management unit (SMMU) component) are introduced to build a secure system for debug.

## NOC error and timeout

NOC\_ERROR and timeout are fatal errors when NOC detected decode error or unclocked bus access,
        and so on. The NOC generates fast interrupt request (FIQ) to TrustZone (TZ).

## AHB timeout

The AHBs are used in the system for interconnections in peripherals. If access timeout occurs on
        a transaction, it generates a FIQ report of the AHB timeout to TZ.

## XPU violations

The XPU violations occur when a master subsystem tries to access a system
        resource. For example, memory region, device controller registers, and so on, for which
        either proper access permission is not set, or the device controller is not functional due
        to unavailability of the clocks.

The XPU violations should be configured as fatal during the development and testing phase to
        ensure capturing all the unexpected issues. To configure the XPU violation as a fatal error,
        the Linux kernel config should set CONFIG\_MSM\_XPU\_ERR\_FATAL=y.

The various fields in the XPU dump can be interpreted as follows:

- XPU ID – ID to identify a device controller or hardware module
- uPhysicalAddress – Address that was read/write with reference to XPU ID
- BID or Bus ID – SNOC, PNOC, and CNOC
- PID or Port ID – Port number on the bus identified with BID from which the transaction originated
- Master ID (MID) – MID that initiated the transaction
- Virtual Master ID (VMID) – May be the same as MID, but will uniquely identify a master

## TBU (SMMU) error

- TBU is used for a system-level memory management unit. It supports address translation from an
          input address to an output address, based on address mapping and memory attribute
          information held in translation tables.
- SMMU error is a fatal error, such as when a subsystem or peripheral tries to access an invalid address or with invalid attribute.
- SMMU error is routed to TZ.

For more information, see <cite class="cite">Arm System Memory Management Unit
          Architecture Specification</cite>, [IHI0062D](http://infocenter.arm.com/help/topic/com.arm.doc.ihi0062c/IHI0062C_system_mmu_architecture_specification.pdf).

**Parent Topic:** Debug

Last Published: Aug 18, 2023

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