# USB clocks and interrupts
Source: [https://docs.qualcomm.com/doc/80-88500-4/topic/usb_clocks_and_interrupts.html](https://docs.qualcomm.com/doc/80-88500-4/topic/usb_clocks_and_interrupts.html)
The USB and USB PHY primary and secondary controller clocks operate at different
frequencies based on the speed modes (HS and SS). The controller clocks also manage the
various reset mechanisms and interrupts for USB and USB SS-PHY and HS-PHY.
The following tables list the primary and secondary USB and USB PHY clocks and their
respective operating frequencies.
Table : Primary USB controller clocks
| Clock name | Operating frequency | Description |
| --- | --- | --- |
| gcc\_usb30\_prim\_master\_clk“core\_clk” |
200 MHz – SS
66 MHz – HS
| Asynchronous to the bus clock; clock rates defined within the device tree node |
| gcc\_cfg\_noc\_usb3\_prim\_axi\_clk“iface\_clk” |
| Clock that feeds into the aggregator2 module, which controls data flow from USB AXI to the NOC |
| gcc\_usb30\_prim\_mock\_utmi\_clk“utmi\_clk” | 19.2 MHz | Internal controller ref\_clk used for generating the ITP counter when the USB Transceiver Macrocell Interface (UTMI)/ UTMI + Low Pin Interface (ULPI) is suspended |
| gcc\_usb30\_prim\_sleep\_clk“sleep\_clk” | 32 kHz | Sleep clock |
| gcc\_usb3\_sec\_clkref\_clk“xo” | 19.2 MHz |
Primary controller uses the same reference clock as the secondary controller
External reference clock source to the HS-PHY (PMIC)
|
Table : Secondary USB controller clocks
| Clock name | Operating frequency | Description |
| --- | --- | --- |
| gcc\_usb30\_sec\_master\_clk“core\_clk” |
200 MHz – SS
66 MHz – HS
| Asynchronous to the bus clock; clock rates are defined within the device tree node |
| gcc\_cfg\_noc\_usb3\_sec\_axi\_clk“iface\_clk” |
| Clock that feeds into the aggregator2 module, which controls data flow from USB AXI to the NOC |
| gcc\_usb30\_sec\_mock\_utmi\_clk“utmi\_clk” | 19.2 MHz | Internal controller ref\_clk used to generate the ITP counter when the UTMI/ULPI is suspended |
| gcc\_usb30\_sec\_sleep\_clk“sleep\_clk” | 32 kHz | Sleep clock |
| gcc\_usb3\_sec\_clkref\_clk“xo” | 19.2 MHz |
Primary controller uses the same reference clock as the secondary controller
External reference clock source to the HS-PHY (PMIC)
|
Table : Primary and secondary USB HS-PHY clocks
| Clock name | Operating frequency | Description |
| --- | --- | --- |
| rpmh\_cxo\_clk“ref\_clk\_src” | 19.2 MHz | Reference clock source to the HS-PHY |
| gcc\_usb\_phy\_cfg\_ahb2phy\_clk“cfg\_ahb\_clk” | 100 MHz | Clock required for AHB2PHY block (frequency based off PNOC frequency) |
Table : Primary USB SS-PHY clocks
| Clock name | Operating frequency | Description |
| --- | --- | --- |
| gcc\_usb3\_prim\_phy\_aux\_clk“aux\_clk” | 19.2 MHz | PHY interface for PCI express (PIPE) auxiliary clock for power states |
| gcc\_usb3\_prim\_phy\_pipe\_clk“pipe\_clk” | 125 MHz | Input source for PIPE, which allows for data transfers between PHY and controller |
| GCC\_USB3\_PRIM\_PHY\_PIPE\_CLK\_SRC“pipe\_clk\_mux” | N/A | Mux input selector for PIPE, switchable between “ref\_clk\_src” and “pipe\_clk\_ext\_src” |
| USB3\_PHY\_WRAPPER\_GCC\_USB30\_PIPE\_CLK“pipe\_clk\_ext\_src” | 312.5 MHz (Gen2)
125 MHz (Gen1) | Generated output of PHY clock |
| rpmh\_cxo\_clk“ref\_clk\_src” | 19.2 MHz | Parent clock for ref\_clk |
| gcc\_usb3\_prim\_phy\_com\_aux\_clk“com\_aux\_clk” | 19.2 MHz | Auxiliary clock input to the common block |
Table : Secondary USB SS-PHY clocks
| Clock name | Operating frequency | Description |
| --- | --- | --- |
| gcc\_usb3\_sec\_phy\_aux\_clk“aux\_clk” | 19.2 MHz | PIPE auxiliary clock for power states |
| gcc\_usb3\_sec\_phy\_pipe\_clk“pipe\_clk” | 125 MHz | Input source for PIPE, which allows for data transfers between PHY and controller |
| GCC\_USB3\_SEC\_PHY\_PIPE\_CLK\_SRC“pipe\_clk\_mux” | N/A | Mux input selector for PIPE, switchable between “ref\_clk\_src” and “pipe\_clk\_ext\_src” |
| USB3\_UNI\_PHY\_SEC\_GCC\_USB30\_PIPE\_CLK“pipe\_clk\_ext\_src” |
312.5 MHz (Gen2)
125 MHz (Gen1)
| Generated output of PHY clock |
| rpmh\_cxo\_clk“ref\_clk\_src” | 19.2 MHz | Parent clock for ref\_clk |
| gcc\_usb3\_sec\_clkref\_clk“ref\_clk” | 19.2 MHz | Reference clock source to the SS-PHY |
| GCC\_USB3\_SEC\_PHY\_COM\_AUX\_CLK“com\_aux\_clk” | 19.2 MHz | Auxiliary clock input to the common block |
## Reset mechanisms
Table : Clock controller reset mechanisms
| Clock name | Reset control for | Description |
| --- | --- | --- |
| gcc\_usb3\_dp\_phy\_prim\_bcr“global\_phy\_reset” | SS-PHY | Resets the SS-PHY control and status registers |
| gcc\_usb3\_phy\_prim\_bcr“phy\_reset” | SS-PHY | Resets the SS-PHY |
| gcc\_usb3\_phy\_sec\_bcr“phy\_reset” | SS-PHY | Resets the SS-PHY related to secondary controller |
| gcc\_qusb2phy\_prim\_bcr“phy\_reset” | HS-PHY | Resets the HS-PHY |
| gcc\_qusb2phy\_sec\_bcr“phy\_reset” | HS-PHY | Resets the HS-PHY related to secondary controller |
| gcc\_usb30\_prim\_bcr“core\_reset” | DWC3 controller | Clock controller output to reset the USB controller |
Table : USB controller reset mechanisms
| USB controller register | USB register bit field | Reset control for | Description |
| --- | --- | --- | --- |
| DWC\_USB3\_DCTL | CSFTRST [Bit 30] | DWC3 controller | Resets the entire USB controller; must redo controller initialization |
## USB controller interrupts
| Interrupt name | Interrupt number | Interrupt events | Interrupt events | Description |
| --- | --- | --- | --- | --- |
| Interrupt name | Interrupt number | PDC wakeup | Kernel handling | Description |
| dp\_hs\_phy\_irq | 14 | DP changes | – | Used only when system is in VDD min/XO shutdown |
| dm\_hs\_phy\_irq | 15 | DM changes | – | Used only when system is in VDD min/XO shutdown |
| ss\_phy\_irq | 17 | LFPS detection | – | Only used when system is in VDD min/XO shutdown |
| pwr\_event\_irq | 130 | – |
USB PHY power state changes
Exit/enter P3/L2
| Used as main controller wake-up handler |
| irq | 133 | – |
Bus events
Suspend
Resume
Reset
Controller event completion
Transfer completion
Command completion
| Main USB interrupt that handles all USB controller events |
| sps | 132 | – |
BAM inactivity timer
BAM data threshold hit
| Used to service the BAM events that occur on the USB pipes |
| | | | | |
Note: The listed interrupt numbers do not include the
offset added by the interrupt manager (offset of 32). For more information on the
interrupt handling, see Linux USB Implementation Guide
(80-NF283-1).
| Interrupt name | Interrupt number | Interrupt events | Interrupt events | Description |
| --- | --- | --- | --- | --- |
| Interrupt name | Interrupt number | PDC wakeup | Kernel handling | Description |
| dp\_hs\_phy\_irq | 12 | DP changes | – | Used only when system is in VDD min/XO shutdown |
| dm\_hs\_phy\_irq | 13 | DM changes | – | Used only when system is in VDD min/XO shutdown |
| ss\_phy\_irq | 16 | LFPS detection | – | Used only when system is in VDD min/XO shutdown |
| pwr\_event\_irq | 135 | – |
USB PHY power state changes
Exit/enter P3/L2
| Used as main controller wake-up handler |
| irq | 138 | – |
Bus events
Suspend
Resume
Reset
Controller event completion
Transfer completion
Command completion
| Main USB interrupt that handles all USB controller events |
| | | | | |
Note: The listed interrupt numbers do not include the
offset added by the interrupt manager (offset of 32). For information on the
interrupt handling, see Linux USB Implementation Guide
(80-NF283-1).
**Parent Topic:** [USB](https://docs.qualcomm.com/doc/80-88500-4/topic/106_USB.html)
Last Published: Aug 18, 2023
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