# Hardware overview
This section explains the system block diagram, electrical design, features, and capabilities of the IQ-9075 EVK.
## System block diagram
The following figure shows the system block diagram of the Dragonwing IQ-9075 EVK which provides a visual representation of the Dragonwing IQ-9075 EVK architecture, highlighting the main components and their interactions.
**Figure : Dragonwing IQ-9075 EVK main board block diagram**
## Hardware specification
The following table outlines the key hardware features of the Dragonwing IQ-9075 EVK.
| Interface or feature | Description |
| --- | --- |
| SoC | IQ-9075 *(part of IQ-9075M)* |
| Memory | 6 × 16 bit 36 GB LP5 3200 MHz (3x 12GB LPDDR5) *(part of IQ-9075M)* |
| PMIC | 4 × PMM8650AU *(part of IQ-9075M)* |
| External MCU | Not present |
| Storage | 2 × 128 GB UFS, micro-SD card, EEPROMs for MACs, eMMC on mezzanine card |
| Display | 4 total:
> > >
>
2 × mini-DP (one with MST)
>
2 × DSIs (one to DSI flex, one to expansion)
>
|
| Display | DSI flex connection with touchscreen |
| Camera/Video input | 4 × Quad deserializers |
| Camera/Video input | 4 × CSI (C-PHY or D-PHY) cameras |
| USB | USB0 Type-C (host or device mode) |
| USB | USB1 Type-C (host mode) |
| USB | USB2 uUSB 2.0 (host or device mode) |
| WLAN/Bluetooth^®^ | m.2 module (NFA765A) |
| WLAN/Bluetooth^®^ | 2 × printed antennas (Bluetooth shared with one WLAN antenna) |
| PCIe | Mainboard support OR expanded options (selected via switch): |
| PCIe | 1 × PCIe x4 slot or expansion (switched) |
| PCIe | 1 × m.2 E key (WI-Fi) or expansion (switched) |
| Audio | 1 × I^2^ S mic |
| Audio | 2 × I^2^ S speaker amps |
| Audio | Additional I^2^ S on GPIOs |
| Ethernet | RJ45 2.5GbE MD |
| CAN/CAN-FD | 1 × CAN/CAN-FD on LS header on mainboard |
| Low-speed expansion | 3.3 V header for developer community with CAN, SPI, I^2^ C, UART, I^2^ S |
| Second low-speed expansion | QUPs and GPIOs on mezzanine connectors |
| Sensors | IMU: ICM-42688 |
| Sensors | QUPs on expansion |
| Trusted platform module (TPM) | ST33HTPH2x32AHE4 on mainboard (EVT-WNC version) |
| | |
| | |
## Exterior view
The following figures show a visual overview of the exterior of the Dragonwing IQ-9075 EVK.
**Figure : Exterior view of the EVK with bottom case**
The following figures show the side views of the Dragonwing IQ-9075 EVK, with labeled ports, connectors, and switches.
The following figure shows the top view of the core board.
**Figure : Top view of the core board**
## EVK ports and interfaces
The following figure shows a detailed view of all the connectors on the Dragonwing IQ-9075 EVK.
**Figure : Connector overview of Dragonwing IQ-9075 EVK**
The following figure shows the Dragonwing IQ-9075 EVK with few cables plugged in.
**Figure : Platform with cables plugged in**
Table : Connectors and functions
| Connectors | Functions |
| --- | --- |
| JPWR | DC power (barrel connector) plug, 12 V–36 V input voltage |
| JLS1 | Low speed IO header receptacle (LS1) |
| SW1 | 8 position surface mount DIP switch (functions described later) |
| SW2 | 4 position surface mount DIP switch (functions described later) |
| SW3 | 6 position surface mount DIP switch (functions described later) |
| JCAM0 | MIPI CSI0 camera interconnect receptacle |
| JCAM1 | MIPI CSI1 camera interconnect receptacle |
| JCAM2 | MIPI CSI2 camera interconnect receptacle |
| JCAM3 | MIPI CSI3 camera interconnect receptacle |
| JPCIE | PCI Express v4 female connector (PCIe1) |
| JEDP1 | EDP1 connector |
| JEDP0 | EDP0 connector |
| JETH | Ethernet connector (2.5GbE) |
| JUSB1 | USB-C (USB Type-C) receptacle connector for USB1 |
| JUSB0 | USB-C (USB Type-C) receptacle connector for USB0 |
| JUSB2 | Micro USB receptacle for USB2 |
| JRST | Tactile switch for system reset (initiates graceful shutdown) |
| J13 | Antenna for WLAN |
| S4 | Slide switch for power or automation control |
| JDISP | Connector for DSI display |
| JTAC | Micro USB receptacle for debug UART |
| JTAG | Header connector for JTAG |
| J14 | Antenna for WLAN/Bluetooth |
| JEXP1–JEXP4 | Board-to-board 120 position connector receptacle |
## DIP switch
The following image shows the location of the DIP switches on the board.
**Figure : DIP switches 1, 2, and 3 on Dragonwing IQ-9075 EVK**
**Figure : DIP switches 4, 7, 8, and 9 on Dragonwing IQ-9075 EVK**
Note
- If a DIP switch is facing up, it indicates that the switch is on.
The following table provides detailed information about the DIP switch operations for the Dragonwing IQ-9075 EVK. The table provides information about the specific functions and settings of each switch that you can use to configure the board.
Table : DIP switch position and its respective functions
| Switch | Connection when ON | Connection when OFF (default from factory) | Notes |
| --- | --- | --- | --- |
| SW1–1 | PCIE0 routed to mezzanine | PCIE0 connected to mainboard Wi-Fi module | – |
| SW1–2 | PCIE1 routed to mezzanine | PCIE1 connected to mainboard PCIe connector | – |
| SW1–3 | SDIO routed to mezzanine | SDIO routed to mainboard SD card | – |
| SW1–4 | DSI0 routed to mezzanine | DSI0 routed to mainboard DSI flex connector | – |
| SW1–5 | CSI0 routed to mezzanine | CSI0 routed to mainboard CSI flex connector | – |
| SW1–6 | CSI1 routed to mezzanine | CSI1 routed to mainboard CSI flex connector | – |
| SW1–7 | CSI1 routed to mezzanine | CSI2 routed to mainboard CSI flex connector | – |
| SW1–8 | CSI2 routed to mezzanine | CSI3 routed to mainboard CSI flex connector | – |
| SW2–1 | main domain forced USB boot/EDL | no impact | Currently, this switch isn’t enabled in software. |
| SW2–2 | main domain fastboot | no impact | – |
| SW2–3 | main domain and sail domain forced USB boot/EDL (combined) | no impact | Currently, the software implementation puts both domains into EDL mode together. This is important for software download. |
| SW2–4 | sail domain fastboot mode | no impact | – |
| SW3–1 | OSPI routed to mezzanine | OSPI connected to onboard memory for MCU | – |
| SW3–2 | force MD and MCU PS\_HOLD | no impact | – |
| SW3–3 | watchdog disabled | RAM dump enabled | – |
| SW3–4 | boot from eMMC | boot from UFS | eMMC located on interface plus mezzanine |
| SW3–5 | EUD enable | no impact | – |
| SW3–6 | skip MD BIST | no impact | – |
| SW4–1 | reserved for internal use | reserved for internal use | Don’t change |
| SW7–1 | reserved for internal use | reserved for internal use | Don’t change |
| SW9–1 | reserved for internal use | reserved for internal use | Don’t change |
| SW8–1 | reserved for internal use | reserved for internal use | Don’t change |
## LEDs
The Dragonwing IQ-9075 EVK has multiple status LEDs used to monitor system functions such as power-on or board faults, which could be crucial for debugging or bringup purposes. The following table lists and summarizes the functions of the LEDs. The [Connector overview of Dragonwing IQ-9075 EVK](https://docs.qualcomm.com/doc/80-90441-253/topic/hw-overview.html#fig-jmq-qqy-w2c) shows the location and the LEDs present on the board.
Table : Summary of reference designator, location, color, and function of LEDs
| Reference designator | Location | Color | Function |
| --- | --- | --- | --- |
| DS1 | Mainboard | Green | Reserved for debugging |
| DS8 | Mainboard | Green | Ethernet status LEDs |
| DS9 | Mainboard | Green | Ethernet status LEDs |
| DS10 | Mainboard | Green | VREG\_3P3\_SIP indicator |
| DS11 | Mainboard | Orange | VREG\_3P3\_SIP indicator |
| LED1 | Mainboard | RGB | software controlled RGB lighting through GPIOs |
## Hardware components and interfaces
This section provides an overview of the Dragonwing IQ-9075 processor, power supply, memory, and various interfaces, such as camera, USB, and DisplayPort. It also includes sensors, flash memory, expansion options, a debug interface, audio support, thermal management, fan control, and accessory boards.
### Processor
The target processor used in the Dragonwing IQ-9075 EVK is the Dragonwing IQ-9075 SoC, also known as the IQ-9075. This SoC features an octa-core Kryo^™^ Gen 6 CPU built on Arm v8.2 Cortex technology, with clock support up to 2.55 GHz.
In addition to the eight high-performance CPU cores, the SoC includes a GPU and two Hexagon Tensor Processors with vector and matrix extensions, enabling the management of various concurrent compute and AI workloads simultaneously. The SoC offers extensive peripheral support, including integrated Ethernet, USB, Wi-Fi, PCIe, and Bluetooth. It’s capable of delivering up to 100 INT8 TOPS, making it suitable for powering high-performance, AI-centric, and edge AI industrial use cases.
Target applications include:
- Factory automation
- Industrial robots
- Industrial personal computers
- Drones
- Edge AI Boxes
- Machine Vision
- Autonomous Mobile Robots (AMRs)
- Industrial gateways
The SoC is integrated within the IQ-9075M module, which also houses the four PMICs and three LPDDR5 SDRAM memories. The following figure shows the IQ-9075 SoC within IQ-9075M module.
**Figure : IQ-9075 SoC within IQ-9075M module**
### Power
The main power input to the Dragonwing IQ-9075 board is provided through the 2.10 mm Barrel Jack Connector (JPWR, JACK-C-PC-10A-RA(R)), supporting an input voltage range of 12 V to 36 V. Four regulators manage the respective power supplies to various system blocks, including the SoC, PMIC, PCIe, and expansion ports.
The following picture highlights the four PMICs on the IQ-9075M module.
**Figure : Four PMICs on the IQ-9075M module**
### Memory
The IQ-9075 contains three 12 GB LPDDR5 SDRAM chips. The following picture highlights the LPDDR5 memory ICs on the module.
**Figure : LPDDR5 memory on the IQ-9075M module**
### Camera interface
An analog switch is used for each MIPI CSI interface, allowing the MIPI CSI interfaces to be accessible through both the JCAM camera interconnect receptacle and the B2B expansion connector (JEXP4).
The following table lists the CSI interfaces, their analog switch, camera connector, and B2B connector pinout.
Note
You can connect the CSI interfaces to the mainboard connector or to GSML mezzanine through a DIP switch setting. For the correct setting, See table [DIP switch position and its respective functions](https://docs.qualcomm.com/doc/80-90441-253/topic/hw-overview.html#table-dip-switch-position).
Table : CSI settings
| CSI interface | Analog switch | Camera connector | B2B connector pinout |
| --- | --- | --- | --- |
| CSI0 | - U45 - (TMUX646ZECR) | JCAM0 | JEXP4, Pins 111-120 |
| CSI1 | - U42 - (TMUX646ZECR) | JCAM1 | JEXP4, Pins 51-60 |
| CSI2 | - U44 - (TMUX646ZECR) | JCAM2 | JEXP4, Pins 40-49 |
| CSI3 | U43
> > > (TMUX646ZECR) | JCAM3 | JEXP4, Pins 29-38 |
The four MIPI CSI ports can operate in either C-PHY or D-PHY mode.
They can support a range of existing cameras and flexes, including the OV9282, IMX577.
To use a GMSL camera with the Dragonwing IQ-9075 EVK, connect it through the GMSL mezzanine, which must be ordered separately.
The CSI ports are routed through the DIP switches, allowing configuration and setup.
Note
Four cameras have been validated concurrently, which includes two YUV GMSL cameras connected to GMSL Port2 and Port3, and two MIPI camera connected to MIPI CSI0 and CSI1 slots.
The following figure shows the Dragonwing IQ-9075 EVK with different camera configurations.
**Figure : Dragonwing IQ-9075 EVK with (L) GMSL mezzanine attached; (R) MIPI CSI cameras**
### USB interface
The board features three USB connectors: two Type-C connectors (USB0 and USB1) and one micro-USB connector (USB2). The following table outlines the USB properties of the board.
[Connector overview of Dragonwing IQ-9075 EVK](https://docs.qualcomm.com/doc/80-90441-253/topic/hw-overview.html#fig-jmq-qqy-w2c) shows the location of the USB connectors on the board.
Table : Summary of reference designator, USB interface and type, and description
| Reference designator | USB interface and type | Description |
| --- | --- | --- |
| JUSB0 | USB0 USB-C (USB Type-C) | USB 3.1 Gen 2, HS + SS, supports host or device mode |
| JUSB1 | USB1 USB-C (USB Type-C) | USB 3.1 Gen 2, HS + SS, supports host mode |
| JUSB2 | USB2 Micro USB | USB2.0, HS, supports host modes |
### DisplayPort (eDP) interface
The target processor is equipped with four eDP interfaces. EDP0 and EDP1 are routed to the DP connector receptacles JEDP0 and JEDP1, respectively. Meanwhile, EDP2 and EDP3 are routed to the board-to-board expansion connector JEXP3 (pins 1 – 29).
For the precise location of the DP connectors on the Dragonwing IQ-9075 EVK, see [Connector overview of Dragonwing IQ-9075 EVK](https://docs.qualcomm.com/doc/80-90441-253/topic/hw-overview.html#fig-jmq-qqy-w2c).
Table : eDP interface connections
| eDP interface | Connected to |
| --- | --- |
| EDP0 | JEDP0 (DP3AR020SU32JQ1R400) |
| EDP1 | JEDP0 (DP3AR020SU32JQ1R400) |
| EDP2 | JEXP3 (10139781-121422LF, pins 1-14) |
| EDP3 | JEXP3 (10139781-121422LF, pins 16-29) |
### DSI interface
The IQ-9075 processor supports two 4-lane MIPI-DSI with VESA DSC v1.2.
The Dragonwing IQ-9075 EVK utilizes an analog switch for DSI0 interface, allowing the interface to be accessible through both the JDISP LCD receptacle and the B2B expansion connector (JEXP1). Due to having the analog switch, there is a DIP switch setting to select between connecting DSI0 interfaces to the mainboard LCD connector or to GSML mezzanine. See [Table: DIP switch position and its respective functions](https://docs.qualcomm.com/doc/80-90441-253/topic/hw-overview.html#table-dip-switch-position) for the preferred DSI setting.
The following image shows how the DSI1 is routed to the B2B expansion connector (JEXP3).
**Figure : DSI1 routed to JEXP3**
### Storage interfaces
The Dragonwing IQ-9075 has three types of storage interfaces: SD card, UFS, and EEPROM.
#### SD card
The target processor supports a single SDIO interface (SDC1). The SDC pins are routed through analog switches (U2, U3) to facilitate connections through the micro SD card connector (JSDC) on the board, as well as through the expansion connector (JEXP4, pins 61–71) for eMMC connectivity on a mezzanine board.
Note that there is a DIP switch setting to select between connecting the SDIO to the mezzanine or the micro SD card. See [Table: DIP switch position and its respective functions](https://docs.qualcomm.com/doc/80-90441-253/topic/hw-overview.html#table-dip-switch-position) for the correct setting.
| SDC interface | Analog switch | uSD connector | B2B connector pinout |
| --- | --- | --- | --- |
| SDC1 | U2, U3 (TXS02612RTWR) | JSDC | JEXP4, pins 61-71 |
#### UFS
The target processor supports two UFS 3.1 Gear 4 interfaces, each with two lanes for on-board memory. UFS0 serves as the main domain boot-up device. The Dragonwing IQ-9075 EVK is equipped with two 128 GB UFS devices on the mainboard.
The following table summarizes the part numbers and manufacturers of these UFS devices.
| Reference designator | Interface identifier | MPN | MFR | Description |
| --- | --- | --- | --- | --- |
| U38 | UFS0 | THGJFGT0T25BAB8 | KIOXIA AMERICA INC | 128 GB UFS3.1 (Gear4) Q100-GR2 RoHS |
| | | THGJFGT0T25BAB8 | KIOXIA AMERICA INC | 128 GB UFS3.1 (Gear4) Q100-GR2 RoHS |
#### EEPROM
The Dragonwing IQ-9075 EVK has a single EEPROM device dedicated to storing MAC addresses for Ethernet and Wi-Fi/Bluetooth.
The following table provides a summary of the part number, manufacturer, and description of the EEPROM device.
Table : Summary of the part number, manufacturer, and description of the EEPROM device
| Reference designator | Device | MPN | MFR | Description |
| --- | --- | --- | --- | --- |
| U20 | EEPROM | 93LC46B-I/SN | Microchip Technology Inc. | 1 Kbit low-voltage serial electrically erasable PROMs (EEPROM) |
### On-board sensors
The Dragonwing IQ-9075 EVK platform includes an on-board IMU and a temperature sensor. They are connected to the real-time subsystem (RTSS) domain of IQ-9075 EVK.
Note
Support for IMU and temperature sensors is currently unavailable. Refer to the release notes for your software version to verify if support has been added.
The following table provides a summary of the part numbers, manufacturers, and descriptions of these sensors.
Table : Summary of the part numbers, manufacturers, and descriptions of the sensors
| Reference designator | Sensor type | Communication protocol used | MPN | MFR |
| --- | --- | --- | --- | --- |
| U97 | IMU Sensor | I^2^C | ICM-42688 | TDK InvenSense |
| U109 | Temp Sensor | SPI | TMP411DQDGKRQ1 | Texas Instruments |
### PCIe interface
The target processor supports two PCIe interfaces. PCIe0 is Gen4 2-lane and PCIe1 is Gen4 4-lane PCIe interface.
Both PCIe interfaces are connected to an A/B switch, which by default, connects them to the expansion mezzanine. By configuring the DIP switches (see [Table: DIP switch position and its respective functions](https://docs.qualcomm.com/doc/80-90441-253/topic/hw-overview.html#table-dip-switch-position)), PCIe0 can be connected to the Wi-Fi/Bluetooth module and PCIe1 to the full size PCIe x4 connector on the mainboard.
The following image shows the PCIe configuration.
**Figure : PCIe interface**
### Flash memory
The Dragonwing IQ-9075 evaluation kit utilizes OSPI interface to support 2GBIT flash memory.
It utilizes an analog switch for OSPI interface, allowing the interface to be accessible through both the flash memory device and the B2B expansion connector (JEXP2). Due to having the analog switch, there is a DIP switch setting to select between connecting OSPI to the memory device or to B2B connector. See [Table: DIP switch position and its respective functions](https://docs.qualcomm.com/doc/80-90441-253/topic/hw-overview.html#table-dip-switch-position) for the intended OSPI setting.
The following image shows the flash memory configuration.
**Figure : Flash memory**
### Mezzanine expansion
The evaluation kit features four high-speed expansion connectors (JEXP1-4, 10139781-121422LF), which can be used to connect various accessory cards such as GMSL mezzanine, RBx adapters, and so on. Additionally, various other interfaces mentioned throughout this document are also routed to these connectors. The position of the connectors is shown in [Connector overview of Dragonwing IQ-9075 EVK](https://docs.qualcomm.com/doc/80-90441-253/topic/hw-overview.html#fig-jmq-qqy-w2c). The following four tables provide the pin mapping for these connectors.
The following table details the pin mapping for the **JEXP1** connector.
Table : Pin mapping for the JEXP1 connector
| Pin name | Pin number | Pin number | Pin name |
| --- | --- | --- | --- |
| GND | 61 | 1 | VREG\_SYSTEM\_PWR |
| DSI0\_A0\_LN0\_P\_CONN | 62 | 2 | VREG\_SYSTEM\_PWR |
| DSI0\_B0\_LN0\_M\_CONN | 63 | 3 | VREG\_SYSTEM\_PWR |
| GND | 64 | 4 | VREG\_SYSTEM\_PWR |
| DSI0\_C0\_LN1\_P\_CONN | 65 | 5 | VREG\_SYSTEM\_PWR |
| DSI0\_A1\_LN1\_M\_CONN | 66 | 6 | GND |
| GND | 67 | 7 | GND |
| DSI0\_B1\_CLK\_P\_CONN | 68 | 8 | GND |
| DSI0\_C1\_CLK\_M\_CONN | 69 | 9 | GND |
| GND | 70 | 10 | VREG\_3P3\_SIP |
| DSI0\_A2\_LN2\_P\_CONN | 71 | 11 | VREG\_3P3\_SIP |
| DSI0\_B2\_LN2\_M\_CONN | 72 | 12 | GND |
| GND | 73 | 13 | GND |
| DSI0\_C2\_LN3\_P\_CONN | 74 | 14 | PME\_GPIO\_3\_USB1\_FAULT\_3P3\_N |
| DSI0\_NC\_LN3\_M\_CONN | 75 | 15 | PME\_GPIO\_4\_USB0\_FAULT\_3P3\_N |
| GND | 76 | 16 | MD\_GPIO\_17\_MDPX3\_1P8 |
| VREG\_L7C\_1P8 | 77 | 17 | MD\_GPIO\_18\_MDPX3\_1P8 |
| GND | 78 | 18 | SGMII0\_MDC\_MDPX3\_1P8 |
| VREG\_MDPX3\_1P8 | 79 | 19 | SGMII0\_MDIO\_MDPX3\_1P8 |
| GND | 80 | 20 | SGMII0\_CONN\_RX\_P |
| IOEXPAN1\_INT\_MDPX3\_1P8\_N | 81 | 21 | SGMII0\_CONN\_RX\_M |
| STR\_WAKE\_MDPX3\_1P8 | 82 | 22 | SGMII0\_CONN\_TX\_P |
| SGMII1\_RX\_P | 83 | 23 | SGMII0\_CONN\_TX\_M |
| SGMII1\_RX\_M | 84 | 24 | SGMII0\_INT\_MDPX3\_1P8\_N |
| SGMII1\_TX\_P | 85 | 25 | SGMII0\_RST\_MDPX3\_1P8\_N |
| SGMII1\_TX\_M | 86 | 26 | MD\_GPIO\_13\_MDPX3\_1P8 |
| SGMII1\_INT\_MDPX3\_1P8\_N | 87 | 27 | MD\_GPIO\_14\_MDPX3\_1P8 |
| SGMII1\_RST\_MDPX3\_1P8\_N | 88 | 28 | MD\_GPIO\_15\_MDPX3\_1P8 |
| SAIL\_ERR0\_SPX3\_1P8 | 89 | 29 | MD\_GPIO\_16\_MDPX3\_1P8 |
| SAIL\_ERR1\_SPX3\_1P8 | 90 | 30 | SAIL\_CAN0\_TX\_SPX3\_1P8 |
| SAIL\_SPI\_MISO\_SPX3\_1P8 | 91 | 31 | SAIL\_CAN0\_RX\_SPX3\_1P8 |
| SAIL\_SPI\_MOSI\_SPX3\_1P8 | 92 | 32 | SAIL\_CAN1\_TX\_SPX3\_1P8 |
| SAIL\_SPI\_SCLK\_SPX3\_1P8 | 93 | 33 | SAIL\_CAN1\_RX\_SPX3\_1P8 |
| SAIL\_SPI\_CS\_0\_SPX3\_1P8 | 94 | 34 | SAIL\_CAN2\_TX\_SPX3\_1P8 |
| SAIL\_SPI\_CS\_1\_SPX3\_1P8 | 95 | 35 | SAIL\_CAN2\_RX\_SPX3\_1P8 |
| SAIL\_GPIO\_15\_SPX3\_1P8 | 96 | 36 | SAIL\_CAN3\_TX\_SPX3\_1P8 |
| SAIL\_GPIO\_16\_SPX3\_1P8 | 97 | 37 | SAIL\_CAN3\_RX\_SPX3\_1P8 |
| SAIL\_GPIO\_17\_SPX3\_1P8 | 98 | 38 | SAIL\_CAN4\_TX\_SPX3\_1P8 |
| SAIL\_GPIO\_18\_SPX3\_1P8 | 99 | 39 | SAIL\_CAN4\_RX\_SPX3\_1P8 |
| SAIL\_PMIC\_INT\_SPX3\_1P8\_N | 100 | 40 | SAIL\_CAN5\_TX\_SPX3\_1P8 |
| SAIL\_INT\_SPX3\_1P8\_N | 101 | 41 | SAIL\_CAN5\_RX\_SPX3\_1P8 |
| SAIL\_PWR\_READY\_SPX3\_1P8 | 102 | 42 | SAIL\_CAN6\_TX\_SPX3\_1P8 |
| SAIL\_SLP\_EN\_SPX3\_1P8 | 103 | 43 | SAIL\_CAN6\_RX\_SPX3\_1P8 |
| SAIL\_DBG\_UART\_TX\_SPX3\_1P8 | 104 | 44 | SAIL\_CAN7\_TX\_SPX3\_1P8 |
| SAIL\_DBG\_UART\_RX\_SPX3\_1P8 | 105 | 45 | SAIL\_CAN7\_RX\_SPX3\_1P8 |
| GND | 106 | 46 | SAIL\_CAN\_INT0\_SPX3\_1P8 |
| PCIE0\_MEZZCONN\_CLK\_P | 107 | 47 | SAIL\_CAN\_INT1\_SPX3\_1P8 |
| PCIE0\_MEZZCONN\_CLK\_N | 108 | 48 | SAIL\_CAN\_STB\_0\_SPX3\_1P8 |
| GND | 109 | 49 | SAIL\_CAN\_STB\_1\_SPX3\_1P8 |
| PCIE0\_MEZZCONN\_RX0\_P | 110 | 50 | SAIL\_CAN\_STB\_2\_SPX3\_1P8 |
| PCIE0\_MEZZCONN\_RX0\_N | 111 | 51 | SAIL\_CAN\_STB\_3\_SPX3\_1P8 |
| GND | 112 | 52 | SAIL\_CAN6\_CTL\_SPX3\_1P8 |
| PCIE0\_MEZZCONN\_RX1\_P | 113 | 53 | SAIL\_CAN7\_CTL\_SPX3\_1P8 |
| PCIE0\_MEZZCONN\_RX1\_N | 114 | 54 | SAIL\_CAN8\_CTL\_SPX3\_1P8 |
| GND | 115 | 55 | PCIE0\_MEZZCONN\_RST\_1P8\_N |
| PCIE0\_MEZZCONN\_TX0\_P | 116 | 56 | PCIE0\_MEZZCONN\_CLKREQ\_1P8\_N |
| PCIE0\_MEZZCONN\_TX0\_N | 117 | 57 | PCIE0\_MEZZCONN\_WAKE\_1P8\_N |
| GND | 118 | 58 | PMG\_GPIO\_3\_GNSS\_RESET\_1P8 |
| PCIE0\_MEZZCONN\_TX1\_P | 119 | 59 | PMG\_GPIO\_4\_GNSS\_EN\_1P8 |
| PCIE0\_MEZZCONN\_TX1\_N | 120 | 60 | PMG\_GPIO\_5\_GNSS\_BOOT\_MODE\_1P8 |
The following table details the pin mapping for the **JEXP2** connector.
Table : Pin mapping for the JEXP2 connector
| Pin name | Pin number | Pin number | Pin name |
| --- | --- | --- | --- |
| VREG\_MDPX3\_1P8 | 61 | 1 | VREG\_SPX3\_1P8 |
| GND | 62 | 2 | GND |
| SOC\_MI2S\_MCLK0\_MDPX3\_1P8 | 63 | 3 | VREG\_SPX8 |
| SOC\_MI2S1\_SCK\_MDPX3\_1P8 | 64 | 4 | GND |
| SOC\_MI2S1\_WS\_MDPX3\_1P8 | 65 | 5 | USB01\_I2C\_SDA\_MDPX3\_1P8 |
| SOC\_MI2S1\_DATA0\_MDPX3\_1P8 | 66 | 6 | USB01\_I2C\_SCL\_MDPX3\_1P8 |
| SOC\_MI2S1\_DATA1\_MDPX3\_1P8 | 67 | 7 | VREG\_1P8\_EN |
| MI2S2\_SCK\_MDPX3\_1P8 | 68 | 8 | VREG\_1P2\_EN |
| MI2S2\_WS\_MDPX3\_1P8 | 69 | 9 | USB\_VBUS\_DET\_MDPX3\_1P8 |
| MI2S2\_DATA0\_MDPX3\_1P8 | 70 | 10 | USB\_RESET\_MDPX3\_1P8\_N |
| MI2S2\_DATA1\_MDPX3\_1P8 | 71 | 11 | USB1\_ID\_MDPX3\_1P8 |
| HS0\_MI2S\_SCK\_CONN | 72 | 12 | USB0\_ID\_MDPX3\_1P8 |
| HS0\_MI2S\_WS\_CONN | 73 | 13 | PMG\_GPIO\_8 |
| HS0\_MI2S\_DATA0\_CONN | 74 | 14 | PME\_GPIO\_7\_SENSOR\_RST\_1P8 |
| HS0\_MI2S\_DATA1\_CONN | 75 | 15 | PME\_GPIO\_6\_USB1\_INT\_3P3\_N |
| HS1\_MI2S\_SCK\_CONN | 76 | 16 | PME\_GPIO\_5\_USB0\_INT\_3P3\_N |
| HS1\_MI2S\_WS\_CONN | 77 | 17 | MD\_GPIO\_70\_MDPX3\_1P8 |
| HS1\_MI2S\_DATA0\_CONN | 78 | 18 | EXP\_I2C\_SDA\_MDPX3\_1P8 |
| HS1\_MI2S\_DATA1\_CONN | 79 | 19 | EXP\_I2C\_SCL\_MDPX3\_1P8 |
| HS2\_MI2S\_SCK\_CONN | 80 | 20 | FAN\_INT\_MDPX3\_1P8\_N |
| HS2\_MI2S\_WS\_CONN | 81 | 21 | HUB\_P2\_USB\_HS\_P |
| HS2\_MI2S\_DATA0\_CONN | 82 | 22 | HUB\_P2\_USB\_HS\_M |
| HS2\_MI2S\_DATA1\_CONN | 83 | 23 | HUB\_P2\_USB\_SS\_RX\_P |
| SOC\_QUA\_MI2S\_SCK\_MDPX3\_1P8 | 84 | 24 | HUB\_P2\_USB\_SS\_RX\_M |
| SOC\_QUA\_MI2S\_WS\_MDPX3\_1P8 | 85 | 25 | HUB\_P2\_USB\_SS\_TX\_P |
| SOC\_QUA\_MI2S\_DATA0\_MDPX3\_1P8 | 86 | 26 | HUB\_P2\_USB\_SS\_TX\_M |
| SOC\_QUA\_MI2S\_DATA1\_MDPX3\_1P8 | 87 | 27 | GND |
| SOC\_QUA\_MI2S\_DATA2\_MDPX3\_1P8 | 88 | 28 | HUB\_P3\_USB\_HS\_M |
| SOC\_QUA\_MI2S\_DATA3\_MDPX3\_1P8 | 89 | 29 | HUB\_P3\_USB\_HS\_P |
| SOC\_I2S1\_SCK\_MDPX3\_1P8 | 90 | 30 | HUB\_P3\_USB\_SS\_TX\_P |
| SOC\_I2S1\_WS\_MDPX3\_1P8 | 91 | 31 | HUB\_P3\_USB\_SS\_TX\_M |
| SOC\_I2S1\_DATA0\_MDPX3\_1P8 | 92 | 32 | HUB\_P3\_USB\_SS\_RX\_P |
| SOC\_I2S1\_DATA1\_MDPX3\_1P8 | 93 | 33 | HUB\_P3\_USB\_SS\_RX\_M |
| I2S2\_CLK\_MDPX3\_1P8 | 94 | 34 | GND |
| I2S2\_WS\_MDPX3\_1P8 | 95 | 35 | HUB\_P4\_USB\_HS\_M |
| I2S2\_DATA0\_MDPX3\_1P8 | 96 | 36 | HUB\_P4\_USB\_HS\_P |
| I2S2\_DATA1\_MDPX3\_1P8 | 97 | 37 | HUB\_P4\_USB\_SS\_TX\_P |
| SOC\_I2S3\_SCK\_MDPX3\_1P8 | 98 | 38 | HUB\_P4\_USB\_SS\_TX\_M |
| SOC\_I2S3\_WS\_MDPX3\_1P8 | 99 | 39 | HUB\_P4\_USB\_SS\_RX\_P |
| SOC\_I2S3\_DATA0\_MDPX3\_1P8 | 100 | 40 | HUB\_P4\_USB\_SS\_RX\_M |
| SOC\_I2S3\_DATA1\_MDPX3\_1P8 | 101 | 41 | GND |
| I2S4\_SCK\_MDPX3\_1P8 | 102 | 42 | SAIL\_RGMII\_RESET\_SPX8\_N |
| I2S4\_WS\_MDPX3\_1P8 | 103 | 43 | SAIL\_RGMII\_INT\_SPX8\_N |
| I2S4\_DATA0\_MDPX3\_1P8 | 104 | 44 | SAIL\_RGMII\_MDIO\_SPX8 |
| I2S4\_DATA1\_MDPX3\_1P8 | 105 | 45 | SAIL\_RGMII\_MDC\_SPX8 |
| SAIL\_CONN\_OSPI0\_CS0\_SPX3\_1P8\_N | 106 | 46 | SAIL\_RGMII\_RX\_CTL\_SPX8 |
| SAIL\_CONN\_OSPI0\_DQS\_SPX3\_1P9 | 107 | 47 | SAIL\_RGMII\_RXC\_SPX8 |
| SAIL\_CONN\_OSPI0\_WR\_SPX3\_1P8\_N | 108 | 48 | SAIL\_RGMII\_RXD0\_SPX8 |
| SAIL\_CONN\_OSPI0\_CLK\_SPX3\_1P9 | 109 | 49 | SAIL\_RGMII\_RXD1\_SPX8 |
| SAIL\_CONN\_OSPI0\_DATA\_0\_SPX3\_1P9 | 110 | 50 | SAIL\_RGMII\_RXD2\_SPX8 |
| SAIL\_CONN\_OSPI0\_DATA\_1\_SPX3\_1P9 | 111 | 51 | SAIL\_RGMII\_RXD3\_SPX8 |
| SAIL\_CONN\_OSPI0\_DATA\_2\_SPX3\_1P9 | 112 | 52 | SAIL\_RGMII\_TX\_CTL\_SPX8 |
| SAIL\_CONN\_OSPI0\_DATA\_3\_SPX3\_1P9 | 113 | 53 | SAIL\_RGMII\_TXC\_SPX8 |
| SAIL\_CONN\_OSPI0\_DATA\_4\_SPX3\_1P9 | 114 | 54 | SAIL\_RGMII\_TXD0\_SPX8 |
| SAIL\_CONN\_OSPI0\_DATA\_5\_SPX3\_1P9 | 115 | 55 | SAIL\_RGMII\_TXD1\_SPX8 |
| SAIL\_CONN\_OSPI0\_DATA\_6\_SPX3\_1P9 | 116 | 56 | SAIL\_RGMII\_TXD2\_SPX8 |
| SAIL\_CONN\_OSPI0\_DATA\_7\_SPX3\_1P9 | 117 | 57 | SAIL\_RGMII\_TXD3\_SPX8 |
| SAIL\_RESOUT\_SPX3\_1P8\_N | 118 | 58 | GND |
| MD\_GPIO\_34\_MDPX3\_1P8 | 119 | 59 | VREG\_5P0 |
| MD\_GPIO\_35\_MDPX3\_1P8 | 120 | 60 | VREG\_5P0 |
The following table details the pin mapping for the **JEXP3** connector.
Table : Pin mapping for the JEXP3 connector
| Pin name | Pin number | Pin number | Pin name |
| --- | --- | --- | --- |
| MD\_GPIO\_52\_MDPX3\_1P8 | 61 | 1 | EDP2\_LN0\_P |
| MD\_GPIO\_53\_MDPX3\_1P8 | 62 | 2 | EDP2\_LN0\_M |
| MD\_GPIO\_54\_MDPX3\_1P8 | 63 | 3 | GND |
| MD\_GPIO\_55\_MDPX3\_1P8 | 64 | 4 | EDP2\_LN1\_P |
| MD\_RESOUT\_MDPX3\_1P8\_N | 65 | 5 | EDP2\_LN1\_M |
| PMC\_GPIO\_7\_WLAN\_EN\_1P8 | 66 | 6 | GND |
| HST\_SW\_CTRL\_MDPX3\_1P8 | 67 | 7 | EDP2\_LN2\_P |
| PMC\_GPIO\_8\_BT\_EN\_1P8 | 68 | 8 | EDP2\_LN2\_M |
| BT0\_UART\_CTS\_MDPX3\_1P8 | 69 | 9 | GND |
| BT0\_UART\_RFR\_MDPX3\_1P8 | 70 | 10 | EDP2\_LN3\_P |
| BT0\_UART\_TX\_MDPX3\_1P8 | 71 | 11 | EDP2\_LN3\_M |
| BT0\_UART\_RX\_MDPX3\_1P8 | 72 | 12 | GND |
| MD\_GPIO\_28\_MDPX3\_1P8 | 73 | 13 | EDP2\_AUX\_P |
| MD\_GPIO\_29\_MDPX3\_1P8
> > > TPM\_SPI\_PIRQ | 74 | 14 | EDP2\_AUX\_M |
| BTLE\_UART\_TX\_MDPX3\_1P8 | 75 | 15 | GND |
| BTLE\_UART\_RX\_MDPX3\_1P8 | 76 | 16 | EDP3\_LN0\_P |
| VREG\_L8C\_UFS1 | 77 | 17 | EDP3\_LN0\_M |
| GND | 78 | 18 | GND |
| DSI1\_A0\_LN0\_P | 79 | 19 | EDP3\_LN1\_P |
| DSI1\_A0\_LN0\_M | 80 | 20 | EDP3\_LN1\_M |
| GND | 81 | 21 | GND |
| DSI1\_C0\_LN1\_P | 82 | 22 | EDP3\_LN2\_P |
| DSI1\_A1\_LN1\_M | 83 | 23 | EDP3\_LN2\_M |
| GND | 84 | 24 | GND |
| DSI1\_B1\_CLK\_P | 85 | 25 | EDP3\_LN3\_P |
| DSI1\_C1\_CLK\_M | 86 | 26 | EDP3\_LN3\_M |
| GND | 87 | 27 | GND |
| DSI1\_A2\_LN2\_P | 88 | 28 | EDP3\_AUX\_P |
| DSI1\_B2\_LN2\_M | 89 | 29 | EDP3\_AUX\_M |
| GND | 90 | 30 | MDP\_VSYNC\_MDPX3\_1P8 |
| DSI1\_C2\_LN3\_P | 91 | 31 | VREG\_5P0\_PGOOD |
| DSI1\_NC\_LN3\_M | 92 | 32 | PG\_VREG\_3P3\_SIP |
| GND | 93 | 33 | EDP2\_HPD\_MDPX3\_1P8 |
| PMC\_GPIO\_4\_IPA\_PWR\_EN\_1P8 | 94 | 34 | EDP3\_HPD\_MDPX3\_1P8 |
| PMC\_GPIO\_5\_WLAN\_PWR\_EN2\_1P8 | 95 | 35 | MD\_GPIO\_78\_MDPX3\_1P8 |
| PMC\_GPIO\_6\_WLAN\_DBU4\_EN\_1P8 | 96 | 36 | DISP\_RST\_MDPX3\_1P8\_N |
| PMC\_GPIO\_11\_WLAN\_EN2\_1P8 | 97 | 37 | DISP\_INT\_MDPX3\_1P8\_N |
| PMC\_GPIO\_12\_BT\_EN2\_1P8 | 98 | 38 | MD\_GPIO\_76\_MDPX3\_1P8 |
| MD\_GPIO\_79\_MDPX3\_1P8 | 99 | 39 | LCD\_RESET\_MDPX3\_1P8 |
| SENSOR\_I2C\_SDA\_MDPX3\_1P8 | 100 | 40 | MD\_GPIO\_40\_MDPX3\_1P8 |
| SENSOR\_I2C\_SCL\_MDPX3\_1P8 | 101 | 41 | MD\_GPIO\_41\_MDPX3\_1P8 |
| MD\_GPIO\_84\_MDPX3\_1P8 | 102 | 42 | MD\_GPIO\_42\_MDPX3\_1P8 |
| MD\_GPIO\_85\_MDPX3\_1P8 | 103 | 43 | MD\_GPIO\_43\_MDPX3\_1P8 |
| MD\_GPIO\_86\_MDPX3\_1P8 | 104 | 44 | MD\_GPIO\_44\_MDPX3\_1P8 |
| MD\_GPIO\_87\_MDPX3\_1P8 | 105 | 45 | MD\_GPIO\_45\_MDPX3\_1P8 |
| MD\_GPIO\_88\_MDPX3\_1P8 | 106 | 46 | PMS\_GPIO\_4\_USB0\_VBUS\_ON |
| MD\_GPIO\_89\_MDPX3\_1P8 | 107 | 47 | MD\_GPIO\_10\_MDPX3\_1P8 |
| MD\_GPIO\_90\_MDPX3\_1P8 | 108 | 48 | SENSOR\_SLP\_CLK\_MDPX3\_1P8 |
| MD\_GPIO\_140\_MDPX3\_1P8 | 109 | 49 | DISP\_I2C\_SDA\_MDPX3\_1P8 |
| MD\_GPIO\_77\_MDPX3\_1P8 | 110 | 50 | DISP\_I2C\_SCL\_MDPX3\_1P8 |
| MD\_DBG\_UART\_TX\_MDPX3\_1P8 | 111 | 51 | MD\_GPIO\_20\_MDPX3\_1P8 |
| MD\_DBG\_UART\_RX\_MDPX3\_1P8 | 112 | 52 | MD\_GPIO\_21\_MDPX3\_1P8 |
| MD\_GPIO\_56\_MDPX3\_1P8 | 113 | 53 | MD\_GPIO\_22\_MDPX3\_1P8 |
| MD\_GPIO\_57\_MDPX3\_1P8 | 114 | 54 | MD\_GPIO\_23\_MDPX3\_1P8 |
| PMA\_GPIO\_02\_POFF\_COMPLETE\_3P3\_N | 115 | 55 | MD\_GPIO\_36\_MDPX3\_1P8 |
| PMA\_GPIO\_06\_AOSS\_SLP\_ENT\_3P3 | 116 | 56 | MD\_GPIO\_37\_MDPX3\_1P8 |
| VREG\_S5A\_WLAN\_BT\_1P95 | 117 | 57 | MD\_GPIO\_38\_MDPX3\_1P8 |
| VREG\_L2C\_WLAN\_BT\_1P05 | 118 | 58 | IOEXPAN3\_INT\_MDPX3\_1P8\_N |
| VREG\_L6E\_WLAN\_BT\_1P35 | 119 | 59 | MD\_GPIO\_71\_MDPX3\_1P8 |
| PMS\_GPIO\_8\_USB1\_VBUS\_ON | 120 | 60 | MD\_GPIO\_69\_MDPX3\_1P8 |
The following table details the pin mapping for the **JEXP4** connector.
Table : Pin mapping for the JEXP4 connector
| Pin name | Pin number | Pin number | Pin name |
| --- | --- | --- | --- |
| SDIO\_EMMC\_CMD\_MDPX7\_1P8 | 61 | 1 | PCIE2USB\_PWR\_EN\_1P8 |
| SDIO\_EMMC\_CLK\_MDPX7\_1P8 | 62 | 2 | PCIE1\_MEZZCONN\_CLK\_N |
| SDIO\_EMMC\_RCLK\_MDPX7\_1P8 | 63 | 3 | PCIE1\_MEZZCONN\_CLK\_P |
| SDIO\_EMMC\_DATA\_7\_MDPX7\_1P8 | 64 | 4 | GND |
| SDIO\_EMMC\_DATA\_6\_MDPX7\_1P8 | 65 | 5 | PCIE1\_MEZZCONN\_RX0\_N |
| SDIO\_EMMC\_DATA\_5\_MDPX7\_1P8 | 66 | 6 | PCIE1\_MEZZCONN\_RX0\_P |
| SDIO\_EMMC\_DATA\_4\_MDPX7\_1P8 | 67 | 7 | GND |
| SDIO\_EMMC\_DATA\_3\_MDPX7\_1P8 | 68 | 8 | PCIE1\_MEZZCONN\_RX1\_N |
| SDIO\_EMMC\_DATA\_2\_MDPX7\_1P8 | 69 | 9 | PCIE1\_MEZZCONN\_RX1\_P |
| SDIO\_EMMC\_DATA\_1\_MDPX7\_1P8 | 70 | 10 | GND |
| SDIO\_EMMC\_DATA\_0\_MDPX7\_1P8 | 71 | 11 | PCIE1\_MEZZCONN\_RX2\_N |
| MD\_GPIO\_68\_MDPX3\_1P8 | 72 | 12 | PCIE1\_MEZZCONN\_RX2\_P |
| PCIE\_SWITCH\_PWR\_EN\_1P8 | 73 | 13 | GND |
| PCIE2USB\_RST\_MDPX3\_1P8\_N | 74 | 14 | PCIE1\_MEZZCONN\_RX3\_N |
| PCIE1\_MEZZCONN\_RST\_1P8\_N | 75 | 15 | PCIE1\_MEZZCONN\_RX3\_P |
| PCIE1\_MEZZCONN\_CLKREQ\_1P8\_N | 76 | 16 | GND |
| PCIE1\_MEZZCONN\_WAKE\_1P8\_N | 77 | 17 | PCIE1\_MEZZCONN\_TX0\_N |
| CAM3\_PWR\_EN\_MDPX3\_1P8 | 78 | 18 | PCIE1\_MEZZCONN\_TX0\_P |
| PME\_GPIO\_11\_USB2\_ID | 79 | 19 | GND |
| CCI6\_I2C\_SDA\_MDPX3\_1P8 | 80 | 20 | PCIE1\_MEZZCONN\_TX1\_N |
| CCI6\_I2C\_SCL\_MDPX3\_1P8 | 81 | 21 | PCIE1\_MEZZCONN\_TX1\_P |
| CAM3\_MCLK\_MDPX3\_1P8 | 82 | 22 | GND |
| CAM3\_PWDN\_MDPX3\_1P8 | 83 | 23 | PCIE1\_MEZZCONN\_TX2\_N |
| CAM3\_STROBE\_MDPX3\_1P8 | 84 | 24 | PCIE1\_MEZZCONN\_TX2\_P |
| CAM3\_SPARE\_GPIO\_MDPX3\_1P8 | 85 | 25 | GND |
| CAM2\_PWR\_EN\_MDPX3\_1P8 | 86 | 26 | PCIE1\_MEZZCONN\_TX3\_N |
| PME\_GPIO\_10\_USB1\_PWR\_EN\_1P8 | 87 | 27 | PCIE1\_MEZZCONN\_TX3\_P |
| CCI4\_I2C\_SDA\_MDPX3\_1P8 | 88 | 28 | GND |
| CCI4\_I2C\_SCL\_MDPX3\_1P8 | 89 | 29 | CSI3\_CONN\_NC\_CLK\_P |
| CAM2\_MCLK\_MDPX3\_1P8 | 90 | 30 | CSI3\_CONN\_A0\_CLK\_M |
| CAM2\_PWDN\_MDPX3\_1P8 | 91 | 31 | CSI3\_CONN\_B0\_LN0\_P |
| CAM2\_STROBE\_MDPX3\_1P8 | 92 | 32 | CSI3\_CONN\_C0\_LN0\_M |
| CAM2\_SPARE\_GPIO\_MDPX3\_1P8 | 93 | 33 | CSI3\_CONN\_A1\_LN1\_P |
| CAM1\_PWR\_EN\_MDPX3\_1P8 | 94 | 34 | CSI3\_CONN\_B1\_LN1\_M |
| MD\_GPIO\_12\_MDPX3\_1P8 | 95 | 35 | CSI3\_CONN\_C1\_LN2\_P |
| CCI2\_I2C\_SDA\_MDPX3\_1P8 | 96 | 36 | CSI3\_CONN\_A2\_LN2\_M |
| CCI2\_I2C\_SCL\_MDPX3\_1P8 | 97 | 37 | CSI3\_CONN\_B2\_LN3\_P |
| CAM1\_MCLK\_MDPX3\_1P8 | 98 | 38 | CSI3\_CONN\_C2\_LN3\_M |
| CAM1\_PWDN\_MDPX3\_1P8 | 99 | 39 | GND |
| CAM1\_STROBE\_MDPX3\_1P8 | 100 | 40 | CSI2\_CONN\_NC\_CLK\_P |
| CAM1\_SPARE\_GPIO\_MDPX3\_1P8 | 101 | 41 | CSI2\_CONN\_A0\_CLK\_M |
| CAM0\_PWR\_EN\_MDPX3\_1P8 | 102 | 42 | CSI2\_CONN\_B0\_LN0\_P |
| MD\_GPIO\_11\_MDPX3\_1P8 | 103 | 43 | CSI2\_CONN\_C0\_LN0\_M |
| CCI0\_I2C\_SDA\_MDPX3\_1P8 | 104 | 44 | CSI2\_CONN\_A1\_LN1\_P |
| CCI0\_I2C\_SCL\_MDPX3\_1P8 | 105 | 45 | CSI2\_CONN\_B1\_LN1\_M |
| CAM0\_MCLK\_MDPX3\_1P8 | 106 | 46 | CSI2\_CONN\_C1\_LN2\_P |
| CAM0\_PWDN\_MDPX3\_1P8 | 107 | 47 | CSI2\_CONN\_A2\_LN2\_M |
| CAM0\_STROBE\_MDPX3\_1P8 | 108 | 48 | CSI2\_CONN\_B2\_LN3\_P |
| CAM0\_SPARE\_GPIO\_MDPX3\_1P8 | 109 | 49 | CSI2\_CONN\_C2\_LN3\_M |
| GND | 110 | 50 | GND |
| CSI0\_CONN\_NC\_CLK\_P | 111 | 51 | CSI1\_CONN\_NC\_CLK\_P |
| CSI0\_CONN\_A0\_CLK\_M | 112 | 52 | CSI1\_CONN\_A0\_CLK\_M |
| CSI0\_CONN\_B0\_LN0\_P | 113 | 53 | CSI1\_CONN\_B0\_LN0\_P |
| CSI0\_CONN\_C0\_LN0\_M | 114 | 54 | CSI1\_CONN\_C0\_LN0\_M |
| CSI0\_CONN\_A1\_LN1\_P | 115 | 55 | CSI1\_CONN\_A1\_LN1\_P |
| CSI0\_CONN\_B1\_LN1\_M | 116 | 56 | CSI1\_CONN\_B1\_LN1\_M |
| CSI0\_CONN\_C1\_LN2\_P | 117 | 57 | CSI1\_CONN\_C1\_LN2\_P |
| CSI0\_CONN\_A2\_LN2\_M | 118 | 58 | CSI1\_CONN\_A2\_LN2\_M |
| CSI0\_CONN\_B2\_LN3\_P | 119 | 59 | CSI1\_CONN\_B2\_LN3\_P |
| CSI0\_CONN\_C2\_LN3\_M | 120 | 60 | CSI1\_CONN\_C2\_LN3\_M |
### Low speed header
In the Dragonwing IQ-9075, there’s one low speed connector (JLS1, 87381-4063) that provides access to various GPIOs, CAN, QUPs, and other interfaces. The position of this connector is shown in [Connector overview of Dragonwing IQ-9075 EVK](https://docs.qualcomm.com/doc/80-90441-253/topic/hw-overview.html#fig-jmq-qqy-w2c).
The following table details the pin mapping for the **JLS1** connector
Table : Pin mapping for the JLS1 connector
| Pin name | Pin number | Pin number | Pin name |
| --- | --- | --- | --- |
| GND | 1 | 2 | GND |
| MD\_GPIO\_52\_3P3 (UART CTS) | 3 | 4 | CAN\_H |
| MD\_GPIO\_54\_3P3 (UART TX) | 5 | 6 | CAN\_L |
| MD\_GPIO\_55\_3P3 (UART RX) | 7 | 8 | MD\_GPIO\_32\_3P3 (SPI MISO) |
| MD\_GPIO\_53\_3P3 (UART RFR) | 9 | 10 | MD\_GPIO\_33\_3P3 (SPI MOSI) |
| MD\_GPIO\_44\_3P3 (UART TX) | 11 | 12 | MD\_GPIO\_34\_3P3 (SPI CLK) |
| MD\_GPIO\_45\_3P3 (UART RX) | 13 | 14 | MD\_GPIO\_35\_3P3 (SPI CS) |
| EXP\_I2C\_SCL\_3P3 (GPIO 95) | 15 | 16 | SOC\_MI2S1\_WS\_3P3 |
| EXP\_I2C\_SDA\_3P3 (GPIO 96) | 17 | 18 | SOC\_MI2S1\_SCK\_3P3 |
| SENSOR\_I2C\_SCL\_3P3 | 19 | 20 | SOC\_MI2S1\_DATA1\_3P3 |
| SENSOR\_I2C\_SDA\_3P3 | 21 | 22 | SOC\_MI2S1\_DATA0\_3P3 |
| MD\_GPIO\_40\_3P3 (UART CTS) | 23 | 24 | SOC\_MI2S\_MCLK0\_3P3 |
| MD\_GPIO\_41\_3P3 (UART RFR) | 25 | 26 | MD\_GPIO\_43\_3P3 (UART RX) |
| MD\_GPIO\_42\_3P3 (UART TX) | 27 | 28 | SAIL\_GP1\_CLK\_A\_3P3 |
| PME\_GPIO\_11\_USB2\_ID | 29 | 30 | SAIL\_GP3\_CLK\_A\_3P3 |
| MD\_GPIO\_140\_3P3 | 31 | 32 | SAIL\_GP4\_CLK\_A\_3P3 |
| IOEXPAN3\_GPIO\_7\_3P3 | 33 | 34 | SAIL\_GP5\_CLK\_A\_3P3 |
| VREG\_3P3\_SIP | 35 | 36 | VREG\_SYSTEM\_PWR |
| VREG\_5P0 | 37 | 38 | VREG\_SYSTEM\_PWR |
| GND | 39 | 40 | GND |
### Debug interface
The Dragonwing IQ-9075 EVK includes a micro-USB connector receptacle (JTAC, part number: 0475890001) connected to an FTDI chip (U19, part number: FT4232HL-REEL), which is used for debugging purposes.
For the precise location of the debug interface connector on the Dragonwing IQ-9075 EVK, see [Connector overview of Dragonwing IQ-9075 EVK](https://docs.qualcomm.com/doc/80-90441-253/topic/hw-overview.html#fig-jmq-qqy-w2c).
### JTAG interface
The JTAG connector header on the board is a 20-position male interconnect with a 0.050” (1.27 mm) pitch and 0.050” (1.27 mm) row spacing. The reference designator for the JTAG connector component is “JTAG,” and its part number is FTSH-110-01-L-D-RA-K. To use a traditional JTAG connector, an adapter such as the 65-PM339-1 may be required.
For the precise location of the JTAG connectors on the Dragonwing IQ-9075 EVK, see [Connector overview of Dragonwing IQ-9075 EVK](https://docs.qualcomm.com/doc/80-90441-253/topic/hw-overview.html#fig-jmq-qqy-w2c).
### Audio support
For speaker and audio support on the board, the HS0\_MI2S interface is used for the two onboard audio amplifiers, while the HS2\_MI2S interface is used for the I^2^S microphone on the mainboard. Both interfaces can optionally be switched to the mezzanine connectors for expansion purposes.
The following block diagram shows the audio connections.
**Figure : Audio connections**
Consider the following details about speakers and microphones on the IQ-9075 EVK:
- **Speakers:** Onboard speakers (with MAX98357 I^2^S-amps): HS0\_MI2S is shared for both left and right speakers to be stereo.
- **Microphones:** The EVK includes a single onboard microphone (MMICT5848) that utilizes the HS2\_MI2S interface. By default, the microphone is configured to the right side. To switch the microphone to the left side, there are rework instructions available that involve moving one resistor.
The following figure shows the Dragonwing IQ-9075 EVK connected to two mini speakers.
**Dragonwing IQ-9075 EVK connected to two mini speakers**
### Thermal management and fan control
The Dragonwing IQ-9075 EVK can consume up to 70 W, so it requires an effective thermal solution. The default cooling solution is fan-based, utilizing a CPU cooler mounted to the bottom of the IQ-9075 EVK. The following figures show the thermal management solutions implemented in the Dragonwing IQ-9075 EVK. The fan controller used on this board is a Texas Instruments AMC6821SQDBQRQ1 PWM fan controller IC. The fan used in the system is connected using JFAN connector (S6B-XH-SM4-TB(LF)(SN)) on the mainboard.
Future versions of the IQ-9075 EVK may offer different thermal options, including smaller fans or heatsinks, depending on the expected use cases.
**Figure : Thermal management on Dragonwing IQ-9075 EVK**
### Accessory boards
This information will be provided in a future revision of the document.
Last Published: Feb 20, 2026
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Source: [https://docs.qualcomm.com/doc/80-90441-253/topic/hw-overview.html](https://docs.qualcomm.com/doc/80-90441-253/topic/hw-overview.html)