# Data processing
The Hexagon processor provides operations for
processing scalar and vector data. Instructions operate
on fixed-point or floating-point data. The
fixed-point operations support scalar and vector data in a range of
sizes. The floating-point operations support single-precision data.
This chapter presents an overview of the operations provided by the
following Hexagon processor instruction classes:
- XTYPE - General-purpose data operations
- ALU32 - Arithmetic/logical operations on 32-bit data
## Data types
The Hexagon processor provides operations for processing the
following data types.
### Fixed-point data
The Hexagon processor provides operations to process 8-, 16-, 32-, or
64-bit fixed-point data. The data is either integer or fractional,
and in signed or unsigned format.
#### Scalar operations
The Hexagon processor includes the following scalar operations on
fixed-point data:
- Multiplication of 16-bit, 32-bit, and complex data
- Addition and subtraction of 16-, 32-, and 64-bit data (with and
without saturation)
- Logical operations on 32-bit and 64-bit data (AND, OR, XOR, NOT)
- Shifts on 32-bit and 64-bit data (arithmetic and logical)
- Min/max, negation, absolute value, parity, norm, swizzle
- Compares of 8-, 16-, 32-, and 64-bit data
- Sign and zero extension (8- and 16-bit to 32-bit, 32-bit to 64-bit)
- Bit manipulation
- Predicate operations
#### Vector operations
The Hexagon processor includes the following vector operations on
fixed-point data:
- Multiplication (halfwords, word by half, vector reduce, dual
multiply)
- Addition and subtraction of word and halfword data
- Shifts on word and halfword data (arithmetic and logical)
- Min/max, average, negative average, absolute difference, absolute
value
- Compares of word, halfword, and byte data
- Reduce, sum of absolute differences on unsigned bytes
- Special-purpose data arrangement (such as pack, splat, shuffle,
align, saturate, splice, truncate, complex conjugate, complex rotate,
zero extend)
Note
Certain vector operations support automatic scaling,
saturation, and rounding.
For example, the following instruction performs a vector operation:
R1:0 += vrmpyh(R3:2,R5:4)
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It is defined to perform the following operations in one cycle:
R1:0 += ((R2.L * R4.L) + (R2.H * R4.H) + (R3.L * R5.L) + (R3.H * R5.H))
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[Vector instruction example](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#v79-vector-instruction-example) shows a schematic of this instruction type.
**Vector instruction example**
### Floating-point data
The Hexagon processor provides operations to process 32-bit
floating-point numbers. The numbers are stored in IEEE
single-precision floating-point format.
Per the IEEE standard, certain floating-point values are defined to
represent positive or negative infinity, as well as Not-a-Number
(NaN), which represents values that have no mathematical meaning.
Floating-point numbers can be held in a general register.
The Hexagon processor includes the following operations on
floating-point data:
- Addition and subtraction
- Multiplication (with optional scaling)
- Min/max/compare
- Reciprocal/square root approximation
- Format conversion
### Complex data
The Hexagon processor provides operations to process 32-bit or 64-bit
complex data.
Complex numbers include a signed real portion and a signed imaginary
portion. Given two complex numbers (a + bi) and (c + di), the complex
multiply operations compute both the real portion (ac - bd) and the
imaginary portion (ad + bc) in a single instruction.
Complex numbers can be packed in a general register or register pair.
When packed, the imaginary portion occupies the most-significant
portion of the register or register pair.
### Vector data
The Hexagon processor provides operations to process 64-bit vector
data.
Vector data types pack multiple data items—bytes, halfwords, or
words—into 64-bit registers.
Eight 8-bit bytes can be packed into a 64-bit register.
**Vector byte operation example**
Four 16-bit halfword values can be packed in a single 64-bit register
pair.
**Vector halfword operation example**
Two 32-bit word values can be packed in a single 64-bit register
pair.
**Vector word operation example**
## Instruction options
Some instructions support optional scaling, saturation, and rounding.
There are no mode bits controlling these options - instead, the
instruction syntax explicitly specifies the options.
### Fractional scaling
In fractional data format, word length and radix point position
determine the range of the fixed-point fractional values.
The `:<<1` specifies fractional scaling. For example:
R3:2 = cmpy(R0,R1):<<1:sat
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When two fractional numbers are multiplied, the product must be
scaled to restore the original fractional data format. The Hexagon
processor allows specification of the fractional scaling of the
product in the instruction for shifts of 0 and 1. Perform a shift of
1 for Q1.15 numbers. Perform a shift of 0 for integer multiplication.
### Saturation
Certain instructions are available in saturating form. If a
saturating arithmetic instruction has a result that is smaller than
the minimum value, the result is set to the minimum value. Similarly,
if the operation has a result that is greater than the maximum value,
the result is set to the maximum value.
Saturation is specified in an instruction by adding the `:sat`
option. For example:
R2 = abs(R1):sat
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When a saturating operation saturates to the maximum or minimum value,
hardware sets the overflow (OVF) bit in the [user status register](https://docs.qualcomm.com/doc/80-N2040-60/topic/registers.html#v79-prm-user-status-register).
It remains set until explicitly cleared by a control register transfer to USR. For
vector-type saturating operations, saturation for any individual elements of the vector
sets USR.OVF.
### Arithmetic rounding
Certain signed multiply instructions support optional arithmetic
rounding also known as biased rounding. The arithmetic rounding
operation takes a double precision fractional value and adds 0x8000
to the low 16 bits.
The `:rnd` option specifies rounding. For example:
R2 = mpy(R1.h,R2.h):rnd
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Note
Arithmetic rounding can accumulate numerical errors,
especially when the number to round is exactly 0.5. This occurs most
frequently when dividing by two or averaging.
### Convergent rounding
To address the problem of error accumulation in convergent rounding, the
Hexagon processor includes four instructions that support positive and
negative averaging with a convergent rounding option. The `:crnd` option
specifies roudning. For example:
R3:2 = vnavgh(R1:0,R5:4):crnd:sat
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Convergent rounding computes (A + B) or (A - B) for the signed average
and negative average respectively. If the two least significant bits
after the addition/subtraction are 11, a rounding constant of 1 is added,
otherwise a 0 is added. The result is then shifted right by one bit.
Convergent rounding accumulates less error than arithmetic rounding.
### Scaling for divide and square-root
On the Hexagon processor, floating point divide and square-root
operations are implemented in software using library functions. To
enable the efficient implementation of these operations, the
processor supports special variants of the multiply-accumulate
instruction, named scale fused multiply add (FMA).
Scale FMA supports optional scaling of the product generated by the
floating-point fused multiply-add instruction.
The `:scale` option and a predicate register operand specifies scaling.
For example:
R3 += sfmpy(R0,R1,P2):scale
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For single precision, the scaling factor is two raised to the power
specified by the contents of the predicate register (which is treated
as an 8-bit two’s complement value). For double precision, the
predicate register value is doubled before use as a power of two.
Note
Do not use scale FMA instructions outside of divide and
square-root library routines. No guarantee is provided that future
versions of the Hexagon processor implements these instructions using
the same semantics. Future versions assume only that compatibility
for scale FMA is limited to the needs of divide and square-root
library routines.
## XTYPE operations
The XTYPE instruction class includes most of the data-processing
operations performed by the Hexagon processor. These operations are
categorized by their operation type.
### ALU
[XTYPE ALU](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#xtype-alu) operations modify 8-, 16-, 32-, and 64-bit
data. These operations include:
- Add and subtract with and without saturation
- Add and subtract with accumulate
- Absolute value
- Logical operations
- Min, max, negate instructions
- Register transfers of 64-bit data
- Word to doubleword sign extension
- Comparisons
### Bit manipulation
[XTYPE bit](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#xtype-bit) manipulation operations modify bit fields
in a register or register pair. These operations include:
- Bit field insert
- Bit field signed and unsigned extract
- Count leading and trailing bits
- Compare bitmasks
- Set/clear/toggle bit
- Test bit operation
- Interleave/deinterleave bits
- Bit reverse
- Split bit field
- Masked parity and linear feedback shift
- Table index formation
### Complex
[XTYPE complex](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#xtype-complex) operations manipulate complex
numbers. These operations include:
- Complex add and subtract
- Complex multiply with optional round and pack
- Vector complex multiply
- Vector complex conjugate
- Vector complex rotate
- Vector reduce complex multiply real or imaginary
### Floating point
[XTYPE FP](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#xtype-fp) operations manipulate single-precision
floating point numbers. These operations include:
- Addition and subtraction
- Multiplication (with optional scaling)
- Min/max/compare
- Format conversion
The Hexagon floating-point operations are defined to support the IEEE
floating-point standard. However, certain IEEE-required operations,
such as divide and square root, are not supported directly. Instead,
special instructions are defined to support the implementation of the
required operations as library routines. These instructions include:
- A special version of the fused multiply-add instruction designed
specifically for use in library routines.
- Reciprocal/square root approximations which compute the approximate
initial values used in reciprocal and reciprocal-square-root
routines.
- Extreme value assistance which adjusts input values if they cannot
produce correct results using convergence algorithms.
Note
The special floating-point instructions are not intended
for use directly in user code; use the special floating-point
instructions only in the floating point library.
#### Format conversion
The floating-point conversion instructions sfmake and dfmake convert
an unsigned 10-bit immediate value into the corresponding
floating-point value.
The immediate value must be encoded so that bits [5:0] contain the
significand, and bits [9:6] contain the exponent. The exponent value is added
to the initial exponent value (bias - 6).
For example, to generate the single-precision floating point value
2.0, bits [5:0] must be set to 0, and bits [9:6] set to 7. Performing
the sfmake operation on this immediate value yields the floating
point value 0x40000000, which is 2.0.
Note
The conversion instructions are designed to handle common
floating point values, including most integers and many basic
fractions (1/2, 3/4, and so on).
#### Rounding
The Hexagon [User status register](https://docs.qualcomm.com/doc/80-N2040-60/topic/registers.html#v79-prm-user-status-register) includes
the FPRND field, which specifies the IEEE-defined floating-point
rounding mode.
#### Exceptions
The Hexagon user status register includes five status fields, which
work as sticky flags for the five IEEE-defined exception conditions:
inexact, overflow, underflow, divide by zero, and invalid. A sticky
flag is set when the corresponding exception occurs, and remains set
until explicitly cleared.
The user status register also includes five mode fields that enable
or disable the floating-point exceptions. For every instruction packet
containing a floating-point operation, if a floating-point sticky
flag and the corresponding exception-enable bit are both set, a
floating-point exception is generated. After the packet commits, the
Hexagon processor takes the exception.
Note
Non-floating-point instructions never generate a
floating-point exception, regardless of the state of the sticky flag and
exception -enable bits.
### Multiply
Multiply operations support fixed-point multiplication, including
both single- and double- precision multiplication, and polynomial
multiplication.
#### Single precision
In single-precision arithmetic, a 16-bit value is multiplied by
another 16-bit value. These operands can come from the high portion
or low portion of any register. Depending on the instruction, the
result of the 16 x 16 operation can optionally be accumulated,
saturated, rounded, or shifted left by 0 bits to 1 bits.
The instruction set supports operations on any combination of signed
and unsigned data.
[Single-precision multiply options](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#v79-tbl-single-precision-multiply-options) summarizes the options available for 16
x 16 single precision multiplications. The symbols used in the table
are as follows:
- SS: Perform signed x signed multiply
- UU: Perform unsigned x unsigned multiply
- SU: Perform signed x unsigned multiply
- A+: Result added to accumulator
- A-: Result subtracted from accumulator
- 0: Result not added to accumulator
Single-precision multiply options
| **Multiply** | **Result** | **Sign** | **Accumulate** | **Sat** | **Rnd** | **Scale** |
| --- | --- | --- | --- | --- | --- | --- |
| 16 x 16 | 32 | SS | A+, A- | Yes | No | 0-1 |
| 16 x 16 | 32 | SS | 0 | Yes | Yes | 0-1 |
| 16 x 16 | 64 | SS | A+, A- | No | No | 0-1 |
| 16 x 16 | 64 | SS | 0 | No | Yes | 0-1 |
| 16 x 16 | 32 | UU | A+, A-, 0 | No | No | 0-1 |
| 16 x 16 | 64 | UU | A+, A-, 0 | No | No | 0-1 |
| 16 x 16 | 32 | SU | A+, 0 | Yes | No | 0-1 |
#### Double precision
Double precision instructions are available for both 32 x 32 and 32 x
16 multiplication:
- For 32 x 32 multiplication the result is either 64 bits or 32 bits.
The 32-bit result is either the high or low portion of the 64-bit
product.
- For 32 x 16 multiplication the result is always taken as the upper 32
bits. The operands are either signed or unsigned.
Double precision multiply options
| **Multiply** | **Result** | **Sign** | **Accumulate** | **Sat** | **Rnd** | **Scale** |
| --- | --- | --- | --- | --- | --- | --- |
| 32 x 32 | 64 | SS, UU | A+, A-, 0 | No | No | 0 |
| 32 x 32 | 32 (upper) | SS, UU | 0 | No | Yes | 0 |
| 32 x 32 | 32 (low) | SS, UU | A+, 0 | No | No | 0 |
| 32 x 16 | 32 (upper) | SS, UU | A+, 0 | Yes | Yes | 0-1 |
| 32 x 32 | 32 (upper) | SU | 0 | No | No | 0 |
#### Polynomial
Polynomial [XTYPE MPY](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#xtype-mpy) instructions are available for
both words and vector halfwords.
These instructions are useful for many algorithms including scramble
code generation, cryptographic algorithms, convolutional, and Reed
Solomon code.
### Permute
[XTYPE perm](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#xtype-perm) operations perform operations on vector
data that includes arithmetic, format conversion, and rearrangement
of vector elements. The following types of conversions are supported:
- Swizzle bytes
- Vector shuffle
- Vector align
- Vector saturate and pack
- Vector splat bytes
- Vector splice
- Vector sign extend halfwords
- Vector zero extend bytes
- Vector zero extend halfwords
- Scalar saturate to byte, halfword, word
- Vector pack high and low halfwords
- Vector round and pack
- Vector splat halfwords
### Predicate
[XTYPE PRED](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#xtype-pred) operations modify predicate source data.
Available categories of instructions include:
- Vector mask generation
- Predicate transfers
- Viterbi packing
### Shift
Scalar [XTYPE SHIFT](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#xtype-shift) operations perform 32 and
64-bit shifts followed by an optional addition/subtraction or logical
operation. 64-bit shift and add/sub/logical <v79-fig-64-bit-shift-and-add-sub-logical> shows the general
operation.
**64-bit shift and add/sub/logical**
Four shift types are supported:
- ASR: Arithmetic shift right
- ASL: Arithmetic shift left
- LSR: Logical shift right
- LSL: Logical shift left
When arithmetic right shifts are performed, the sign bit is shifted
in, whereas logical right shifts shift in zeros. Left shifts always
shift in zeros.
In register-based shifts, the Rt[6:0] register holds the number of bits
to shift and is a signed two’s complement number. If this value is positive,
the instruction opcode tells the direction of shift (right or left).
If this value is negative, the shift direction indicated by the opcode is reversed.
Some shifts are available with saturation and rounding options.
## ALU32 operations
The [ALU32](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#alu32) instruction class includes general
arithmetic/logical operations on 32-bit data:
- Add, subtract, negate without saturation on 32-bit data
- Logical operations such as AND, OR, XOR, AND with immediate, and OR
with immediate
- Scalar 32-bit compares
- Combine halfwords, combine words, combine with immediates, shift
halfwords, and Mux
- Conditional add, combine, logical, subtract, and transfer.
- NOP
- Sign and zero-extend bytes and halfwords
- Transfer immediates and registers
- Vector add, subtract, and average halfwords
Note
ALU32 instructions can execute on any slot
([resource constraints](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#v79-prm-resource-constraints)).
[Conditional execution](https://docs.qualcomm.com/doc/80-N2040-60/topic/conditional-execution.html) describes the conditional execution and
compare instructions.
## Vector operations
Vector operations support arithmetic operations on vectors of bytes,
halfwords, and words.
The vector operations belong to the XTYPE instruction class (except
for vector add, subtract, and average halfwords, which are ALU32).
### Vector byte operations
The vector byte operations process packed vectors of signed or
unsigned bytes. They include the following operations:
- Vector add and subtract signed or unsigned bytes
- Vector min and max signed or unsigned bytes
- Vector compare signed or unsigned bytes
- Vector average unsigned bytes
- Vector reduce add unsigned bytes
- Vector sum of absolute differences unsigned bytes
### Vector halfword operations
The vector halfword operations process packed 16-bit halfwords. They
include the following operations:
- Vector add and subtract halfwords
- Vector average halfwords
- Vector compare halfwords
- Vector min and max halfwords
- Vector shift halfwords
- Vector dual multiply
- Vector dual multiply with round and pack
- Vector multiply even halfwords with an optional round and pack
- Vector multiply halfwords
- Vector reduce multiply halfwords
For example, [vector halfword shift right](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#v79-fig-vector-halfword-shift-right)
shows the operation of the vector arithmetic shift right halfword (vasrh)
instruction. In this instruction, each 16-bit half-word shifts right
by the amount specified in a register or an immediate
value. Because the shift is arithmetic, the bits shifted in are copies of
the sign bit.
### Vector word operations
The vector word operations process packed vectors of two words. They
include the following operations:
- Vector add and subtract words
- Vector average words
- Vector compare words
- Vector min and max words
- Vector shift words with optional truncate and pack
For more information on vector operations, see
[ALU32](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#alu32-alu) and
[XTYPE ALU](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#xtype-alu).
## CR operations
The [CR](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#cr) instruction class includes operations that access
the [control registers](https://docs.qualcomm.com/doc/80-N2040-60/topic/registers.html#v79-prm-control-registers).
Control register transfer instructions
| **Syntax** | **Operation** |
| --- | --- |
| Rd = Cs Cd = Rs | Move control register to / from a general register. |
| Rdd = Css Cdd = Rss | Move control register pair to / from a general register pair. |
Note
In register-pair transfers, control registers must be
specified using their numeric alias names - see
[control registers](https://docs.qualcomm.com/doc/80-N2040-60/topic/registers.html#v79-prm-control-registers) for details.
Note
PC is not a valid destination register.
## Compound operations
The instruction set includes a number of instructions that perform
multiple logical or arithmetic operations in a single instruction.
They include the following operations:
- AND/OR with inverted input
- Compound logical register
- Compound logical predicate
- Compound add-subtract with immediates
- Compound shift-operation with immediates (arithmetic or logical)
- Multiply-add with immediates
For example:
Rd=add(Rs,add(Ru,#s6))
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For more information, see [XTYPE ALU](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#xtype-alu).
## Special operations
The instruction set includes a number of special-purpose instructions
to support specific applications.
### IP Internet checksum
Key features of the Internet checksum[\[1\]](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#dpf1) include:
- The checksum can be summed in any order
- Carries can be accumulated using an accumulator larger than size
being added, and added back in at any time
Using standard data-processing instructions, the Internet checksum
can be computed at eight bytes per cycle in the main loop, by loading
words and accumulating into doublewords. After the loop, the upper
word is added to the lower word; the upper halfword is added to the
lower halfword, and any carries are added back in.
The Hexagon processor supports a dedicated
[Vector reduce add halfwords](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#vector-reduce-add-halfwords) (vradduh) instruction
that computes the Internet checksum at a rate of 16 bytes per cycle.
The vradduh instruction accepts the halfwords of the two input
vectors, adds them together, and places the result in a 32-bit
destination register. This operation can both compute the sum of 16
bytes of input while preserving the carries, and accumulate carries
at the end of computation.
Note
This operation uses the maximum load bandwidth available in
the Hexagon processor.
**Code example**
.text
.global fast_ip_check
// Assumes that data is 8-byte aligned
// Assumes thatdata is padded at least 16 bytes after words with 0's.
// Input R0 points to data
// Input R1 is thelength of data
// Returns IP checksum in R0
fast_ip_check:
{
R1 = lsr(R1,#4) // 16-byte chunks, rounded down, +1
R9:8 = combine(#0,#0)
R3:2 = combine(#0,#0)
}
{
loop0(1f,R1)
R7:6 = memd(R0+#8)
R5:4 = memd(R0++#16)
}
.falign
1:
{
R7:6 = memd(R0+#8)
R5:4 = memd(R0++#16)
R2 = vradduh(R5:4,R7:6) // Accumulate 8 halfwords
R8 = vradduh(R3:2,R9:8) // Accumulate carries
}:endloop0
// Drain pipeline
{
R2 = vradduh(R5:4,R7:6)
R8 = vradduh(R3:2,R9:8)
R5:4 = combine(#0,#0)
}
{
R8 = vradduh(R3:2,R9:8)
R1 = #0
}
// Might have some carries to add back in
{
R0 = vradduh(R5:4,R9:8)
}
// Possible for one more to pop out
{
R0 = vradduh(R5:4,R1:0)
}
{
R0 = not(R0)
jumpr LR
}
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### Software-defined radio
The Hexagon processor includes six special-purpose instructions that
support the implementation of software-defined radio. The
instructions greatly accelerate the following algorithms.
#### Rake despreading
A fundamental operation in despreading is the PN multiply operation.
In this operation, the received complex chips are compared against a
pseudorandom sequence of Quadrature Amplitude Modulation (QAM)
constellation points and accumulated.
[Vector reduce complex rotate](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#v79-fig-vector-reduce-complex-rotate)
shows the vrcrotate instruction that performs this operation. The products
are summed to form a soft 32-bit complex symbol. The instruction has both
accumulating and non-accumulating versions.
**Vector reduce complex rotate**
For more information on the vrcrotate instruction, see
[Vector reduce complex rotate](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#vector-reduce-complex-rotate).
Note
Using this instruction, the Hexagon processor can process
5.3 chips per cycle, and a 12-finger WCDMA user requires only 15 MHz.
#### Polynomial operations
The polynomial multiply instructions support the following
operations:
- Scramble code generation (at a rate of eight symbols per cycle for WCDMA)
- Cryptographic algorithms (such as elliptic curve)
- CRCs (at a rate of 21 bits per cycle)
- Convolutional encoding
- Reed-Solomon codes
The four versions of this instruction support 32 x 32 and vector 16 x 16
multiplication both with and without accumulation, as shown in
[Polynomial multiply](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#v79-fig-polynomial-multiply).
**Polynomial multiply**
For more information on the pmpy instructions, see
[Polynomial multiply words](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#polynomial-multiply-words).
[[1](https://docs.qualcomm.com/doc/80-N2040-60/topic/data-processing.html#id2)]
See RFC 1071 [(http://www.faqs.org/rfcs/rfc1071.html)](http://www.faqs.org/rfcs/rfc1071.html%29)
Last Published: Jan 16, 2025
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