# Instruction set This chapter describes the instruction set for version 6 of the Hexagon processor. The following information is provided for each instruction: - Instruction name - A brief description of the instruction - A high-level functional description (syntax and behavior) with all possible operand types - Instruction class and slot information for grouping instructions in packets - Notes on miscellaneous issues - Any C intrinsic functions that provide access to the instruction - Instruction encoding ## ALU32 The ALU32 instruction class includes instructions which perform arithmetic and logical operations on 32-bit data. ALU32 instructions are executable on any slot. ### ALU The ALU32/ALU instruction subclass includes instructions which perform arithmetic and logical operations on individual 32-bit items. #### Add Add a source register either to another source register or to a signed 16-bit immediate value. Store result in destination register. Source and destination registers are 32 bits. If the result overflows 32 bits, it wraps around. Optionally saturate result to a signed value between 0x80000000 and 0x7fffffff. For 64-bit versions of this operation, see the XTYPE add instructions. Add instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=add(Rs,Rt) | Rd=Rs+Rt;
Copy to clipboard | | Rd=add(Rs,Rt):sat | Rd=sat_32(Rs+Rt);
Copy to clipboard | | Rd=add(Rs,#s16) | apply_extension(s);
Rd=Rs+s;
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rd=add(Rs,Rt)

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Rd=add(Rs,Rt):sat

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Rd=add(Rs,#s16)

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Intrinsics
Add intrinsics

Rd=add(Rs,Rt)

Word32 Q6_R_add_RR(Word32 Rs, Word32 Rt)

Rd=add(Rs,Rt):sat

Word32 Q6_R_add_RR_sat(Word32 Rs, Word32 Rt)

Rd=add(Rs,#s16)

Word32 Q6_R_add_RI(Word32 Rs, Word32 Is16)
#### Logical operations Perform bitwise logical operations (AND, OR, XOR, NOT) either on two source registers or on a source register and a signed 10-bit immediate value. Store result in destination register. Source and destination registers are 32 bits. For 64-bit versions of these operations, see the XTYPE logical instructions. Logical operations instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=and(Rs,Rt) | Rd=Rs&Rt;
Copy to clipboard | | Rd=or(Rs,Rt) | Rd=Rs|Rt;
Copy to clipboard | | Rd=xor(Rs,Rt) | Rd=Rs^Rt;
Copy to clipboard | | Rd=not(Rs) | Assembler mapped to: "Rd=sub(-1,Rs)"
Copy to clipboard | | Rd=and(Rt,~Rs) | Rd = (Rt & ~Rs);
Copy to clipboard | | Rd=or(Rt,~Rs) | Rd = (Rt | ~Rs);
Copy to clipboard | | Rd=and(Rs,#s10) | apply_extension(s);
Rd=Rs&s;
Copy to clipboard | | Rd=or(Rs,#s10) | apply_extension(s);
Rd=Rs|s;
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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Rd=and(Rs,Rt)

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Rd=or(Rs,Rt)

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Rd=xor(Rs,Rt)

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Rd=and(Rt,~Rs)

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Rd=or(Rt,~Rs)

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Rd=and(Rs,#s10)

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Rd=or(Rs,#s10)

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Intrinsics
Logical operations intrinsics

Rd=and(Rs,Rt)

Word32 Q6_R_and_RR(Word32 Rs, Word32 Rt)

Rd=or(Rs,Rt)

Word32 Q6_R_or_RR(Word32 Rs, Word32 Rt)

Rd=xor(Rs,Rt)

Word32 Q6_R_xor_RR(Word32 Rs, Word32 Rt)

Rd=not(Rs)

Word32 Q6_R_not_R(Word32 Rs)

Rd=and(Rt,~Rs)

Word32 Q6_R_and_RnR(Word32 Rt, Word32 Rs)

Rd=or(Rt,~Rs)

Word32 Q6_R_or_RnR(Word32 Rt, Word32 Rs)

Rd=and(Rs,#s10)

Word32 Q6_R_and_RI(Word32 Rs, Word32 Is10)

Rd=or(Rs,#s10)

Word32 Q6_R_or_RI(Word32 Rs, Word32 Is10)
#### Negate Perform arithmetic negation on a source register. Store result in destination register. Source and destination registers are 32 bits. For 64-bit and saturating versions of this instruction, see the XTYPE-class negate instructions. Negate instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=neg(Rs) | Assembler mapped to: "Rd=sub(0,Rs)"
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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Intrinsics
Negate intrinsics

Rd=neg(Rs)

Word32 Q6_R_neg_R(Word32 Rs)
#### Nop Perform no operation. This instruction is used for padding and alignment. Within a packet it can be positioned in any slot 0-3. Nop instructions | **Syntax** | **Behavior** | | --- | --- | | nop | Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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#### Subtract Subtract a source register from either another source register or from a signed 10-bit immediate value. Store result in destination register. Source and destination registers are 32 bits. If the result underflows 32 bits, it wraps around. Optionally saturate result to a signed value between 0x8000\_0000 and 0x7fff\_ffff. For 64-bit versions of this operation, see the XTYPE subtract instructions. Subtract instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=sub(Rt,Rs) | Rd=Rt-Rs;
Copy to clipboard | | Rd=sub(Rt,Rs):sat | Rd=sat_32(Rt - Rs);
Copy to clipboard | | Rd=sub(#s10,Rs) | apply_extension(s);
Rd=s-Rs;
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rd=sub(Rt,Rs)

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Rd=sub(Rt,Rs):sat

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Rd=sub(#s10,Rs)

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Intrinsics
Subtract intrinsics

Rd=sub(Rt,Rs)

Word32 Q6_R_sub_RR(Word32 Rt, Word32 Rs)

Rd=sub(Rt,Rs):sat

Word32 Q6_R_sub_RR_sat(Word32 Rt, Word32 Rs)

Rd=sub(#s10,Rs)

Word32 Q6_R_sub_IR(Word32 Is10, Word32 Rs)
#### Sign extend Sign-extend the least-significant byte or halfword from the source register and place the 32-bit result in the destination register. pic_addh Page-1 Sheet.31 Rectangle.14 Sheet.27 Rs Rs Rectangle.29 Sign-extend Sign-extend Sheet.30 Rd Rd Sheet.16 Rectangle.1 Rectangle.2 Sheet.3 Rd=sxth(Rs) Rd=sxth(Rs) Sheet.5 Rs Rs Rectangle.6 Sign-extend Sign-extend Sheet.8 Rd Rd Sheet.9 Rectangle.10 Rectangle.11 Sheet.12 Rd=sxtb(Rs) Rd=sxtb(Rs) Rectangle.13 Sign extend instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=sxtb(Rs) | Rd = sxt_8_to_32(Rs);
Copy to clipboard | | Rd=sxth(Rs) | Rd = sxt_16_to_32(Rs);
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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Rd=sxtb(Rs)

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Rd=sxth(Rs)

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Intrinsics
Sign extend intrinsics

Rd=sxtb(Rs)

Word32 Q6_R_sxtb_R(Word32 Rs)

Rd=sxth(Rs)

Word32 Q6_R_sxth_R(Word32 Rs)
#### Transfer immediate Assign an immediate value to a 32-bit destination register. Two types of assignment are supported. The first sign-extends a 16-bit signed immediate value to 32 bits. The second assigns a 16-bit unsigned immediate value to either the upper or lower 16 bits of the destination register, leaving the other 16 bits unchanged. pic_addh Page-1 Sheet.10 Sheet.1 Rd=#s16 Rd=#s16 Rectangle.73 16-bit immediate 16-bit immediate Rectangle.74 Sign-extend Sign-extend Sheet.2 Rx.H=#u16 Rx.H=#u16 Rectangle.5 Unchanged Unchanged Rectangle.6 16-bit immediate 16-bit immediate Sheet.7 Rx.L=#u16 Rx.L=#u16 Rectangle.8 Unchanged Unchanged Rectangle.9 16-bit immediate 16-bit immediate Transfer immediate instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=#s16 | apply_extension(s);
Rd=s;
Copy to clipboard | | Rdd=#s8 | if ("s8<0") {
Assembler mapped to: "Rdd=combine(-1,s8)";
} else {
Assembler mapped to: "Rdd=combine(0,s8)";
}
Copy to clipboard | | Rx.L=#u16 | Rx.h[0]=u;
Copy to clipboard | | Rx.H=#u16 | Rx.h[1]=u;
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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Rd=#s16

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Rx.L=#u16

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Rx.H=#u16

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Intrinsics
Transfer immediate intrinsics

Rd=#s16

Word32 Q6_R_equals_I(Word32 Is16)

Rdd=#s8

Word64 Q6_P_equals_I(Word32 Is8)

Rx.L=#u16

Word32 Q6_Rl_equals_I(Word32 Rx, Word32 Iu16)

Rx.H=#u16

Word32 Q6_Rh_equals_I(Word32 Rx, Word32 Iu16)
#### Transfer register Transfer a source register to a destination register. Source and destination registers are either 32 bits or 64 bits. Transfer register instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=Rs | Rd=Rs;
Copy to clipboard | | Rdd=Rss | Assembler mapped to: "Rdd=combine(Rss.H32,Rss.L32)"
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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Rd=Rs

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Intrinsics
Transfer register intrinsics

Rd=Rs

Word32 Q6_R_equals_R(Word32 Rs)

Rdd=Rss

Word64 Q6_P_equals_P(Word64 Rss)
#### Vector add halfwords Add the two 16-bit halfwords of Rs to the two 16-bit halfwords of Rt. The results are optionally saturated to signed or unsigned 16-bit values. Vector add halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=vaddh(Rs,Rt) | for (i=0;i<2;i++) {
Rd.h[i]=Rs.h[i]+Rt.h[i];
}
Copy to clipboard | | Rd=vaddh(Rs,Rt):sat | for (i=0;i<2;i++) {
Rd.h[i]=sat_16(Rs.h[i]+Rt.h[i]);
}
Copy to clipboard | | Rd=vadduh(Rs,Rt):sat | for (i=0;i<2;i++) {
Rd.h[i]=usat_16(Rs.uh[i]+Rt.uh[i]);
}
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rd=vaddh(Rs,Rt)

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Rd=vaddh(Rs,Rt):sat

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Rd=vadduh(Rs,Rt):sat

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Intrinsics
Vector add halfwords intrinsics

Rd=vaddh(Rs,Rt)

Word32 Q6_R_vaddh_RR(Word32 Rs, Word32 Rt)

Rd=vaddh(Rs,Rt):sat

Word32 Q6_R_vaddh_RR_sat(Word32 Rs, Word32 Rt)

Rd=vadduh(Rs,Rt):sat

Word32 Q6_R_vadduh_RR_sat(Word32 Rs, Word32 Rt)
#### Vector average halfwords VAVGH adds the two 16-bit halfwords of Rs to the two 16-bit halfwords of Rd, and shifts the result right by 1 bit. Optionally, a rounding constant is added before shifting. VNAVGH subtracts the two 16-bit halfwords of Rt from the two 16-bit halfwords of Rs, and shifts the result right by 1 bit. For vector negative average with rounding, see the XTYPE VNAVGH instruction. Vector average halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=vavgh(Rs,Rt) | for (i=0;i<2;i++) {
Rd.h[i]=((Rs.h[i]+Rt.h[i])>>1);
}
Copy to clipboard | | Rd=vavgh(Rs,Rt):rnd | for (i=0;i<2;i++) {
Rd.h[i]=((Rs.h[i]+Rt.h[i]+1)>>1);
}
Copy to clipboard | | Rd=vnavgh(Rt,Rs) | for (i=0;i<2;i++) {
Rd.h[i]=((Rt.h[i]-Rs.h[i])>>1);
}
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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Rd=vavgh(Rs,Rt)

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Rd=vavgh(Rs,Rt):rnd

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Rd=vnavgh(Rt,Rs)

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Intrinsics
Vector average halfwords intrinsics

Rd=vavgh(Rs,Rt)

Word32 Q6_R_vavgh_RR(Word32 Rs, Word32 Rt)

Rd=vavgh(Rs,Rt):rnd

Word32 Q6_R_vavgh_RR_rnd(Word32 Rs, Word32 Rt)

Rd=vnavgh(Rt,Rs)

Word32 Q6_R_vnavgh_RR(Word32 Rt, Word32 Rs)
#### Vector subtract halfwords Subtract each of the two halfwords in 32-bit vector Rs from the corresponding halfword in vector Rt. Optionally saturate each 16-bit addition to either a signed or unsigned 16-bit value. Applying saturation to the VSUBH instruction clamps the result to the signed range 0x8000 to 0x7fff, whereas applying saturation to VSUBUH ensures that the unsigned result is in the range 0 to 0xffff. When saturation is not needed, VSUBH should be used. Vector subtract halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=vsubh(Rt,Rs) | for (i=0;i<2;i++) {
Rd.h[i]=Rt.h[i]-Rs.h[i];
}
Copy to clipboard | | Rd=vsubh(Rt,Rs):sat | for (i=0;i<2;i++) {
Rd.h[i]=sat_16(Rt.h[i]-Rs.h[i]);
}
Copy to clipboard | | Rd=vsubuh(Rt,Rs):sat | for (i=0;i<2;i++) {
Rd.h[i]=usat_16(Rt.uh[i]-Rs.uh[i]);
}
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rd=vsubh(Rt,Rs)

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Rd=vsubh(Rt,Rs):sat

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Rd=vsubuh(Rt,Rs):sat

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Intrinsics
Vector subtract halfwords intrinsics

Rd=vsubh(Rt,Rs)

Word32 Q6_R_vsubh_RR(Word32 Rt, Word32 Rs)

Rd=vsubh(Rt,Rs):sat

Word32 Q6_R_vsubh_RR_sat(Word32 Rt, Word32 Rs)

Rd=vsubuh(Rt,Rs):sat

Word32 Q6_R_vsubuh_RR_sat(Word32 Rt, Word32 Rs)
#### Zero extend Zero-extend the least significant byte or halfword from Rs and place the 32-bit result in Rd. pic_addh Page-1 Sheet.31 Rectangle.14 Sheet.27 Rs Rs Rectangle.29 0x0000 0x0000 Sheet.30 Rd Rd Sheet.16 Rectangle.1 Rectangle.2 Sheet.3 Rd = zxth(Rs) Rd = zxth(Rs) Sheet.5 Rs Rs Rectangle.6 0x000000 0x000000 Sheet.8 Rd Rd Sheet.9 Rectangle.10 Rectangle.11 Sheet.12 Rd = zxtb(Rs) Rd = zxtb(Rs) Rectangle.13 Zero extend instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=zxtb(Rs) | Assembler mapped to: "Rd=and(Rs,255)"
Copy to clipboard | | Rd=zxth(Rs) | Rd = zxt_16_to_32(Rs);
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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Rd=zxth(Rs)

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Intrinsics
Zero extend intrinsics

Rd=zxtb(Rs)

Word32 Q6_R_zxtb_R(Word32 Rs)

Rd=zxth(Rs)

Word32 Q6_R_zxth_R(Word32 Rs)
### PERM The ALU32/PERM instruction subclass includes instructions which rearrange or perform format conversion on vector data types. #### Combine words into doubleword Combine halfwords or words into larger values. In a halfword combine, either the high or low halfword of the first source register is transferred to the most-significant halfword of the destination register, while either the high or low halfword of the second source register is transferred to the least-significant halfword of the destination register. Source and destination registers are 32 bits. In a word combine, the first source register is transferred to the most-significant word of the destination register, while the second source register is transferred to the least-significant word of the destination register. Source registers are 32 bits and the destination register is 64 bits. In a variant of word combine, signed 8-bit immediate values (instead of registers) are transferred to the most- and least-significant words of the 64-bit destination register. Optionally one of the immediate values can be 32 bits. pic_addh Page-1 Sheet.31 Rectangle.14 Rt.L Rt.L Sheet.12 Sheet.13 Rectangle.28 Rt.H Rt.H Rectangle.6 Rs.L Rs.L Rectangle.9 Rs.H Rs.H Rectangle.29 Sheet.30 Rd Rd Rounded rectangle.4 Mux Mux Rounded rectangle.5 Mux Mux Sheet.14 Sheet.16 Sheet.17 Sheet.18 Rectangle.1 Sheet.8 Rd = combine(Rt.[HL],Rs.[HL]) Rd = combine(Rt.[HL],Rs.[HL]) Sheet.10 Rdd = combine(Rs,Rt) Rdd = combine(Rs,Rt) Rectangle.11 Sheet.15 Rdd Rdd Rectangle.19 Rectangle.20 Rt Rt Rectangle.21 Rs Rs Sheet.22 Sheet.23 Combine words into doubleword instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=combine(Rs,Rt) | Rdd.w[0]=Rt;
Rdd.w[1]=Rs;
Copy to clipboard | | Rdd=combine(Rs,#s8) | apply_extension(s);
Rdd.w[0]=s;
Rdd.w[1]=Rs;
Copy to clipboard | | Rdd=combine(#s8,Rs) | apply_extension(s);
Rdd.w[0]=Rs;
Rdd.w[1]=s;
Copy to clipboard | | Rdd=combine(#s8,#S8) | apply_extension(s);
Rdd.w[0]=S;
Rdd.w[1]=s;
Copy to clipboard | | Rdd=combine(#s8,#U6) | apply_extension(U);
Rdd.w[0]=U;
Rdd.w[1]=s;
Copy to clipboard | | Rd=combine(Rt.H,Rs.H) | Rd = (Rt.uh[1]<<16) | Rs.uh[1];
Copy to clipboard | | Rd=combine(Rt.H,Rs.L) | Rd = (Rt.uh[1]<<16) | Rs.uh[0];
Copy to clipboard | | Rd=combine(Rt.L,Rs.H) | Rd = (Rt.uh[0]<<16) | Rs.uh[1];
Copy to clipboard | | Rd=combine(Rt.L,Rs.L) | Rd = (Rt.uh[0]<<16) | Rs.uh[0];
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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Rdd=combine(Rs,Rt)

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Rdd=combine(Rs,#s8)

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Rdd=combine(#s8,Rs)

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Rdd=combine(#s8,#S8)

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Rdd=combine(#s8,#U6)

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Rd=combine(Rt.H,Rs.H)

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Rd=combine(Rt.H,Rs.L)

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Rd=combine(Rt.L,Rs.H)

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Rd=combine(Rt.L,Rs.L)

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Intrinsics
Combine words into doubleword intrinsics

Rdd=combine(Rs,Rt)

Word64 Q6_P_combine_RR(Word32 Rs, Word32 Rt)

Rdd=combine(Rs,#s8)

Word64 Q6_P_combine_RI(Word32 Rs, Word32 Is8)

Rdd=combine(#s8,Rs)

Word64 Q6_P_combine_IR(Word32 Is8, Word32 Rs)

Rdd=combine(#s8,#S8)

Word64 Q6_P_combine_II(Word32 Is8, Word32 IS8)

Rd=combine(Rt.H,Rs.H)

Word32 Q6_R_combine_RhRh(Word32 Rt, Word32 Rs)

Rd=combine(Rt.H,Rs.L)

Word32 Q6_R_combine_RhRl(Word32 Rt, Word32 Rs)

Rd=combine(Rt.L,Rs.H)

Word32 Q6_R_combine_RlRh(Word32 Rt, Word32 Rs)

Rd=combine(Rt.L,Rs.L)

Word32 Q6_R_combine_RlRl(Word32 Rt, Word32 Rs)
#### Mux Select between two source registers based on the least-significant bit of a predicate register. If the bit is 1, transfer the first source register to the destination register; otherwise, transfer the second source register. Source and destination registers are 32 bits. In a variant of mux, signed 8-bit immediate values can be used instead of registers for either or both source operands. For 64-bit versions of this instruction, see the XTYPE vmux instruction. Mux instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=mux(Pu,Rs,Rt) | Rd = (Pu[0] ? Rs : Rt);
Copy to clipboard | | Rd=mux(Pu,#s8,#S8) | apply_extension(s);
Rd = (Pu[0] ? s : S);
Copy to clipboard | | Rd=mux(Pu,Rs,#s8) | apply_extension(s);
Rd = (Pu[0] ? Rs : s);
Copy to clipboard | | Rd=mux(Pu,#s8,Rs) | apply_extension(s);
Rd = (Pu[0] ? s : Rs);
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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Rd=mux(Pu,Rs,Rt)

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Rd=mux(Pu,#s8,#S8)

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Rd=mux(Pu,Rs,#s8)

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Rd=mux(Pu,#s8,Rs)

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Intrinsics
Mux intrinsics

Rd=mux(Pu,Rs,Rt)

Word32 Q6_R_mux_pRR(Byte Pu, Word32 Rs, Word32 Rt)

Rd=mux(Pu,#s8,#S8)

Word32 Q6_R_mux_pII(Byte Pu, Word32 Is8, Word32 IS8)

Rd=mux(Pu,Rs,#s8)

Word32 Q6_R_mux_pRI(Byte Pu, Word32 Rs, Word32 Is8)

Rd=mux(Pu,#s8,Rs)

Word32 Q6_R_mux_pIR(Byte Pu, Word32 Is8, Word32 Rs)
#### Shift word by 16 ASLH performs an arithmetic left shift of the 32-bit source register by 16 bits (one halfword). The lower 16 bits of the destination are zero-filled. pic_addh Page-1 Sheet.31 Rectangle.14 Sheet.27 Rs Rs Rectangle.29 Sheet.30 Rd Rd Sheet.16 Rectangle.1 0x0000 0x0000 Rectangle.2 ASRH performs an arithmetic right shift of the 32-bit source register by 16 bits (one halfword). The upper 16 bits of the destination are sign-extended. pic_addh Page-1 Sheet.31 Rectangle.14 Sheet.27 Rs Rs Rectangle.29 Sign-extend Sign-extend Sheet.30 Rd Rd Sheet.16 Rectangle.1 Rectangle.2 Shift word by 16 instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=aslh(Rs) | Rd=Rs<<16;
Copy to clipboard | | Rd=asrh(Rs) | Rd=Rs>>16;
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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Rd=aslh(Rs)

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Rd=asrh(Rs)

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Intrinsics
Shift word by 16 intrinsics

Rd=aslh(Rs)

Word32 Q6_R_aslh_R(Word32 Rs)

Rd=asrh(Rs)

Word32 Q6_R_asrh_R(Word32 Rs)
#### Pack high and low halfwords Pack together the most-significant halfwords from Rs and Rt into the most-significant word of register pair Rdd, and the least-significant halfwords from Rs and Rt into the least-significant halfword of Rdd. pic_addh Page-1 Sheet.30 Rectangle.59 Rectangle.61 Rectangle.62 Rectangle.63 Sheet.12 Rdd Rdd Sheet.13 Rt Rt Sheet.21 Rectangle.25 Rectangle.26 Sheet.5 Sheet.27 Rs Rs Rectangle.28 Rectangle.29 Sheet.22 Sheet.23 Pack high and low halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=packhl(Rs,Rt) | Rdd.h[0]=Rt.h[0];
Rdd.h[1]=Rs.h[0];
Rdd.h[2]=Rt.h[1];
Rdd.h[3]=Rs.h[1];
Copy to clipboard | | Rdd=packhl(Rs,Rt):deprecated | Rdd.h[0]=Rt.h[0];
Rdd.h[1]=Rs.h[0];
Rdd.h[2]=Rt.h[1];
Rdd.h[3]=Rs.h[1];
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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Rdd=packhl(Rs,Rt)

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Rdd=packhl(Rs,Rt):deprecated

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Intrinsics
Pack high and low halfwords intrinsics

Rdd=packhl(Rs,Rt)

Word64 Q6_P_packhl_RR(Word32 Rs, Word32 Rt)
### PRED The ALU32/PRED instruction subclass includes instructions which perform conditional arithmetic and logical operations based on the values stored in a predicate register, and which produce predicate results. They are executable on any slot. #### Conditional add If the least-significant bit of predicate Pu is set, then add a 32-bit source register to either another register or an immediate value. The result is placed in 32-bit destination register. If the predicate is false, the instruction does nothing. Conditional add instructions | **Syntax** | **Behavior** | | --- | --- | | if (Pu) Rd=add(Rs,Rt) | if(Pu[0]){
Rd=Rs+Rt;
} else {
NOP;
}
Copy to clipboard | | if (!Pu) Rd=add(Rs,Rt) | if(!Pu[0]){
Rd=Rs+Rt;
} else {
NOP;
}
Copy to clipboard | | if (Pu.new) Rd=add(Rs,Rt) | if(Pu.new[0]){
Rd=Rs+Rt;
} else {
NOP;
}
Copy to clipboard | | if (!Pu.new) Rd=add(Rs,Rt) | if(!Pu.new[0]){
Rd=Rs+Rt;
} else {
NOP;
}
Copy to clipboard | | if (Pu) Rd=add(Rs,#s8) | if(Pu[0]){
apply_extension(s);
Rd=Rs+s;
} else {
NOP;
}
Copy to clipboard | | if (!Pu) Rd=add(Rs,#s8) | if(!Pu[0]){
apply_extension(s);
Rd=Rs+s;
} else {
NOP;
}
Copy to clipboard | | if (Pu.new) Rd=add(Rs,#s8) | if(Pu.new[0]){
apply_extension(s);
Rd=Rs+s;
} else {
NOP;
}
Copy to clipboard | | if (!Pu.new) Rd=add(Rs,#s8) | if(!Pu.new[0]){
apply_extension(s);
Rd=Rs+s;
} else {
NOP;
}
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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if (Pu) Rd=add(Rs,Rt)

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if (!Pu) Rd=add(Rs,Rt)

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if (Pu.new) Rd=add(Rs,Rt)

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if (!Pu.new) Rd=add(Rs,Rt)

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if (Pu) Rd=add(Rs,#s8)

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if (!Pu) Rd=add(Rs,#s8)

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if (Pu.new) Rd=add(Rs,#s8)

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if (!Pu.new) Rd=add(Rs,#s8)

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#### Conditional shift halfword Conditionally shift a halfword. ASLH performs an arithmetic left shift of the 32-bit source register by 16 bits (one halfword). The lower 16 bits of the destination are zero-filled. pic_addh Page-1 Sheet.31 Rectangle.14 Sheet.27 Rs Rs Rectangle.29 Sheet.30 Rd Rd Sheet.16 Rectangle.1 0x0000 0x0000 Rectangle.2 ASRH performs an arithmetic right shift of the 32-bit source register by 16 bits (one halfword). The upper 16 bits of the destination are sign-extended. pic_addh Page-1 Sheet.31 Rectangle.14 Sheet.27 Rs Rs Rectangle.29 Sign-extend Sign-extend Sheet.30 Rd Rd Sheet.16 Rectangle.1 Rectangle.2 Conditional shift halfword instructions | **Syntax** | **Behavior** | | --- | --- | | if (Pu) Rd=aslh(Rs) | if(Pu[0]){
Rd=Rs<<16;
} else {
NOP;
}
Copy to clipboard | | if (!Pu) Rd=aslh(Rs) | if(!Pu[0]){
Rd=Rs<<16;
} else {
NOP;
}
Copy to clipboard | | if (Pu.new) Rd=aslh(Rs) | if(Pu.new[0]){
Rd=Rs<<16;
} else {
NOP;
}
Copy to clipboard | | if (!Pu.new) Rd=aslh(Rs) | if(!Pu.new[0]){
Rd=Rs<<16;
} else {
NOP;
}
Copy to clipboard | | if (Pu) Rd=asrh(Rs) | if(Pu[0]){
Rd=Rs>>16;
} else {
NOP;
}
Copy to clipboard | | if (!Pu) Rd=asrh(Rs) | if(!Pu[0]){
Rd=Rs>>16;
} else {
NOP;
}
Copy to clipboard | | if (Pu.new) Rd=asrh(Rs) | if(Pu.new[0]){
Rd=Rs>>16;
} else {
NOP;
}
Copy to clipboard | | if (!Pu.new) Rd=asrh(Rs) | if(!Pu.new[0]){
Rd=Rs>>16;
} else {
NOP;
}
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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if (Pu) Rd=aslh(Rs)

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if (Pu) Rd=asrh(Rs)

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if (!Pu) Rd=asrh(Rs)

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if (Pu.new) Rd=asrh(Rs)

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if (!Pu.new) Rd=asrh(Rs)

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#### Conditional combine If the least-significant bit of predicate Pu is set, then the most-significant word of destination Rdd is taken from the first source register Rs, while the least-significant word is taken from the second source register Rt. If the predicate is false, this instruction does nothing. Conditional combine instructions | **Syntax** | **Behavior** | | --- | --- | | if (Pu.new) Rdd=combine(Rs,Rt) | if (Pu.new[0]) {
Rdd.w[0]=Rt;
Rdd.w[1]=Rs;
} else {
NOP;
}
Copy to clipboard | | if (!Pu.new) Rdd=combine(Rs,Rt) | if (!Pu.new[0]) {
Rdd.w[0]=Rt;
Rdd.w[1]=Rs;
} else {
NOP;
}
Copy to clipboard | | if (Pu) Rdd=combine(Rs,Rt) | if (Pu[0]) {
Rdd.w[0]=Rt;
Rdd.w[1]=Rs;
} else {
NOP;
}
Copy to clipboard | | if (!Pu) Rdd=combine(Rs,Rt) | if (!Pu[0]) {
Rdd.w[0]=Rt;
Rdd.w[1]=Rs;
} else {
NOP;
}
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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if (Pu.new) Rdd=combine(Rs,Rt)

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if (!Pu.new) Rdd=combine(Rs,Rt)

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if (Pu) Rdd=combine(Rs,Rt)

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if (!Pu) Rdd=combine(Rs,Rt)

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#### Conditional logical operations If the least-significant bit of predicate Pu is set, then do a logical operation on the source values. The result is placed in 32-bit destination register. If the predicate is false, the instruction does nothing. Conditional logical operations instructions | **Syntax** | **Behavior** | | --- | --- | | if (Pu) Rd=xor(Rs,Rt) | if(Pu[0]){
Rd=Rs^Rt;
} else {
NOP;
}
Copy to clipboard | | if (!Pu) Rd=xor(Rs,Rt) | if(!Pu[0]){
Rd=Rs^Rt;
} else {
NOP;
}
Copy to clipboard | | if (Pu.new) Rd=xor(Rs,Rt) | if(Pu.new[0]){
Rd=Rs^Rt;
} else {
NOP;
}
Copy to clipboard | | if (!Pu.new) Rd=xor(Rs,Rt) | if(!Pu.new[0]){
Rd=Rs^Rt;
} else {
NOP;
}
Copy to clipboard | | if (Pu) Rd=and(Rs,Rt) | if(Pu[0]){
Rd=Rs&Rt;
} else {
NOP;
}
Copy to clipboard | | if (!Pu) Rd=and(Rs,Rt) | if(!Pu[0]){
Rd=Rs&Rt;
} else {
NOP;
}
Copy to clipboard | | if (Pu.new) Rd=and(Rs,Rt) | if(Pu.new[0]){
Rd=Rs&Rt;
} else {
NOP;
}
Copy to clipboard | | if (!Pu.new) Rd=and(Rs,Rt) | if(!Pu.new[0]){
Rd=Rs&Rt;
} else {
NOP;
}
Copy to clipboard | | if (Pu) Rd=or(Rs,Rt) | if(Pu[0]){
Rd=Rs|Rt;
} else {
NOP;
}
Copy to clipboard | | if (!Pu) Rd=or(Rs,Rt) | if(!Pu[0]){
Rd=Rs|Rt;
} else {
NOP;
}
Copy to clipboard | | if (Pu.new) Rd=or(Rs,Rt) | if(Pu.new[0]){
Rd=Rs|Rt;
} else {
NOP;
}
Copy to clipboard | | if (!Pu.new) Rd=or(Rs,Rt) | if(!Pu.new[0]){
Rd=Rs|Rt;
} else {
NOP;
}
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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if (Pu) Rd=xor(Rs,Rt)

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if (!Pu) Rd=xor(Rs,Rt)

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if (Pu.new) Rd=xor(Rs,Rt)

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if (!Pu.new) Rd=xor(Rs,Rt)

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if (Pu) Rd=and(Rs,Rt)

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if (!Pu) Rd=and(Rs,Rt)

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if (Pu.new) Rd=and(Rs,Rt)

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if (!Pu.new) Rd=and(Rs,Rt)

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if (Pu) Rd=or(Rs,Rt)

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if (!Pu) Rd=or(Rs,Rt)

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if (Pu.new) Rd=or(Rs,Rt)

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if (!Pu.new) Rd=or(Rs,Rt)

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#### Conditional subtract If the least-significant bit of predicate Pu is set, then subtract a 32-bit source register Rt from register Rs. The result is placed in a 32-bit destination register. If the predicate is false, the instruction does nothing. Conditional subtract instructions | **Syntax** | **Behavior** | | --- | --- | | if (Pu) Rd=sub(Rt,Rs) | if(Pu[0]){
Rd=Rt-Rs;
} else {
NOP;
}
Copy to clipboard | | if (!Pu) Rd=sub(Rt,Rs) | if(!Pu[0]){
Rd=Rt-Rs;
} else {
NOP;
}
Copy to clipboard | | if (Pu.new) Rd=sub(Rt,Rs) | if(Pu.new[0]){
Rd=Rt-Rs;
} else {
NOP;
}
Copy to clipboard | | if (!Pu.new) Rd=sub(Rt,Rs) | if(!Pu.new[0]){
Rd=Rt-Rs;
} else {
NOP;
}
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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if (Pu) Rd=sub(Rt,Rs)

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if (!Pu) Rd=sub(Rt,Rs)

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if (Pu.new) Rd=sub(Rt,Rs)

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if (!Pu.new) Rd=sub(Rt,Rs)

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#### Conditional sign extend Conditionally sign-extend the least-significant byte or halfword from Rs and put the 32-bit result in Rd. pic_addh Page-1 Sheet.31 Rectangle.14 Sheet.27 Rs Rs Rectangle.29 Sign-extend Sign-extend Sheet.30 Rd Rd Sheet.16 Rectangle.1 Rectangle.2 Sheet.3 Rd=sxth(Rs) Rd=sxth(Rs) Sheet.5 Rs Rs Rectangle.6 Sign-extend Sign-extend Sheet.8 Rd Rd Sheet.9 Rectangle.10 Rectangle.11 Sheet.12 Rd=sxtb(Rs) Rd=sxtb(Rs) Rectangle.13 Conditional sign extend instructions | **Syntax** | **Behavior** | | --- | --- | | if (Pu) Rd=sxtb(Rs) | if(Pu[0]){
Rd=sxt_8_to_32(Rs);
} else {
NOP;
}
Copy to clipboard | | if (!Pu) Rd=sxtb(Rs) | if(!Pu[0]){
Rd=sxt_8_to_32(Rs);
} else {
NOP;
}
Copy to clipboard | | if (Pu.new) Rd=sxtb(Rs) | if(Pu.new[0]){
Rd=sxt_8_to_32(Rs);
} else {
NOP;
}
Copy to clipboard | | if (!Pu.new) Rd=sxtb(Rs) | if(!Pu.new[0]){
Rd=sxt_8_to_32(Rs);
} else {
NOP;
}
Copy to clipboard | | if (Pu) Rd=sxth(Rs) | if(Pu[0]){
Rd=sxt_16_to_32(Rs);
} else {
NOP;
}
Copy to clipboard | | if (!Pu) Rd=sxth(Rs) | if(!Pu[0]){
Rd=sxt_16_to_32(Rs);
} else {
NOP;
}
Copy to clipboard | | if (Pu.new) Rd=sxth(Rs) | if(Pu.new[0]){
Rd=sxt_16_to_32(Rs);
} else {
NOP;
}
Copy to clipboard | | if (!Pu.new) Rd=sxth(Rs) | if(!Pu.new[0]){
Rd=sxt_16_to_32(Rs);
} else {
NOP;
}
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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if (Pu) Rd=sxtb(Rs)

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if (!Pu) Rd=sxtb(Rs)

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if (Pu.new) Rd=sxtb(Rs)

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if (!Pu.new) Rd=sxtb(Rs)

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if (Pu) Rd=sxth(Rs)

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if (!Pu) Rd=sxth(Rs)

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if (Pu.new) Rd=sxth(Rs)

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if (!Pu.new) Rd=sxth(Rs)

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#### Conditional transfer If the LSB of predicate Pu is set, transfer register Rs or a signed immediate into destination Rd. If the predicate is false, this instruction does nothing. Conditional transfer instructions | **Syntax** | **Behavior** | | --- | --- | | if (Pu) Rd=Rs | Assembler mapped to: "if (Pu) Rd=add(Rs,0)"
Copy to clipboard | | if (!Pu) Rd=Rs | Assembler mapped to: "if (!Pu) Rd=add(Rs,0)"
Copy to clipboard | | if (Pu.new) Rd=Rs | Assembler mapped to: "if (Pu.new) Rd=add(Rs,0)"
Copy to clipboard | | if (!Pu.new) Rd=Rs | Assembler mapped to: "if (!Pu.new) Rd=add(Rs,0)"
Copy to clipboard | | if (Pu) Rdd=Rss | Assembler mapped to: "if (Pu) Rdd=combine(Rss.H32,Rss.L32)"
Copy to clipboard | | if (!Pu) Rdd=Rss | Assembler mapped to: "if (!Pu) Rdd=combine(Rss.H32,Rss.L32)"
Copy to clipboard | | if (Pu.new) Rdd=Rss | Assembler mapped to: "if (Pu.new) Rdd=combine(Rss.H32,Rss.L32)"
Copy to clipboard | | if (!Pu.new) Rdd=Rss | Assembler mapped to: "if (!Pu.new) Rdd=combine(Rss.H32,Rss.L32)"
Copy to clipboard | | if (Pu.new) Rd=#s12 | apply_extension(s);
if (Pu.new[0]) Rd=s;
else NOP;
Copy to clipboard | | if (!Pu.new) Rd=#s12 | apply_extension(s);
if (!Pu.new[0]) Rd=s;
else NOP;
Copy to clipboard | | if (Pu) Rd=#s12 | apply_extension(s);
if (Pu[0]) Rd=s;
else NOP;
Copy to clipboard | | if (!Pu) Rd=#s12 | apply_extension(s);
if (!Pu[0]) Rd=s;
else NOP;
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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1

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if (Pu.new) Rd=#s12

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if (!Pu.new) Rd=#s12

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if (Pu) Rd=#s12

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if (!Pu) Rd=#s12

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#### Conditional zero extend Conditionally zero-extend the least-significant byte or halfword from Rs and put the 32-bit result in Rd. pic_addh Page-1 Sheet.31 Rectangle.14 Sheet.27 Rs Rs Rectangle.29 0x0000 0x0000 Sheet.30 Rd Rd Sheet.16 Rectangle.1 Rectangle.2 Sheet.3 Rd = zxth(Rs) Rd = zxth(Rs) Sheet.5 Rs Rs Rectangle.6 0x000000 0x000000 Sheet.8 Rd Rd Sheet.9 Rectangle.10 Rectangle.11 Sheet.12 Rd = zxtb(Rs) Rd = zxtb(Rs) Rectangle.13 Conditional zero extend instructions | **Syntax** | **Behavior** | | --- | --- | | if (Pu) Rd=zxtb(Rs) | if(Pu[0]){
Rd=zxt_8_to_32(Rs);
} else {
NOP;
}
Copy to clipboard | | if (!Pu) Rd=zxtb(Rs) | if(!Pu[0]){
Rd=zxt_8_to_32(Rs);
} else {
NOP;
}
Copy to clipboard | | if (Pu.new) Rd=zxtb(Rs) | if(Pu.new[0]){
Rd=zxt_8_to_32(Rs);
} else {
NOP;
}
Copy to clipboard | | if (!Pu.new) Rd=zxtb(Rs) | if(!Pu.new[0]){
Rd=zxt_8_to_32(Rs);
} else {
NOP;
}
Copy to clipboard | | if (Pu) Rd=zxth(Rs) | if(Pu[0]){
Rd=zxt_16_to_32(Rs);
} else {
NOP;
}
Copy to clipboard | | if (!Pu) Rd=zxth(Rs) | if(!Pu[0]){
Rd=zxt_16_to_32(Rs);
} else {
NOP;
}
Copy to clipboard | | if (Pu.new) Rd=zxth(Rs) | if(Pu.new[0]){
Rd=zxt_16_to_32(Rs);
} else {
NOP;
}
Copy to clipboard | | if (!Pu.new) Rd=zxth(Rs) | if(!Pu.new[0]){
Rd=zxt_16_to_32(Rs);
} else {
NOP;
}
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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if (Pu) Rd=zxtb(Rs)

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if (!Pu) Rd=zxtb(Rs)

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if (Pu.new) Rd=zxtb(Rs)

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if (!Pu.new) Rd=zxtb(Rs)

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if (Pu) Rd=zxth(Rs)

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if (!Pu) Rd=zxth(Rs)

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if (Pu.new) Rd=zxth(Rs)

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if (!Pu.new) Rd=zxth(Rs)

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#### Compare The register form compares two 32-bit registers for unsigned greater than, greater than, or equal. The immediate form compares a register against a signed or unsigned immediate value. The 8-bit predicate register Pd is set to all 1’s or all 0’s depending on the result. For 64-bit versions of this instruction, see the XTYPE compare instructions. Compare instructions | **Syntax** | **Behavior** | | --- | --- | | Pd=cmp.eq(Rs,Rt) | Pd=Rs==Rt ? 0xff : 0x00;
Copy to clipboard | | Pd=cmp.gt(Rs,Rt) | Pd=Rs>Rt ? 0xff : 0x00;
Copy to clipboard | | Pd=cmp.gtu(Rs,Rt) | Pd=Rs.uw[0]>Rt.uw[0] ? 0xff : 0x00;
Copy to clipboard | | Pd=cmp.eq(Rs,#s10) | apply_extension(s);
Pd=Rs==s ? 0xff : 0x00;
Copy to clipboard | | Pd=cmp.gt(Rs,#s10) | apply_extension(s);
Pd=Rs>s ? 0xff : 0x00;
Copy to clipboard | | Pd=cmp.gtu(Rs,#u9) | apply_extension(u);
Pd=Rs.uw[0]>u.uw[0] ? 0xff : 0x00;
Copy to clipboard | | Pd=cmp.ge(Rs,#s8) | Assembler mapped to: "Pd=cmp.gt(Rs,s8-1)"
Copy to clipboard | | Pd=cmp.geu(Rs,#u8) | if ("u8==0") {
Assembler mapped to: "Pd=cmp.eq(Rs,Rs)";
} else {
Assembler mapped to: "Pd=cmp.gtu(Rs,u8-1)";
}
Copy to clipboard | | Pd=cmp.lt(Rs,Rt) | Assembler mapped to: "Pd=cmp.gt(Rt,Rs)"
Copy to clipboard | | Pd=cmp.ltu(Rs,Rt) | Assembler mapped to: "Pd=cmp.gtu(Rt,Rs)"
Copy to clipboard | | Pd=!cmp.eq(Rs,#s10) | apply_extension(s);
Pd=Rs!=s ? 0xff : 0x00;
Copy to clipboard | | Pd=!cmp.gt(Rs,#s10) | apply_extension(s);
Pd=Rs<=s ? 0xff : 0x00;
Copy to clipboard | | Pd=!cmp.gtu(Rs,#u9) | apply_extension(u);
Pd=Rs.uw[0]<=u.uw[0] ? 0xff : 0x00;
Copy to clipboard | | Pd=!cmp.eq(Rs,Rt) | Pd=Rs!=Rt ? 0xff : 0x00;
Copy to clipboard | | Pd=!cmp.gt(Rs,Rt) | Pd=Rs<=Rt ? 0xff : 0x00;
Copy to clipboard | | Pd=!cmp.gtu(Rs,Rt) | Pd=Rs.uw[0]<=Rt.uw[0] ? 0xff : 0x00;
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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Pd=cmp.eq(Rs,Rt)

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Pd=cmp.gt(Rs,Rt)

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Pd=cmp.gtu(Rs,Rt)

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Pd=cmp.eq(Rs,#s10)

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Pd=cmp.gt(Rs,#s10)

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Pd=cmp.gtu(Rs,#u9)

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Pd=!cmp.eq(Rs,#s10)

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Pd=!cmp.gt(Rs,#s10)

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Pd=!cmp.gtu(Rs,#u9)

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Pd=!cmp.eq(Rs,Rt)

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Pd=!cmp.gt(Rs,Rt)

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Pd=!cmp.gtu(Rs,Rt)

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Intrinsics
Compare intrinsics

Pd=cmp.eq(Rs,Rt)

Byte Q6_p_cmp_eq_RR(Word32 Rs, Word32 Rt)

Pd=cmp.gt(Rs,Rt)

Byte Q6_p_cmp_gt_RR(Word32 Rs, Word32 Rt)

Pd=cmp.gtu(Rs,Rt)

Byte Q6_p_cmp_gtu_RR(Word32 Rs, Word32 Rt)

Pd=cmp.eq(Rs,#s10)

Byte Q6_p_cmp_eq_RI(Word32 Rs, Word32 Is10)

Pd=cmp.gt(Rs,#s10)

Byte Q6_p_cmp_gt_RI(Word32 Rs, Word32 Is10)

Pd=cmp.gtu(Rs,#u9)

Byte Q6_p_cmp_gtu_RI(Word32 Rs, Word32 Iu9)

Pd=cmp.ge(Rs,#s8)

Byte Q6_p_cmp_ge_RI(Word32 Rs, Word32 Is8)

Pd=cmp.geu(Rs,#u8)

Byte Q6_p_cmp_geu_RI(Word32 Rs, Word32 Iu8)

Pd=cmp.lt(Rs,Rt)

Byte Q6_p_cmp_lt_RR(Word32 Rs, Word32 Rt)

Pd=cmp.ltu(Rs,Rt)

Byte Q6_p_cmp_ltu_RR(Word32 Rs, Word32 Rt)

Pd=!cmp.eq(Rs,#s10)

Byte Q6_p_not_cmp_eq_RI(Word32 Rs, Word32 Is10)

Pd=!cmp.gt(Rs,#s10)

Byte Q6_p_not_cmp_gt_RI(Word32 Rs, Word32 Is10)

Pd=!cmp.gtu(Rs,#u9)

Byte Q6_p_not_cmp_gtu_RI(Word32 Rs, Word32 Iu9)

Pd=!cmp.eq(Rs,Rt)

Byte Q6_p_not_cmp_eq_RR(Word32 Rs, Word32 Rt)

Pd=!cmp.gt(Rs,Rt)

Byte Q6_p_not_cmp_gt_RR(Word32 Rs, Word32 Rt)

Pd=!cmp.gtu(Rs,Rt)

Byte Q6_p_not_cmp_gtu_RR(Word32 Rs, Word32 Rt)
#### Compare to general register The register form compares two 32-bit registers for unsigned greater than, greater than, or equal. The immediate form compares a register against a signed or unsigned immediate value. The resulting zero or one is placed in a general register. Compare to general register instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=cmp.eq(Rs,#s8) | apply_extension(s);
Rd=(Rs==s);
Copy to clipboard | | Rd=!cmp.eq(Rs,#s8) | apply_extension(s);
Rd=(Rs!=s);
Copy to clipboard | | Rd=cmp.eq(Rs,Rt) | Rd=(Rs==Rt);
Copy to clipboard | | Rd=!cmp.eq(Rs,Rt) | Rd=(Rs!=Rt);
Copy to clipboard | **Class: ALU32 (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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Rd=cmp.eq(Rs,#s8)

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Rd=!cmp.eq(Rs,#s8)

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Rd=cmp.eq(Rs,Rt)

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Rd=!cmp.eq(Rs,Rt)

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Intrinsics
Compare to general register intrinsics

Rd=cmp.eq(Rs,#s8)

Word32 Q6_R_cmp_eq_RI(Word32 Rs, Word32 Is8)

Rd=!cmp.eq(Rs,#s8)

Word32 Q6_R_not_cmp_eq_RI(Word32 Rs, Word32 Is8)

Rd=cmp.eq(Rs,Rt)

Word32 Q6_R_cmp_eq_RR(Word32 Rs, Word32 Rt)

Rd=!cmp.eq(Rs,Rt)

Word32 Q6_R_not_cmp_eq_RR(Word32 Rs, Word32 Rt)
## CR The CR instruction class includes instructions which manage control registers, including hardware looping, modulo addressing, and status flags. CR instructions are executable on slot 3. ### End loop instructions The endloop instructions mark the end of a hardware loop. If the Loop Count (LC) register indicates that a loop should continue to iterate, the LC register is decremented and the program flow changes to the address in the Start Address (SA) register. The endloopN instruction is actually a pseudo-instruction encoded in bits 15:14 of each instruction. Therefore, no distinct 32-bit encoding exists for this instruction. End loop instructions instructions | **Syntax** | **Behavior** | | --- | --- | | endloop01 | if (USR.LPCFG) {
if (USR.LPCFG==1) {
P3=0xff;
}
USR.LPCFG=USR.LPCFG-1;
}
if (LC0>1) {
PC=SA0;
LC0=LC0-1;
} else {
if (LC1>1) {
PC=SA1;
LC1=LC1-1;
}
}
Copy to clipboard | | endloop0 | if (USR.LPCFG) {
if (USR.LPCFG==1) {
P3=0xff;
}
USR.LPCFG=USR.LPCFG-1;
}
if (LC0>1) {
PC=SA0;
LC0=LC0-1;
}
Copy to clipboard | | endloop1 | if (LC1>1) {
PC=SA1;
LC1=LC1-1;
}
Copy to clipboard | **Class: CR (slots 0,1,2,3)** Note - This instruction cannot be grouped in a packet with any program flow instructions. - The Next PC value is the address immediately following the last instruction in the packet containing this instruction. - The PC value is the address of the start of the packet
Encodings
Bitmap

Syntax

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### Corner detection acceleration The FASTCORNER9 instruction takes the Ps and Pt values and treats them as a circular bit string. If any contiguous nine bits are set around the circle, the result is true, false otherwise. The sense may be optionally inverted. This instruction is used to accelerate FAST corner detection. Corner detection acceleration instructions | **Syntax** | **Behavior** | | --- | --- | | Pd=fastcorner9(Ps,Pt) | tmp.h[0]=(Ps<<8)|Pt;
tmp.h[1]=(Ps<<8)|Pt;
for (i = 1; i < 9; i++) {
tmp &= tmp >> 1;
}
Pd = tmp != 0 ? 0xff : 0x00;
Copy to clipboard | | Pd=!fastcorner9(Ps,Pt) | tmp.h[0]=(Ps<<8)|Pt;
tmp.h[1]=(Ps<<8)|Pt;
for (i = 1; i < 9; i++) {
tmp &= tmp >> 1;
}
Pd = tmp == 0 ? 0xff : 0x00;
Copy to clipboard | **Class: CR (slots 2,3)** Note - This instruction may execute on either slot2 or slot3, even though it is a CR-type
Encodings
Bitmap

Syntax

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Pd=fastcorner9(Ps,Pt)

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Pd=!fastcorner9(Ps,Pt)

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Intrinsics
Corner detection acceleration intrinsics

Pd=fastcorner9(Ps,Pt)

Byte Q6_p_fastcorner9_pp(Byte Ps, Byte Pt)

Pd=!fastcorner9(Ps,Pt)

Byte Q6_p_not_fastcorner9_pp(Byte Ps, Byte Pt)
### Logical reductions on predicates The ANY8 instruction sets a destination predicate register to 0xff if any of the low 8 bits in source predicate register Ps are set. Otherwise, the predicate is set to 0x00. The ALL8 instruction sets a destination predicate register to 0xff if all of the low 8 bits in the source predicate register Ps are set. Otherwise, the predicate is set to 0x00. Logical reductions on predicates instructions | **Syntax** | **Behavior** | | --- | --- | | Pd=any8(Ps) | Pd = (Ps ? 0xff : 0x00);
Copy to clipboard | | Pd=all8(Ps) | Pd = (Ps == 0xff ? 0xff : 0x00);
Copy to clipboard | **Class: CR (slots 2,3)** Note - This instruction may execute on either slot2 or slot3, even though it is a CR-type
Encodings
Bitmap

Syntax

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Pd=any8(Ps)

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Pd=all8(Ps)

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Intrinsics
Logical reductions on predicates intrinsics

Pd=any8(Ps)

Byte Q6_p_any8_p(Byte Ps)

Pd=all8(Ps)

Byte Q6_p_all8_p(Byte Ps)
### Looping instructions loopN is a single instruction which sets up a hardware loop. The N in the instruction name indicates the set of loop registers to use. Loop0 is the innermost loop, while loop1 is the outer loop.The loopN instruction first sets the Start Address (SA) register based on a PC-relative immediate add. The relative immediate is added to the PC and stored in SA. The Loop Count (LC) register is set to either an unsigned immediate or to a register value. Looping instructions instructions | **Syntax** | **Behavior** | | --- | --- | | loop0(#r7:2,Rs) | apply_extension(r);
r=r & ~PCALIGN_MASK;
SA0=PC+r;
LC0=Rs;
USR.LPCFG=0;
Copy to clipboard | | loop1(#r7:2,Rs) | apply_extension(r);
r=r & ~PCALIGN_MASK;
SA1=PC+r;
LC1=Rs;
Copy to clipboard | | loop0(#r7:2,#U10) | apply_extension(r);
r=r & ~PCALIGN_MASK;
SA0=PC+r;
LC0=U;
USR.LPCFG=0;
Copy to clipboard | | loop1(#r7:2,#U10) | apply_extension(r);
r=r & ~PCALIGN_MASK;
SA1=PC+r;
LC1=U;
Copy to clipboard | **Class: CR (slots 3)** Note - This instruction cannot execute in the last address of a hardware loop. - The Next PC value is the address immediately following the last instruction in the packet containing this instruction. - The PC value is the address of the start of the packet - A PC-relative address is formed by taking the decoded immediate value and adding it to the current PC value.
Encodings
Bitmap

Syntax

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loop0(#r7:2,Rs)

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loop1(#r7:2,Rs)

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loop0(#r7:2,#U10)

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loop1(#r7:2,#U10)

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### Add to PC Add an immediate value to the Program Counter (PC) and place the result in a destination register. This instruction is typically used with a constant extender to add a 32-bit immediate value to PC. Add to PC instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=add(pc,#u6) | Rd=PC+apply_extension(u);
Copy to clipboard | **Class: CR (slots 3)**
Encodings
Bitmap

Syntax

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Rd=add(pc,#u6)

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### Pipelined loop instructions spNloop0 is a single instruction which sets up a hardware loop with automatic predicate control. This features saves code size by enabling many software pipelined loops to be generated without prologue code. Upon executing this instruction, the P3 register is automatically cleared. After the loop has been executed N times (where N is selectable from 1-3), the P3 register is set. The intent is that store instructions in the loop are predicated with P3 and thus not enabled during the pipeline warm-up. In the spNloop0 instruction the loop 0 (inner-loop) registers are used. This instruction sets the Start Address (SA0) register based on a PC-relative immediate add. The relative immediate is added to the PC and stored in SA0. The Loop Count (LC0) is set to either an unsigned immediate or to a register value. The predicate P3 is cleared. The USR.LPCFG bits are set based on the N value. Pipelined loop instructions instructions | **Syntax** | **Behavior** | | --- | --- | | p3=sp1loop0(#r7:2,Rs) | apply_extension(r);
r=r & ~PCALIGN_MASK;
SA0=PC+r;
LC0=Rs;
USR.LPCFG=1;
P3=0;
Copy to clipboard | | p3=sp1loop0(#r7:2,#U10) | apply_extension(r);
r=r & ~PCALIGN_MASK;
SA0=PC+r;
LC0=U;
USR.LPCFG=1;
P3=0;
Copy to clipboard | | p3=sp2loop0(#r7:2,Rs) | apply_extension(r);
r=r & ~PCALIGN_MASK;
SA0=PC+r;
LC0=Rs;
USR.LPCFG=2;
P3=0;
Copy to clipboard | | p3=sp2loop0(#r7:2,#U10) | apply_extension(r);
r=r & ~PCALIGN_MASK;
SA0=PC+r;
LC0=U;
USR.LPCFG=2;
P3=0;
Copy to clipboard | | p3=sp3loop0(#r7:2,Rs) | apply_extension(r);
r=r & ~PCALIGN_MASK;
SA0=PC+r;
LC0=Rs;
USR.LPCFG=3;
P3=0;
Copy to clipboard | | p3=sp3loop0(#r7:2,#U10) | apply_extension(r);
r=r & ~PCALIGN_MASK;
SA0=PC+r;
LC0=U;
USR.LPCFG=3;
P3=0;
Copy to clipboard | **Class: CR (slots 3)** Note - The predicate generated by this instruction can not be used as a .new predicate, nor can it be automatically ANDed with another predicate. - This instruction cannot execute in the last address of a hardware loop. - The Next PC value is the address immediately following the last instruction in the packet containing this instruction. - The PC value is the address of the start of the packet - A PC-relative address is formed by taking the decoded immediate value and adding it to the current PC value.
Encodings
Bitmap

Syntax

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p3=sp1loop0(#r7:2,Rs)

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p3=sp1loop0(#r7:2,#U10)

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p3=sp2loop0(#r7:2,Rs)

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p3=sp2loop0(#r7:2,#U10)

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p3=sp3loop0(#r7:2,Rs)

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p3=sp3loop0(#r7:2,#U10)

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### Logical operations on predicates Perform bitwise logical operations on predicate registers. Logical operations on predicates instructions | **Syntax** | **Behavior** | | --- | --- | | Pd=and(Pt,Ps) | Pd=Ps & Pt;
Copy to clipboard | | Pd=or(Pt,Ps) | Pd=Ps | Pt;
Copy to clipboard | | Pd=xor(Ps,Pt) | Pd=Ps ^ Pt;
Copy to clipboard | | Pd=and(Pt,!Ps) | Pd=Pt & (~Ps);
Copy to clipboard | | Pd=not(Ps) | Pd=~Ps;
Copy to clipboard | | Pd=or(Pt,!Ps) | Pd=Pt | (~Ps);
Copy to clipboard | | Pd=and(Ps,and(Pt,Pu)) | Pd = Ps & Pt & Pu;
Copy to clipboard | | Pd=and(Ps,or(Pt,Pu)) | Pd = Ps & (Pt | Pu);
Copy to clipboard | | Pd=or(Ps,and(Pt,Pu)) | Pd = Ps | (Pt & Pu);
Copy to clipboard | | Pd=or(Ps,or(Pt,Pu)) | Pd = Ps | Pt | Pu;
Copy to clipboard | | Pd=and(Ps,and(Pt,!Pu)) | Pd = Ps & Pt & (~Pu);
Copy to clipboard | | Pd=and(Ps,or(Pt,!Pu)) | Pd = Ps & (Pt | (~Pu));
Copy to clipboard | | Pd=or(Ps,and(Pt,!Pu)) | Pd = Ps | (Pt & (~Pu));
Copy to clipboard | | Pd=or(Ps,or(Pt,!Pu)) | Pd = Ps | Pt | (~Pu);
Copy to clipboard | | Pd=Ps | Assembler mapped to: "Pd=or(Ps,Ps)"
Copy to clipboard | **Class: CR (slots 2,3)** Note - This instruction may execute on either slot2 or slot3, even though it is a CR-type
Encodings
Bitmap

Syntax

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Pd=and(Pt,Ps)

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Pd=or(Pt,Ps)

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Pd=xor(Ps,Pt)

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Pd=and(Pt,!Ps)

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Pd=not(Ps)

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Pd=or(Pt,!Ps)

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Pd=and(Ps,and(Pt,Pu))

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Pd=and(Ps,or(Pt,Pu))

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Pd=or(Ps,and(Pt,Pu))

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Pd=or(Ps,or(Pt,Pu))

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Pd=and(Ps,and(Pt,!Pu))

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Pd=and(Ps,or(Pt,!Pu))

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Pd=or(Ps,and(Pt,!Pu))

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Pd=or(Ps,or(Pt,!Pu))

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Intrinsics
Logical operations on predicates intrinsics

Pd=and(Pt,Ps)

Byte Q6_p_and_pp(Byte Pt, Byte Ps)

Pd=or(Pt,Ps)

Byte Q6_p_or_pp(Byte Pt, Byte Ps)

Pd=xor(Ps,Pt)

Byte Q6_p_xor_pp(Byte Ps, Byte Pt)

Pd=and(Pt,!Ps)

Byte Q6_p_and_pnp(Byte Pt, Byte Ps)

Pd=not(Ps)

Byte Q6_p_not_p(Byte Ps)

Pd=or(Pt,!Ps)

Byte Q6_p_or_pnp(Byte Pt, Byte Ps)

Pd=and(Ps,and(Pt,Pu))

Byte Q6_p_and_and_ppp(Byte Ps, Byte Pt, Byte Pu)

Pd=and(Ps,or(Pt,Pu))

Byte Q6_p_and_or_ppp(Byte Ps, Byte Pt, Byte Pu)

Pd=or(Ps,and(Pt,Pu))

Byte Q6_p_or_and_ppp(Byte Ps, Byte Pt, Byte Pu)

Pd=or(Ps,or(Pt,Pu))

Byte Q6_p_or_or_ppp(Byte Ps, Byte Pt, Byte Pu)

Pd=and(Ps,and(Pt,!Pu))

Byte Q6_p_and_and_ppnp(Byte Ps, Byte Pt, Byte Pu)

Pd=and(Ps,or(Pt,!Pu))

Byte Q6_p_and_or_ppnp(Byte Ps, Byte Pt, Byte Pu)

Pd=or(Ps,and(Pt,!Pu))

Byte Q6_p_or_and_ppnp(Byte Ps, Byte Pt, Byte Pu)

Pd=or(Ps,or(Pt,!Pu))

Byte Q6_p_or_or_ppnp(Byte Ps, Byte Pt, Byte Pu)

Pd=Ps

Byte Q6_p_equals_p(Byte Ps)
### User control register transfer Move 32- or 64-bit values between a user control register and a general register. The user control registers include SA, LC, Predicates, M, USR, PC, UGP, GP, and CS, and UPCYCLE. The figure shows the user control registers and their register field encodings. Registers can be moved as singles or as aligned 64-bit pairs. Note that the PC register is not writable. A program flow instruction must be used to change the PC value. pic_addh Page-1 Sheet.117 Rectangle.72 LC0 LC0 Rectangle.5.73 SA0 SA0 Rectangle.3 LC1 LC1 Rectangle.4 SA1 SA1 Rectangle.76 M0 M0 Rectangle.6 P3:0 P3:0 Sheet.78 0 0 Sheet.79 1 1 Sheet.80 2 2 Sheet.81 3 3 Sheet.82 4 4 Sheet.83 5 5 Sheet.84 6 6 Rectangle.85 UGP UGP Rectangle.86 PC PC Sheet.87 8 8 Sheet.88 9 9 Sheet.89 10 10 Sheet.90 15 15 Rectangle.68 M1 M1 Sheet.92 7 7 Rectangle.93 USR USR Rectangle.94 Reserved Reserved Sheet.95 11 11 Sheet.96 12 12 Sheet.100 24 24 Sheet.103 31 31 Rectangle.106 GP GP Rectangle.33 Reserved Reserved Sheet.109 16 16 Sheet.110 23 23 Rectangle.41 CS0 CS0 Rectangle.43 CS1 CS1 Sheet.113 13 13 Rectangle.16 UPCYCLELO UPCYCLELO Rectangle.45 UPCYCLEHI UPCYCLEHI Sheet.116 14 14 Rectangle.97 Reserved Reserved User control register transfer instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=Cs | Rd=Cs;
Copy to clipboard | | Cd=Rs | Cd=Rs;
Copy to clipboard | | Rdd=Css | Rdd=Css;
Copy to clipboard | | Cdd=Rss | Cdd=Rss;
Copy to clipboard | **Class: CR (slots 3)**
Encodings
Bitmap

Syntax

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Rd=Cs

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Cd=Rs

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Rdd=Css

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Cdd=Rss

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## JR The JR instruction class includes instructions to change the program flow to a new location contained in a register. JR instructions are executable on slot 2. ### Call subroutine from register Change the program flow to a subroutine. This instruction first transfers the Next Program Counter (NPC) value into the Link Register, and then jumps to a target address contained in a register. This instruction can only appear in slot 2. Call subroutine from register instructions | **Syntax** | **Behavior** | | --- | --- | | callr Rs | LR=NPC;
PC=Rs;
Copy to clipboard | | if (Pu) callr Rs | ;
if (Pu[0]) {
LR=NPC;
PC=Rs;
}
Copy to clipboard | | if (!Pu) callr Rs | ;
if (!Pu[0]) {
LR=NPC;
PC=Rs;
}
Copy to clipboard | | callrh Rs | LR=NPC;
PC=Rs;
Copy to clipboard | **Class: JR (slots 2)** Note - This instruction can be conditionally executed based on the value of a predicate register. If the instruction is preceded by ‘if Pn’, then the instruction only executes if the least-significant bit of the predicate register is 1. Similarly, if the instruction is preceded by ‘if !Pn’, then the instruction is executed only if the least-significant bit of Pn is 0.
Encodings
Bitmap

Syntax

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callr Rs

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callrh Rs

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### Hinted call subroutine from register Change the program flow to a subroutine. This instruction first transfers the Next Program Counter (NPC) value into the Link Register, and then jumps to a target address contained in a register. This instruction is effective only when a preceding hintjr exists. This instruction can only appear in slot 2. Hinted call subroutine from register instructions | **Syntax** | **Behavior** | | --- | --- | | callrh Rs | LR=NPC;
PC=Rs;
Copy to clipboard | **Class: JR (slots 2)**
Encodings
Bitmap

Syntax

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callrh Rs

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### Hint an indirect jump address Provide a hint indicating that there will soon be an indirect call to the address specified in Rs. The indirect call can be either jumprh or callrh. This instruction can appear in either slot 2 or slot 3. Hint an indirect jump address instructions | **Syntax** | **Behavior** | | --- | --- | | hintjr(Rs) | ;
Copy to clipboard | **Class: JR (slots 2,3)**
Encodings
Bitmap

Syntax

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hintjr(Rs)

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### Jump to address from register Change the program flow to a target address. This instruction changes the Program Counter to a target address contained in a register. This instruction can appear only in slot 2. Jump to address from register instructions | **Syntax** | **Behavior** | | --- | --- | | jumpr Rs | PC=Rs;
Copy to clipboard | | jumprh Rs | PC=Rs;
Copy to clipboard | | if (Pu) jumpr:nt Rs | if (Pu[0]) {
PC=Rs;
}
Copy to clipboard | | if (!Pu) jumpr:nt Rs | if (!Pu[0]) {
PC=Rs;
}
Copy to clipboard | | if (Pu) jumpr:t Rs | if (Pu[0]) {
PC=Rs;
}
Copy to clipboard | | if (!Pu) jumpr:t Rs | if (!Pu[0]) {
PC=Rs;
}
Copy to clipboard | | if (Pu) jumpr Rs | Assembler mapped to: "if (Pu) jumpr:nt Rs"
Copy to clipboard | | if (!Pu) jumpr Rs | Assembler mapped to: "if (!Pu) jumpr:nt Rs"
Copy to clipboard | | if (Pu.new) jumpr:nt Rs | }
{
if(Pu.new[0]){
PC=Rs;
}
Copy to clipboard | | if (!Pu.new) jumpr:nt Rs | }
{
if(!Pu.new[0]){
PC=Rs;
}
Copy to clipboard | | if (Pu.new) jumpr:t Rs | }
{
if(Pu.new[0]){
PC=Rs;
}
Copy to clipboard | | if (!Pu.new) jumpr:t Rs | }
{
if(!Pu.new[0]){
PC=Rs;
}
Copy to clipboard | **Class: JR (slots 2)** Note - This instruction can be conditionally executed based on the value of a predicate register. If the instruction is preceded by ‘if Pn’, then the instruction only executes if the least-significant bit of the predicate register is 1. Similarly, if the instruction is preceded by ‘if !Pn’, then the instruction is executed only if the least-significant bit of Pn is 0.
Encodings
Bitmap

Syntax

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jumpr Rs

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if (Pu.new) jumpr:nt Rs

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if (!Pu.new) jumpr:nt Rs

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if (!Pu.new) jumpr:t Rs

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### Hinted jump to address from register Change the program flow to a target address. This instruction changes the Program Counter to a target address contained in a register. This instruction is effective only when a preceding hintjr exists. This instruction can appear only in slot 2. Hinted jump to address from register instructions | **Syntax** | **Behavior** | | --- | --- | | jumprh Rs | PC=Rs;
Copy to clipboard | **Class: JR (slots 2)**
Encodings
Bitmap

Syntax

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jumprh Rs

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## J The J instruction class includes branch instructions (jumps and calls) that obtain the target address from a (PC-relative) immediate address value. J instructions are executable on slot 2 and slot 3. ### Call subroutine Change the program flow to a subroutine. This instruction first transfers the Next Program Counter (NPC) value into the Link Register, and then jumps to the target address. This instruction can appear in slots 2 or 3. Call subroutine instructions | **Syntax** | **Behavior** | | --- | --- | | call #r22:2 | apply_extension(r);
r=r & ~PCALIGN_MASK;
LR=NPC;
PC=PC+r;
Copy to clipboard | | if (Pu) call #r15:2 | apply_extension(r);
r=r & ~PCALIGN_MASK;
if (Pu[0]) {
LR=NPC;
PC=PC+r;
}
Copy to clipboard | | if (!Pu) call #r15:2 | apply_extension(r);
r=r & ~PCALIGN_MASK;
if (!Pu[0]) {
LR=NPC;
PC=PC+r;
}
Copy to clipboard | **Class: J (slots 2,3)** Note - This instruction can be conditionally executed based on the value of a predicate register. If the instruction is preceded by ‘if Pn’, then the instruction only executes if the least-significant bit of the predicate register is 1. Similarly, if the instruction is preceded by ‘if !Pn’, then the instruction is executed only if the least-significant bit of Pn is 0. - The Next PC value is the address immediately following the last instruction in the packet containing this instruction. - The PC value is the address of the start of the packet - A PC-relative address is formed by taking the decoded immediate value and adding it to the current PC value.
Encodings
Bitmap

Syntax

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call #r22:2

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if (Pu) call #r15:2

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if (!Pu) call #r15:2

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### Compare and jump Compare two registers, or a register and immediate value, and write a predicate with the result. Then use the predicate result to conditionally jump to a PC-relative target address. The registers available as operands are restricted to R0-R7 and R16-R23. The predicate destination is restricted to P0 and P1. In assembly syntax, this instruction appears as two instructions in the packet: a compare and a separate conditional jump. The assembler may convert adjacent compare and jump instructions into compound compare-jump form. Compare and jump instructions | **Syntax** | **Behavior** | | --- | --- | | p0=cmp.eq(Rs,#U5); if (p0.new) jump:nt #r9:2 | P0=(Rs==U) ? 0xff : 0x00 if (P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.eq(Rs,#U5); if (!p0.new) jump:nt #r9:2 | P0=(Rs==U) ? 0xff : 0x00 if (!P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.eq(Rs,#U5); if (p0.new) jump:t #r9:2 | P0=(Rs==U) ? 0xff : 0x00 if (P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.eq(Rs,#U5); if (!p0.new) jump:t #r9:2 | P0=(Rs==U) ? 0xff : 0x00 if (!P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.eq(Rs,#U5); if (p1.new) jump:nt #r9:2 | P1=(Rs==U) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.eq(Rs,#U5); if (!p1.new) jump:nt #r9:2 | P1=(Rs==U) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.eq(Rs,#U5); if (p1.new) jump:t #r9:2 | P1=(Rs==U) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.eq(Rs,#U5); if (!p1.new) jump:t #r9:2 | P1=(Rs==U) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.gt(Rs,#U5); if (p0.new) jump:nt #r9:2 | P0=(Rs>U) ? 0xff : 0x00 if (P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.gt(Rs,#U5); if (!p0.new) jump:nt #r9:2 | P0=(Rs>U) ? 0xff : 0x00 if (!P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.gt(Rs,#U5); if (p0.new) jump:t #r9:2 | P0=(Rs>U) ? 0xff : 0x00 if (P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.gt(Rs,#U5); if (!p0.new) jump:t #r9:2 | P0=(Rs>U) ? 0xff : 0x00 if (!P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.gt(Rs,#U5); if (p1.new) jump:nt #r9:2 | P1=(Rs>U) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.gt(Rs,#U5); if (!p1.new) jump:nt #r9:2 | P1=(Rs>U) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.gt(Rs,#U5); if (p1.new) jump:t #r9:2 | P1=(Rs>U) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.gt(Rs,#U5); if (!p1.new) jump:t #r9:2 | P1=(Rs>U) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.gtu(Rs,#U5); if (p0.new) jump:nt #r9:2 | P0=(Rs.uw[0]>U) ? 0xff : 0x00 if (P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.gtu(Rs,#U5); if (!p0.new) jump:nt #r9:2 | P0=(Rs.uw[0]>U) ? 0xff : 0x00 if (!P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.gtu(Rs,#U5); if (p0.new) jump:t #r9:2 | P0=(Rs.uw[0]>U) ? 0xff : 0x00 if (P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.gtu(Rs,#U5); if (!p0.new) jump:t #r9:2 | P0=(Rs.uw[0]>U) ? 0xff : 0x00 if (!P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.gtu(Rs,#U5); if (p1.new) jump:nt #r9:2 | P1=(Rs.uw[0]>U) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.gtu(Rs,#U5); if (!p1.new) jump:nt #r9:2 | P1=(Rs.uw[0]>U) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.gtu(Rs,#U5); if (p1.new) jump:t #r9:2 | P1=(Rs.uw[0]>U) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.gtu(Rs,#U5); if (!p1.new) jump:t #r9:2 | P1=(Rs.uw[0]>U) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.eq(Rs,#-1); if (p0.new) jump:nt #r9:2 | P0=(Rs==-1) ? 0xff : 0x00 if (P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.eq(Rs,#-1); if (!p0.new) jump:nt #r9:2 | P0=(Rs==-1) ? 0xff : 0x00 if (!P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.eq(Rs,#-1); if (p0.new) jump:t #r9:2 | P0=(Rs==-1) ? 0xff : 0x00 if (P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.eq(Rs,#-1); if (!p0.new) jump:t #r9:2 | P0=(Rs==-1) ? 0xff : 0x00 if (!P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.eq(Rs,#-1); if (p1.new) jump:nt #r9:2 | P1=(Rs==-1) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.eq(Rs,#-1); if (!p1.new) jump:nt #r9:2 | P1=(Rs==-1) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.eq(Rs,#-1); if (p1.new) jump:t #r9:2 | P1=(Rs==-1) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.eq(Rs,#-1); if (!p1.new) jump:t #r9:2 | P1=(Rs==-1) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.gt(Rs,#-1); if (p0.new) jump:nt #r9:2 | P0=(Rs>-1) ? 0xff : 0x00 if (P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.gt(Rs,#-1); if (!p0.new) jump:nt #r9:2 | P0=(Rs>-1) ? 0xff : 0x00 if (!P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.gt(Rs,#-1); if (p0.new) jump:t #r9:2 | P0=(Rs>-1) ? 0xff : 0x00 if (P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.gt(Rs,#-1); if (!p0.new) jump:t #r9:2 | P0=(Rs>-1) ? 0xff : 0x00 if (!P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.gt(Rs,#-1); if (p1.new) jump:nt #r9:2 | P1=(Rs>-1) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.gt(Rs,#-1); if (!p1.new) jump:nt #r9:2 | P1=(Rs>-1) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.gt(Rs,#-1); if (p1.new) jump:t #r9:2 | P1=(Rs>-1) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.gt(Rs,#-1); if (!p1.new) jump:t #r9:2 | P1=(Rs>-1) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=tstbit(Rs,#0); if (p0.new) jump:nt #r9:2 | P0=(Rs & 1) ? 0xff : 0x00 if (P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=tstbit(Rs,#0); if (!p0.new) jump:nt #r9:2 | P0=(Rs & 1) ? 0xff : 0x00 if (!P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=tstbit(Rs,#0); if (p0.new) jump:t #r9:2 | P0=(Rs & 1) ? 0xff : 0x00 if (P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=tstbit(Rs,#0); if (!p0.new) jump:t #r9:2 | P0=(Rs & 1) ? 0xff : 0x00 if (!P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=tstbit(Rs,#0); if (p1.new) jump:nt #r9:2 | P1=(Rs & 1) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=tstbit(Rs,#0); if (!p1.new) jump:nt #r9:2 | P1=(Rs & 1) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=tstbit(Rs,#0); if (p1.new) jump:t #r9:2 | P1=(Rs & 1) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=tstbit(Rs,#0); if (!p1.new) jump:t #r9:2 | P1=(Rs & 1) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.eq(Rs,Rt); if (p0.new) jump:nt #r9:2 | P0=(Rs==Rt) ? 0xff : 0x00 if (P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.eq(Rs,Rt); if (!p0.new) jump:nt #r9:2 | P0=(Rs==Rt) ? 0xff : 0x00 if (!P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.eq(Rs,Rt); if (p0.new) jump:t #r9:2 | P0=(Rs==Rt) ? 0xff : 0x00 if (P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.eq(Rs,Rt); if (!p0.new) jump:t #r9:2 | P0=(Rs==Rt) ? 0xff : 0x00 if (!P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.eq(Rs,Rt); if (p1.new) jump:nt #r9:2 | P1=(Rs==Rt) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.eq(Rs,Rt); if (!p1.new) jump:nt #r9:2 | P1=(Rs==Rt) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.eq(Rs,Rt); if (p1.new) jump:t #r9:2 | P1=(Rs==Rt) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.eq(Rs,Rt); if (!p1.new) jump:t #r9:2 | P1=(Rs==Rt) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.gt(Rs,Rt); if (p0.new) jump:nt #r9:2 | P0=(Rs>Rt) ? 0xff : 0x00 if (P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.gt(Rs,Rt); if (!p0.new) jump:nt #r9:2 | P0=(Rs>Rt) ? 0xff : 0x00 if (!P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.gt(Rs,Rt); if (p0.new) jump:t #r9:2 | P0=(Rs>Rt) ? 0xff : 0x00 if (P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.gt(Rs,Rt); if (!p0.new) jump:t #r9:2 | P0=(Rs>Rt) ? 0xff : 0x00 if (!P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.gt(Rs,Rt); if (p1.new) jump:nt #r9:2 | P1=(Rs>Rt) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.gt(Rs,Rt); if (!p1.new) jump:nt #r9:2 | P1=(Rs>Rt) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.gt(Rs,Rt); if (p1.new) jump:t #r9:2 | P1=(Rs>Rt) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.gt(Rs,Rt); if (!p1.new) jump:t #r9:2 | P1=(Rs>Rt) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.gtu(Rs,Rt); if (p0.new) jump:nt #r9:2 | P0=(Rs.uw[0]>Rt) ? 0xff : 0x00 if (P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.gtu(Rs,Rt); if (!p0.new) jump:nt #r9:2 | P0=(Rs.uw[0]>Rt) ? 0xff : 0x00 if (!P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.gtu(Rs,Rt); if (p0.new) jump:t #r9:2 | P0=(Rs.uw[0]>Rt) ? 0xff : 0x00 if (P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p0=cmp.gtu(Rs,Rt); if (!p0.new) jump:t #r9:2 | P0=(Rs.uw[0]>Rt) ? 0xff : 0x00 if (!P0.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.gtu(Rs,Rt); if (p1.new) jump:nt #r9:2 | P1=(Rs.uw[0]>Rt) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.gtu(Rs,Rt); if (!p1.new) jump:nt #r9:2 | P1=(Rs.uw[0]>Rt) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.gtu(Rs,Rt); if (p1.new) jump:t #r9:2 | P1=(Rs.uw[0]>Rt) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | p1=cmp.gtu(Rs,Rt); if (!p1.new) jump:t #r9:2 | P1=(Rs.uw[0]>Rt) ? 0xff : 0x00 if (P1.new[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | **Class: J (slots 0,1,2,3)**
Encodings
Bitmap

Syntax

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p0=cmp.eq(Rs,#U5); if (p0.new) jump:nt #r9:2

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p0=cmp.eq(Rs,#U5); if (!p0.new) jump:nt #r9:2

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p0=cmp.eq(Rs,#U5); if (p0.new) jump:t #r9:2

0

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p0=cmp.eq(Rs,#U5); if (!p0.new) jump:t #r9:2

0

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p1=cmp.eq(Rs,#U5); if (p1.new) jump:nt #r9:2

0

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0

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p1=cmp.eq(Rs,#U5); if (!p1.new) jump:nt #r9:2

0

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p1=cmp.eq(Rs,#U5); if (p1.new) jump:t #r9:2

0

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p1=cmp.eq(Rs,#U5); if (!p1.new) jump:t #r9:2

0

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p0=cmp.gt(Rs,#U5); if (p0.new) jump:nt #r9:2

0

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p0=cmp.gt(Rs,#U5); if (!p0.new) jump:nt #r9:2

0

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p0=cmp.gt(Rs,#U5); if (p0.new) jump:t #r9:2

0

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p0=cmp.gt(Rs,#U5); if (!p0.new) jump:t #r9:2

0

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p1=cmp.gt(Rs,#U5); if (p1.new) jump:nt #r9:2

0

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p1=cmp.gt(Rs,#U5); if (!p1.new) jump:nt #r9:2

0

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p1=cmp.gt(Rs,#U5); if (p1.new) jump:t #r9:2

0

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-

p1=cmp.gt(Rs,#U5); if (!p1.new) jump:t #r9:2

0

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-

p0=cmp.gtu(Rs,#U5); if (p0.new) jump:nt #r9:2

0

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0

0

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0

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p0=cmp.gtu(Rs,#U5); if (!p0.new) jump:nt #r9:2

0

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1

0

0

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p0=cmp.gtu(Rs,#U5); if (p0.new) jump:t #r9:2

0

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1

0

0

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-

p0=cmp.gtu(Rs,#U5); if (!p0.new) jump:t #r9:2

0

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1

0

0

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1

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-

p1=cmp.gtu(Rs,#U5); if (p1.new) jump:nt #r9:2

0

0

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1

0

0

1

1

0

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0

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-

p1=cmp.gtu(Rs,#U5); if (!p1.new) jump:nt #r9:2

0

0

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1

0

0

1

1

0

1

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s

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0

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-

p1=cmp.gtu(Rs,#U5); if (p1.new) jump:t #r9:2

0

0

0

1

0

0

1

1

0

0

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1

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-

p1=cmp.gtu(Rs,#U5); if (!p1.new) jump:t #r9:2

0

0

0

1

0

0

1

1

0

1

i

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s

s

s

s

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1

I

I

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i

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-

p0=cmp.eq(Rs,#-1); if (p0.new) jump:nt #r9:2

0

0

0

1

0

0

0

1

1

0

i

i

s

s

s

s

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0

-

-

-

0

0

i

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-

p0=cmp.eq(Rs,#-1); if (!p0.new) jump:nt #r9:2

0

0

0

1

0

0

0

1

1

1

i

i

s

s

s

s

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0

-

-

-

0

0

i

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-

p0=cmp.eq(Rs,#-1); if (p0.new) jump:t #r9:2

0

0

0

1

0

0

0

1

1

0

i

i

s

s

s

s

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1

-

-

-

0

0

i

i

i

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-

p0=cmp.eq(Rs,#-1); if (!p0.new) jump:t #r9:2

0

0

0

1

0

0

0

1

1

1

i

i

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s

s

s

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1

-

-

-

0

0

i

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-

p1=cmp.eq(Rs,#-1); if (p1.new) jump:nt #r9:2

0

0

0

1

0

0

1

1

1

0

i

i

s

s

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s

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0

-

-

-

0

0

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-

p1=cmp.eq(Rs,#-1); if (!p1.new) jump:nt #r9:2

0

0

0

1

0

0

1

1

1

1

i

i

s

s

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s

P

P

0

-

-

-

0

0

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p1=cmp.eq(Rs,#-1); if (p1.new) jump:t #r9:2

0

0

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1

0

0

1

1

1

0

i

i

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s

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s

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1

-

-

-

0

0

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-

p1=cmp.eq(Rs,#-1); if (!p1.new) jump:t #r9:2

0

0

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1

0

0

1

1

1

1

i

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s

s

s

P

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1

-

-

-

0

0

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i

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-

p0=cmp.gt(Rs,#-1); if (p0.new) jump:nt #r9:2

0

0

0

1

0

0

0

1

1

0

i

i

s

s

s

s

P

P

0

-

-

-

0

1

i

i

i

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-

p0=cmp.gt(Rs,#-1); if (!p0.new) jump:nt #r9:2

0

0

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1

0

0

0

1

1

1

i

i

s

s

s

s

P

P

0

-

-

-

0

1

i

i

i

i

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i

i

-

p0=cmp.gt(Rs,#-1); if (p0.new) jump:t #r9:2

0

0

0

1

0

0

0

1

1

0

i

i

s

s

s

s

P

P

1

-

-

-

0

1

i

i

i

i

i

i

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-

p0=cmp.gt(Rs,#-1); if (!p0.new) jump:t #r9:2

0

0

0

1

0

0

0

1

1

1

i

i

s

s

s

s

P

P

1

-

-

-

0

1

i

i

i

i

i

i

i

-

p1=cmp.gt(Rs,#-1); if (p1.new) jump:nt #r9:2

0

0

0

1

0

0

1

1

1

0

i

i

s

s

s

s

P

P

0

-

-

-

0

1

i

i

i

i

i

i

i

-

p1=cmp.gt(Rs,#-1); if (!p1.new) jump:nt #r9:2

0

0

0

1

0

0

1

1

1

1

i

i

s

s

s

s

P

P

0

-

-

-

0

1

i

i

i

i

i

i

i

-

p1=cmp.gt(Rs,#-1); if (p1.new) jump:t #r9:2

0

0

0

1

0

0

1

1

1

0

i

i

s

s

s

s

P

P

1

-

-

-

0

1

i

i

i

i

i

i

i

-

p1=cmp.gt(Rs,#-1); if (!p1.new) jump:t #r9:2

0

0

0

1

0

0

1

1

1

1

i

i

s

s

s

s

P

P

1

-

-

-

0

1

i

i

i

i

i

i

i

-

p0=tstbit(Rs,#0); if (p0.new) jump:nt #r9:2

0

0

0

1

0

0

0

1

1

0

i

i

s

s

s

s

P

P

0

-

-

-

1

1

i

i

i

i

i

i

i

-

p0=tstbit(Rs,#0); if (!p0.new) jump:nt #r9:2

0

0

0

1

0

0

0

1

1

1

i

i

s

s

s

s

P

P

0

-

-

-

1

1

i

i

i

i

i

i

i

-

p0=tstbit(Rs,#0); if (p0.new) jump:t #r9:2

0

0

0

1

0

0

0

1

1

0

i

i

s

s

s

s

P

P

1

-

-

-

1

1

i

i

i

i

i

i

i

-

p0=tstbit(Rs,#0); if (!p0.new) jump:t #r9:2

0

0

0

1

0

0

0

1

1

1

i

i

s

s

s

s

P

P

1

-

-

-

1

1

i

i

i

i

i

i

i

-

p1=tstbit(Rs,#0); if (p1.new) jump:nt #r9:2

0

0

0

1

0

0

1

1

1

0

i

i

s

s

s

s

P

P

0

-

-

-

1

1

i

i

i

i

i

i

i

-

p1=tstbit(Rs,#0); if (!p1.new) jump:nt #r9:2

0

0

0

1

0

0

1

1

1

1

i

i

s

s

s

s

P

P

0

-

-

-

1

1

i

i

i

i

i

i

i

-

p1=tstbit(Rs,#0); if (p1.new) jump:t #r9:2

0

0

0

1

0

0

1

1

1

0

i

i

s

s

s

s

P

P

1

-

-

-

1

1

i

i

i

i

i

i

i

-

p1=tstbit(Rs,#0); if (!p1.new) jump:t #r9:2

0

0

0

1

0

0

1

1

1

1

i

i

s

s

s

s

P

P

1

-

-

-

1

1

i

i

i

i

i

i

i

-

p0=cmp.eq(Rs,Rt); if (p0.new) jump:nt #r9:2

0

0

0

1

0

1

0

0

0

0

i

i

s

s

s

s

P

P

0

0

t

t

t

t

i

i

i

i

i

i

i

-

p0=cmp.eq(Rs,Rt); if (!p0.new) jump:nt #r9:2

0

0

0

1

0

1

0

0

0

1

i

i

s

s

s

s

P

P

0

0

t

t

t

t

i

i

i

i

i

i

i

-

p0=cmp.eq(Rs,Rt); if (p0.new) jump:t #r9:2

0

0

0

1

0

1

0

0

0

0

i

i

s

s

s

s

P

P

1

0

t

t

t

t

i

i

i

i

i

i

i

-

p0=cmp.eq(Rs,Rt); if (!p0.new) jump:t #r9:2

0

0

0

1

0

1

0

0

0

1

i

i

s

s

s

s

P

P

1

0

t

t

t

t

i

i

i

i

i

i

i

-

p1=cmp.eq(Rs,Rt); if (p1.new) jump:nt #r9:2

0

0

0

1

0

1

0

0

0

0

i

i

s

s

s

s

P

P

0

1

t

t

t

t

i

i

i

i

i

i

i

-

p1=cmp.eq(Rs,Rt); if (!p1.new) jump:nt #r9:2

0

0

0

1

0

1

0

0

0

1

i

i

s

s

s

s

P

P

0

1

t

t

t

t

i

i

i

i

i

i

i

-

p1=cmp.eq(Rs,Rt); if (p1.new) jump:t #r9:2

0

0

0

1

0

1

0

0

0

0

i

i

s

s

s

s

P

P

1

1

t

t

t

t

i

i

i

i

i

i

i

-

p1=cmp.eq(Rs,Rt); if (!p1.new) jump:t #r9:2

0

0

0

1

0

1

0

0

0

1

i

i

s

s

s

s

P

P

1

1

t

t

t

t

i

i

i

i

i

i

i

-

p0=cmp.gt(Rs,Rt); if (p0.new) jump:nt #r9:2

0

0

0

1

0

1

0

0

1

0

i

i

s

s

s

s

P

P

0

0

t

t

t

t

i

i

i

i

i

i

i

-

p0=cmp.gt(Rs,Rt); if (!p0.new) jump:nt #r9:2

0

0

0

1

0

1

0

0

1

1

i

i

s

s

s

s

P

P

0

0

t

t

t

t

i

i

i

i

i

i

i

-

p0=cmp.gt(Rs,Rt); if (p0.new) jump:t #r9:2

0

0

0

1

0

1

0

0

1

0

i

i

s

s

s

s

P

P

1

0

t

t

t

t

i

i

i

i

i

i

i

-

p0=cmp.gt(Rs,Rt); if (!p0.new) jump:t #r9:2

0

0

0

1

0

1

0

0

1

1

i

i

s

s

s

s

P

P

1

0

t

t

t

t

i

i

i

i

i

i

i

-

p1=cmp.gt(Rs,Rt); if (p1.new) jump:nt #r9:2

0

0

0

1

0

1

0

0

1

0

i

i

s

s

s

s

P

P

0

1

t

t

t

t

i

i

i

i

i

i

i

-

p1=cmp.gt(Rs,Rt); if (!p1.new) jump:nt #r9:2

0

0

0

1

0

1

0

0

1

1

i

i

s

s

s

s

P

P

0

1

t

t

t

t

i

i

i

i

i

i

i

-

p1=cmp.gt(Rs,Rt); if (p1.new) jump:t #r9:2

0

0

0

1

0

1

0

0

1

0

i

i

s

s

s

s

P

P

1

1

t

t

t

t

i

i

i

i

i

i

i

-

p1=cmp.gt(Rs,Rt); if (!p1.new) jump:t #r9:2

0

0

0

1

0

1

0

0

1

1

i

i

s

s

s

s

P

P

1

1

t

t

t

t

i

i

i

i

i

i

i

-

p0=cmp.gtu(Rs,Rt); if (p0.new) jump:nt #r9:2

0

0

0

1

0

1

0

1

0

0

i

i

s

s

s

s

P

P

0

0

t

t

t

t

i

i

i

i

i

i

i

-

p0=cmp.gtu(Rs,Rt); if (!p0.new) jump:nt #r9:2

0

0

0

1

0

1

0

1

0

1

i

i

s

s

s

s

P

P

0

0

t

t

t

t

i

i

i

i

i

i

i

-

p0=cmp.gtu(Rs,Rt); if (p0.new) jump:t #r9:2

0

0

0

1

0

1

0

1

0

0

i

i

s

s

s

s

P

P

1

0

t

t

t

t

i

i

i

i

i

i

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p0=cmp.gtu(Rs,Rt); if (!p0.new) jump:t #r9:2

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p1=cmp.gtu(Rs,Rt); if (p1.new) jump:nt #r9:2

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p1=cmp.gtu(Rs,Rt); if (!p1.new) jump:nt #r9:2

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p1=cmp.gtu(Rs,Rt); if (p1.new) jump:t #r9:2

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p1=cmp.gtu(Rs,Rt); if (!p1.new) jump:t #r9:2

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### Jump to address Change the program flow to a target address. This instruction changes the Program Counter to a target address which is relative to the PC address. The offset from the current PC address is contained in the instruction encoding. A speculated jump instruction includes a hint (“taken” or “not taken”) which specifies the expected value of the conditional expression. If the actual generated value of the predicate differs from this expected value, the jump instruction incurs a performance penalty. This instruction can appear in slots 2 or 3. Jump to address instructions | **Syntax** | **Behavior** | | --- | --- | | jump #r22:2 | apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
Copy to clipboard | | if (Pu) jump:nt #r15:2 | if (Pu[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!Pu) jump:nt #r15:2 | if (!Pu[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (Pu) jump:t #r15:2 | if (Pu[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!Pu) jump:t #r15:2 | if (!Pu[0]) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (Pu) jump #r15:2 | Assembler mapped to: "if (Pu) jump:nt r15:2"
Copy to clipboard | | if (!Pu) jump #r15:2 | Assembler mapped to: "if (!Pu) jump:nt r15:2"
Copy to clipboard | **Class: J (slots 0,1,2,3)** Note - This instruction can be conditionally executed based on the value of a predicate register. If the instruction is preceded by ‘if Pn’, then the instruction only executes if the least-significant bit of the predicate register is 1. Similarly, if the instruction is preceded by ‘if !Pn’, then the instruction is executed only if the least-significant bit of Pn is 0.
Encodings
Bitmap

Syntax

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jump #r22:2

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if (Pu) jump:nt #r15:2

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if (!Pu) jump:nt #r15:2

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if (Pu) jump:t #r15:2

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if (!Pu) jump:t #r15:2

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### Jump to address conditioned on new predicate Perform speculated jump. Jump if the LSB of the newly-generated predicate is true. The predicate must be generated in the same packet as the speculated jump instruction. A speculated jump instruction includes a hint (“taken” or “not taken”) which specifies the expected value of the conditional expression. If the actual generated value of the predicate differs from this expected value, the jump instruction incurs a performance penalty. This instruction can appear in slots 2 or 3. Jump to address conditioned on new predicate instructions | **Syntax** | **Behavior** | | --- | --- | | if (Pu.new) jump:nt #r15:2 | }
{
if(Pu.new[0]){
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!Pu.new) jump:nt #r15:2 | }
{
if(!Pu.new[0]){
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (Pu.new) jump:t #r15:2 | }
{
if(Pu.new[0]){
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!Pu.new) jump:t #r15:2 | }
{
if(!Pu.new[0]){
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | **Class: J (slots 0,1,2,3)** Note - This instruction can be conditionally executed based on the value of a predicate register. If the instruction is preceded by ‘if Pn’, then the instruction only executes if the least-significant bit of the predicate register is 1. Similarly, if the instruction is preceded by ‘if !Pn’, then the instruction is executed only if the least-significant bit of Pn is 0.
Encodings
Bitmap

Syntax

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if (Pu.new) jump:nt #r15:2

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if (!Pu.new) jump:nt #r15:2

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if (Pu.new) jump:t #r15:2

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if (!Pu.new) jump:t #r15:2

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### Jump to address condition on register value Perform register-conditional jump. Jump if the specified register expression is true. A register-conditional jump includes a hint (“taken” or “not taken”) which specifies the expected value of the register expression. If the actual generated value of the expression differs from this expected value, the jump instruction incurs a performance penalty. This instruction can appear only in slot 3. Jump to address condition on register value instructions | **Syntax** | **Behavior** | | --- | --- | | if (Rs!=#0) jump:nt #r13:2 | if (Rs != 0) {
PC=PC+r;
}
Copy to clipboard | | if (Rs==#0) jump:nt #r13:2 | if (Rs == 0) {
PC=PC+r;
}
Copy to clipboard | | if (Rs!=#0) jump:t #r13:2 | if (Rs != 0) {
PC=PC+r;
}
Copy to clipboard | | if (Rs==#0) jump:t #r13:2 | if (Rs == 0) {
PC=PC+r;
}
Copy to clipboard | | if (Rs>=#0) jump:nt #r13:2 | if (Rs>=0) {
PC=PC+r;
}
Copy to clipboard | | if (Rs>=#0) jump:t #r13:2 | if (Rs>=0) {
PC=PC+r;
}
Copy to clipboard | | if (Rs<=#0) jump:nt #r13:2 | if (Rs<=0) {
PC=PC+r;
}
Copy to clipboard | | if (Rs<=#0) jump:t #r13:2 | if (Rs<=0) {
PC=PC+r;
}
Copy to clipboard | **Class: J (slots 3)** Note - This instruction will be deprecated in a future version.
Encodings
Bitmap

Syntax

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if (Rs!=#0) jump:nt #r13:2

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if (Rs==#0) jump:nt #r13:2

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if (Rs!=#0) jump:t #r13:2

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if (Rs==#0) jump:t #r13:2

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if (Rs>=#0) jump:nt #r13:2

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if (Rs>=#0) jump:t #r13:2

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if (Rs<=#0) jump:nt #r13:2

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if (Rs<=#0) jump:t #r13:2

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### Transfer and jump Move an unsigned immediate or register value into a destination register and unconditionally jump. In assembly syntax, this instruction appears as two instructions in the packet, a transfer and a separate jump. The assembler may convert adjacent transfer and jump instructions into compound transfer-jump form. Transfer and jump instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=#U6 ; jump #r9:2 | apply_extension(r);
r=r & ~PCALIGN_MASK;
Rd=U;
PC=PC+r;
Copy to clipboard | | Rd=Rs ; jump #r9:2 | apply_extension(r);
r=r & ~PCALIGN_MASK;
Rd=Rs;
PC=PC+r;
Copy to clipboard | **Class: J (slots 2,3)**
Encodings
Bitmap

Syntax

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Rd=#U6 ; jump #r9:2

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Rd=Rs ; jump #r9:2

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## LD The LD instruction class includes load instructions, which are used to load values into registers. LD instructions are executable on slot 0 and slot 1. ### Load doubleword Load a 64-bit doubleword from memory and place in a destination register pair. Load doubleword instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=memd(Rs+#s11:3) | apply_extension(s);
EA=Rs+s;
Rdd = *EA;
Copy to clipboard | | Rdd=memd(Rt<<#u2+#U6) | apply_extension(U);
EA=U+(Rt< Rdd = *EA;
Copy to clipboard | | Rdd=memd(Re=#U6) | apply_extension(U);
EA=U;
Rdd = *EA;
Re=U;
Copy to clipboard | | Rdd=memd(Rx++Mu) | EA=Rx;
Rx=Rx+MuV;
Rdd = *EA;
Copy to clipboard | | Rdd=memd(Rx++Mu:brev) | EA=Rx.h[1] | brev(Rx.h[0]);
Rx=Rx+MuV;
Rdd = *EA;
Copy to clipboard | | Rdd=memd(Rx++#s4:3) | EA=Rx;
Rx=Rx+s;
Rdd = *EA;
Copy to clipboard | | Rdd=memd(Rx++#s4:3:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,s,MuV);
Rdd = *EA;
Copy to clipboard | | Rdd=memd(Rx++I:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,I<<3,MuV);
Rdd = *EA;
Copy to clipboard | | Rdd=memd(Rs) | Assembler mapped to: "Rdd=memd""(Rs+0)"
Copy to clipboard | | Rdd=memd(Rs+Rt<<#u2) | EA=Rs+(Rt< Rdd = *EA;
Copy to clipboard | | Rdd=memd(gp+#u16:3) | apply_extension(u);
EA=(Constant_extended ? (0) : GP)+u;
Rdd = *EA;
Copy to clipboard | **Class: LD (slots 0,1)**
Encodings
Bitmap

Syntax

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Rdd=memd(Rs+#s11:3)

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Rdd=memd(Rt<<#u2+#U6)

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Rdd=memd(Re=#U6)

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Rdd=memd(Rx++Mu)

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Rdd=memd(Rx++Mu:brev)

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Rdd=memd(Rx++#s4:3)

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Rdd=memd(Rx++#s4:3:circ(Mu))

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Rdd=memd(Rx++I:circ(Mu))

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Rdd=memd(Rs+Rt<<#u2)

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Rdd=memd(gp+#u16:3)

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Intrinsics
Load doubleword intrinsics

Rdd=memd(Rx++#s4:3:circ(Mu))

Word32 Q6_R_memd_IM_circ(void** StartAddress, Word32 Is4_3, Word32 Mu, void* BaseAddress)

Rdd=memd(Rx++I:circ(Mu))

Word32 Q6_R_memd_M_circ(void** StartAddress, Word32 Mu, void* BaseAddress)
### Load-acquire doubleword Load a 64-bit doubleword from memory and place in a destination register pair. The load-acquire memory operation is observed before any following memory operations (in program order) have been observed at the local point of serialization. A different order may be observed at the global point of serialization. (see Ordering and Synchronization). Load-acquire doubleword instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=memd\_aq(Rs) | EA=Rs;
Rdd = *EA
Copy to clipboard | **Class: LD (slots 0)**
Encodings
Bitmap

Syntax

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Rdd=memd_aq(Rs)

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### Load doubleword conditionally Load a 64-bit doubleword from memory and place in a destination register pair. This instruction is conditional based on a predicate value. If the predicate is true, the instruction is performed, otherwise it is treated as a NOP. Load doubleword conditionally instructions | **Syntax** | **Behavior** | | --- | --- | | if (Pt) Rdd=memd(Rs+#u6:3) | apply_extension(u);
EA=Rs+u;
if(Pt[0]){
Rdd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt) Rdd=memd(Rx++#s4:3) | EA=Rx;
if(Pt[0]){
Rx=Rx+s;
Rdd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt) Rdd=memd(Rs+#u6:3) | apply_extension(u);
EA=Rs+u;
if(!Pt[0]){
Rdd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt) Rdd=memd(Rx++#s4:3) | EA=Rx;
if(!Pt[0]){
Rx=Rx+s;
Rdd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt.new) Rdd=memd(Rs+#u6:3) | apply_extension(u);
EA=Rs+u;
if (Pt.new[0]) {
Rdd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt.new) Rdd=memd(Rs+#u6:3) | apply_extension(u);
EA=Rs+u;
if (!Pt.new[0]) {
Rdd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pv) Rdd=memd(Rs+Rt<<#u2) | EA=Rs+(Rt< if(Pv[0]){
Rdd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pv) Rdd=memd(Rs+Rt<<#u2) | EA=Rs+(Rt< if(!Pv[0]){
Rdd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) Rdd=memd(Rs+Rt<<#u2) | EA=Rs+(Rt< if (Pv.new[0]) {
Rdd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) Rdd=memd(Rs+Rt<<#u2) | EA=Rs+(Rt< if (!Pv.new[0]) {
Rdd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt.new) Rdd=memd(Rx++#s4:3) | EA=Rx;
if(Pt.new[0]){
Rx=Rx+s;
Rdd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt.new) Rdd=memd(Rx++#s4:3) | EA=Rx;
if(!Pt.new[0]){
Rx=Rx+s;
Rdd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt) Rdd=memd(#u6) | apply_extension(u);
EA=u;
if(Pt[0]){
Rdd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt) Rdd=memd(#u6) | apply_extension(u);
EA=u;
if(!Pt[0]){
Rdd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt.new) Rdd=memd(#u6) | apply_extension(u);
EA=u;
if (Pt.new[0]) {
Rdd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt.new) Rdd=memd(#u6) | apply_extension(u);
EA=u;
if (!Pt.new[0]) {
Rdd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt) Rdd=memd(Rs) | Assembler mapped to: "if (Pt) ""Rdd=memd""(Rs+0)"
Copy to clipboard | | if (!Pt) Rdd=memd(Rs) | Assembler mapped to: "if (!Pt) ""Rdd=memd""(Rs+0)"
Copy to clipboard | | if (Pt.new) Rdd=memd(Rs) | Assembler mapped to: "if (Pt.new) ""Rdd=memd""(Rs+0)"
Copy to clipboard | | if (!Pt.new) Rdd=memd(Rs) | Assembler mapped to: "if (!Pt.new) ""Rdd=memd""(Rs+0)"
Copy to clipboard | **Class: LD (slots 0,1)**
Encodings
Bitmap

Syntax

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if (Pt) Rdd=memd(Rs+#u6:3)

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if (Pt) Rdd=memd(Rx++#s4:3)

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if (Pv) Rdd=memd(Rs+Rt<<#u2)

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if (!Pv) Rdd=memd(Rs+Rt<<#u2)

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if (Pt.new) Rdd=memd(Rx++#s4:3)

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if (Pt) Rdd=memd(#u6)

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if (!Pt.new) Rdd=memd(#u6)

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### Load byte Load a signed byte from memory. The byte at the effective address in memory is placed in the least-significant 8 bits of the destination register. The destination register is then sign-extended from 8 bits to 32. Load byte instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=memb(Rs+#s11:0) | apply_extension(s);
EA=Rs+s;
Rd = *EA;
Copy to clipboard | | Rd=memb(Rt<<#u2+#U6) | apply_extension(U);
EA=U+(Rt< Rd = *EA;
Copy to clipboard | | Rd=memb(Re=#U6) | apply_extension(U);
EA=U;
Rd = *EA;
Re=U;
Copy to clipboard | | Rd=memb(Rx++Mu) | EA=Rx;
Rx=Rx+MuV;
Rd = *EA;
Copy to clipboard | | Rd=memb(Rx++Mu:brev) | EA=Rx.h[1] | brev(Rx.h[0]);
Rx=Rx+MuV;
Rd = *EA;
Copy to clipboard | | Rd=memb(Rx++#s4:0) | EA=Rx;
Rx=Rx+s;
Rd = *EA;
Copy to clipboard | | Rd=memb(Rx++#s4:0:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,s,MuV);
Rd = *EA;
Copy to clipboard | | Rd=memb(Rx++I:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,I<<0,MuV);
Rd = *EA;
Copy to clipboard | | Rd=memb(Rs) | Assembler mapped to: "Rd=memb""(Rs+0)"
Copy to clipboard | | Rd=memb(Rs+Rt<<#u2) | EA=Rs+(Rt< Rd = *EA;
Copy to clipboard | | Rd=memb(gp+#u16:0) | apply_extension(u);
EA=(Constant_extended ? (0) : GP)+u;
Rd = *EA;
Copy to clipboard | **Class: LD (slots 0,1)**
Encodings
Bitmap

Syntax

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Rd=memb(Rs+#s11:0)

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Rd=memb(Rt<<#u2+#U6)

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Rd=memb(Re=#U6)

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Rd=memb(Rx++Mu)

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Rd=memb(Rx++Mu:brev)

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Rd=memb(Rx++#s4:0)

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Rd=memb(Rx++#s4:0:circ(Mu))

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Rd=memb(Rx++I:circ(Mu))

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Rd=memb(Rs+Rt<<#u2)

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Rd=memb(gp+#u16:0)

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Intrinsics
Load byte intrinsics

Rd=memb(Rx++#s4:0:circ(Mu))

Word32 Q6_R_memb_IM_circ(void** StartAddress, Word32 Is4_0, Word32 Mu, void* BaseAddress)

Rd=memb(Rx++I:circ(Mu))

Word32 Q6_R_memb_M_circ(void** StartAddress, Word32 Mu, void* BaseAddress)
### Load byte conditionally Load a signed byte from memory. The byte at the effective address in memory is placed in the least-significant 8 bits of the destination register. The destination register is then sign-extended from 8 bits to 32. This instruction is conditional based on a predicate value. If the predicate is true, the instruction is performed, otherwise it is treated as a NOP. Load byte conditionally instructions | **Syntax** | **Behavior** | | --- | --- | | if (Pt) Rd=memb(Rs+#u6:0) | apply_extension(u);
EA=Rs+u;
if(Pt[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt) Rd=memb(Rx++#s4:0) | EA=Rx;
if(Pt[0]){
Rx=Rx+s;
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt) Rd=memb(Rs+#u6:0) | apply_extension(u);
EA=Rs+u;
if(!Pt[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt) Rd=memb(Rx++#s4:0) | EA=Rx;
if(!Pt[0]){
Rx=Rx+s;
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt.new) Rd=memb(Rs+#u6:0) | apply_extension(u);
EA=Rs+u;
if (Pt.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt.new) Rd=memb(Rs+#u6:0) | apply_extension(u);
EA=Rs+u;
if (!Pt.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pv) Rd=memb(Rs+Rt<<#u2) | EA=Rs+(Rt< if(Pv[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pv) Rd=memb(Rs+Rt<<#u2) | EA=Rs+(Rt< if(!Pv[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) Rd=memb(Rs+Rt<<#u2) | EA=Rs+(Rt< if (Pv.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) Rd=memb(Rs+Rt<<#u2) | EA=Rs+(Rt< if (!Pv.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt.new) Rd=memb(Rx++#s4:0) | EA=Rx;
if(Pt.new[0]){
Rx=Rx+s;
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt.new) Rd=memb(Rx++#s4:0) | EA=Rx;
if(!Pt.new[0]){
Rx=Rx+s;
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt) Rd=memb(#u6) | apply_extension(u);
EA=u;
if(Pt[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt) Rd=memb(#u6) | apply_extension(u);
EA=u;
if(!Pt[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt.new) Rd=memb(#u6) | apply_extension(u);
EA=u;
if (Pt.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt.new) Rd=memb(#u6) | apply_extension(u);
EA=u;
if (!Pt.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt) Rd=memb(Rs) | Assembler mapped to: "if (Pt) ""Rd=memb""(Rs+0)"
Copy to clipboard | | if (!Pt) Rd=memb(Rs) | Assembler mapped to: "if (!Pt) ""Rd=memb""(Rs+0)"
Copy to clipboard | | if (Pt.new) Rd=memb(Rs) | Assembler mapped to: "if (Pt.new) ""Rd=memb""(Rs+0)"
Copy to clipboard | | if (!Pt.new) Rd=memb(Rs) | Assembler mapped to: "if (!Pt.new) ""Rd=memb""(Rs+0)"
Copy to clipboard | **Class: LD (slots 0,1)**
Encodings
Bitmap

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if (Pv) Rd=memb(Rs+Rt<<#u2)

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### Load byte into shifted vector Shift a 64-bit vector right by one byte. Insert a byte from memory into the vacated upper byte of the vector. pic_addh Page-1 Sheet.32 Rectangle.74 Sheet.3 Ryy Ryy Rectangle.32 Sheet.5 Rectangle.60 Rectangle.61 Rectangle.62 Rectangle.63 Rectangle.64 Rectangle.65 Rectangle.15 Rectangle.16 Rectangle.17 Rectangle.18 Rectangle.19 Rectangle.20 Rectangle.66 Rectangle.67 Sheet.28 Sheet.30 Sheet.31 Ryy Ryy Sheet.1 Mem Mem Load byte into shifted vector instructions | **Syntax** | **Behavior** | | --- | --- | | Ryy=memb\_fifo(Rs+#s11:0) | apply_extension(s);
EA=Rs+s;
{
tmpV = *EA;
Ryy = (((size8u_t)Ryy)>>8)|(tmpV<<56);
}
Copy to clipboard | | Ryy=memb\_fifo(Rt<<#u2+#U6) | apply_extension(U);
EA=U+(Rt< {
tmpV = *EA;
Ryy = (((size8u_t)Ryy)>>8)|(tmpV<<56);
}
Copy to clipboard | | Ryy=memb\_fifo(Re=#U6) | apply_extension(U);
EA=U;
{
tmpV = *EA;
Ryy = (((size8u_t)Ryy)>>8)|(tmpV<<56);
}
Re=U;
Copy to clipboard | | Ryy=memb\_fifo(Rx++Mu) | EA=Rx;
Rx=Rx+MuV;
{
tmpV = *EA;
Ryy = (((size8u_t)Ryy)>>8)|(tmpV<<56);
}
Copy to clipboard | | Ryy=memb\_fifo(Rx++Mu:brev) | EA=Rx.h[1] | brev(Rx.h[0]);
Rx=Rx+MuV;
{
tmpV = *EA;
Ryy = (((size8u_t)Ryy)>>8)|(tmpV<<56);
}
Copy to clipboard | | Ryy=memb\_fifo(Rx++#s4:0) | EA=Rx;
Rx=Rx+s;
{
tmpV = *EA;
Ryy = (((size8u_t)Ryy)>>8)|(tmpV<<56);
}
Copy to clipboard | | Ryy=memb\_fifo(Rx++#s4:0:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,s,MuV);
{
tmpV = *EA;
Ryy = (((size8u_t)Ryy)>>8)|(tmpV<<56);
}
Copy to clipboard | | Ryy=memb\_fifo(Rx++I:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,I<<0,MuV);
{
tmpV = *EA;
Ryy = (((size8u_t)Ryy)>>8)|(tmpV<<56);
}
Copy to clipboard | | Ryy=memb\_fifo(Rs) | Assembler mapped to: "Ryy=memb_fifo""(Rs+0)"
Copy to clipboard | **Class: LD (slots 0,1)**
Encodings
Bitmap

Syntax

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Ryy=memb_fifo(Rs+#s11:0)

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Ryy=memb_fifo(Rt<<#u2+#U6)

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Ryy=memb_fifo(Re=#U6)

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Ryy=memb_fifo(Rx++Mu)

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Ryy=memb_fifo(Rx++Mu:brev)

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Ryy=memb_fifo(Rx++#s4:0)

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Ryy=memb_fifo(Rx++#s4:0:circ(Mu))

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Ryy=memb_fifo(Rx++I:circ(Mu))

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### Load half into shifted vector Shift a 64-bit vector right by one halfword. Insert a halfword from memory into the vacated upper halfword of the vector. pic_addh Page-1 Sheet.32 Rectangle.74 Sheet.3 Ryy Ryy Sheet.5 Rectangle.60 Rectangle.62 Rectangle.64 Sheet.28 Sheet.30 Sheet.31 Ryy Ryy Sheet.1 Mem Mem Rectangle.4 Rectangle.7 Rectangle.9 Rectangle.11 Load half into shifted vector instructions | **Syntax** | **Behavior** | | --- | --- | | Ryy=memh\_fifo(Rs+#s11:1) | apply_extension(s);
EA=Rs+s;
{
tmpV = *EA;
Ryy = (((size8u_t)Ryy)>>16)|(tmpV<<48);
}
Copy to clipboard | | Ryy=memh\_fifo(Rt<<#u2+#U6) | apply_extension(U);
EA=U+(Rt< {
tmpV = *EA;
Ryy = (((size8u_t)Ryy)>>16)|(tmpV<<48);
}
Copy to clipboard | | Ryy=memh\_fifo(Re=#U6) | apply_extension(U);
EA=U;
{
tmpV = *EA;
Ryy = (((size8u_t)Ryy)>>16)|(tmpV<<48);
}
Re=U;
Copy to clipboard | | Ryy=memh\_fifo(Rx++Mu) | EA=Rx;
Rx=Rx+MuV;
{
tmpV = *EA;
Ryy = (((size8u_t)Ryy)>>16)|(tmpV<<48);
}
Copy to clipboard | | Ryy=memh\_fifo(Rx++Mu:brev) | EA=Rx.h[1] | brev(Rx.h[0]);
Rx=Rx+MuV;
{
tmpV = *EA;
Ryy = (((size8u_t)Ryy)>>16)|(tmpV<<48);
}
Copy to clipboard | | Ryy=memh\_fifo(Rx++#s4:1) | EA=Rx;
Rx=Rx+s;
{
tmpV = *EA;
Ryy = (((size8u_t)Ryy)>>16)|(tmpV<<48);
}
Copy to clipboard | | Ryy=memh\_fifo(Rx++#s4:1:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,s,MuV);
{
tmpV = *EA;
Ryy = (((size8u_t)Ryy)>>16)|(tmpV<<48);
}
Copy to clipboard | | Ryy=memh\_fifo(Rx++I:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,I<<1,MuV);
{
tmpV = *EA;
Ryy = (((size8u_t)Ryy)>>16)|(tmpV<<48);
}
Copy to clipboard | | Ryy=memh\_fifo(Rs) | Assembler mapped to: "Ryy=memh_fifo""(Rs+0)"
Copy to clipboard | **Class: LD (slots 0,1)**
Encodings
Bitmap

Syntax

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Ryy=memh_fifo(Rs+#s11:1)

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Ryy=memh_fifo(Rt<<#u2+#U6)

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Ryy=memh_fifo(Re=#U6)

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Ryy=memh_fifo(Rx++Mu)

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Ryy=memh_fifo(Rx++Mu:brev)

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Ryy=memh_fifo(Rx++#s4:1)

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Ryy=memh_fifo(Rx++#s4:1:circ(Mu))

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Ryy=memh_fifo(Rx++I:circ(Mu))

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### Load halfword Load a signed halfword from memory. The 16-bit halfword at the effective address in memory is placed in the least-significant 16 bits of the destination register. The destination register is then sign-extended from 16 bits to 32. Load halfword instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=memh(Rs+#s11:1) | apply_extension(s);
EA=Rs+s;
Rd = *EA;
Copy to clipboard | | Rd=memh(Rt<<#u2+#U6) | apply_extension(U);
EA=U+(Rt< Rd = *EA;
Copy to clipboard | | Rd=memh(Re=#U6) | apply_extension(U);
EA=U;
Rd = *EA;
Re=U;
Copy to clipboard | | Rd=memh(Rx++Mu) | EA=Rx;
Rx=Rx+MuV;
Rd = *EA;
Copy to clipboard | | Rd=memh(Rx++Mu:brev) | EA=Rx.h[1] | brev(Rx.h[0]);
Rx=Rx+MuV;
Rd = *EA;
Copy to clipboard | | Rd=memh(Rx++#s4:1) | EA=Rx;
Rx=Rx+s;
Rd = *EA;
Copy to clipboard | | Rd=memh(Rx++#s4:1:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,s,MuV);
Rd = *EA;
Copy to clipboard | | Rd=memh(Rx++I:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,I<<1,MuV);
Rd = *EA;
Copy to clipboard | | Rd=memh(Rs) | Assembler mapped to: "Rd=memh""(Rs+0)"
Copy to clipboard | | Rd=memh(Rs+Rt<<#u2) | EA=Rs+(Rt< Rd = *EA;
Copy to clipboard | | Rd=memh(gp+#u16:1) | apply_extension(u);
EA=(Constant_extended ? (0) : GP)+u;
Rd = *EA;
Copy to clipboard | **Class: LD (slots 0,1)**
Encodings
Bitmap

Syntax

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Rd=memh(Rs+#s11:1)

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Rd=memh(Rt<<#u2+#U6)

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Rd=memh(Re=#U6)

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Rd=memh(Rx++Mu)

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Rd=memh(Rx++Mu:brev)

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Rd=memh(Rx++#s4:1)

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Rd=memh(Rx++#s4:1:circ(Mu))

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Rd=memh(Rx++I:circ(Mu))

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Rd=memh(Rs+Rt<<#u2)

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Rd=memh(gp+#u16:1)

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Intrinsics
Load halfword intrinsics

Rd=memh(Rx++#s4:1:circ(Mu))

Word32 Q6_R_memh_IM_circ(void** StartAddress, Word32 Is4_1, Word32 Mu, void* BaseAddress)

Rd=memh(Rx++I:circ(Mu))

Word32 Q6_R_memh_M_circ(void** StartAddress, Word32 Mu, void* BaseAddress)
### Load halfword conditionally Load a signed halfword from memory. The 16-bit halfword at the effective address in memory is placed in the least-significant 16 bits of the destination register. The destination register is then sign-extended from 16 bits to 32. This instruction is conditional based on a predicate value. If the predicate is true, the instruction is performed, otherwise it is treated as a NOP. Load halfword conditionally instructions | **Syntax** | **Behavior** | | --- | --- | | if (Pt) Rd=memh(Rs+#u6:1) | apply_extension(u);
EA=Rs+u;
if(Pt[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt) Rd=memh(Rx++#s4:1) | EA=Rx;
if(Pt[0]){
Rx=Rx+s;
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt) Rd=memh(Rs+#u6:1) | apply_extension(u);
EA=Rs+u;
if(!Pt[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt) Rd=memh(Rx++#s4:1) | EA=Rx;
if(!Pt[0]){
Rx=Rx+s;
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt.new) Rd=memh(Rs+#u6:1) | apply_extension(u);
EA=Rs+u;
if (Pt.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt.new) Rd=memh(Rs+#u6:1) | apply_extension(u);
EA=Rs+u;
if (!Pt.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pv) Rd=memh(Rs+Rt<<#u2) | EA=Rs+(Rt< if(Pv[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pv) Rd=memh(Rs+Rt<<#u2) | EA=Rs+(Rt< if(!Pv[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) Rd=memh(Rs+Rt<<#u2) | EA=Rs+(Rt< if (Pv.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) Rd=memh(Rs+Rt<<#u2) | EA=Rs+(Rt< if (!Pv.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt.new) Rd=memh(Rx++#s4:1) | EA=Rx;
if(Pt.new[0]){
Rx=Rx+s;
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt.new) Rd=memh(Rx++#s4:1) | EA=Rx;
if(!Pt.new[0]){
Rx=Rx+s;
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt) Rd=memh(#u6) | apply_extension(u);
EA=u;
if(Pt[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt) Rd=memh(#u6) | apply_extension(u);
EA=u;
if(!Pt[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt.new) Rd=memh(#u6) | apply_extension(u);
EA=u;
if (Pt.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt.new) Rd=memh(#u6) | apply_extension(u);
EA=u;
if (!Pt.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt) Rd=memh(Rs) | Assembler mapped to: "if (Pt) ""Rd=memh""(Rs+0)"
Copy to clipboard | | if (!Pt) Rd=memh(Rs) | Assembler mapped to: "if (!Pt) ""Rd=memh""(Rs+0)"
Copy to clipboard | | if (Pt.new) Rd=memh(Rs) | Assembler mapped to: "if (Pt.new) ""Rd=memh""(Rs+0)"
Copy to clipboard | | if (!Pt.new) Rd=memh(Rs) | Assembler mapped to: "if (!Pt.new) ""Rd=memh""(Rs+0)"
Copy to clipboard | **Class: LD (slots 0,1)**
Encodings
Bitmap

Syntax

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if (Pt) Rd=memh(Rs+#u6:1)

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if (Pt) Rd=memh(Rx++#s4:1)

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if (!Pt) Rd=memh(Rx++#s4:1)

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if (Pv) Rd=memh(Rs+Rt<<#u2)

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if (Pt.new) Rd=memh(Rx++#s4:1)

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if (!Pt.new) Rd=memh(Rx++#s4:1)

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if (Pt) Rd=memh(#u6)

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if (!Pt) Rd=memh(#u6)

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if (Pt.new) Rd=memh(#u6)

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if (!Pt.new) Rd=memh(#u6)

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### Load unsigned byte Load an unsigned byte from memory. The byte at the effective address in memory is placed in the least-significant 8 bits of the destination register. The destination register is then zero-extended from 8 bits to 32. Load unsigned byte instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=memub(Rs+#s11:0) | apply_extension(s);
EA=Rs+s;
Rd = *EA;
Copy to clipboard | | Rd=memub(Rt<<#u2+#U6) | apply_extension(U);
EA=U+(Rt< Rd = *EA;
Copy to clipboard | | Rd=memub(Re=#U6) | apply_extension(U);
EA=U;
Rd = *EA;
Re=U;
Copy to clipboard | | Rd=memub(Rx++Mu) | EA=Rx;
Rx=Rx+MuV;
Rd = *EA;
Copy to clipboard | | Rd=memub(Rx++Mu:brev) | EA=Rx.h[1] | brev(Rx.h[0]);
Rx=Rx+MuV;
Rd = *EA;
Copy to clipboard | | Rd=memub(Rx++#s4:0) | EA=Rx;
Rx=Rx+s;
Rd = *EA;
Copy to clipboard | | Rd=memub(Rx++#s4:0:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,s,MuV);
Rd = *EA;
Copy to clipboard | | Rd=memub(Rx++I:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,I<<0,MuV);
Rd = *EA;
Copy to clipboard | | Rd=memub(Rs) | Assembler mapped to: "Rd=memub""(Rs+0)"
Copy to clipboard | | Rd=memub(Rs+Rt<<#u2) | EA=Rs+(Rt< Rd = *EA;
Copy to clipboard | | Rd=memub(gp+#u16:0) | apply_extension(u);
EA=(Constant_extended ? (0) : GP)+u;
Rd = *EA;
Copy to clipboard | **Class: LD (slots 0,1)**
Encodings
Bitmap

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Rd=memub(Rs+#s11:0)

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Rd=memub(Rt<<#u2+#U6)

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Rd=memub(Re=#U6)

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Rd=memub(Rx++Mu)

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Rd=memub(Rx++Mu:brev)

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Rd=memub(Rx++#s4:0)

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Rd=memub(Rx++#s4:0:circ(Mu))

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Rd=memub(Rx++I:circ(Mu))

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Rd=memub(Rs+Rt<<#u2)

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Rd=memub(gp+#u16:0)

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Intrinsics
Load unsigned byte intrinsics

Rd=memub(Rx++#s4:0:circ(Mu))

Word32 Q6_R_memub_IM_circ(void** StartAddress, Word32 Is4_0, Word32 Mu, void* BaseAddress)

Rd=memub(Rx++I:circ(Mu))

Word32 Q6_R_memub_M_circ(void** StartAddress, Word32 Mu, void* BaseAddress)
### Load unsigned byte conditionally Load an unsigned byte from memory. The byte at the effective address in memory is placed in the least-significant 8 bits of the destination register. The destination register is then zero-extended from 8 bits to 32. This instruction is conditional based on a predicate value. If the predicate is true, the instruction is performed, otherwise it is treated as a NOP. Load unsigned byte conditionally instructions | **Syntax** | **Behavior** | | --- | --- | | if (Pt) Rd=memub(Rs+#u6:0) | apply_extension(u);
EA=Rs+u;
if(Pt[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt) Rd=memub(Rx++#s4:0) | EA=Rx;
if(Pt[0]){
Rx=Rx+s;
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt) Rd=memub(Rs+#u6:0) | apply_extension(u);
EA=Rs+u;
if(!Pt[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt) Rd=memub(Rx++#s4:0) | EA=Rx;
if(!Pt[0]){
Rx=Rx+s;
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt.new) Rd=memub(Rs+#u6:0) | apply_extension(u);
EA=Rs+u;
if (Pt.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt.new) Rd=memub(Rs+#u6:0) | apply_extension(u);
EA=Rs+u;
if (!Pt.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pv) Rd=memub(Rs+Rt<<#u2) | EA=Rs+(Rt< if(Pv[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pv) Rd=memub(Rs+Rt<<#u2) | EA=Rs+(Rt< if(!Pv[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) Rd=memub(Rs+Rt<<#u2) | EA=Rs+(Rt< if (Pv.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) Rd=memub(Rs+Rt<<#u2) | EA=Rs+(Rt< if (!Pv.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt.new) Rd=memub(Rx++#s4:0) | EA=Rx;
if(Pt.new[0]){
Rx=Rx+s;
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt.new) Rd=memub(Rx++#s4:0) | EA=Rx;
if(!Pt.new[0]){
Rx=Rx+s;
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt) Rd=memub(#u6) | apply_extension(u);
EA=u;
if(Pt[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt) Rd=memub(#u6) | apply_extension(u);
EA=u;
if(!Pt[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt.new) Rd=memub(#u6) | apply_extension(u);
EA=u;
if (Pt.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt.new) Rd=memub(#u6) | apply_extension(u);
EA=u;
if (!Pt.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt) Rd=memub(Rs) | Assembler mapped to: "if (Pt) ""Rd=memub""(Rs+0)"
Copy to clipboard | | if (!Pt) Rd=memub(Rs) | Assembler mapped to: "if (!Pt) ""Rd=memub""(Rs+0)"
Copy to clipboard | | if (Pt.new) Rd=memub(Rs) | Assembler mapped to: "if (Pt.new) ""Rd=memub""(Rs+0)"
Copy to clipboard | | if (!Pt.new) Rd=memub(Rs) | Assembler mapped to: "if (!Pt.new) ""Rd=memub""(Rs+0)"
Copy to clipboard | **Class: LD (slots 0,1)**
Encodings
Bitmap

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if (Pt) Rd=memub(Rs+#u6:0)

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if (Pt) Rd=memub(Rx++#s4:0)

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if (!Pt) Rd=memub(Rs+#u6:0)

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if (!Pt) Rd=memub(Rx++#s4:0)

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if (!Pt.new) Rd=memub(Rs+#u6:0)

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if (Pv) Rd=memub(Rs+Rt<<#u2)

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if (Pt.new) Rd=memub(Rx++#s4:0)

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if (!Pt.new) Rd=memub(Rx++#s4:0)

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if (Pt) Rd=memub(#u6)

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if (!Pt) Rd=memub(#u6)

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if (Pt.new) Rd=memub(#u6)

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if (!Pt.new) Rd=memub(#u6)

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### Load unsigned halfword Load an unsigned halfword from memory. The 16-bit halfword at the effective address in memory is placed in the least-significant 16 bits of the destination register. The destination register is zero-extended from 16 bits to 32. Load unsigned halfword instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=memuh(Rs+#s11:1) | apply_extension(s);
EA=Rs+s;
Rd = *EA;
Copy to clipboard | | Rd=memuh(Rt<<#u2+#U6) | apply_extension(U);
EA=U+(Rt< Rd = *EA;
Copy to clipboard | | Rd=memuh(Re=#U6) | apply_extension(U);
EA=U;
Rd = *EA;
Re=U;
Copy to clipboard | | Rd=memuh(Rx++Mu) | EA=Rx;
Rx=Rx+MuV;
Rd = *EA;
Copy to clipboard | | Rd=memuh(Rx++Mu:brev) | EA=Rx.h[1] | brev(Rx.h[0]);
Rx=Rx+MuV;
Rd = *EA;
Copy to clipboard | | Rd=memuh(Rx++#s4:1) | EA=Rx;
Rx=Rx+s;
Rd = *EA;
Copy to clipboard | | Rd=memuh(Rx++#s4:1:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,s,MuV);
Rd = *EA;
Copy to clipboard | | Rd=memuh(Rx++I:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,I<<1,MuV);
Rd = *EA;
Copy to clipboard | | Rd=memuh(Rs) | Assembler mapped to: "Rd=memuh""(Rs+0)"
Copy to clipboard | | Rd=memuh(Rs+Rt<<#u2) | EA=Rs+(Rt< Rd = *EA;
Copy to clipboard | | Rd=memuh(gp+#u16:1) | apply_extension(u);
EA=(Constant_extended ? (0) : GP)+u;
Rd = *EA;
Copy to clipboard | **Class: LD (slots 0,1)**
Encodings
Bitmap

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Rd=memuh(Rs+#s11:1)

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Rd=memuh(Rt<<#u2+#U6)

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Rd=memuh(Re=#U6)

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Rd=memuh(Rx++Mu)

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Rd=memuh(Rx++Mu:brev)

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Rd=memuh(Rx++#s4:1)

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Rd=memuh(Rx++#s4:1:circ(Mu))

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Rd=memuh(Rx++I:circ(Mu))

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Rd=memuh(Rs+Rt<<#u2)

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Rd=memuh(gp+#u16:1)

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Intrinsics
Load unsigned halfword intrinsics

Rd=memuh(Rx++#s4:1:circ(Mu))

Word32 Q6_R_memuh_IM_circ(void** StartAddress, Word32 Is4_1, Word32 Mu, void* BaseAddress)

Rd=memuh(Rx++I:circ(Mu))

Word32 Q6_R_memuh_M_circ(void** StartAddress, Word32 Mu, void* BaseAddress)
### Load unsigned halfword conditionally Load an unsigned halfword from memory. The 16-bit halfword at the effective address in memory is placed in the least-significant 16 bits of the destination register. The destination register is zero-extended from 16 bits to 32. This instruction is conditional based on a predicate value. If the predicate is true, the instruction is performed, otherwise it is treated as a NOP. Load unsigned halfword conditionally instructions | **Syntax** | **Behavior** | | --- | --- | | if (Pt) Rd=memuh(Rs+#u6:1) | apply_extension(u);
EA=Rs+u;
if(Pt[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt) Rd=memuh(Rx++#s4:1) | EA=Rx;
if(Pt[0]){
Rx=Rx+s;
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt) Rd=memuh(Rs+#u6:1) | apply_extension(u);
EA=Rs+u;
if(!Pt[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt) Rd=memuh(Rx++#s4:1) | EA=Rx;
if(!Pt[0]){
Rx=Rx+s;
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt.new) Rd=memuh(Rs+#u6:1) | apply_extension(u);
EA=Rs+u;
if (Pt.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt.new) Rd=memuh(Rs+#u6:1) | apply_extension(u);
EA=Rs+u;
if (!Pt.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pv) Rd=memuh(Rs+Rt<<#u2) | EA=Rs+(Rt< if(Pv[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pv) Rd=memuh(Rs+Rt<<#u2) | EA=Rs+(Rt< if(!Pv[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) Rd=memuh(Rs+Rt<<#u2) | EA=Rs+(Rt< if (Pv.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) Rd=memuh(Rs+Rt<<#u2) | EA=Rs+(Rt< if (!Pv.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt.new) Rd=memuh(Rx++#s4:1) | EA=Rx;
if(Pt.new[0]){
Rx=Rx+s;
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt.new) Rd=memuh(Rx++#s4:1) | EA=Rx;
if(!Pt.new[0]){
Rx=Rx+s;
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt) Rd=memuh(#u6) | apply_extension(u);
EA=u;
if(Pt[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt) Rd=memuh(#u6) | apply_extension(u);
EA=u;
if(!Pt[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt.new) Rd=memuh(#u6) | apply_extension(u);
EA=u;
if (Pt.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt.new) Rd=memuh(#u6) | apply_extension(u);
EA=u;
if (!Pt.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt) Rd=memuh(Rs) | Assembler mapped to: "if (Pt) ""Rd=memuh""(Rs+0)"
Copy to clipboard | | if (!Pt) Rd=memuh(Rs) | Assembler mapped to: "if (!Pt) ""Rd=memuh""(Rs+0)"
Copy to clipboard | | if (Pt.new) Rd=memuh(Rs) | Assembler mapped to: "if (Pt.new) ""Rd=memuh""(Rs+0)"
Copy to clipboard | | if (!Pt.new) Rd=memuh(Rs) | Assembler mapped to: "if (!Pt.new) ""Rd=memuh""(Rs+0)"
Copy to clipboard | **Class: LD (slots 0,1)**
Encodings
Bitmap

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if (Pt) Rd=memuh(Rs+#u6:1)

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if (Pt) Rd=memuh(Rx++#s4:1)

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if (Pv) Rd=memuh(Rs+Rt<<#u2)

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if (!Pv) Rd=memuh(Rs+Rt<<#u2)

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if (Pt.new) Rd=memuh(Rx++#s4:1)

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if (Pt) Rd=memuh(#u6)

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### Load word Load a 32-bit word from memory and place in a destination register. Load word instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=memw(Rs+#s11:2) | apply_extension(s);
EA=Rs+s;
Rd = *EA;
Copy to clipboard | | Rd=memw(Rt<<#u2+#U6) | apply_extension(U);
EA=U+(Rt< Rd = *EA;
Copy to clipboard | | Rd=memw(Re=#U6) | apply_extension(U);
EA=U;
Rd = *EA;
Re=U;
Copy to clipboard | | Rd=memw(Rx++Mu) | EA=Rx;
Rx=Rx+MuV;
Rd = *EA;
Copy to clipboard | | Rd=memw(Rx++Mu:brev) | EA=Rx.h[1] | brev(Rx.h[0]);
Rx=Rx+MuV;
Rd = *EA;
Copy to clipboard | | Rd=memw(Rx++#s4:2) | EA=Rx;
Rx=Rx+s;
Rd = *EA;
Copy to clipboard | | Rd=memw(Rx++#s4:2:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,s,MuV);
Rd = *EA;
Copy to clipboard | | Rd=memw(Rx++I:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,I<<2,MuV);
Rd = *EA;
Copy to clipboard | | Rd=memw(Rs) | Assembler mapped to: "Rd=memw""(Rs+0)"
Copy to clipboard | | Rd=memw(Rs+Rt<<#u2) | EA=Rs+(Rt< Rd = *EA;
Copy to clipboard | | Rd=memw(gp+#u16:2) | apply_extension(u);
EA=(Constant_extended ? (0) : GP)+u;
Rd = *EA;
Copy to clipboard | **Class: LD (slots 0,1)**
Encodings
Bitmap

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Rd=memw(Rs+#s11:2)

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Rd=memw(Rt<<#u2+#U6)

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Rd=memw(Re=#U6)

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Rd=memw(Rx++Mu)

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Rd=memw(Rx++Mu:brev)

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Rd=memw(Rx++#s4:2)

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Rd=memw(Rx++#s4:2:circ(Mu))

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Rd=memw(Rx++I:circ(Mu))

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Rd=memw(Rs+Rt<<#u2)

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Rd=memw(gp+#u16:2)

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Intrinsics
Load word intrinsics

Rd=memw(Rx++#s4:2:circ(Mu))

Word32 Q6_R_memw_IM_circ(void** StartAddress, Word32 Is4_2, Word32 Mu, void* BaseAddress)

Rd=memw(Rx++I:circ(Mu))

Word32 Q6_R_memw_M_circ(void** StartAddress, Word32 Mu, void* BaseAddress)
### Load-acquire word Load a 32-bit word from memory and place in a destination register. The load-acquire memory operation is observed before any following memory operations (in program order) have been observed at the local point of serialization. A different order may be observed at the global point of serialization. (see Ordering and Synchronization). Load-acquire word instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=memw\_aq(Rs) | EA=Rs;
Rd = *EA
Copy to clipboard | **Class: LD (slots 0)**
Encodings
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Rd=memw_aq(Rs)

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### Load word conditionally Load a 32-bit word from memory and place in a destination register. This instruction is conditional based on a predicate value. If the predicate is true, the instruction is performed, otherwise it is treated as a NOP. Load word conditionally instructions | **Syntax** | **Behavior** | | --- | --- | | if (Pt) Rd=memw(Rs+#u6:2) | apply_extension(u);
EA=Rs+u;
if(Pt[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt) Rd=memw(Rx++#s4:2) | EA=Rx;
if(Pt[0]){
Rx=Rx+s;
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt) Rd=memw(Rs+#u6:2) | apply_extension(u);
EA=Rs+u;
if(!Pt[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt) Rd=memw(Rx++#s4:2) | EA=Rx;
if(!Pt[0]){
Rx=Rx+s;
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt.new) Rd=memw(Rs+#u6:2) | apply_extension(u);
EA=Rs+u;
if (Pt.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt.new) Rd=memw(Rs+#u6:2) | apply_extension(u);
EA=Rs+u;
if (!Pt.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pv) Rd=memw(Rs+Rt<<#u2) | EA=Rs+(Rt< if(Pv[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pv) Rd=memw(Rs+Rt<<#u2) | EA=Rs+(Rt< if(!Pv[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) Rd=memw(Rs+Rt<<#u2) | EA=Rs+(Rt< if (Pv.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) Rd=memw(Rs+Rt<<#u2) | EA=Rs+(Rt< if (!Pv.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt.new) Rd=memw(Rx++#s4:2) | EA=Rx;
if(Pt.new[0]){
Rx=Rx+s;
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt.new) Rd=memw(Rx++#s4:2) | EA=Rx;
if(!Pt.new[0]){
Rx=Rx+s;
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt) Rd=memw(#u6) | apply_extension(u);
EA=u;
if(Pt[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt) Rd=memw(#u6) | apply_extension(u);
EA=u;
if(!Pt[0]){
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt.new) Rd=memw(#u6) | apply_extension(u);
EA=u;
if (Pt.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (!Pt.new) Rd=memw(#u6) | apply_extension(u);
EA=u;
if (!Pt.new[0]) {
Rd = *EA;
} else {
NOP;
}
Copy to clipboard | | if (Pt) Rd=memw(Rs) | Assembler mapped to: "if (Pt) ""Rd=memw""(Rs+0)"
Copy to clipboard | | if (!Pt) Rd=memw(Rs) | Assembler mapped to: "if (!Pt) ""Rd=memw""(Rs+0)"
Copy to clipboard | | if (Pt.new) Rd=memw(Rs) | Assembler mapped to: "if (Pt.new) ""Rd=memw""(Rs+0)"
Copy to clipboard | | if (!Pt.new) Rd=memw(Rs) | Assembler mapped to: "if (!Pt.new) ""Rd=memw""(Rs+0)"
Copy to clipboard | **Class: LD (slots 0,1)**
Encodings
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if (Pt) Rd=memw(Rx++#s4:2)

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### Deallocate stack frame Deallocate a stack frame from the call stack. The instruction first loads the saved FP and saved LR values from the address at FP. It then points SP back to the previous frame. The stack layout is seen in the following figure. Page-1 Sheet.2 Sheet.4 FP register FP register Sheet.5 Sheet.6 Sheet.7 Saved LR Saved LR Sheet.8 Sheet.9 Sheet.10 Saved FP Saved FP Sheet.11 Sheet.12 Sheet.13 Procedure local Procedure local Sheet.14 data on stack data on stack Sheet.15 Sheet.16 Sheet.17 Saved LR Saved LR Sheet.18 Sheet.19 Sheet.20 Saved FP Saved FP Sheet.21 Sheet.22 Sheet.23 SP register SP register Sheet.24 Sheet.25 Sheet.26 Sheet.27 Unallocated stack Unallocated stack Sheet.28 Sheet.29 Sheet.30 Higher address Higher address Sheet.31 Lower address Lower address Sheet.32 Sheet.33 Sheet.34 Stack in memory Stack in memory Sheet.35 Sheet.36 Sheet.37 Procedure local Procedure local Sheet.38 data on stack data on stack Sheet.1 Sheet.41 Stack frame Stack frame Sheet.3 Sheet.39 Sheet.40 Deallocate stack frame instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=deallocframe(Rs):raw | EA=Rs;
tmp = *EA;
Rdd = frame_unscramble(tmp);
SP=EA+8;
Copy to clipboard | | deallocframe | Assembler mapped to: "r31:30=deallocframe(r30):raw"
Copy to clipboard | **Class: LD (slots 0,1)**
Encodings
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Syntax

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### Deallocate frame and return Return from a function with a stack frame. This instruction is equivalent to deallocframe followed by jumpr R31. Deallocate frame and return instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=dealloc\_return(Rs):raw | EA=Rs;
tmp = *EA;
Rdd = frame_unscramble(tmp);
SP=EA+8;
PC=Rdd.w[1];
Copy to clipboard | | dealloc\_return | Assembler mapped to: "r31:30=dealloc_return(r30):raw"
Copy to clipboard | | if (Pv) Rdd=dealloc\_return(Rs):raw | EA=Rs;
if (Pv[0]) {
tmp = *EA;
Rdd = frame_unscramble(tmp);
SP=EA+8;
PC=Rdd.w[1];
} else {
NOP;
}
Copy to clipboard | | if (!Pv) Rdd=dealloc\_return(Rs):raw | EA=Rs;
if (!Pv[0]) {
tmp = *EA;
Rdd = frame_unscramble(tmp);
SP=EA+8;
PC=Rdd.w[1];
} else {
NOP;
}
Copy to clipboard | | if (Pv) dealloc\_return | Assembler mapped to: "if (Pv"") r31:30=dealloc_return(r30)"":raw"
Copy to clipboard | | if (!Pv) dealloc\_return | Assembler mapped to: "if (!Pv"") r31:30=dealloc_return(r30)"":raw"
Copy to clipboard | | if (Pv.new) Rdd=dealloc\_return(Rs):t:raw | EA=Rs;
if (Pv.new[0]) {
tmp = *EA;
Rdd = frame_unscramble(tmp);
SP=EA+8;
PC=Rdd.w[1];
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) Rdd=dealloc\_return(Rs):t:raw | EA=Rs;
if (!Pv.new[0]) {
tmp = *EA;
Rdd = frame_unscramble(tmp);
SP=EA+8;
PC=Rdd.w[1];
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) dealloc\_return:t | Assembler mapped to: "if (Pv"".new"") r31:30=dealloc_return(r30)"":t"":raw"
Copy to clipboard | | if (!Pv.new) dealloc\_return:t | Assembler mapped to: "if (!Pv"".new"") r31:30=dealloc_return(r30)"":t"":raw"
Copy to clipboard | | if (Pv.new) Rdd=dealloc\_return(Rs):nt:raw | EA=Rs;
if (Pv.new[0]) {
tmp = *EA;
Rdd = frame_unscramble(tmp);
SP=EA+8;
PC=Rdd.w[1];
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) Rdd=dealloc\_return(Rs):nt:raw | EA=Rs;
if (!Pv.new[0]) {
tmp = *EA;
Rdd = frame_unscramble(tmp);
SP=EA+8;
PC=Rdd.w[1];
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) dealloc\_return:nt | Assembler mapped to: "if (Pv"".new"") r31:30=dealloc_return(r30)"":nt"":raw"
Copy to clipboard | | if (!Pv.new) dealloc\_return:nt | Assembler mapped to: "if (!Pv"".new"") r31:30=dealloc_return(r30)"":nt"":raw"
Copy to clipboard | **Class: LD (slots 0)**
Encodings
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if (!Pv.new) Rdd=dealloc_return(Rs):nt:raw

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### Load and unpack bytes to halfwords Load contiguous bytes from memory and vector unpack them into halfwords. pic_addh Page-1 Sheet.131 Rectangle.34 Rectangle.35 Rectangle.36 Rectangle.37 Rectangle.79 Rectangle.39 Rectangle.40 Rectangle.41 Rectangle.22 Sheet.43 Sheet.44 Sheet.45 Sheet.46 Sheet.47 Sheet.48 Sheet.49 zero zero Rectangle.50 Sheet.51 Sheet.52 zero zero Rectangle.47 Sheet.54 Sheet.55 zero zero Rectangle.51 Sheet.57 Sheet.58 zero zero Sheet.59 Rdd Rdd Sheet.60 mem mem Rectangle.64 Rectangle.65 Rectangle.68 Rectangle.69 Sheet.70 Sheet.71 Rectangle.80 Sheet.81 Sheet.82 zero zero Rectangle.83 Sheet.84 Sheet.85 zero zero Sheet.86 Rdd Rdd Sheet.87 mem mem Sheet.61 Rdd = memubh(amode) Rdd = memubh(amode) Sheet.62 Rd = memubh(amode) Rd = memubh(amode) Rectangle.88 Rectangle.89 Rectangle.90 Rectangle.91 Rectangle.92 Rectangle.93 Rectangle.94 Rectangle.95 Rectangle.96 Sheet.97 Sheet.98 Sheet.99 Sheet.100 Sheet.101 Sheet.102 Sheet.103 Sign Sign Rectangle.104 Sheet.105 Sheet.106 Sign Sign Rectangle.107 Sheet.108 Sheet.109 Sign Sign Rectangle.110 Sheet.111 Sheet.112 Sign Sign Sheet.113 Rdd Rdd Sheet.114 mem mem Rectangle.115 Rectangle.116 Rectangle.117 Rectangle.118 Sheet.119 Sheet.120 Rectangle.121 Sheet.122 Sheet.123 Sign Sign Rectangle.124 Sheet.125 Sheet.126 Sign Sign Sheet.127 Rdd Rdd Sheet.128 mem mem Sheet.129 Rdd = membh(amode) Rdd = membh(amode) Sheet.130 Rd = membh(amode) Rd = membh(amode) Load and unpack bytes to halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=memubh(Rs+#s11:1) | apply_extension(s);
EA=Rs+s;
{
tmpV = *EA;
for (i=0;i<2;i++) {
Rd.h[i]=tmpV.ub[i];
}
}
Copy to clipboard | | Rd=memubh(Rt<<#u2+#U6) | apply_extension(U);
EA=U+(Rt< {
tmpV = *EA;
for (i=0;i<2;i++) {
Rd.h[i]=tmpV.ub[i];
}
}
Copy to clipboard | | Rd=memubh(Re=#U6) | apply_extension(U);
EA=U;
{
tmpV = *EA;
for (i=0;i<2;i++) {
Rd.h[i]=tmpV.ub[i];
}
}
Re=U;
Copy to clipboard | | Rd=memubh(Rx++Mu) | EA=Rx;
Rx=Rx+MuV;
{
tmpV = *EA;
for (i=0;i<2;i++) {
Rd.h[i]=tmpV.ub[i];
}
}
Copy to clipboard | | Rd=memubh(Rx++Mu:brev) | EA=Rx.h[1] | brev(Rx.h[0]);
Rx=Rx+MuV;
{
tmpV = *EA;
for (i=0;i<2;i++) {
Rd.h[i]=tmpV.ub[i];
}
}
Copy to clipboard | | Rd=memubh(Rx++#s4:1) | EA=Rx;
Rx=Rx+s;
{
tmpV = *EA;
for (i=0;i<2;i++) {
Rd.h[i]=tmpV.ub[i];
}
}
Copy to clipboard | | Rd=memubh(Rx++#s4:1:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,s,MuV);
{
tmpV = *EA;
for (i=0;i<2;i++) {
Rd.h[i]=tmpV.ub[i];
}
}
Copy to clipboard | | Rd=memubh(Rx++I:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,I<<1,MuV);
{
tmpV = *EA;
for (i=0;i<2;i++) {
Rd.h[i]=tmpV.ub[i];
}
}
Copy to clipboard | | Rd=memubh(Rs) | Assembler mapped to: "Rd=memubh""(Rs+0)"
Copy to clipboard | | Rdd=memubh(Rs+#s11:2) | apply_extension(s);
EA=Rs+s;
{
tmpV = *EA;
for (i=0;i<4;i++) {
Rdd.h[i]=tmpV.ub[i];
}
}
Copy to clipboard | | Rdd=memubh(Rt<<#u2+#U6) | apply_extension(U);
EA=U+(Rt< {
tmpV = *EA;
for (i=0;i<4;i++) {
Rdd.h[i]=tmpV.ub[i];
}
}
Copy to clipboard | | Rdd=memubh(Re=#U6) | apply_extension(U);
EA=U;
{
tmpV = *EA;
for (i=0;i<4;i++) {
Rdd.h[i]=tmpV.ub[i];
}
}
Re=U;
Copy to clipboard | | Rdd=memubh(Rx++Mu) | EA=Rx;
Rx=Rx+MuV;
{
tmpV = *EA;
for (i=0;i<4;i++) {
Rdd.h[i]=tmpV.ub[i];
}
}
Copy to clipboard | | Rdd=memubh(Rx++Mu:brev) | EA=Rx.h[1] | brev(Rx.h[0]);
Rx=Rx+MuV;
{
tmpV = *EA;
for (i=0;i<4;i++) {
Rdd.h[i]=tmpV.ub[i];
}
}
Copy to clipboard | | Rdd=memubh(Rx++#s4:2) | EA=Rx;
Rx=Rx+s;
{
tmpV = *EA;
for (i=0;i<4;i++) {
Rdd.h[i]=tmpV.ub[i];
}
}
Copy to clipboard | | Rdd=memubh(Rx++#s4:2:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,s,MuV);
{
tmpV = *EA;
for (i=0;i<4;i++) {
Rdd.h[i]=tmpV.ub[i];
}
}
Copy to clipboard | | Rdd=memubh(Rx++I:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,I<<2,MuV);
{
tmpV = *EA;
for (i=0;i<4;i++) {
Rdd.h[i]=tmpV.ub[i];
}
}
Copy to clipboard | | Rdd=memubh(Rs) | Assembler mapped to: "Rdd=memubh""(Rs+0)"
Copy to clipboard | | Rd=membh(Rs+#s11:1) | apply_extension(s);
EA=Rs+s;
{
tmpV = *EA;
for (i=0;i<2;i++) {
Rd.h[i]=tmpV.b[i];
}
}
Copy to clipboard | | Rd=membh(Rt<<#u2+#U6) | apply_extension(U);
EA=U+(Rt< {
tmpV = *EA;
for (i=0;i<2;i++) {
Rd.h[i]=tmpV.b[i];
}
}
Copy to clipboard | | Rd=membh(Re=#U6) | apply_extension(U);
EA=U;
{
tmpV = *EA;
for (i=0;i<2;i++) {
Rd.h[i]=tmpV.b[i];
}
}
Re=U;
Copy to clipboard | | Rd=membh(Rx++Mu) | EA=Rx;
Rx=Rx+MuV;
{
tmpV = *EA;
for (i=0;i<2;i++) {
Rd.h[i]=tmpV.b[i];
}
}
Copy to clipboard | | Rd=membh(Rx++Mu:brev) | EA=Rx.h[1] | brev(Rx.h[0]);
Rx=Rx+MuV;
{
tmpV = *EA;
for (i=0;i<2;i++) {
Rd.h[i]=tmpV.b[i];
}
}
Copy to clipboard | | Rd=membh(Rx++#s4:1) | EA=Rx;
Rx=Rx+s;
{
tmpV = *EA;
for (i=0;i<2;i++) {
Rd.h[i]=tmpV.b[i];
}
}
Copy to clipboard | | Rd=membh(Rx++#s4:1:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,s,MuV);
{
tmpV = *EA;
for (i=0;i<2;i++) {
Rd.h[i]=tmpV.b[i];
}
}
Copy to clipboard | | Rd=membh(Rx++I:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,I<<1,MuV);
{
tmpV = *EA;
for (i=0;i<2;i++) {
Rd.h[i]=tmpV.b[i];
}
}
Copy to clipboard | | Rd=membh(Rs) | Assembler mapped to: "Rd=membh""(Rs+0)"
Copy to clipboard | | Rdd=membh(Rs+#s11:2) | apply_extension(s);
EA=Rs+s;
{
tmpV = *EA;
for (i=0;i<4;i++) {
Rdd.h[i]=tmpV.b[i];
}
}
Copy to clipboard | | Rdd=membh(Rt<<#u2+#U6) | apply_extension(U);
EA=U+(Rt< {
tmpV = *EA;
for (i=0;i<4;i++) {
Rdd.h[i]=tmpV.b[i];
}
}
Copy to clipboard | | Rdd=membh(Re=#U6) | apply_extension(U);
EA=U;
{
tmpV = *EA;
for (i=0;i<4;i++) {
Rdd.h[i]=tmpV.b[i];
}
}
Re=U;
Copy to clipboard | | Rdd=membh(Rx++Mu) | EA=Rx;
Rx=Rx+MuV;
{
tmpV = *EA;
for (i=0;i<4;i++) {
Rdd.h[i]=tmpV.b[i];
}
}
Copy to clipboard | | Rdd=membh(Rx++Mu:brev) | EA=Rx.h[1] | brev(Rx.h[0]);
Rx=Rx+MuV;
{
tmpV = *EA;
for (i=0;i<4;i++) {
Rdd.h[i]=tmpV.b[i];
}
}
Copy to clipboard | | Rdd=membh(Rx++#s4:2) | EA=Rx;
Rx=Rx+s;
{
tmpV = *EA;
for (i=0;i<4;i++) {
Rdd.h[i]=tmpV.b[i];
}
}
Copy to clipboard | | Rdd=membh(Rx++#s4:2:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,s,MuV);
{
tmpV = *EA;
for (i=0;i<4;i++) {
Rdd.h[i]=tmpV.b[i];
}
}
Copy to clipboard | | Rdd=membh(Rx++I:circ(Mu)) | EA=Rx;
Rx=Rx=circ_add(Rx,I<<2,MuV);
{
tmpV = *EA;
for (i=0;i<4;i++) {
Rdd.h[i]=tmpV.b[i];
}
}
Copy to clipboard | | Rdd=membh(Rs) | Assembler mapped to: "Rdd=membh""(Rs+0)"
Copy to clipboard | **Class: LD (slots 0,1)**
Encodings
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Rd=membh(Re=#U6)

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Rd=membh(Rx++Mu)

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Rd=membh(Rx++Mu:brev)

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Rd=membh(Rx++#s4:1)

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Rd=membh(Rx++#s4:1:circ(Mu))

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Rd=membh(Rx++I:circ(Mu))

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Rdd=membh(Rs+#s11:2)

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Rdd=membh(Rt<<#u2+#U6)

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Rdd=membh(Re=#U6)

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Rdd=membh(Rx++Mu)

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Rdd=membh(Rx++Mu:brev)

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Rdd=membh(Rx++#s4:2)

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Rdd=membh(Rx++#s4:2:circ(Mu))

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Rdd=membh(Rx++I:circ(Mu))

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d
## MEMOP The MEMOP instruction class includes simple operations on values in memory. MEMOP instructions are executable on slot 0. ### Operation on memory byte Perform ALU or bit operation on the memory byte at the effective address. Operation on memory byte instructions | **Syntax** | **Behavior** | | --- | --- | | memb(Rs+#u6:0)+=Rt | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp += Rt;
*EA = tmp;
Copy to clipboard | | memb(Rs)+=Rt | Assembler mapped to: "memb(Rs+0)""+=Rt"
Copy to clipboard | | memb(Rs+#u6:0)-=Rt | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp -= Rt;
*EA = tmp;
Copy to clipboard | | memb(Rs)-=Rt | Assembler mapped to: "memb(Rs+0)""-=Rt"
Copy to clipboard | | memb(Rs+#u6:0)&=Rt | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp &= Rt;
*EA = tmp;
Copy to clipboard | | memb(Rs)&=Rt | Assembler mapped to: "memb(Rs+0)""&=Rt"
Copy to clipboard | | memb(Rs+#u6:0)|=Rt | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp |= Rt;
*EA = tmp;
Copy to clipboard | | memb(Rs)|=Rt | Assembler mapped to: "memb(Rs+0)""|=Rt"
Copy to clipboard | | memb(Rs+#u6:0)+=#U5 | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp += U;
*EA = tmp;
Copy to clipboard | | memb(Rs)+=#U5 | Assembler mapped to: "memb(Rs+0)""+=U5"
Copy to clipboard | | memb(Rs+#u6:0)-=#U5 | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp -= U;
*EA = tmp;
Copy to clipboard | | memb(Rs)-=#U5 | Assembler mapped to: "memb(Rs+0)""-=U5"
Copy to clipboard | | memb(Rs+#u6:0)=clrbit(#U5) | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp &= (~(1< *EA = tmp;
Copy to clipboard | | memb(Rs)=clrbit(#U5) | Assembler mapped to: "memb(Rs+0)""=clrbit(U5)"
Copy to clipboard | | memb(Rs+#u6:0)=setbit(#U5) | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp |= (1< *EA = tmp;
Copy to clipboard | | memb(Rs)=setbit(#U5) | Assembler mapped to: "memb(Rs+0)""=setbit(U5)"
Copy to clipboard | **Class: MEMOP (slots 0)**
Encodings
Bitmap

Syntax

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memb(Rs+#u6:0)+=Rt

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memb(Rs+#u6:0)-=Rt

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memb(Rs+#u6:0)&=Rt

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memb(Rs+#u6:0)|=Rt

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memb(Rs+#u6:0)+=#U5

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memb(Rs+#u6:0)-=#U5

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memb(Rs+#u6:0)=clrbit(#U5)

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memb(Rs+#u6:0)=setbit(#U5)

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### Operation on memory halfword Perform ALU or bit operation on the memory halfword at the effective address. Operation on memory halfword instructions | **Syntax** | **Behavior** | | --- | --- | | memh(Rs+#u6:1)+=Rt | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp += Rt;
*EA = tmp;
Copy to clipboard | | memh(Rs)+=Rt | Assembler mapped to: "memh(Rs+0)""+=Rt"
Copy to clipboard | | memh(Rs+#u6:1)-=Rt | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp -= Rt;
*EA = tmp;
Copy to clipboard | | memh(Rs)-=Rt | Assembler mapped to: "memh(Rs+0)""-=Rt"
Copy to clipboard | | memh(Rs+#u6:1)&=Rt | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp &= Rt;
*EA = tmp;
Copy to clipboard | | memh(Rs)&=Rt | Assembler mapped to: "memh(Rs+0)""&=Rt"
Copy to clipboard | | memh(Rs+#u6:1)|=Rt | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp |= Rt;
*EA = tmp;
Copy to clipboard | | memh(Rs)|=Rt | Assembler mapped to: "memh(Rs+0)""|=Rt"
Copy to clipboard | | memh(Rs+#u6:1)+=#U5 | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp += U;
*EA = tmp;
Copy to clipboard | | memh(Rs)+=#U5 | Assembler mapped to: "memh(Rs+0)""+=U5"
Copy to clipboard | | memh(Rs+#u6:1)-=#U5 | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp -= U;
*EA = tmp;
Copy to clipboard | | memh(Rs)-=#U5 | Assembler mapped to: "memh(Rs+0)""-=U5"
Copy to clipboard | | memh(Rs+#u6:1)=clrbit(#U5) | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp &= (~(1< *EA = tmp;
Copy to clipboard | | memh(Rs)=clrbit(#U5) | Assembler mapped to: "memh(Rs+0)""=clrbit(U5)"
Copy to clipboard | | memh(Rs+#u6:1)=setbit(#U5) | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp |= (1< *EA = tmp;
Copy to clipboard | | memh(Rs)=setbit(#U5) | Assembler mapped to: "memh(Rs+0)""=setbit(U5)"
Copy to clipboard | **Class: MEMOP (slots 0)**
Encodings
Bitmap

Syntax

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memh(Rs+#u6:1)+=Rt

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memh(Rs+#u6:1)-=Rt

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memh(Rs+#u6:1)&=Rt

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memh(Rs+#u6:1)|=Rt

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memh(Rs+#u6:1)+=#U5

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memh(Rs+#u6:1)-=#U5

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memh(Rs+#u6:1)=clrbit(#U5)

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memh(Rs+#u6:1)=setbit(#U5)

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### Operation on memory word Perform ALU or bit operation on the memory word at the effective address. Operation on memory word instructions | **Syntax** | **Behavior** | | --- | --- | | memw(Rs+#u6:2)+=Rt | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp += Rt;
*EA = tmp;
Copy to clipboard | | memw(Rs)+=Rt | Assembler mapped to: "memw(Rs+0)""+=Rt"
Copy to clipboard | | memw(Rs+#u6:2)-=Rt | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp -= Rt;
*EA = tmp;
Copy to clipboard | | memw(Rs)-=Rt | Assembler mapped to: "memw(Rs+0)""-=Rt"
Copy to clipboard | | memw(Rs+#u6:2)&=Rt | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp &= Rt;
*EA = tmp;
Copy to clipboard | | memw(Rs)&=Rt | Assembler mapped to: "memw(Rs+0)""&=Rt"
Copy to clipboard | | memw(Rs+#u6:2)|=Rt | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp |= Rt;
*EA = tmp;
Copy to clipboard | | memw(Rs)|=Rt | Assembler mapped to: "memw(Rs+0)""|=Rt"
Copy to clipboard | | memw(Rs+#u6:2)+=#U5 | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp += U;
*EA = tmp;
Copy to clipboard | | memw(Rs)+=#U5 | Assembler mapped to: "memw(Rs+0)""+=U5"
Copy to clipboard | | memw(Rs+#u6:2)-=#U5 | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp -= U;
*EA = tmp;
Copy to clipboard | | memw(Rs)-=#U5 | Assembler mapped to: "memw(Rs+0)""-=U5"
Copy to clipboard | | memw(Rs+#u6:2)=clrbit(#U5) | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp &= (~(1< *EA = tmp;
Copy to clipboard | | memw(Rs)=clrbit(#U5) | Assembler mapped to: "memw(Rs+0)""=clrbit(U5)"
Copy to clipboard | | memw(Rs+#u6:2)=setbit(#U5) | apply_extension(u);
EA=Rs+u;
tmp = *EA;
tmp |= (1< *EA = tmp;
Copy to clipboard | | memw(Rs)=setbit(#U5) | Assembler mapped to: "memw(Rs+0)""=setbit(U5)"
Copy to clipboard | **Class: MEMOP (slots 0)**
Encodings
Bitmap

Syntax

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memw(Rs+#u6:2)+=Rt

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memw(Rs+#u6:2)-=Rt

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memw(Rs+#u6:2)&=Rt

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memw(Rs+#u6:2)|=Rt

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memw(Rs+#u6:2)+=#U5

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memw(Rs+#u6:2)-=#U5

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memw(Rs+#u6:2)=clrbit(#U5)

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memw(Rs+#u6:2)=setbit(#U5)

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## NV The NV instruction class includes instructions which take the register source operand from another instruction in the same packet. NV instructions are executable on slot 0. ### J The NV/J instruction subclass includes jump instructions which take the register source operand from another instruction in the same packet. #### Jump to address condition on new register value Compare a register or constant against the value produced by a slot 1 instruction. If the comparison is true, the program counter is changed to a target address, relative to the current PC. This instruction is executable only on slot 0. Jump to address condition on new register value instructions | **Syntax** | **Behavior** | | --- | --- | | if (cmp.eq(Ns.new,#U5)) jump:t #r9:2 | if ((Ns.new==(U))) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (cmp.eq(Ns.new,#U5)) jump:nt #r9:2 | if ((Ns.new==(U))) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!cmp.eq(Ns.new,#U5)) jump:t #r9:2 | if ((Ns.new!=(U))) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!cmp.eq(Ns.new,#U5)) jump:nt #r9:2 | if ((Ns.new!=(U))) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (cmp.gt(Ns.new,#U5)) jump:t #r9:2 | if ((Ns.new>(U))) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (cmp.gt(Ns.new,#U5)) jump:nt #r9:2 | if ((Ns.new>(U))) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!cmp.gt(Ns.new,#U5)) jump:t #r9:2 | if (!(Ns.new>(U))) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!cmp.gt(Ns.new,#U5)) jump:nt #r9:2 | if (!(Ns.new>(U))) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (cmp.gtu(Ns.new,#U5)) jump:t #r9:2 | if ((Ns.new.uw[0]>(U))) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (cmp.gtu(Ns.new,#U5)) jump:nt #r9:2 | if ((Ns.new.uw[0]>(U))) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!cmp.gtu(Ns.new,#U5)) jump:t #r9:2 | if (!(Ns.new.uw[0]>(U))) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!cmp.gtu(Ns.new,#U5)) jump:nt #r9:2 | if (!(Ns.new.uw[0]>(U))) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (cmp.eq(Ns.new,#-1)) jump:t #r9:2 | if ((Ns.new==(-1))) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (cmp.eq(Ns.new,#-1)) jump:nt #r9:2 | if ((Ns.new==(-1))) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!cmp.eq(Ns.new,#-1)) jump:t #r9:2 | if ((Ns.new!=(-1))) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!cmp.eq(Ns.new,#-1)) jump:nt #r9:2 | if ((Ns.new!=(-1))) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (cmp.gt(Ns.new,#-1)) jump:t #r9:2 | if ((Ns.new>(-1))) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (cmp.gt(Ns.new,#-1)) jump:nt #r9:2 | if ((Ns.new>(-1))) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!cmp.gt(Ns.new,#-1)) jump:t #r9:2 | if (!(Ns.new>(-1))) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!cmp.gt(Ns.new,#-1)) jump:nt #r9:2 | if (!(Ns.new>(-1))) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (tstbit(Ns.new,#0)) jump:t #r9:2 | if (((Ns.new) & 1)) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (tstbit(Ns.new,#0)) jump:nt #r9:2 | if (((Ns.new) & 1)) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!tstbit(Ns.new,#0)) jump:t #r9:2 | if (!((Ns.new) & 1)) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!tstbit(Ns.new,#0)) jump:nt #r9:2 | if (!((Ns.new) & 1)) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (cmp.eq(Ns.new,Rt)) jump:t #r9:2 | if ((Ns.new==Rt)) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (cmp.eq(Ns.new,Rt)) jump:nt #r9:2 | if ((Ns.new==Rt)) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (cmp.gt(Ns.new,Rt)) jump:t #r9:2 | if ((Ns.new>Rt)) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (cmp.gt(Ns.new,Rt)) jump:nt #r9:2 | if ((Ns.new>Rt)) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (cmp.gtu(Ns.new,Rt)) jump:t #r9:2 | if ((Ns.new.uw[0]>Rt.uw[0])) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (cmp.gtu(Ns.new,Rt)) jump:nt #r9:2 | if ((Ns.new.uw[0]>Rt.uw[0])) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (cmp.gt(Rt,Ns.new)) jump:t #r9:2 | if ((Rt>Ns.new)) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (cmp.gt(Rt,Ns.new)) jump:nt #r9:2 | if ((Rt>Ns.new)) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (cmp.gtu(Rt,Ns.new)) jump:t #r9:2 | if ((Rt.uw[0]>Ns.new.uw[0])) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (cmp.gtu(Rt,Ns.new)) jump:nt #r9:2 | if ((Rt.uw[0]>Ns.new.uw[0])) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!cmp.eq(Ns.new,Rt)) jump:t #r9:2 | if ((Ns.new!=Rt)) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!cmp.eq(Ns.new,Rt)) jump:nt #r9:2 | if ((Ns.new!=Rt)) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!cmp.gt(Ns.new,Rt)) jump:t #r9:2 | if (!(Ns.new>Rt)) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!cmp.gt(Ns.new,Rt)) jump:nt #r9:2 | if (!(Ns.new>Rt)) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!cmp.gtu(Ns.new,Rt)) jump:t #r9:2 | if (!(Ns.new.uw[0]>Rt.uw[0])) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!cmp.gtu(Ns.new,Rt)) jump:nt #r9:2 | if (!(Ns.new.uw[0]>Rt.uw[0])) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!cmp.gt(Rt,Ns.new)) jump:t #r9:2 | if (!(Rt>Ns.new)) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!cmp.gt(Rt,Ns.new)) jump:nt #r9:2 | if (!(Rt>Ns.new)) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!cmp.gtu(Rt,Ns.new)) jump:t #r9:2 | if (!(Rt.uw[0]>Ns.new.uw[0])) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | | if (!cmp.gtu(Rt,Ns.new)) jump:nt #r9:2 | if (!(Rt.uw[0]>Ns.new.uw[0])) {
apply_extension(r);
r=r & ~PCALIGN_MASK;
PC=PC+r;
}
Copy to clipboard | **Class: NV (slots 0)**
Encodings
Bitmap

Syntax

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if (cmp.eq(Ns.new,#U5)) jump:t #r9:2

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if (cmp.eq(Ns.new,#U5)) jump:nt #r9:2

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if (!cmp.eq(Ns.new,#U5)) jump:t #r9:2

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if (!cmp.eq(Ns.new,#U5)) jump:nt #r9:2

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if (cmp.gt(Ns.new,#U5)) jump:t #r9:2

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if (cmp.gt(Ns.new,#U5)) jump:nt #r9:2

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if (!cmp.gt(Ns.new,#U5)) jump:t #r9:2

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if (!cmp.gt(Ns.new,#U5)) jump:nt #r9:2

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if (cmp.gtu(Ns.new,#U5)) jump:t #r9:2

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if (cmp.gtu(Ns.new,#U5)) jump:nt #r9:2

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if (!cmp.gtu(Ns.new,#U5)) jump:t #r9:2

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if (!cmp.gtu(Ns.new,#U5)) jump:nt #r9:2

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if (cmp.eq(Ns.new,#-1)) jump:t #r9:2

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if (cmp.eq(Ns.new,#-1)) jump:nt #r9:2

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if (!cmp.eq(Ns.new,#-1)) jump:t #r9:2

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if (!cmp.eq(Ns.new,#-1)) jump:nt #r9:2

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if (cmp.gt(Ns.new,#-1)) jump:t #r9:2

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if (cmp.gt(Ns.new,#-1)) jump:nt #r9:2

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if (!cmp.gt(Ns.new,#-1)) jump:t #r9:2

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if (!cmp.gt(Ns.new,#-1)) jump:nt #r9:2

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if (tstbit(Ns.new,#0)) jump:t #r9:2

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if (tstbit(Ns.new,#0)) jump:nt #r9:2

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if (!tstbit(Ns.new,#0)) jump:t #r9:2

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if (!tstbit(Ns.new,#0)) jump:nt #r9:2

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if (cmp.eq(Ns.new,Rt)) jump:t #r9:2

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if (cmp.eq(Ns.new,Rt)) jump:nt #r9:2

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if (cmp.gt(Ns.new,Rt)) jump:t #r9:2

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if (cmp.gt(Ns.new,Rt)) jump:nt #r9:2

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if (cmp.gtu(Ns.new,Rt)) jump:t #r9:2

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if (cmp.gtu(Ns.new,Rt)) jump:nt #r9:2

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if (cmp.gt(Rt,Ns.new)) jump:t #r9:2

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if (cmp.gt(Rt,Ns.new)) jump:nt #r9:2

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if (cmp.gtu(Rt,Ns.new)) jump:t #r9:2

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if (cmp.gtu(Rt,Ns.new)) jump:nt #r9:2

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if (!cmp.eq(Ns.new,Rt)) jump:t #r9:2

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if (!cmp.eq(Ns.new,Rt)) jump:nt #r9:2

0

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if (!cmp.gt(Ns.new,Rt)) jump:t #r9:2

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if (!cmp.gt(Ns.new,Rt)) jump:nt #r9:2

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if (!cmp.gtu(Ns.new,Rt)) jump:t #r9:2

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if (!cmp.gtu(Ns.new,Rt)) jump:nt #r9:2

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if (!cmp.gt(Rt,Ns.new)) jump:t #r9:2

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if (!cmp.gt(Rt,Ns.new)) jump:nt #r9:2

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if (!cmp.gtu(Rt,Ns.new)) jump:t #r9:2

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if (!cmp.gtu(Rt,Ns.new)) jump:nt #r9:2

0

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-
### ST The NV/ST instruction subclass includes store instructions which take the register source operand from another instruction in the same packet. #### Store new-value byte Store the least-significant byte in a source register in memory at the effective address. Store new-value byte instructions | **Syntax** | **Behavior** | | --- | --- | | memb(Rs+#s11:0)=Nt.new | apply_extension(s);
EA=Rs+s;
*EA = Nt.new.b[0];
Copy to clipboard | | memb(Rx++#s4:0)=Nt.new | EA=Rx;
Rx=Rx+s;
*EA = Nt.new.b[0];
Copy to clipboard | | memb(Re=#U6)=Nt.new | apply_extension(U);
EA=U;
*EA = Nt.new.b[0];
Re=U;
Copy to clipboard | | memb(Rx++Mu)=Nt.new | EA=Rx;
Rx=Rx+MuV;
*EA = Nt.new.b[0];
Copy to clipboard | | memb(Ru<<#u2+#U6)=Nt.new | apply_extension(U);
EA=U+(Ru< *EA = Nt.new.b[0];
Copy to clipboard | | memb(Rx++Mu:brev)=Nt.new | EA=Rx.h[1] | brev(Rx.h[0]);
Rx=Rx+MuV;
*EA = Nt.new.b[0];
Copy to clipboard | | memb(Rx++#s4:0:circ(Mu))=Nt.new | EA=Rx;
Rx=Rx=circ_add(Rx,s,MuV);
*EA = Nt.new.b[0];
Copy to clipboard | | memb(Rx++I:circ(Mu))=Nt.new | EA=Rx;
Rx=Rx=circ_add(Rx,I<<0,MuV);
*EA = Nt.new.b[0];
Copy to clipboard | | memb(Rs)=Nt.new | Assembler mapped to: "memb""(Rs+0)=""Nt.new"
Copy to clipboard | | memb(Rs+Ru<<#u2)=Nt.new | EA=Rs+(Ru< *EA = Nt.new.b[0];
Copy to clipboard | | memb(gp+#u16:0)=Nt.new | apply_extension(u);
EA=(Constant_extended ? (0) : GP)+u;
*EA = Nt.new.b[0];
Copy to clipboard | **Class: NV (slots 0)** Note - Forms of this instruction which use a new-value operand produced in the packet must execute on slot 0. - This instruction can execute only in slot 0, even though it is an ST instruction.
Encodings
Bitmap

Syntax

31

30

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22

21

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13

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9

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6

5

4

3

2

1

0

memb(Rs+#s11:0)=Nt.new

1

0

1

0

0

i

i

1

1

0

1

s

s

s

s

s

P

P

i

0

0

t

t

t

i

i

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i

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memb(Rx++#s4:0)=Nt.new

1

0

1

0

1

0

1

1

1

0

1

x

x

x

x

x

P

P

0

0

0

t

t

t

0

i

i

i

i

-

0

-

memb(Re=#U6)=Nt.new

1

0

1

0

1

0

1

1

1

0

1

e

e

e

e

e

P

P

0

0

0

t

t

t

1

-

I

I

I

I

I

I

memb(Rx++Mu)=Nt.new

1

0

1

0

1

1

0

1

1

0

1

x

x

x

x

x

P

P

u

0

0

t

t

t

0

-

-

-

-

-

-

-

memb(Ru<<#u2+#U6)=Nt.new

1

0

1

0

1

1

0

1

1

0

1

u

u

u

u

u

P

P

i

0

0

t

t

t

1

i

I

I

I

I

I

I

memb(Rx++Mu:brev)=Nt.new

1

0

1

0

1

1

1

1

1

0

1

x

x

x

x

x

P

P

u

0

0

t

t

t

0

-

-

-

-

-

-

-

memb(Rx++#s4:0:circ(Mu))=Nt.new

1

0

1

0

1

0

0

1

1

0

1

x

x

x

x

x

P

P

u

0

0

t

t

t

0

i

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-

0

-

memb(Rx++I:circ(Mu))=Nt.new

1

0

1

0

1

0

0

1

1

0

1

x

x

x

x

x

P

P

u

0

0

t

t

t

0

-

-

-

-

-

1

-

memb(Rs+Ru<<#u2)=Nt.new

0

0

1

1

1

0

1

1

1

0

1

s

s

s

s

s

P

P

i

u

u

u

u

u

i

-

-

0

0

t

t

t

memb(gp+#u16:0)=Nt.new

0

1

0

0

1

i

i

0

1

0

1

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i
#### Store new-value byte conditionally Store the least-significant byte in a source register in memory at the effective address. This instruction is conditional based on a predicate value. If the predicate is true, the instruction is performed, otherwise it is treated as a NOP. Store new-value byte conditionally instructions | **Syntax** | **Behavior** | | --- | --- | | if (Pv) memb(Rs+#u6:0)=Nt.new | apply_extension(u);
EA=Rs+u;
if (Pv[0]){
*EA = Nt.new.b[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memb(Rx++#s4:0)=Nt.new | EA=Rx;
if (Pv[0]){
Rx=Rx+s;
*EA = Nt.new.b[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memb(Rs+#u6:0)=Nt.new | apply_extension(u);
EA=Rs+u;
if (!Pv[0]){
*EA = Nt.new.b[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memb(Rx++#s4:0)=Nt.new | EA=Rx;
if (!Pv[0]){
Rx=Rx+s;
*EA = Nt.new.b[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memb(Rs+Ru<<#u2)=Nt.new | EA=Rs+(Ru< if (Pv[0]){
*EA = Nt.new.b[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memb(Rs+Ru<<#u2)=Nt.new | EA=Rs+(Ru< if (!Pv[0]){
*EA = Nt.new.b[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memb(Rs+#u6:0)=Nt.new | apply_extension(u);
EA=Rs+u;
if ( Pv.new[0]) {
*EA = Nt.new.b[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memb(Rs+#u6:0)=Nt.new | apply_extension(u);
EA=Rs+u;
if (!Pv.new[0]) {
*EA = Nt.new.b[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memb(Rs+Ru<<#u2)=Nt.new | EA=Rs+(Ru< if ( Pv.new[0]) {
*EA = Nt.new.b[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memb(Rs+Ru<<#u2)=Nt.new | EA=Rs+(Ru< if (!Pv.new[0]) {
*EA = Nt.new.b[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memb(Rx++#s4:0)=Nt.new | EA=Rx;
if (Pv.new[0]){
Rx=Rx+s;
*EA = Nt.new.b[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memb(Rx++#s4:0)=Nt.new | EA=Rx;
if (!Pv.new[0]){
Rx=Rx+s;
*EA = Nt.new.b[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memb(#u6)=Nt.new | apply_extension(u);
EA=u;
if (Pv[0]){
*EA = Nt.new.b[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memb(#u6)=Nt.new | apply_extension(u);
EA=u;
if (!Pv[0]){
*EA = Nt.new.b[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memb(#u6)=Nt.new | apply_extension(u);
EA=u;
if ( Pv.new[0]) {
*EA = Nt.new.b[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memb(#u6)=Nt.new | apply_extension(u);
EA=u;
if (!Pv.new[0]) {
*EA = Nt.new.b[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memb(Rs)=Nt.new | Assembler mapped to: "if (Pv) ""memb""(Rs+0)=""Nt.new"
Copy to clipboard | | if (!Pv) memb(Rs)=Nt.new | Assembler mapped to: "if (!Pv) ""memb""(Rs+0)=""Nt.new"
Copy to clipboard | | if (Pv.new) memb(Rs)=Nt.new | Assembler mapped to: "if (Pv.new) ""memb""(Rs+0)=""Nt.new"
Copy to clipboard | | if (!Pv.new) memb(Rs)=Nt.new | Assembler mapped to: "if (!Pv.new) ""memb""(Rs+0)=""Nt.new"
Copy to clipboard | **Class: NV (slots 0)** Note - Forms of this instruction which use a new-value operand produced in the packet must execute on slot 0. - This instruction can execute only in slot 0, even though it is an ST instruction.
Encodings
Bitmap

Syntax

31

30

29

28

27

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25

24

23

22

21

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18

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15

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13

12

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9

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6

5

4

3

2

1

0

if (Pv) memb(Rs+#u6:0)=Nt.new

0

1

0

0

0

0

0

0

1

0

1

s

s

s

s

s

P

P

i

0

0

t

t

t

i

i

i

i

i

0

v

v

if (Pv) memb(Rx++#s4:0)=Nt.new

1

0

1

0

1

0

1

1

1

0

1

x

x

x

x

x

P

P

1

0

0

t

t

t

0

i

i

i

i

0

v

v

if (!Pv) memb(Rs+#u6:0)=Nt.new

0

1

0

0

0

1

0

0

1

0

1

s

s

s

s

s

P

P

i

0

0

t

t

t

i

i

i

i

i

0

v

v

if (!Pv) memb(Rx++#s4:0)=Nt.new

1

0

1

0

1

0

1

1

1

0

1

x

x

x

x

x

P

P

1

0

0

t

t

t

0

i

i

i

i

1

v

v

if (Pv) memb(Rs+Ru<<#u2)=Nt.new

0

0

1

1

0

1

0

0

1

0

1

s

s

s

s

s

P

P

i

u

u

u

u

u

i

v

v

0

0

t

t

t

if (!Pv) memb(Rs+Ru<<#u2)=Nt.new

0

0

1

1

0

1

0

1

1

0

1

s

s

s

s

s

P

P

i

u

u

u

u

u

i

v

v

0

0

t

t

t

if (Pv.new) memb(Rs+#u6:0)=Nt.new

0

1

0

0

0

0

1

0

1

0

1

s

s

s

s

s

P

P

i

0

0

t

t

t

i

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i

i

i

0

v

v

if (!Pv.new) memb(Rs+#u6:0)=Nt.new

0

1

0

0

0

1

1

0

1

0

1

s

s

s

s

s

P

P

i

0

0

t

t

t

i

i

i

i

i

0

v

v

if (Pv.new) memb(Rs+Ru<<#u2)=Nt.new

0

0

1

1

0

1

1

0

1

0

1

s

s

s

s

s

P

P

i

u

u

u

u

u

i

v

v

0

0

t

t

t

if (!Pv.new) memb(Rs+Ru<<#u2)=Nt.new

0

0

1

1

0

1

1

1

1

0

1

s

s

s

s

s

P

P

i

u

u

u

u

u

i

v

v

0

0

t

t

t

if (Pv.new) memb(Rx++#s4:0)=Nt.new

1

0

1

0

1

0

1

1

1

0

1

x

x

x

x

x

P

P

1

0

0

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t

t

1

i

i

i

i

0

v

v

if (!Pv.new) memb(Rx++#s4:0)=Nt.new

1

0

1

0

1

0

1

1

1

0

1

x

x

x

x

x

P

P

1

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0

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t

t

1

i

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i

i

1

v

v

if (Pv) memb(#u6)=Nt.new

1

0

1

0

1

1

1

1

1

0

1

-

-

-

i

i

P

P

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v

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if (!Pv) memb(#u6)=Nt.new

1

0

1

0

1

1

1

1

1

0

1

-

-

-

i

i

P

P

0

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t

t

t

1

i

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i

1

v

v

if (Pv.new) memb(#u6)=Nt.new

1

0

1

0

1

1

1

1

1

0

1

-

-

-

i

i

P

P

1

0

0

t

t

t

1

i

i

i

i

0

v

v

if (!Pv.new) memb(#u6)=Nt.new

1

0

1

0

1

1

1

1

1

0

1

-

-

-

i

i

P

P

1

0

0

t

t

t

1

i

i

i

i

1

v

v
#### Store new-value halfword Store the upper or lower 16-bits of a source register in memory at the effective address. Store new-value halfword instructions | **Syntax** | **Behavior** | | --- | --- | | memh(Rs+#s11:1)=Nt.new | apply_extension(s);
EA=Rs+s;
*EA = Nt.new.h[0];
Copy to clipboard | | memh(Rx++#s4:1)=Nt.new | EA=Rx;
Rx=Rx+s;
*EA = Nt.new.h[0];
Copy to clipboard | | memh(Re=#U6)=Nt.new | apply_extension(U);
EA=U;
*EA = Nt.new.h[0];
Re=U;
Copy to clipboard | | memh(Rx++Mu)=Nt.new | EA=Rx;
Rx=Rx+MuV;
*EA = Nt.new.h[0];
Copy to clipboard | | memh(Ru<<#u2+#U6)=Nt.new | apply_extension(U);
EA=U+(Ru< *EA = Nt.new.h[0];
Copy to clipboard | | memh(Rx++Mu:brev)=Nt.new | EA=Rx.h[1] | brev(Rx.h[0]);
Rx=Rx+MuV;
*EA = Nt.new.h[0];
Copy to clipboard | | memh(Rx++#s4:1:circ(Mu))=Nt.new | EA=Rx;
Rx=Rx=circ_add(Rx,s,MuV);
*EA = Nt.new.h[0];
Copy to clipboard | | memh(Rx++I:circ(Mu))=Nt.new | EA=Rx;
Rx=Rx=circ_add(Rx,I<<1,MuV);
*EA = Nt.new.h[0];
Copy to clipboard | | memh(Rs)=Nt.new | Assembler mapped to: "memh""(Rs+0)=""Nt.new"
Copy to clipboard | | memh(Rs+Ru<<#u2)=Nt.new | EA=Rs+(Ru< *EA = Nt.new.h[0];
Copy to clipboard | | memh(gp+#u16:1)=Nt.new | apply_extension(u);
EA=(Constant_extended ? (0) : GP)+u;
*EA = Nt.new.h[0];
Copy to clipboard | **Class: NV (slots 0)** Note - Forms of this instruction which use a new-value operand produced in the packet must execute on slot 0. - This instruction can execute only in slot 0, even though it is an ST instruction.
Encodings
Bitmap

Syntax

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

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15

14

13

12

11

10

9

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7

6

5

4

3

2

1

0

memh(Rs+#s11:1)=Nt.new

1

0

1

0

0

i

i

1

1

0

1

s

s

s

s

s

P

P

i

0

1

t

t

t

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i

i

memh(Rx++#s4:1)=Nt.new

1

0

1

0

1

0

1

1

1

0

1

x

x

x

x

x

P

P

0

0

1

t

t

t

0

i

i

i

i

-

0

-

memh(Re=#U6)=Nt.new

1

0

1

0

1

0

1

1

1

0

1

e

e

e

e

e

P

P

0

0

1

t

t

t

1

-

I

I

I

I

I

I

memh(Rx++Mu)=Nt.new

1

0

1

0

1

1

0

1

1

0

1

x

x

x

x

x

P

P

u

0

1

t

t

t

0

-

-

-

-

-

-

-

memh(Ru<<#u2+#U6)=Nt.new

1

0

1

0

1

1

0

1

1

0

1

u

u

u

u

u

P

P

i

0

1

t

t

t

1

i

I

I

I

I

I

I

memh(Rx++Mu:brev)=Nt.new

1

0

1

0

1

1

1

1

1

0

1

x

x

x

x

x

P

P

u

0

1

t

t

t

0

-

-

-

-

-

-

-

memh(Rx++#s4:1:circ(Mu))=Nt.new

1

0

1

0

1

0

0

1

1

0

1

x

x

x

x

x

P

P

u

0

1

t

t

t

0

i

i

i

i

-

0

-

memh(Rx++I:circ(Mu))=Nt.new

1

0

1

0

1

0

0

1

1

0

1

x

x

x

x

x

P

P

u

0

1

t

t

t

0

-

-

-

-

-

1

-

memh(Rs+Ru<<#u2)=Nt.new

0

0

1

1

1

0

1

1

1

0

1

s

s

s

s

s

P

P

i

u

u

u

u

u

i

-

-

0

1

t

t

t

memh(gp+#u16:1)=Nt.new

0

1

0

0

1

i

i

0

1

0

1

i

i

i

i

i

P

P

i

0

1

t

t

t

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i

i
#### Store new-value halfword conditionally Store the upper or lower 16-bits of a source register in memory at the effective address. This instruction is conditional based on a predicate value. If the predicate is true, the instruction is performed, otherwise it is treated as a NOP. Store new-value halfword conditionally instructions | **Syntax** | **Behavior** | | --- | --- | | if (Pv) memh(Rs+#u6:1)=Nt.new | apply_extension(u);
EA=Rs+u;
if (Pv[0]){
*EA = Nt.new.h[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memh(Rx++#s4:1)=Nt.new | EA=Rx;
if (Pv[0]){
Rx=Rx+s;
*EA = Nt.new.h[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memh(Rs+#u6:1)=Nt.new | apply_extension(u);
EA=Rs+u;
if (!Pv[0]){
*EA = Nt.new.h[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memh(Rx++#s4:1)=Nt.new | EA=Rx;
if (!Pv[0]){
Rx=Rx+s;
*EA = Nt.new.h[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memh(Rs+Ru<<#u2)=Nt.new | EA=Rs+(Ru< if (Pv[0]){
*EA = Nt.new.h[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memh(Rs+Ru<<#u2)=Nt.new | EA=Rs+(Ru< if (!Pv[0]){
*EA = Nt.new.h[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memh(Rs+#u6:1)=Nt.new | apply_extension(u);
EA=Rs+u;
if ( Pv.new[0]) {
*EA = Nt.new.h[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memh(Rs+#u6:1)=Nt.new | apply_extension(u);
EA=Rs+u;
if (!Pv.new[0]) {
*EA = Nt.new.h[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memh(Rs+Ru<<#u2)=Nt.new | EA=Rs+(Ru< if ( Pv.new[0]) {
*EA = Nt.new.h[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memh(Rs+Ru<<#u2)=Nt.new | EA=Rs+(Ru< if (!Pv.new[0]) {
*EA = Nt.new.h[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memh(Rx++#s4:1)=Nt.new | EA=Rx;
if (Pv.new[0]){
Rx=Rx+s;
*EA = Nt.new.h[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memh(Rx++#s4:1)=Nt.new | EA=Rx;
if (!Pv.new[0]){
Rx=Rx+s;
*EA = Nt.new.h[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memh(#u6)=Nt.new | apply_extension(u);
EA=u;
if (Pv[0]){
*EA = Nt.new.h[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memh(#u6)=Nt.new | apply_extension(u);
EA=u;
if (!Pv[0]){
*EA = Nt.new.h[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memh(#u6)=Nt.new | apply_extension(u);
EA=u;
if ( Pv.new[0]) {
*EA = Nt.new.h[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memh(#u6)=Nt.new | apply_extension(u);
EA=u;
if (!Pv.new[0]) {
*EA = Nt.new.h[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memh(Rs)=Nt.new | Assembler mapped to: "if (Pv) ""memh""(Rs+0)=""Nt.new"
Copy to clipboard | | if (!Pv) memh(Rs)=Nt.new | Assembler mapped to: "if (!Pv) ""memh""(Rs+0)=""Nt.new"
Copy to clipboard | | if (Pv.new) memh(Rs)=Nt.new | Assembler mapped to: "if (Pv.new) ""memh""(Rs+0)=""Nt.new"
Copy to clipboard | | if (!Pv.new) memh(Rs)=Nt.new | Assembler mapped to: "if (!Pv.new) ""memh""(Rs+0)=""Nt.new"
Copy to clipboard | **Class: NV (slots 0)** Note - Forms of this instruction which use a new-value operand produced in the packet must execute on slot 0. - This instruction can execute only in slot 0, even though it is an ST instruction.
Encodings
Bitmap

Syntax

31

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if (Pv) memh(Rs+#u6:1)=Nt.new

0

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if (Pv) memh(Rx++#s4:1)=Nt.new

1

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if (!Pv) memh(Rs+#u6:1)=Nt.new

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if (!Pv) memh(Rx++#s4:1)=Nt.new

1

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1

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if (Pv) memh(Rs+Ru<<#u2)=Nt.new

0

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0

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1

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0

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if (!Pv) memh(Rs+Ru<<#u2)=Nt.new

0

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0

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t

t

if (Pv.new) memh(Rs+#u6:1)=Nt.new

0

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0

0

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if (!Pv.new) memh(Rs+#u6:1)=Nt.new

0

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if (Pv.new) memh(Rs+Ru<<#u2)=Nt.new

0

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0

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if (!Pv.new) memh(Rs+Ru<<#u2)=Nt.new

0

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0

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if (Pv.new) memh(Rx++#s4:1)=Nt.new

1

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0

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v

if (!Pv.new) memh(Rx++#s4:1)=Nt.new

1

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v

if (Pv) memh(#u6)=Nt.new

1

0

1

0

1

1

1

1

1

0

1

-

-

-

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0

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if (!Pv) memh(#u6)=Nt.new

1

0

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0

1

1

1

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1

-

-

-

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1

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v

if (Pv.new) memh(#u6)=Nt.new

1

0

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1

1

1

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-

-

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if (!Pv.new) memh(#u6)=Nt.new

1

0

1

0

1

1

1

1

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0

1

-

-

-

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1

v

v
#### Store new-value word Store a 32-bit register in memory at the effective address. Store new-value word instructions | **Syntax** | **Behavior** | | --- | --- | | memw(Rs+#s11:2)=Nt.new | apply_extension(s);
EA=Rs+s;
*EA = Nt.new;
Copy to clipboard | | memw(Rx++#s4:2)=Nt.new | EA=Rx;
Rx=Rx+s;
*EA = Nt.new;
Copy to clipboard | | memw(Re=#U6)=Nt.new | apply_extension(U);
EA=U;
*EA = Nt.new;
Re=U;
Copy to clipboard | | memw(Rx++Mu)=Nt.new | EA=Rx;
Rx=Rx+MuV;
*EA = Nt.new;
Copy to clipboard | | memw(Ru<<#u2+#U6)=Nt.new | apply_extension(U);
EA=U+(Ru< *EA = Nt.new;
Copy to clipboard | | memw(Rx++Mu:brev)=Nt.new | EA=Rx.h[1] | brev(Rx.h[0]);
Rx=Rx+MuV;
*EA = Nt.new;
Copy to clipboard | | memw(Rx++#s4:2:circ(Mu))=Nt.new | EA=Rx;
Rx=Rx=circ_add(Rx,s,MuV);
*EA = Nt.new;
Copy to clipboard | | memw(Rx++I:circ(Mu))=Nt.new | EA=Rx;
Rx=Rx=circ_add(Rx,I<<2,MuV);
*EA = Nt.new;
Copy to clipboard | | memw(Rs)=Nt.new | Assembler mapped to: "memw""(Rs+0)=""Nt.new"
Copy to clipboard | | memw(Rs+Ru<<#u2)=Nt.new | EA=Rs+(Ru< *EA = Nt.new;
Copy to clipboard | | memw(gp+#u16:2)=Nt.new | apply_extension(u);
EA=(Constant_extended ? (0) : GP)+u;
*EA = Nt.new;
Copy to clipboard | **Class: NV (slots 0)** Note - Forms of this instruction which use a new-value operand produced in the packet must execute on slot 0. - This instruction can execute only in slot 0, even though it is an ST instruction.
Encodings
Bitmap

Syntax

31

30

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12

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9

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1

0

memw(Rs+#s11:2)=Nt.new

1

0

1

0

0

i

i

1

1

0

1

s

s

s

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memw(Rx++#s4:2)=Nt.new

1

0

1

0

1

0

1

1

1

0

1

x

x

x

x

x

P

P

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t

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i

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-

0

-

memw(Re=#U6)=Nt.new

1

0

1

0

1

0

1

1

1

0

1

e

e

e

e

e

P

P

0

1

0

t

t

t

1

-

I

I

I

I

I

I

memw(Rx++Mu)=Nt.new

1

0

1

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1

1

0

1

1

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1

x

x

x

x

x

P

P

u

1

0

t

t

t

0

-

-

-

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-

-

memw(Ru<<#u2+#U6)=Nt.new

1

0

1

0

1

1

0

1

1

0

1

u

u

u

u

u

P

P

i

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1

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I

I

I

I

I

I

memw(Rx++Mu:brev)=Nt.new

1

0

1

0

1

1

1

1

1

0

1

x

x

x

x

x

P

P

u

1

0

t

t

t

0

-

-

-

-

-

-

-

memw(Rx++#s4:2:circ(Mu))=Nt.new

1

0

1

0

1

0

0

1

1

0

1

x

x

x

x

x

P

P

u

1

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i

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-

0

-

memw(Rx++I:circ(Mu))=Nt.new

1

0

1

0

1

0

0

1

1

0

1

x

x

x

x

x

P

P

u

1

0

t

t

t

0

-

-

-

-

-

1

-

memw(Rs+Ru<<#u2)=Nt.new

0

0

1

1

1

0

1

1

1

0

1

s

s

s

s

s

P

P

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u

u

u

u

u

i

-

-

1

0

t

t

t

memw(gp+#u16:2)=Nt.new

0

1

0

0

1

i

i

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#### Store new-value word conditionally Store a 32-bit register in memory at the effective address. This instruction is conditional based on a predicate value. If the predicate is true, the instruction is performed, otherwise it is treated as a NOP. Store new-value word conditionally instructions | **Syntax** | **Behavior** | | --- | --- | | if (Pv) memw(Rs+#u6:2)=Nt.new | apply_extension(u);
EA=Rs+u;
if (Pv[0]){
*EA = Nt.new;
} else {
NOP;
}
Copy to clipboard | | if (Pv) memw(Rx++#s4:2)=Nt.new | EA=Rx;
if (Pv[0]){
Rx=Rx+s;
*EA = Nt.new;
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memw(Rs+#u6:2)=Nt.new | apply_extension(u);
EA=Rs+u;
if (!Pv[0]){
*EA = Nt.new;
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memw(Rx++#s4:2)=Nt.new | EA=Rx;
if (!Pv[0]){
Rx=Rx+s;
*EA = Nt.new;
} else {
NOP;
}
Copy to clipboard | | if (Pv) memw(Rs+Ru<<#u2)=Nt.new | EA=Rs+(Ru< if (Pv[0]){
*EA = Nt.new;
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memw(Rs+Ru<<#u2)=Nt.new | EA=Rs+(Ru< if (!Pv[0]){
*EA = Nt.new;
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memw(Rs+#u6:2)=Nt.new | apply_extension(u);
EA=Rs+u;
if ( Pv.new[0]) {
*EA = Nt.new;
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memw(Rs+#u6:2)=Nt.new | apply_extension(u);
EA=Rs+u;
if (!Pv.new[0]) {
*EA = Nt.new;
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memw(Rs+Ru<<#u2)=Nt.new | EA=Rs+(Ru< if ( Pv.new[0]) {
*EA = Nt.new;
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memw(Rs+Ru<<#u2)=Nt.new | EA=Rs+(Ru< if (!Pv.new[0]) {
*EA = Nt.new;
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memw(Rx++#s4:2)=Nt.new | EA=Rx;
if (Pv.new[0]){
Rx=Rx+s;
*EA = Nt.new;
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memw(Rx++#s4:2)=Nt.new | EA=Rx;
if (!Pv.new[0]){
Rx=Rx+s;
*EA = Nt.new;
} else {
NOP;
}
Copy to clipboard | | if (Pv) memw(#u6)=Nt.new | apply_extension(u);
EA=u;
if (Pv[0]){
*EA = Nt.new;
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memw(#u6)=Nt.new | apply_extension(u);
EA=u;
if (!Pv[0]){
*EA = Nt.new;
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memw(#u6)=Nt.new | apply_extension(u);
EA=u;
if ( Pv.new[0]) {
*EA = Nt.new;
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memw(#u6)=Nt.new | apply_extension(u);
EA=u;
if (!Pv.new[0]) {
*EA = Nt.new;
} else {
NOP;
}
Copy to clipboard | | if (Pv) memw(Rs)=Nt.new | Assembler mapped to: "if (Pv) ""memw""(Rs+0)=""Nt.new"
Copy to clipboard | | if (!Pv) memw(Rs)=Nt.new | Assembler mapped to: "if (!Pv) ""memw""(Rs+0)=""Nt.new"
Copy to clipboard | | if (Pv.new) memw(Rs)=Nt.new | Assembler mapped to: "if (Pv.new) ""memw""(Rs+0)=""Nt.new"
Copy to clipboard | | if (!Pv.new) memw(Rs)=Nt.new | Assembler mapped to: "if (!Pv.new) ""memw""(Rs+0)=""Nt.new"
Copy to clipboard | **Class: NV (slots 0)** Note - Forms of this instruction which use a new-value operand produced in the packet must execute on slot 0. - This instruction can execute only in slot 0, even though it is an ST instruction.
Encodings
Bitmap

Syntax

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if (Pv) memw(Rs+#u6:2)=Nt.new

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if (Pv) memw(Rx++#s4:2)=Nt.new

1

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if (!Pv) memw(Rs+#u6:2)=Nt.new

0

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if (!Pv) memw(Rx++#s4:2)=Nt.new

1

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if (Pv) memw(Rs+Ru<<#u2)=Nt.new

0

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1

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0

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if (!Pv) memw(Rs+Ru<<#u2)=Nt.new

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if (Pv.new) memw(Rs+#u6:2)=Nt.new

0

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if (!Pv.new) memw(Rs+#u6:2)=Nt.new

0

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if (Pv.new) memw(Rs+Ru<<#u2)=Nt.new

0

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if (!Pv.new) memw(Rs+Ru<<#u2)=Nt.new

0

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if (Pv.new) memw(Rx++#s4:2)=Nt.new

1

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if (!Pv.new) memw(Rx++#s4:2)=Nt.new

1

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if (Pv) memw(#u6)=Nt.new

1

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1

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1

1

1

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-

-

i

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if (!Pv) memw(#u6)=Nt.new

1

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1

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-

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if (Pv.new) memw(#u6)=Nt.new

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if (!Pv.new) memw(#u6)=Nt.new

1

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1

1

1

1

1

0

1

-

-

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1

v

v
## ST The ST instruction class includes store instructions, used to store values in memory. ST instructions are executable on slot 0 and slot 1. ### Store doubleword Store a 64-bit register pair in memory at the effective address. Store doubleword instructions | **Syntax** | **Behavior** | | --- | --- | | memd(Rx++#s4:3):nt=Rtt | EA=Rx;
Rx=Rx+s;
*EA = Rtt;
Copy to clipboard | | memd(Rs+#s11:3)=Rtt | apply_extension(s);
EA=Rs+s;
*EA = Rtt;
Copy to clipboard | | memd(Rx++#s4:3)=Rtt | EA=Rx;
Rx=Rx+s;
*EA = Rtt;
Copy to clipboard | | memd(Re=#U6)=Rtt | apply_extension(U);
EA=U;
*EA = Rtt;
Re=U;
Copy to clipboard | | memd(Rx++Mu)=Rtt | EA=Rx;
Rx=Rx+MuV;
*EA = Rtt;
Copy to clipboard | | memd(Ru<<#u2+#U6)=Rtt | apply_extension(U);
EA=U+(Ru< *EA = Rtt;
Copy to clipboard | | memd(Rx++Mu:brev)=Rtt | EA=Rx.h[1] | brev(Rx.h[0]);
Rx=Rx+MuV;
*EA = Rtt;
Copy to clipboard | | memd(Rx++#s4:3:circ(Mu))=Rtt | EA=Rx;
Rx=Rx=circ_add(Rx,s,MuV);
*EA = Rtt;
Copy to clipboard | | memd(Rx++I:circ(Mu))=Rtt | EA=Rx;
Rx=Rx=circ_add(Rx,I<<3,MuV);
*EA = Rtt;
Copy to clipboard | | memd(Rs)=Rtt | Assembler mapped to: "memd""(Rs+0)=""Rtt"
Copy to clipboard | | memd(Rs+Ru<<#u2)=Rtt | EA=Rs+(Ru< *EA = Rtt;
Copy to clipboard | | memd(gp+#u16:3)=Rtt | apply_extension(u);
EA=(Constant_extended ? (0) : GP)+u;
*EA = Rtt;
Copy to clipboard | **Class: ST (slots 0,1)** Note - Non Temporal Data. The :nt appendix is a hint to the microarchitecture indicating that the life of the cache line is short. This information is used throughout the cache hierarchy to make replacement and allocation decisions.
Encodings
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memd(Rx++#s4:3):nt=Rtt

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memd(Rs+#s11:3)=Rtt

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memd(Rx++#s4:3)=Rtt

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memd(Re=#U6)=Rtt

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memd(Rx++Mu)=Rtt

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memd(Ru<<#u2+#U6)=Rtt

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memd(Rx++Mu:brev)=Rtt

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memd(Rx++#s4:3:circ(Mu))=Rtt

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memd(Rx++I:circ(Mu))=Rtt

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Intrinsics
Store doubleword intrinsics

memd(Rx++#s4:3:circ(Mu))=Rtt

void Q6_memd_IMP_circ(void** StartAddress, Word32 Is4_3, Word32 Mu, Word64 Rtt, void* BaseAddress)

memd(Rx++I:circ(Mu))=Rtt

void Q6_memd_MP_circ(void** StartAddress, Word32 Mu, Word64 Rtt, void* BaseAddress)
### Store-release doubleword Store a 64-bit register pair in memory at the effective address. The store-release memory operation is observed after all preceding memory operations have been observed at the local point of serialization. A different order may be observed at the global point of serialization. (see Ordering and Synchronization). When the :st (same domain) option is specified, the preceding memory operations are those that were committed on any thread with the same Consistency Domain before this instruction was committed. When the :at (all threads) option is specified, the preceding memory operations are those that were committed on any thread before this instruction was committed. The Store release address is limited to certain memory regions. The following are excluded memory regions: AHB memory space, AXI M2 memory space, Hexagon memory cut-out is excluded with the exception of addressible TCM and VTCM memory, and memory with the CCCC types 2, 3, or 4 are excluded. The :st option does not apply to cache operation by index or global cache operation. The :st option does not apply a consistency domain to vector operations, but instead uses a per hardware thread ordering scope. Store-release doubleword instructions | **Syntax** | **Behavior** | | --- | --- | | memd\_rl(Rs):at=Rtt | EA=Rs;
*EA = Rtt
Copy to clipboard | | memd\_rl(Rs):st=Rtt | EA=Rs;
*EA = Rtt
Copy to clipboard | **Class: ST (slots 0)**
Encodings
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memd_rl(Rs):at=Rtt

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memd_rl(Rs):st=Rtt

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### Store doubleword conditionally Store a 64-bit register pair in memory at the effective address. This instruction is conditional based on a predicate value. If the predicate is true, the instruction is performed, otherwise it is treated as a NOP. Store doubleword conditionally instructions | **Syntax** | **Behavior** | | --- | --- | | if (!Pv) memd(Rx++#s4:3):nt=Rtt | EA=Rx;
if (!Pv[0]){
Rx=Rx+s;
*EA = Rtt;
} else {
NOP;
}
Copy to clipboard | | if (Pv) memd(Rx++#s4:3):nt=Rtt | EA=Rx;
if (Pv[0]){
Rx=Rx+s;
*EA = Rtt;
} else {
NOP;
}
Copy to clipboard | | if (Pv) memd(Rs+#u6:3)=Rtt | apply_extension(u);
EA=Rs+u;
if (Pv[0]){
*EA = Rtt;
} else {
NOP;
}
Copy to clipboard | | if (Pv) memd(Rx++#s4:3)=Rtt | EA=Rx;
if (Pv[0]){
Rx=Rx+s;
*EA = Rtt;
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memd(Rs+#u6:3)=Rtt | apply_extension(u);
EA=Rs+u;
if (!Pv[0]){
*EA = Rtt;
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memd(Rx++#s4:3)=Rtt | EA=Rx;
if (!Pv[0]){
Rx=Rx+s;
*EA = Rtt;
} else {
NOP;
}
Copy to clipboard | | if (Pv) memd(Rs+Ru<<#u2)=Rtt | EA=Rs+(Ru< if (Pv[0]){
*EA = Rtt;
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memd(Rs+Ru<<#u2)=Rtt | EA=Rs+(Ru< if (!Pv[0]){
*EA = Rtt;
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memd(Rs+#u6:3)=Rtt | apply_extension(u);
EA=Rs+u;
if ( Pv.new[0]) {
*EA = Rtt;
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memd(Rs+#u6:3)=Rtt | apply_extension(u);
EA=Rs+u;
if (!Pv.new[0]) {
*EA = Rtt;
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memd(Rs+Ru<<#u2)=Rtt | EA=Rs+(Ru< if ( Pv.new[0]) {
*EA = Rtt;
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memd(Rs+Ru<<#u2)=Rtt | EA=Rs+(Ru< if (!Pv.new[0]) {
*EA = Rtt;
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memd(Rx++#s4:3)=Rtt | EA=Rx;
if (Pv.new[0]){
Rx=Rx+s;
*EA = Rtt;
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memd(Rx++#s4:3)=Rtt | EA=Rx;
if (!Pv.new[0]){
Rx=Rx+s;
*EA = Rtt;
} else {
NOP;
}
Copy to clipboard | | if (Pv) memd(#u6)=Rtt | apply_extension(u);
EA=u;
if (Pv[0]){
*EA = Rtt;
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memd(#u6)=Rtt | apply_extension(u);
EA=u;
if (!Pv[0]){
*EA = Rtt;
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memd(#u6)=Rtt | apply_extension(u);
EA=u;
if ( Pv.new[0]) {
*EA = Rtt;
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memd(#u6)=Rtt | apply_extension(u);
EA=u;
if (!Pv.new[0]) {
*EA = Rtt;
} else {
NOP;
}
Copy to clipboard | | if (Pv) memd(Rs)=Rtt | Assembler mapped to: "if (Pv) ""memd""(Rs+0)=""Rtt"
Copy to clipboard | | if (!Pv) memd(Rs)=Rtt | Assembler mapped to: "if (!Pv) ""memd""(Rs+0)=""Rtt"
Copy to clipboard | | if (Pv.new) memd(Rs)=Rtt | Assembler mapped to: "if (Pv.new) ""memd""(Rs+0)=""Rtt"
Copy to clipboard | | if (!Pv.new) memd(Rs)=Rtt | Assembler mapped to: "if (!Pv.new) ""memd""(Rs+0)=""Rtt"
Copy to clipboard | **Class: ST (slots 0,1)** Note - Non Temporal Data. The :nt appendix is a hint to the microarchitecture indicating that the life of the cache line is short. This information is used throughout the cache hierarchy to make replacement and allocation decisions.
Encodings
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if (!Pv) memd(Rx++#s4:3):nt=Rtt

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### Store byte Store the least-significant byte in a source register at the effective address. Store byte instructions | **Syntax** | **Behavior** | | --- | --- | | memb(Rx++#s4:0):nt=Rt | EA=Rx;
Rx=Rx+s;
*EA = Rt.b[0];
Copy to clipboard | | memb(Rs+#s11:0)=Rt | apply_extension(s);
EA=Rs+s;
*EA = Rt.b[0];
Copy to clipboard | | memb(Rx++#s4:0)=Rt | EA=Rx;
Rx=Rx+s;
*EA = Rt.b[0];
Copy to clipboard | | memb(Re=#U6)=Rt | apply_extension(U);
EA=U;
*EA = Rt.b[0];
Re=U;
Copy to clipboard | | memb(Rx++Mu)=Rt | EA=Rx;
Rx=Rx+MuV;
*EA = Rt.b[0];
Copy to clipboard | | memb(Ru<<#u2+#U6)=Rt | apply_extension(U);
EA=U+(Ru< *EA = Rt.b[0];
Copy to clipboard | | memb(Rx++Mu:brev)=Rt | EA=Rx.h[1] | brev(Rx.h[0]);
Rx=Rx+MuV;
*EA = Rt.b[0];
Copy to clipboard | | memb(Rx++#s4:0:circ(Mu))=Rt | EA=Rx;
Rx=Rx=circ_add(Rx,s,MuV);
*EA = Rt.b[0];
Copy to clipboard | | memb(Rx++I:circ(Mu))=Rt | EA=Rx;
Rx=Rx=circ_add(Rx,I<<0,MuV);
*EA = Rt.b[0];
Copy to clipboard | | memb(Rs)=Rt | Assembler mapped to: "memb""(Rs+0)=""Rt"
Copy to clipboard | | memb(Rs+Ru<<#u2)=Rt | EA=Rs+(Ru< *EA = Rt.b[0];
Copy to clipboard | | memb(Rs+#u6:0)=#S8 | EA=Rs+u;
apply_extension(S);
*EA = S;
Copy to clipboard | | memb(Rs)=#S8 | Assembler mapped to: "memb""(Rs+0)=""S8"
Copy to clipboard | | memb(gp+#u16:0)=Rt | apply_extension(u);
EA=(Constant_extended ? (0) : GP)+u;
*EA = Rt.b[0];
Copy to clipboard | **Class: ST (slots 0,1)** Note - Non Temporal Data. The :nt appendix is a hint to the microarchitecture indicating that the life of the cache line is short. This information is used throughout the cache hierarchy to make replacement and allocation decisions.
Encodings
Bitmap

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memb(Rs+#s11:0)=Rt

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memb(Re=#U6)=Rt

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memb(Rx++Mu)=Rt

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memb(Ru<<#u2+#U6)=Rt

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memb(Rx++#s4:0:circ(Mu))=Rt

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Intrinsics
Store byte intrinsics

memb(Rx++#s4:0:circ(Mu))=Rt

void Q6_memb_IMR_circ(void** StartAddress, Word32 Is4_0, Word32 Mu, Word32 Rt, void* BaseAddress)

memb(Rx++I:circ(Mu))=Rt

void Q6_memb_MR_circ(void** StartAddress, Word32 Mu, Word32 Rt, void* BaseAddress)
### Store byte conditionally Store the least-significant byte in a source register at the effective address. This instruction is conditional based on a predicate value. If the predicate is true, the instruction is performed, otherwise it is treated as a NOP. Store byte conditionally instructions | **Syntax** | **Behavior** | | --- | --- | | if (!Pv) memb(Rx++#s4:0):nt=Rt | EA=Rx;
if (!Pv[0]){
Rx=Rx+s;
*EA = Rt.b[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memb(Rx++#s4:0):nt=Rt | EA=Rx;
if (Pv[0]){
Rx=Rx+s;
*EA = Rt.b[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memb(Rs+#u6:0)=Rt | apply_extension(u);
EA=Rs+u;
if (Pv[0]){
*EA = Rt.b[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memb(Rx++#s4:0)=Rt | EA=Rx;
if (Pv[0]){
Rx=Rx+s;
*EA = Rt.b[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memb(Rs+#u6:0)=Rt | apply_extension(u);
EA=Rs+u;
if (!Pv[0]){
*EA = Rt.b[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memb(Rx++#s4:0)=Rt | EA=Rx;
if (!Pv[0]){
Rx=Rx+s;
*EA = Rt.b[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memb(Rs+Ru<<#u2)=Rt | EA=Rs+(Ru< if (Pv[0]){
*EA = Rt.b[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memb(Rs+Ru<<#u2)=Rt | EA=Rs+(Ru< if (!Pv[0]){
*EA = Rt.b[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memb(Rs+#u6:0)=Rt | apply_extension(u);
EA=Rs+u;
if ( Pv.new[0]) {
*EA = Rt.b[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memb(Rs+#u6:0)=Rt | apply_extension(u);
EA=Rs+u;
if (!Pv.new[0]) {
*EA = Rt.b[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memb(Rs+Ru<<#u2)=Rt | EA=Rs+(Ru< if ( Pv.new[0]) {
*EA = Rt.b[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memb(Rs+Ru<<#u2)=Rt | EA=Rs+(Ru< if (!Pv.new[0]) {
*EA = Rt.b[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memb(Rx++#s4:0)=Rt | EA=Rx;
if (Pv.new[0]){
Rx=Rx+s;
*EA = Rt.b[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memb(Rx++#s4:0)=Rt | EA=Rx;
if (!Pv.new[0]){
Rx=Rx+s;
*EA = Rt.b[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memb(#u6)=Rt | apply_extension(u);
EA=u;
if (Pv[0]){
*EA = Rt.b[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memb(#u6)=Rt | apply_extension(u);
EA=u;
if (!Pv[0]){
*EA = Rt.b[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memb(#u6)=Rt | apply_extension(u);
EA=u;
if ( Pv.new[0]) {
*EA = Rt.b[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memb(#u6)=Rt | apply_extension(u);
EA=u;
if (!Pv.new[0]) {
*EA = Rt.b[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memb(Rs)=Rt | Assembler mapped to: "if (Pv) ""memb""(Rs+0)=""Rt"
Copy to clipboard | | if (!Pv) memb(Rs)=Rt | Assembler mapped to: "if (!Pv) ""memb""(Rs+0)=""Rt"
Copy to clipboard | | if (Pv.new) memb(Rs)=Rt | Assembler mapped to: "if (Pv.new) ""memb""(Rs+0)=""Rt"
Copy to clipboard | | if (!Pv.new) memb(Rs)=Rt | Assembler mapped to: "if (!Pv.new) ""memb""(Rs+0)=""Rt"
Copy to clipboard | | if (Pv) memb(Rs+#u6:0)=#S6 | EA=Rs+u;
if (Pv[0]){
apply_extension(S);
*EA = S;
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memb(Rs+#u6:0)=#S6 | EA=Rs+u;
if (!Pv[0]){
apply_extension(S);
*EA = S;
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memb(Rs+#u6:0)=#S6 | EA=Rs+u;
if (Pv.new[0]){
apply_extension(S);
*EA = S;
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memb(Rs+#u6:0)=#S6 | EA=Rs+u;
if (!Pv.new[0]){
apply_extension(S);
*EA = S;
} else {
NOP;
}
Copy to clipboard | | if (Pv) memb(Rs)=#S6 | Assembler mapped to: "if (Pv) ""memb""(Rs+0)=""S6"
Copy to clipboard | | if (!Pv) memb(Rs)=#S6 | Assembler mapped to: "if (!Pv) ""memb""(Rs+0)=""S6"
Copy to clipboard | | if (Pv.new) memb(Rs)=#S6 | Assembler mapped to: "if (Pv.new) ""memb""(Rs+0)=""S6"
Copy to clipboard | | if (!Pv.new) memb(Rs)=#S6 | Assembler mapped to: "if (!Pv.new) ""memb""(Rs+0)=""S6"
Copy to clipboard | **Class: ST (slots 0,1)** Note - Non Temporal Data. The :nt appendix is a hint to the microarchitecture indicating that the life of the cache line is short. This information is used throughout the cache hierarchy to make replacement and allocation decisions.
Encodings
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if (!Pv) memb(Rx++#s4:0):nt=Rt

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if (Pv) memb(Rs+Ru<<#u2)=Rt

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if (Pv) memb(#u6)=Rt

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if (!Pv) memb(#u6)=Rt

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if (!Pv) memb(Rs+#u6:0)=#S6

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if (!Pv.new) memb(Rs+#u6:0)=#S6

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### Store halfword Store the upper or lower 16-bits of a source register at the effective address. Store halfword instructions | **Syntax** | **Behavior** | | --- | --- | | memh(Rx++#s4:1):nt=Rt | EA=Rx;
Rx=Rx+s;
*EA = Rt.h[0];
Copy to clipboard | | memh(Rs+#s11:1)=Rt | apply_extension(s);
EA=Rs+s;
*EA = Rt.h[0];
Copy to clipboard | | memh(Rx++#s4:1)=Rt | EA=Rx;
Rx=Rx+s;
*EA = Rt.h[0];
Copy to clipboard | | memh(Re=#U6)=Rt | apply_extension(U);
EA=U;
*EA = Rt.h[0];
Re=U;
Copy to clipboard | | memh(Rx++Mu)=Rt | EA=Rx;
Rx=Rx+MuV;
*EA = Rt.h[0];
Copy to clipboard | | memh(Ru<<#u2+#U6)=Rt | apply_extension(U);
EA=U+(Ru< *EA = Rt.h[0];
Copy to clipboard | | memh(Rx++Mu:brev)=Rt | EA=Rx.h[1] | brev(Rx.h[0]);
Rx=Rx+MuV;
*EA = Rt.h[0];
Copy to clipboard | | memh(Rx++#s4:1:circ(Mu))=Rt | EA=Rx;
Rx=Rx=circ_add(Rx,s,MuV);
*EA = Rt.h[0];
Copy to clipboard | | memh(Rx++I:circ(Mu))=Rt | EA=Rx;
Rx=Rx=circ_add(Rx,I<<1,MuV);
*EA = Rt.h[0];
Copy to clipboard | | memh(Rs)=Rt | Assembler mapped to: "memh""(Rs+0)=""Rt"
Copy to clipboard | | memh(Rs+#s11:1)=Rt.H | apply_extension(s);
EA=Rs+s;
*EA = Rt.h[1];
Copy to clipboard | | memh(Rx++#s4:1)=Rt.H | EA=Rx;
Rx=Rx+s;
*EA = Rt.h[1];
Copy to clipboard | | memh(Re=#U6)=Rt.H | apply_extension(U);
EA=U;
*EA = Rt.h[1];
Re=U;
Copy to clipboard | | memh(Rx++Mu)=Rt.H | EA=Rx;
Rx=Rx+MuV;
*EA = Rt.h[1];
Copy to clipboard | | memh(Ru<<#u2+#U6)=Rt.H | apply_extension(U);
EA=U+(Ru< *EA = Rt.h[1];
Copy to clipboard | | memh(Rx++Mu:brev)=Rt.H | EA=Rx.h[1] | brev(Rx.h[0]);
Rx=Rx+MuV;
*EA = Rt.h[1];
Copy to clipboard | | memh(Rx++#s4:1:circ(Mu))=Rt.H | EA=Rx;
Rx=Rx=circ_add(Rx,s,MuV);
*EA = Rt.h[1];
Copy to clipboard | | memh(Rx++I:circ(Mu))=Rt.H | EA=Rx;
Rx=Rx=circ_add(Rx,I<<1,MuV);
*EA = Rt.h[1];
Copy to clipboard | | memh(Rs)=Rt.H | Assembler mapped to: "memh""(Rs+0)=""Rt.H32"
Copy to clipboard | | memh(Rs+Ru<<#u2)=Rt | EA=Rs+(Ru< *EA = Rt.h[0];
Copy to clipboard | | memh(Rs+Ru<<#u2)=Rt.H | EA=Rs+(Ru< *EA = Rt.h[1];
Copy to clipboard | | memh(Rs+#u6:1)=#S8 | EA=Rs+u;
apply_extension(S);
*EA = S;
Copy to clipboard | | memh(Rs)=#S8 | Assembler mapped to: "memh""(Rs+0)=""S8"
Copy to clipboard | | memh(gp+#u16:1)=Rt | apply_extension(u);
EA=(Constant_extended ? (0) : GP)+u;
*EA = Rt.h[0];
Copy to clipboard | | memh(gp+#u16:1)=Rt.H | apply_extension(u);
EA=(Constant_extended ? (0) : GP)+u;
*EA = Rt.h[1];
Copy to clipboard | **Class: ST (slots 0,1)** Note - Non Temporal Data. The :nt appendix is a hint to the microarchitecture indicating that the life of the cache line is short. This information is used throughout the cache hierarchy to make replacement and allocation decisions.
Encodings
Bitmap

Syntax

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memh(Rx++#s4:1):nt=Rt

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memh(Rs+#s11:1)=Rt

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memh(Rx++#s4:1)=Rt

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memh(Re=#U6)=Rt

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memh(Rx++Mu)=Rt

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memh(Ru<<#u2+#U6)=Rt

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memh(Rx++Mu:brev)=Rt

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memh(Rx++#s4:1:circ(Mu))=Rt

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memh(Rx++I:circ(Mu))=Rt

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memh(Rs+#s11:1)=Rt.H

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memh(Rx++#s4:1)=Rt.H

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memh(Re=#U6)=Rt.H

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memh(Rx++Mu)=Rt.H

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memh(Ru<<#u2+#U6)=Rt.H

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memh(Rx++Mu:brev)=Rt.H

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memh(Rx++#s4:1:circ(Mu))=Rt.H

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memh(Rx++I:circ(Mu))=Rt.H

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P

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u

t

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0

-

-

-

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1

-

memh(Rs+Ru<<#u2)=Rt

0

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memh(Rs+Ru<<#u2)=Rt.H

0

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memh(Rs+#u6:1)=#S8

0

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I

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I

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I

memh(gp+#u16:1)=Rt

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memh(gp+#u16:1)=Rt.H

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Intrinsics
Store halfword intrinsics

memh(Rx++#s4:1:circ(Mu))=Rt

void Q6_memh_IMR_circ(void** StartAddress, Word32 Is4_1, Word32 Mu, Word32 Rt, void* BaseAddress)

memh(Rx++I:circ(Mu))=Rt

void Q6_memh_MR_circ(void** StartAddress, Word32 Mu, Word32 Rt, void* BaseAddress)

memh(Rx++#s4:1:circ(Mu))=Rt.H

void Q6_memh_IMRh_circ(void** StartAddress, Word32 Is4_1, Word32 Mu, Word32 Rt, void* BaseAddress)

memh(Rx++I:circ(Mu))=Rt.H

void Q6_memh_MRh_circ(void** StartAddress, Word32 Mu, Word32 Rt, void* BaseAddress)
### Store halfword conditionally Store the upper or lower 16-bits of a source register in memory at the effective address. This instruction is conditional based on a predicate value. If the predicate is true, the instruction is performed, otherwise it is treated as a NOP. Store halfword conditionally instructions | **Syntax** | **Behavior** | | --- | --- | | if (!Pv) memh(Rx++#s4:1):nt=Rt | EA=Rx;
if (!Pv[0]){
Rx=Rx+s;
*EA = Rt.h[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memh(Rx++#s4:1):nt=Rt | EA=Rx;
if (Pv[0]){
Rx=Rx+s;
*EA = Rt.h[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memh(Rs+#u6:1)=Rt | apply_extension(u);
EA=Rs+u;
if (Pv[0]){
*EA = Rt.h[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memh(Rx++#s4:1)=Rt | EA=Rx;
if (Pv[0]){
Rx=Rx+s;
*EA = Rt.h[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memh(Rs+#u6:1)=Rt | apply_extension(u);
EA=Rs+u;
if (!Pv[0]){
*EA = Rt.h[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memh(Rx++#s4:1)=Rt | EA=Rx;
if (!Pv[0]){
Rx=Rx+s;
*EA = Rt.h[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memh(Rs+Ru<<#u2)=Rt | EA=Rs+(Ru< if (Pv[0]){
*EA = Rt.h[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memh(Rs+Ru<<#u2)=Rt | EA=Rs+(Ru< if (!Pv[0]){
*EA = Rt.h[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memh(Rs+#u6:1)=Rt | apply_extension(u);
EA=Rs+u;
if ( Pv.new[0]) {
*EA = Rt.h[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memh(Rs+#u6:1)=Rt | apply_extension(u);
EA=Rs+u;
if (!Pv.new[0]) {
*EA = Rt.h[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memh(Rs+Ru<<#u2)=Rt | EA=Rs+(Ru< if ( Pv.new[0]) {
*EA = Rt.h[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memh(Rs+Ru<<#u2)=Rt | EA=Rs+(Ru< if (!Pv.new[0]) {
*EA = Rt.h[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memh(Rx++#s4:1)=Rt | EA=Rx;
if (Pv.new[0]){
Rx=Rx+s;
*EA = Rt.h[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memh(Rx++#s4:1)=Rt | EA=Rx;
if (!Pv.new[0]){
Rx=Rx+s;
*EA = Rt.h[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memh(#u6)=Rt | apply_extension(u);
EA=u;
if (Pv[0]){
*EA = Rt.h[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memh(#u6)=Rt | apply_extension(u);
EA=u;
if (!Pv[0]){
*EA = Rt.h[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memh(#u6)=Rt | apply_extension(u);
EA=u;
if ( Pv.new[0]) {
*EA = Rt.h[0];
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memh(#u6)=Rt | apply_extension(u);
EA=u;
if (!Pv.new[0]) {
*EA = Rt.h[0];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memh(Rs)=Rt | Assembler mapped to: "if (Pv) ""memh""(Rs+0)=""Rt"
Copy to clipboard | | if (!Pv) memh(Rs)=Rt | Assembler mapped to: "if (!Pv) ""memh""(Rs+0)=""Rt"
Copy to clipboard | | if (Pv.new) memh(Rs)=Rt | Assembler mapped to: "if (Pv.new) ""memh""(Rs+0)=""Rt"
Copy to clipboard | | if (!Pv.new) memh(Rs)=Rt | Assembler mapped to: "if (!Pv.new) ""memh""(Rs+0)=""Rt"
Copy to clipboard | | if (Pv) memh(Rs+#u6:1)=Rt.H | apply_extension(u);
EA=Rs+u;
if (Pv[0]){
*EA = Rt.h[1];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memh(Rx++#s4:1)=Rt.H | EA=Rx;
if (Pv[0]){
Rx=Rx+s;
*EA = Rt.h[1];
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memh(Rs+#u6:1)=Rt.H | apply_extension(u);
EA=Rs+u;
if (!Pv[0]){
*EA = Rt.h[1];
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memh(Rx++#s4:1)=Rt.H | EA=Rx;
if (!Pv[0]){
Rx=Rx+s;
*EA = Rt.h[1];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memh(Rs+Ru<<#u2)=Rt.H | EA=Rs+(Ru< if (Pv[0]){
*EA = Rt.h[1];
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memh(Rs+Ru<<#u2)=Rt.H | EA=Rs+(Ru< if (!Pv[0]){
*EA = Rt.h[1];
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memh(Rs+#u6:1)=Rt.H | apply_extension(u);
EA=Rs+u;
if ( Pv.new[0]) {
*EA = Rt.h[1];
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memh(Rs+#u6:1)=Rt.H | apply_extension(u);
EA=Rs+u;
if (!Pv.new[0]) {
*EA = Rt.h[1];
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memh(Rs+Ru<<#u2)=Rt.H | EA=Rs+(Ru< if ( Pv.new[0]) {
*EA = Rt.h[1];
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memh(Rs+Ru<<#u2)=Rt.H | EA=Rs+(Ru< if (!Pv.new[0]) {
*EA = Rt.h[1];
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memh(Rx++#s4:1)=Rt.H | EA=Rx;
if (Pv.new[0]){
Rx=Rx+s;
*EA = Rt.h[1];
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memh(Rx++#s4:1)=Rt.H | EA=Rx;
if (!Pv.new[0]){
Rx=Rx+s;
*EA = Rt.h[1];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memh(#u6)=Rt.H | apply_extension(u);
EA=u;
if (Pv[0]){
*EA = Rt.h[1];
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memh(#u6)=Rt.H | apply_extension(u);
EA=u;
if (!Pv[0]){
*EA = Rt.h[1];
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memh(#u6)=Rt.H | apply_extension(u);
EA=u;
if ( Pv.new[0]) {
*EA = Rt.h[1];
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memh(#u6)=Rt.H | apply_extension(u);
EA=u;
if (!Pv.new[0]) {
*EA = Rt.h[1];
} else {
NOP;
}
Copy to clipboard | | if (Pv) memh(Rs)=Rt.H | Assembler mapped to: "if (Pv) ""memh""(Rs+0)=""Rt.H32"
Copy to clipboard | | if (!Pv) memh(Rs)=Rt.H | Assembler mapped to: "if (!Pv) ""memh""(Rs+0)=""Rt.H32"
Copy to clipboard | | if (Pv.new) memh(Rs)=Rt.H | Assembler mapped to: "if (Pv.new) ""memh""(Rs+0)=""Rt.H32"
Copy to clipboard | | if (!Pv.new) memh(Rs)=Rt.H | Assembler mapped to: "if (!Pv.new) ""memh""(Rs+0)=""Rt.H32"
Copy to clipboard | | if (Pv) memh(Rs+#u6:1)=#S6 | EA=Rs+u;
if (Pv[0]){
apply_extension(S);
*EA = S;
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memh(Rs+#u6:1)=#S6 | EA=Rs+u;
if (!Pv[0]){
apply_extension(S);
*EA = S;
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memh(Rs+#u6:1)=#S6 | EA=Rs+u;
if (Pv.new[0]){
apply_extension(S);
*EA = S;
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memh(Rs+#u6:1)=#S6 | EA=Rs+u;
if (!Pv.new[0]){
apply_extension(S);
*EA = S;
} else {
NOP;
}
Copy to clipboard | | if (Pv) memh(Rs)=#S6 | Assembler mapped to: "if (Pv) ""memh""(Rs+0)=""S6"
Copy to clipboard | | if (!Pv) memh(Rs)=#S6 | Assembler mapped to: "if (!Pv) ""memh""(Rs+0)=""S6"
Copy to clipboard | | if (Pv.new) memh(Rs)=#S6 | Assembler mapped to: "if (Pv.new) ""memh""(Rs+0)=""S6"
Copy to clipboard | | if (!Pv.new) memh(Rs)=#S6 | Assembler mapped to: "if (!Pv.new) ""memh""(Rs+0)=""S6"
Copy to clipboard | **Class: ST (slots 0,1)** Note - Non Temporal Data. The :nt appendix is a hint to the microarchitecture indicating that the life of the cache line is short. This information is used throughout the cache hierarchy to make replacement and allocation decisions.
Encodings
Bitmap

Syntax

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if (!Pv) memh(Rx++#s4:1):nt=Rt

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if (Pv) memh(Rx++#s4:1):nt=Rt

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if (Pv) memh(Rs+#u6:1)=Rt

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if (Pv) memh(Rx++#s4:1)=Rt

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if (!Pv) memh(Rs+#u6:1)=Rt

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if (!Pv) memh(Rx++#s4:1)=Rt

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if (Pv) memh(Rs+Ru<<#u2)=Rt

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if (!Pv) memh(Rs+Ru<<#u2)=Rt

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if (!Pv.new) memh(Rs+#u6:1)=Rt

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if (Pv.new) memh(Rs+Ru<<#u2)=Rt

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if (!Pv.new) memh(Rs+Ru<<#u2)=Rt

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if (Pv.new) memh(Rx++#s4:1)=Rt

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if (!Pv.new) memh(Rx++#s4:1)=Rt

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if (Pv) memh(#u6)=Rt

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if (!Pv) memh(#u6)=Rt

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if (Pv.new) memh(#u6)=Rt

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if (!Pv.new) memh(#u6)=Rt

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if (Pv) memh(Rs+#u6:1)=Rt.H

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if (Pv) memh(Rx++#s4:1)=Rt.H

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if (!Pv) memh(Rs+#u6:1)=Rt.H

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if (!Pv) memh(Rx++#s4:1)=Rt.H

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if (Pv) memh(Rs+Ru<<#u2)=Rt.H

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if (!Pv) memh(Rs+Ru<<#u2)=Rt.H

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if (Pv.new) memh(Rs+#u6:1)=Rt.H

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if (!Pv.new) memh(Rs+#u6:1)=Rt.H

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if (Pv.new) memh(Rs+Ru<<#u2)=Rt.H

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if (!Pv.new) memh(Rs+Ru<<#u2)=Rt.H

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if (Pv.new) memh(Rx++#s4:1)=Rt.H

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if (!Pv.new) memh(Rx++#s4:1)=Rt.H

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if (Pv) memh(#u6)=Rt.H

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-

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if (!Pv) memh(#u6)=Rt.H

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if (Pv.new) memh(#u6)=Rt.H

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if (!Pv.new) memh(#u6)=Rt.H

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if (Pv) memh(Rs+#u6:1)=#S6

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if (!Pv) memh(Rs+#u6:1)=#S6

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if (Pv.new) memh(Rs+#u6:1)=#S6

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if (!Pv.new) memh(Rs+#u6:1)=#S6

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### Release The release memory operation is observed after all preceding memory operations have been observed at the local point of serialization. A different order may be observed at the global point of serialization. (see Ordering and Synchronization). No data is modified by this instruction. When the :st (same domain) option is specified, the preceding memory operations are those that were committed on any thread with the same Consistency Domain before this instruction was committed. When the :at (all threads) option is specified, the preceding memory operations are those that were committed on any thread before this instruction was committed. The Store release address is limited to certain memory regions. The following are excluded memory regions: AHB memory space, AXI M2 memory space, Hexagon memory cut-out is excluded with the exception of addressible TCM and VTCM memory, and memory with the CCCC types 2, 3, or 4 are excluded. The :st option does not apply to cache operation by index or global cache operation. The :st option does not apply a consistency domain to vector operations, but instead uses a per hardware thread ordering scope. Note: Observing the release operation means a later access to the target address by the issuing software thread. Release instructions | **Syntax** | **Behavior** | | --- | --- | | release(Rs):at | EA=Rs;
*EA = Rs
Copy to clipboard | | release(Rs):st | EA=Rs;
*EA = Rs
Copy to clipboard | **Class: ST (slots 0)**
Encodings
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### Store word Store a 32-bit register in memory at the effective address. Store word instructions | **Syntax** | **Behavior** | | --- | --- | | memw(Rx++#s4:2):nt=Rt | EA=Rx;
Rx=Rx+s;
*EA = Rt;
Copy to clipboard | | memw(Rs+#s11:2)=Rt | apply_extension(s);
EA=Rs+s;
*EA = Rt;
Copy to clipboard | | memw(Rx++#s4:2)=Rt | EA=Rx;
Rx=Rx+s;
*EA = Rt;
Copy to clipboard | | memw(Re=#U6)=Rt | apply_extension(U);
EA=U;
*EA = Rt;
Re=U;
Copy to clipboard | | memw(Rx++Mu)=Rt | EA=Rx;
Rx=Rx+MuV;
*EA = Rt;
Copy to clipboard | | memw(Ru<<#u2+#U6)=Rt | apply_extension(U);
EA=U+(Ru< *EA = Rt;
Copy to clipboard | | memw(Rx++Mu:brev)=Rt | EA=Rx.h[1] | brev(Rx.h[0]);
Rx=Rx+MuV;
*EA = Rt;
Copy to clipboard | | memw(Rx++#s4:2:circ(Mu))=Rt | EA=Rx;
Rx=Rx=circ_add(Rx,s,MuV);
*EA = Rt;
Copy to clipboard | | memw(Rx++I:circ(Mu))=Rt | EA=Rx;
Rx=Rx=circ_add(Rx,I<<2,MuV);
*EA = Rt;
Copy to clipboard | | memw(Rs)=Rt | Assembler mapped to: "memw""(Rs+0)=""Rt"
Copy to clipboard | | memw(Rs+Ru<<#u2)=Rt | EA=Rs+(Ru< *EA = Rt;
Copy to clipboard | | memw(Rs+#u6:2)=#S8 | EA=Rs+u;
apply_extension(S);
*EA = S;
Copy to clipboard | | memw(Rs)=#S8 | Assembler mapped to: "memw""(Rs+0)=""S8"
Copy to clipboard | | memw(gp+#u16:2)=Rt | apply_extension(u);
EA=(Constant_extended ? (0) : GP)+u;
*EA = Rt;
Copy to clipboard | **Class: ST (slots 0,1)** Note - Non Temporal Data. The :nt appendix is a hint to the microarchitecture indicating that the life of the cache line is short. This information is used throughout the cache hierarchy to make replacement and allocation decisions.
Encodings
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memw(Rx++#s4:2):nt=Rt

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memw(Rx++#s4:2)=Rt

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memw(Rx++I:circ(Mu))=Rt

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Intrinsics
Store word intrinsics

memw(Rx++#s4:2:circ(Mu))=Rt

void Q6_memw_IMR_circ(void** StartAddress, Word32 Is4_2, Word32 Mu, Word32 Rt, void* BaseAddress)

memw(Rx++I:circ(Mu))=Rt

void Q6_memw_MR_circ(void** StartAddress, Word32 Mu, Word32 Rt, void* BaseAddress)
### Store-release word Store a 32-bit register in memory at the effective address. The store-release memory operation is observed after all preceding memory operations have been observed at the local point of serialization. A different order may be observed at the global point of serialization. (see Ordering and Synchronization). When the :st (same domain) option is specified, the preceding memory operations are those that were committed on any thread with the same Consistency Domain before the release:st was committed. When the :at (all threads) option is specified, the preceding memory operations are those that were committed on any thread before the release:at instruction was committed. The Store release address is limited to certain memory regions. The following are excluded memory regions: AHB memory space, AXI M2 memory space, Hexagon memory cut-out is excluded with the exception of addressible TCM and VTCM memory, and memory with the CCCC types 2, 3, or 4 are excluded. The :st option does not apply to cache operation by index or global cache operation. The :st option does not apply a consistency domain to vector operations, but instead uses a per hardware thread ordering scope. Store-release word instructions | **Syntax** | **Behavior** | | --- | --- | | memw\_rl(Rs):at=Rt | EA=Rs;
*EA = Rt
Copy to clipboard | | memw\_rl(Rs):st=Rt | EA=Rs;
*EA = Rt
Copy to clipboard | **Class: ST (slots 0)**
Encodings
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### Store word conditionally Store a 32-bit register in memory at the effective address. This instruction is conditional based on a predicate value. If the predicate is true, the instruction is performed, otherwise it is treated as a NOP. Store word conditionally instructions | **Syntax** | **Behavior** | | --- | --- | | if (!Pv) memw(Rx++#s4:2):nt=Rt | EA=Rx;
if (!Pv[0]){
Rx=Rx+s;
*EA = Rt;
} else {
NOP;
}
Copy to clipboard | | if (Pv) memw(Rx++#s4:2):nt=Rt | EA=Rx;
if (Pv[0]){
Rx=Rx+s;
*EA = Rt;
} else {
NOP;
}
Copy to clipboard | | if (Pv) memw(Rs+#u6:2)=Rt | apply_extension(u);
EA=Rs+u;
if (Pv[0]){
*EA = Rt;
} else {
NOP;
}
Copy to clipboard | | if (Pv) memw(Rx++#s4:2)=Rt | EA=Rx;
if (Pv[0]){
Rx=Rx+s;
*EA = Rt;
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memw(Rs+#u6:2)=Rt | apply_extension(u);
EA=Rs+u;
if (!Pv[0]){
*EA = Rt;
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memw(Rx++#s4:2)=Rt | EA=Rx;
if (!Pv[0]){
Rx=Rx+s;
*EA = Rt;
} else {
NOP;
}
Copy to clipboard | | if (Pv) memw(Rs+Ru<<#u2)=Rt | EA=Rs+(Ru< if (Pv[0]){
*EA = Rt;
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memw(Rs+Ru<<#u2)=Rt | EA=Rs+(Ru< if (!Pv[0]){
*EA = Rt;
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memw(Rs+#u6:2)=Rt | apply_extension(u);
EA=Rs+u;
if ( Pv.new[0]) {
*EA = Rt;
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memw(Rs+#u6:2)=Rt | apply_extension(u);
EA=Rs+u;
if (!Pv.new[0]) {
*EA = Rt;
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memw(Rs+Ru<<#u2)=Rt | EA=Rs+(Ru< if ( Pv.new[0]) {
*EA = Rt;
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memw(Rs+Ru<<#u2)=Rt | EA=Rs+(Ru< if (!Pv.new[0]) {
*EA = Rt;
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memw(Rx++#s4:2)=Rt | EA=Rx;
if (Pv.new[0]){
Rx=Rx+s;
*EA = Rt;
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memw(Rx++#s4:2)=Rt | EA=Rx;
if (!Pv.new[0]){
Rx=Rx+s;
*EA = Rt;
} else {
NOP;
}
Copy to clipboard | | if (Pv) memw(#u6)=Rt | apply_extension(u);
EA=u;
if (Pv[0]){
*EA = Rt;
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memw(#u6)=Rt | apply_extension(u);
EA=u;
if (!Pv[0]){
*EA = Rt;
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memw(#u6)=Rt | apply_extension(u);
EA=u;
if ( Pv.new[0]) {
*EA = Rt;
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memw(#u6)=Rt | apply_extension(u);
EA=u;
if (!Pv.new[0]) {
*EA = Rt;
} else {
NOP;
}
Copy to clipboard | | if (Pv) memw(Rs)=Rt | Assembler mapped to: "if (Pv) ""memw""(Rs+0)=""Rt"
Copy to clipboard | | if (!Pv) memw(Rs)=Rt | Assembler mapped to: "if (!Pv) ""memw""(Rs+0)=""Rt"
Copy to clipboard | | if (Pv.new) memw(Rs)=Rt | Assembler mapped to: "if (Pv.new) ""memw""(Rs+0)=""Rt"
Copy to clipboard | | if (!Pv.new) memw(Rs)=Rt | Assembler mapped to: "if (!Pv.new) ""memw""(Rs+0)=""Rt"
Copy to clipboard | | if (Pv) memw(Rs+#u6:2)=#S6 | EA=Rs+u;
if (Pv[0]){
apply_extension(S);
*EA = S;
} else {
NOP;
}
Copy to clipboard | | if (!Pv) memw(Rs+#u6:2)=#S6 | EA=Rs+u;
if (!Pv[0]){
apply_extension(S);
*EA = S;
} else {
NOP;
}
Copy to clipboard | | if (Pv.new) memw(Rs+#u6:2)=#S6 | EA=Rs+u;
if (Pv.new[0]){
apply_extension(S);
*EA = S;
} else {
NOP;
}
Copy to clipboard | | if (!Pv.new) memw(Rs+#u6:2)=#S6 | EA=Rs+u;
if (!Pv.new[0]){
apply_extension(S);
*EA = S;
} else {
NOP;
}
Copy to clipboard | | if (Pv) memw(Rs)=#S6 | Assembler mapped to: "if (Pv) ""memw""(Rs+0)=""S6"
Copy to clipboard | | if (!Pv) memw(Rs)=#S6 | Assembler mapped to: "if (!Pv) ""memw""(Rs+0)=""S6"
Copy to clipboard | | if (Pv.new) memw(Rs)=#S6 | Assembler mapped to: "if (Pv.new) ""memw""(Rs+0)=""S6"
Copy to clipboard | | if (!Pv.new) memw(Rs)=#S6 | Assembler mapped to: "if (!Pv.new) ""memw""(Rs+0)=""S6"
Copy to clipboard | **Class: ST (slots 0,1)** Note - Non Temporal Data. The :nt appendix is a hint to the microarchitecture indicating that the life of the cache line is short. This information is used throughout the cache hierarchy to make replacement and allocation decisions.
Encodings
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### Allocate stack frame Allocate a stack frame on the call stack. This instruction first pushes LR and FP to the top of stack. It then subtracts an unsigned immediate from SP to allocate room for local variables. FP is set to the address of the old frame pointer on the stack. The following figure shows the stack layout. Page-1 Sheet.2 Sheet.4 FP register FP register Sheet.5 Sheet.6 Sheet.7 Saved LR Saved LR Sheet.8 Sheet.9 Sheet.10 Saved FP Saved FP Sheet.11 Sheet.12 Sheet.13 Procedure local Procedure local Sheet.14 data on stack data on stack Sheet.15 Sheet.16 Sheet.17 Saved LR Saved LR Sheet.18 Sheet.19 Sheet.20 Saved FP Saved FP Sheet.21 Sheet.22 Sheet.23 SP register SP register Sheet.24 Sheet.25 Sheet.26 Sheet.27 Unallocated stack Unallocated stack Sheet.28 Sheet.29 Sheet.30 Higher address Higher address Sheet.31 Lower address Lower address Sheet.32 Sheet.33 Sheet.34 Stack in memory Stack in memory Sheet.35 Sheet.36 Sheet.37 Procedure local Procedure local Sheet.38 data on stack data on stack Sheet.1 Sheet.41 Stack frame Stack frame Sheet.3 Sheet.39 Sheet.40 Allocate stack frame instructions | **Syntax** | **Behavior** | | --- | --- | | allocframe(Rx,#u11:3):raw | apply_extension(u);
EA=Rx+-8;
*EA = frame_scramble((LR << 32) | FP);
FP=EA;
frame_check_limit(EA-u);
Rx = EA-u;
Copy to clipboard | | allocframe(#u11:3) | Assembler mapped to: "allocframe(r29,u11:3):raw"
Copy to clipboard | **Class: ST (slots 0)**
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## SYSTEM The SYSTEM instruction class includes instructions for managing system resources. ### USER The SYSTEM/USER instruction subclass allows user access to system resources. #### Load locked The memory lock instructions perform a word or double-word locked load. The instructions return the contents of the memory at address Rs and reserves a lock reservation at that address. For more information, see the section on atomic operations. Load locked instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=memw\_locked(Rs) | EA=Rs;
Rd = *EA;
Copy to clipboard | | Rdd=memd\_locked(Rs) | EA=Rs;
Rdd = *EA;
Copy to clipboard | **Class: SYSTEM (slots 0)** Note - This instruction may only be grouped with ALU32 or non-floating-point XTYPE instructions.
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#### Store conditional The memory lock instructions perform a word or double-word conditional store operation. When the hardware thread holds the address reservation, and there are no intervening accesses to the address location, then the store completes and the predicate is true. Otherwise, the store does not occur and the predicate is false. For more information, see the section on atomic operations. Store conditional instructions | **Syntax** | **Behavior** | | --- | --- | | memw\_locked(Rs,Pd)=Rt | EA=Rs;
if (lock_valid) {
*EA = Rt;
Pd = 0xff;
lock_valid = 0;
} else {
Pd = 0;
}
Copy to clipboard | | memd\_locked(Rs,Pd)=Rtt | EA=Rs;
if (lock_valid) {
*EA = Rtt;
Pd = 0xff;
lock_valid = 0;
} else {
Pd = 0;
}
Copy to clipboard | **Class: SYSTEM (slots 0)** Note - This instruction may only be grouped with ALU32 or non-floating-point XTYPE instructions. - The predicate generated by this instruction can not be used as a .new predicate, nor can it be automatically ANDed with another predicate.
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#### Zero a cache line The dczeroa instruction clears 32 bytes of memory. The level 1 data cache allocates the cache line and clears 32 bytes when the address is write-back cacheable. The level 2 unified cache allocates the cache line and clears 32 bytes when the address is write-through cacheable. If the level 2 unified cache is disabled, then the Hexagon sends 32 bytes of zero to the memory address. This instruction efficiently handles write-only data by pre-allocating lines in the appropriate cache or memory. When the the address is not 32-byte aligned, the hardware will raise an unaligned error exception. Zero a cache line instructions | **Syntax** | **Behavior** | | --- | --- | | dczeroa(Rs) | EA=Rs;
dcache_zero_addr(EA);
Copy to clipboard | | dczeroa(Rs):nt | EA=Rs;
dcache_zero_addr(EA);
Copy to clipboard | **Class: SYSTEM (slots 0)** Note - A packet containing this instruction must have slot 1 either empty or executing an ALU32 instruction. - Non Temporal Data. The :nt appendix is a hint to the microarchitecture indicating that the life of the cache line is short. This information is used throughout the cache hierarchy to make replacement and allocation decisions.
Encodings
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Intrinsics
Zero a cache line intrinsics

dczeroa(Rs)

void Q6_dczeroa_A(Address a)
#### Memory barrier The barrier instruction establishes a memory barrier to ensure proper ordering between load/store accesses within a consistency domain before the barrier instruction and accesses after the barrier instruction. All scalar loads, stores, and cache operation by address within a consistency domain before the barrier are globally observable before any access after the barrier. The use of this instruction is system-dependent. Memory barrier instructions | **Syntax** | **Behavior** | | --- | --- | | barrier | memory_barrier;
Copy to clipboard | **Class: SYSTEM (slots 0)** Note - This is a solo instruction. It must not be grouped with other instructions in a packet.
Encodings
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#### Breakpoint The brkpt instruction causes the program to enter debug mode if enabled by ISDB. Execution control is handed to ISDB and the program will not proceed until directed by the debugger. When ISDB is disabled, this instruction is treated as a nop. Breakpoint instructions | **Syntax** | **Behavior** | | --- | --- | | brkpt | Enter Debug mode;
Copy to clipboard | **Class: SYSTEM (slots 3)** Note - This is a solo instruction. It must not be grouped with other instructions in a packet.
Encodings
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#### Data cache prefetch The dcfetch instruction prefetches the data at address Rs + unsigned immediate. This instruction is a hint to the memory system and its behavior is implementation-dependent. Data cache prefetch instructions | **Syntax** | **Behavior** | | --- | --- | | dcfetch(Rs+#u11:3):nt | EA=Rs+u;
dcache_fetch(EA);
Copy to clipboard | | dcfetch(Rs+#u11:3) | EA=Rs+u;
dcache_fetch(EA);
Copy to clipboard | | dcfetch(Rs) | Assembler mapped to: "dcfetch(Rs+0)"
Copy to clipboard | **Class: SYSTEM (slots 0)** Note - Non Temporal Data Cache Prefetch. The :nt appendix is a hint to the microarchitecture indicating that the life of the cache line fetched is short. This information is used throughout the cache hierarchy to make replacement and allocation decisions.
Encodings
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dcfetch(Rs+#u11:3)

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Intrinsics
Data cache prefetch intrinsics

dcfetch(Rs)

void Q6_dcfetch_A(Address a)
#### Data cache maintenance user operations These instructions perform maintenance operations on the data cache. The dccleaninva instruction looks up the data cache at address Rs. If this address is in the cache and has dirty data, the data is flushed out to memory and the line is invalidated. The dccleana instructions looks up the data cache at address Rs. If this address is in the cache and has dirty data, the data is flushed out to memory. The dcinva instruction maps to dccleaninva. In implementations that support L2 cache, these instructions operate on both L1 data and L2 caches. Data cache maintenance user operations instructions | **Syntax** | **Behavior** | | --- | --- | | dccleana(Rs) | EA=Rs;
dcache_clean_addr(EA);
Copy to clipboard | | dccleaninva(Rs) | EA=Rs;
dcache_cleaninv_addr(EA);
Copy to clipboard | | dcinva(Rs) | EA=Rs;
dcache_cleaninv_addr(EA);
Copy to clipboard | **Class: SYSTEM (slots 0)** Note - A packet containing this instruction must have slot 1 either empty or executing an ALU32 instruction.
Encodings
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Intrinsics
Data cache maintenance user operations intrinsics

dccleana(Rs)

void Q6_dccleana_A(Address a)

dccleaninva(Rs)

void Q6_dccleaninva_A(Address a)

dcinva(Rs)

void Q6_dcinva_A(Address a)
#### Send value to DIAG trace These instructions send the sources to the external DIAG trace. The diag instruction sends Rs to the DIAG trace port. The diag0/diag1 instructions sends Rss and Rtt (128 bits) to the DIAG trace port. For format details, see DTM instructions in the architecture spec. Send value to DIAG trace instructions | **Syntax** | **Behavior** | | --- | --- | | diag(Rs) | Copy to clipboard | | diag0(Rss,Rtt) | Copy to clipboard | | diag1(Rss,Rtt) | Copy to clipboard | **Class: SYSTEM (slots 3)**
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#### Instruction cache maintenance user operations The icinva instruction looks up the address in Rs in the instruction cache. If a translation for Rs cannot be found then the Hexagon raises a TLB-miss-X exception with cause code 0x62. When in user mode, the X bit must be set for the address. Otherwise Hexagon executes the instruction as a nop. Monitor mode ignores the permission bits. The instruction invalidates all ways of all 32B segments matching the set index in Rs.. Due to aliasing only Rs[11:5] are significant, meaning in caches above 16 KB in size the instruction will invalidate multiple sets. Instruction cache maintenance user operations instructions | **Syntax** | **Behavior** | | --- | --- | | icinva(Rs) | EA=Rs;
icache_inv_addr(EA);
Copy to clipboard | **Class: SYSTEM (slots 2)** Note - This is a solo instruction. It must not be grouped with other instructions in a packet.
Encodings
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#### Instruction synchronization The isync instruction ensures that all previous instructions have committed before continuing to the next instruction. Execute this instruction after the following events (when subsequent instructions must observe the results of the event): After modifying the TLB with a tlbw instruction After modifying the SSR register After modifying the SYSCFG register After any instruction cache maintenance operation After modifying the HTID register Instruction synchronization instructions | **Syntax** | **Behavior** | | --- | --- | | isync | instruction_sync;
Copy to clipboard | **Class: SYSTEM (slots 2)** Note - This is a solo instruction. It must not be grouped with other instructions in a packet.
Encodings
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#### L2 cache prefetch The l2fetch instruction initiates background prefetch of code or data into the L2 cache. There are two forms of this instruction. In the first form, Rs,Rt specify the start address and dimensions of the area to prefetch as follows: <ul> <li>Rs specifies the 32-bit virtual start address.</li> <li>Rt[15:8] = Width of a fetch block in bytes.</li> <li>Rt[7:0] = Height: the number of Width-sized blocks to fetch.</li> <li>Rt[31:16] = Stride: an unsigned byte offset added to the pointer after fetching each Width-sized block.</li> </ul> In the second form, Rs,Rtt specify the start address and dimensions of the area to prefetch as follows: <ul> <li>Rs specifies the 32-bit virtual start address.</li> <li>Rtt[31:16] = Width of a fetch block in bytes.</li> <li>Rtt[15:0] = Height: the number of Width-sized blocks to fetch.</li> <li>Rtt[47:32] = Stride: an unsigned byte offset added to the pointer after fetching each Width-sized block.</li> <li>Rtt[48] = Direction. If 0, prefetches in row-major order. All cache lines in a row are fetched before proceeding to the next row. If 1, prefetches in column-major order. All cache lines in a column are fetched before proceeding to the next column.</li> </ul> The following figure shows two examples of using the L2FETCH instruction. Page-1 Rectangle.4 Rectangle Start address Start address Rectangle.2 Stride Stride Sheet.9 Rs Rs Sheet.10 Stride Stride Sheet.140 L2FETCH for box prefetch L2FETCH for box prefetch Rectangle.3 Prefetch area Prefetch area Dynamic connector.5 Dynamic connector.7 Dynamic connector.11 Sheet.6 Width Width Sheet.12 Height Height Directed line 1 Rectangle.14 Width Width Rectangle.15 Height Height Sheet.13 Rt Rt Rectangle.16 Rectangle.17 Start address Start address Rectangle.18 128 128 Sheet.19 Rs Rs Sheet.21 L2FETCH for large linear prefetch L2FETCH for large linear prefetch Directed line 1.28 Rectangle.29 128 128 Rectangle.30 Lines Lines Sheet.31 Rt Rt Sheet.23 0 0 Sheet.25 7 7 Sheet.27 8 8 Sheet.36 15 15 Sheet.37 16 16 Sheet.38 31 31 Sheet.39 0 0 Sheet.40 7 7 Sheet.41 8 8 Sheet.42 15 15 Sheet.43 16 16 Sheet.44 31 31 Sheet.22 128 × Lines 128 × Lines Rectangle.32 Rectangle.33 Rectangle.34 Rectangle.45 Rectangle.46 Dynamic connector.20 In the box prefetch, a 2-D range of memory is defined within a larger frame. The second example shows prefetch for a large linear area of memory which has size Lines \* 128. The l2fetch instruction is non-blocking. After the instruction is initiated, the program will continue to the next instruction while prefetching occurs in the background. If and only if the lines are missing from the L2 cache, the hardware attempts to fetch them from the system memory. The hardware prefetch engine requests all lines in the programmed memory range and prefetches at a lower priority than demand fetches. This prevents prefetch from adding traffic while the system is under heavy load. If a program initiates an l2fetch while an older l2fetch request is pending, the new request is queued, up to 3 deep. If 3 l2fetch requests are pending, the next l2fetch stalls the hardware thread until the oldest request is complete. During the time an l2fetch is active for a thread, USR.PFA==1 indicates that prefetches are in progress. Executing an l2fetch with any subfield programmed as zero cancels all pending prefetches by the calling thread. The implementation may drop prefetches. L2 cache prefetch instructions | **Syntax** | **Behavior** | | --- | --- | | l2fetch(Rs,Rt) | l2fetch(Rs,INFO);
Copy to clipboard | | l2fetch(Rs,Rtt) | l2fetch(Rs,INFO);
Copy to clipboard | **Class: SYSTEM (slots 0)** Note - This instruction may only be grouped with ALU32 or non-floating-point XTYPE instructions.
Encodings
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Intrinsics
L2 cache prefetch intrinsics

l2fetch(Rs,Rt)

void Q6_l2fetch_AR(Address a, Word32 Rt)

l2fetch(Rs,Rtt)

void Q6_l2fetch_AP(Address a, Word64 Rtt)
#### Pause The pause instruction suspends execution of the hardware thread for a specified maximum number of cycles. During the pause duration, the program enters a low-power state and will not fetch and execute instructions. The instruction provides a short immediate which indicates the pause duration. The program will pause for at most the number of cycles specified in the immediate plus 8. The minimum pause interval is 8 cycles and the maximum pause interval is implementation defined. System events such as interrupts and exceptions trigger exits from pause mode. An implementation is free to pause for durations shorter than the pause interval but not longer. Pause instructions | **Syntax** | **Behavior** | | --- | --- | | pause(#u10) | Pause for u cycles;
Copy to clipboard | **Class: SYSTEM (slots 2)** Note - This is a solo instruction. It must not be grouped with other instructions in a packet.
Encodings
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pause(#u10)

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#### Memory thread synchronization The syncht instruction ensures that all currently outstanding memory transactions from all hardware threads have completed and are globally observable before continuing. Memory thread synchronization instructions | **Syntax** | **Behavior** | | --- | --- | | syncht | memory_synch;
Copy to clipboard | **Class: SYSTEM (slots 0)** Note - This is a solo instruction. It must not be grouped with other instructions in a packet.
Encodings
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#### Send value to ETM trace The trace instruction emits the value of register Rs to the ETM trace. Enable ETM to perform tracing. Send value to ETM trace instructions | **Syntax** | **Behavior** | | --- | --- | | trace(Rs) | Send value to ETM trace;
Copy to clipboard | **Class: SYSTEM (slots 3)** Note - This instruction may only be grouped with ALU32 or non-floating-point XTYPE instructions.
Encodings
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#### Trap The trap instruction causes a precise exception. Executing a trap instruction sets the SSR.EX to 1, which disables interrupts and enables monitor mode. The program then jumps to the vector location (either TRAP0 or TRAP1). The instruction specifies an 8-bit immediate field. This field is copied into the system status register cause field. Upon returning from the service routine with a RTE, execution resumes at the packet after the trap instruction. Hardware provides two trap instructions. Trap instructions | **Syntax** | **Behavior** | | --- | --- | | trap0(#u8) | SSR.CAUSE = u;
TRAP "0";
Copy to clipboard | | trap1(Rx,#u8) | if (!(IN_GUEST_MODE & CCR.GRE & (u == 1/2/3/4/6))) {
SSR.CAUSE = u;
TRAP "1";
} else if (u == 1) {
SSR[SR] = GSR[SS];
CCR[GIE] = GSR[IE];
SSR[GM] = GSR[UM];
PC = (GELR & -4);
} else if (u == 3) {
TEMP = CCR[GIE];
CCR[GIE] = Rx & 0x1;
Rx = TEMP;
} else if (u == 4) {
Rx=CCR[GIE];
} else if (u == 6) {
TEMP=SP;
SP=Rx;
Rx=TEMP;
Copy to clipboard | | trap1(#u8) | Assembler mapped to: "trap1(R0,u8)"
Copy to clipboard | **Class: SYSTEM (slots 2)** Note - This is a solo instruction. It must not be grouped with other instructions in a packet.
Encodings
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#### Unpause The unpause instruction resumes all hardware threads whose execution has been stalled with a pause instruction. Unpause instructions | **Syntax** | **Behavior** | | --- | --- | | unpause | Unpause threads currently in pause state;
Copy to clipboard | **Class: SYSTEM (slots 2)** Note - This is a solo instruction. It must not be grouped with other instructions in a packet.
Encodings
Bitmap

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## XTYPE The XTYPE instruction class includes instructions which perform most of the data processing done by the Hexagon processor. XTYPE instructions are executable on slot 2 or slot 3. ### ALU The XTYPE/ALU instruction subclass includes instructions which perform arithmetic and logical operations. #### Absolute value doubleword Take the absolute value of the 64-bit source register and place it in the destination register. Absolute value doubleword instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=abs(Rss) | Rdd = ABS(Rss);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
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Rdd=abs(Rss)

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Intrinsics
Absolute value doubleword intrinsics

Rdd=abs(Rss)

Word64 Q6_P_abs_P(Word64 Rss)
#### Absolute value word Take the absolute value of the source register and place it in the destination register. The 32-bit absolute value is available with optional saturation. The single case of saturation is if the source register is equal to 0x8000\_0000, then the destination saturates to 0x7fff\_ffff. Absolute value word instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=abs(Rs) | Rd = ABS(Rs);
Copy to clipboard | | Rd=abs(Rs):sat | Rd = sat_32(ABS(sxt_32_to_64(Rs)));
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

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Rd=abs(Rs)

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Intrinsics
Absolute value word intrinsics

Rd=abs(Rs)

Word32 Q6_R_abs_R(Word32 Rs)

Rd=abs(Rs):sat

Word32 Q6_R_abs_R_sat(Word32 Rs)
#### Add and accumulate Add Rs and Rt or a signed immediate, then add or subtract the resulting value. The result is saved in Rx. Add and accumulate instructions | **Syntax** | **Behavior** | | --- | --- | | Rx+=add(Rs,Rt) | Rx=Rx + Rs + Rt;
Copy to clipboard | | Rx+=add(Rs,#s8) | apply_extension(s);
Rx=Rx + Rs + s;
Copy to clipboard | | Rx-=add(Rs,Rt) | Rx=Rx - (Rs + Rt);
Copy to clipboard | | Rx-=add(Rs,#s8) | apply_extension(s);
Rx=Rx - (Rs + s);
Copy to clipboard | | Rd=add(Rs,add(Ru,#s6)) | Rd = Rs + Ru + apply_extension(s);
Copy to clipboard | | Rd=add(Rs,sub(#s6,Ru)) | Rd = Rs - Ru + apply_extension(s);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

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Rx+=add(Rs,Rt)

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Rd=add(Rs,add(Ru,#s6))

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Rd=add(Rs,sub(#s6,Ru))

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Intrinsics
Add and accumulate intrinsics

Rx+=add(Rs,Rt)

Word32 Q6_R_addacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=add(Rs,#s8)

Word32 Q6_R_addacc_RI(Word32 Rx, Word32 Rs, Word32 Is8)

Rx-=add(Rs,Rt)

Word32 Q6_R_addnac_RR(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=add(Rs,#s8)

Word32 Q6_R_addnac_RI(Word32 Rx, Word32 Rs, Word32 Is8)

Rd=add(Rs,add(Ru,#s6))

Word32 Q6_R_add_add_RRI(Word32 Rs, Word32 Ru, Word32 Is6)

Rd=add(Rs,sub(#s6,Ru))

Word32 Q6_R_add_sub_RIR(Word32 Rs, Word32 Is6, Word32 Ru)
#### Add doublewords The first form of this instruction adds two 32-bit registers. If the result overflows 32 bits, then the result is saturated to 0x7FFF\_FFFF for a positive result, or 0x8000\_0000 for a negative result. Note that 32-bit non-saturating register add is a ALU32-class instruction and can be executed on any slot. The second instruction form sign-extends a 32-bit register Rt to 64-bits and performs a 64-bit add with Rss. The result is stored in Rdd. The third instruction form adds 64-bit registers Rss and Rtt and places the result in Rdd. The final instruction form adds two 64-bit registers Rss and Rtt. If the result overflows 64 bits, then it is saturated to 0x7fff\_ffff\_ffff\_ffff for a positive result, or 0x8000\_0000\_0000\_0000 for a negative result. Add doublewords instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=add(Rss,Rtt) | Rdd=Rss+Rtt;
Copy to clipboard | | Rdd=add(Rss,Rtt):sat | Rdd=sat64(Rss+Rtt);
Copy to clipboard | | Rdd=add(Rss,Rtt):raw:lo | Rdd=Rtt+sxt_32_to_64(Rss.w[0]);
Copy to clipboard | | Rdd=add(Rss,Rtt):raw:hi | Rdd=Rtt+sxt_32_to_64(Rss.w[1]);
Copy to clipboard | | Rdd=add(Rs,Rtt) | if ("Rs & 1") {
Assembler mapped to: "Rdd=add(Rss,Rtt):raw:hi";
} else {
Assembler mapped to: "Rdd=add(Rss,Rtt):raw:lo";
}
Copy to clipboard | | Rd=add(Rs,Rt):sat:deprecated | Rd=sat_32(Rs+Rt);
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

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Intrinsics
Add doublewords intrinsics

Rdd=add(Rss,Rtt)

Word64 Q6_P_add_PP(Word64 Rss, Word64 Rtt)

Rdd=add(Rss,Rtt):sat

Word64 Q6_P_add_PP_sat(Word64 Rss, Word64 Rtt)

Rdd=add(Rs,Rtt)

Word64 Q6_P_add_RP(Word32 Rs, Word64 Rtt)
#### Add halfword Perform a 16-bit add with optional saturation, and place the result in either the upper or lower half of a register. If the result goes in the upper half, then the sources can be any high or low halfword of Rs and Rt. The lower 16 bits of the result are zeroed. If the result is to be placed in the lower 16 bits of Rd, then the Rs source can be either high or low, but the other source must be the low halfword of Rt. In this case, the upper halfword of Rd is the sign-extension of the low halfword. pic_addh Page-1 Rectangle.14 Rs.L Rs.L Sheet.2 Sheet.3 Sheet.5 Sheet.6 Rs Rs Rectangle.28 Rs.H Rs.H Rectangle.6 Rt.L Rt.L Sheet.9 Rt Rt Rectangle.9 Rt.H Rt.H Rectangle.15 Result Result Rectangle.29 Sign-extend Sign-extend Sheet.13 Rd Rd Rounded rectangle.107 16-bit add 16-bit add Rounded rectangle.32 Saturate Saturate Sheet.16 0x8000 0x8000 Sheet.17 Sheet.18 0x7FFF 0x7FFF Rounded rectangle.4 Mux Mux Sheet.21 Sheet.22 Sheet.24 Sheet.25 Sheet.26 Rd = add(Rt.l, Rs.[hl])[:sat] Rd = add(Rt.l, Rs.[hl])[:sat] Rectangle.27 Rs.L Rs.L Sheet.28 Sheet.29 Sheet.30 Sheet.31 Sheet.32 Rs Rs Rectangle.40 Rs.H Rs.H Rectangle.41 Rt.L Rt.L Sheet.35 Rt Rt Rectangle.43 Rt.H Rt.H Rectangle.44 Result Result Rectangle.45 0x0000 0x0000 Sheet.39 Rd Rd Rounded rectangle.47 16-bit add 16-bit add Rounded rectangle.48 Saturate Saturate Sheet.42 0x8000 0x8000 Sheet.43 Sheet.44 0x7FFF 0x7FFF Rounded rectangle.52 Mux Mux Rounded rectangle.53 Mux Mux Sheet.47 Sheet.48 Sheet.49 Sheet.50 Sheet.51 Sheet.52 Rd = add(Rt.[hl], Rs.[hl])[:sat]:<<16 Rd = add(Rt.[hl], Rs.[hl])[:sat]:<<16 Add halfword instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=add(Rt.L,Rs.L) | Rd=sxt_16_to_32((Rt.h[0]+Rs.h[0]));
Copy to clipboard | | Rd=add(Rt.L,Rs.H) | Rd=sxt_16_to_32((Rt.h[0]+Rs.h[1]));
Copy to clipboard | | Rd=add(Rt.L,Rs.L):sat | Rd=sat_16(Rt.h[0]+Rs.h[0]);
Copy to clipboard | | Rd=add(Rt.L,Rs.H):sat | Rd=sat_16(Rt.h[0]+Rs.h[1]);
Copy to clipboard | | Rd=add(Rt.L,Rs.L):<<16 | Rd=(Rt.h[0]+Rs.h[0])<<16;
Copy to clipboard | | Rd=add(Rt.L,Rs.H):<<16 | Rd=(Rt.h[0]+Rs.h[1])<<16;
Copy to clipboard | | Rd=add(Rt.H,Rs.L):<<16 | Rd=(Rt.h[1]+Rs.h[0])<<16;
Copy to clipboard | | Rd=add(Rt.H,Rs.H):<<16 | Rd=(Rt.h[1]+Rs.h[1])<<16;
Copy to clipboard | | Rd=add(Rt.L,Rs.L):sat:<<16 | Rd=(sat_16(Rt.h[0]+Rs.h[0]))<<16;
Copy to clipboard | | Rd=add(Rt.L,Rs.H):sat:<<16 | Rd=(sat_16(Rt.h[0]+Rs.h[1]))<<16;
Copy to clipboard | | Rd=add(Rt.H,Rs.L):sat:<<16 | Rd=(sat_16(Rt.h[1]+Rs.h[0]))<<16;
Copy to clipboard | | Rd=add(Rt.H,Rs.H):sat:<<16 | Rd=(sat_16(Rt.h[1]+Rs.h[1]))<<16;
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

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Rd=add(Rt.H,Rs.H):sat:<<16

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Intrinsics
Add halfword intrinsics

Rd=add(Rt.L,Rs.L)

Word32 Q6_R_add_RlRl(Word32 Rt, Word32 Rs)

Rd=add(Rt.L,Rs.H)

Word32 Q6_R_add_RlRh(Word32 Rt, Word32 Rs)

Rd=add(Rt.L,Rs.L):sat

Word32 Q6_R_add_RlRl_sat(Word32 Rt, Word32 Rs)

Rd=add(Rt.L,Rs.H):sat

Word32 Q6_R_add_RlRh_sat(Word32 Rt, Word32 Rs)

Rd=add(Rt.L,Rs.L):<<16

Word32 Q6_R_add_RlRl_s16(Word32 Rt, Word32 Rs)

Rd=add(Rt.L,Rs.H):<<16

Word32 Q6_R_add_RlRh_s16(Word32 Rt, Word32 Rs)

Rd=add(Rt.H,Rs.L):<<16

Word32 Q6_R_add_RhRl_s16(Word32 Rt, Word32 Rs)

Rd=add(Rt.H,Rs.H):<<16

Word32 Q6_R_add_RhRh_s16(Word32 Rt, Word32 Rs)

Rd=add(Rt.L,Rs.L):sat:<<16

Word32 Q6_R_add_RlRl_sat_s16(Word32 Rt, Word32 Rs)

Rd=add(Rt.L,Rs.H):sat:<<16

Word32 Q6_R_add_RlRh_sat_s16(Word32 Rt, Word32 Rs)

Rd=add(Rt.H,Rs.L):sat:<<16

Word32 Q6_R_add_RhRl_sat_s16(Word32 Rt, Word32 Rs)

Rd=add(Rt.H,Rs.H):sat:<<16

Word32 Q6_R_add_RhRh_sat_s16(Word32 Rt, Word32 Rs)
#### Add or subtract doublewords with carry Add or subtract with carry. Predicate register Px is used as an extra input and output. For adds, the LSB of the predicate is added to the sum of the two input pairs. For subtracts, the predicate is considered a not-borrow. The LSB of the predicate is added to the first source register and the logical complement of the second argument. The carry-out from the sum is saved in predicate Px. These instructions allow efficient addition or subtraction of numbers larger than 64 bits. Add or subtract doublewords with carry instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=add(Rss,Rtt,Px):carry | Rdd = Rss + Rtt + Px[0];
Px = carry_from_add(Rss,Rtt,Px[0]) ? 0xff : 0x00;
Copy to clipboard | | Rdd=sub(Rss,Rtt,Px):carry | Rdd = Rss + ~Rtt + Px[0];
Px = carry_from_add(Rss,~Rtt,Px[0]) ? 0xff : 0x00;
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - The predicate generated by this instruction can not be used as a .new predicate, nor can it be automatically ANDed with another predicate.
Encodings
Bitmap

Syntax

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Rdd=add(Rss,Rtt,Px):carry

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Rdd=sub(Rss,Rtt,Px):carry

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#### Logical doublewords Perform bitwise logical AND, OR, XOR, and NOT operations. The source and destination registers are 64-bit. For 32-bit logical operations, see the ALU32 logical instructions. Logical doublewords instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=and(Rtt,~Rss) | Rdd = (Rtt & ~Rss);
Copy to clipboard | | Rdd=or(Rtt,~Rss) | Rdd = (Rtt | ~Rss);
Copy to clipboard | | Rdd=and(Rss,Rtt) | Rdd=Rss&Rtt;
Copy to clipboard | | Rdd=or(Rss,Rtt) | Rdd=Rss|Rtt;
Copy to clipboard | | Rdd=xor(Rss,Rtt) | Rdd=Rss^Rtt;
Copy to clipboard | | Rdd=not(Rss) | Rdd=~Rss;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rdd=and(Rtt,~Rss)

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Rdd=or(Rtt,~Rss)

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Rdd=and(Rss,Rtt)

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Rdd=or(Rss,Rtt)

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Rdd=xor(Rss,Rtt)

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Rdd=not(Rss)

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Intrinsics
Logical doublewords intrinsics

Rdd=and(Rtt,~Rss)

Word64 Q6_P_and_PnP(Word64 Rtt, Word64 Rss)

Rdd=or(Rtt,~Rss)

Word64 Q6_P_or_PnP(Word64 Rtt, Word64 Rss)

Rdd=and(Rss,Rtt)

Word64 Q6_P_and_PP(Word64 Rss, Word64 Rtt)

Rdd=or(Rss,Rtt)

Word64 Q6_P_or_PP(Word64 Rss, Word64 Rtt)

Rdd=xor(Rss,Rtt)

Word64 Q6_P_xor_PP(Word64 Rss, Word64 Rtt)

Rdd=not(Rss)

Word64 Q6_P_not_P(Word64 Rss)
#### Logical-logical doublewords Perform a logical operation of the two source operands, then perform a second logical operation of the result with the destination register Rxx. The source and destination registers are 64-bit. Logical-logical doublewords instructions | **Syntax** | **Behavior** | | --- | --- | | Rxx^=xor(Rss,Rtt) | Rxx^=Rss^Rtt;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rxx^=xor(Rss,Rtt)

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Intrinsics
Logical-logical doublewords intrinsics

Rxx^=xor(Rss,Rtt)

Word64 Q6_P_xorxacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
#### Logical-logical words Perform a logical operation of the two source operands, then perform a second logical operation of the result with the destination register Rx. The source and destination registers are 32-bit. Logical-logical words instructions | **Syntax** | **Behavior** | | --- | --- | | Rx^=xor(Rs,Rt) | Rx^=Rs^Rt;
Copy to clipboard | | Rx&=and(Rs,Rt) | Rx &= (Rs & Rt);
Copy to clipboard | | Rx&=and(Rs,~Rt) | Rx &= (Rs & ~Rt);
Copy to clipboard | | Rx&=or(Rs,Rt) | Rx &= (Rs | Rt);
Copy to clipboard | | Rx&=xor(Rs,Rt) | Rx &= (Rs ^ Rt);
Copy to clipboard | | Rx|=and(Rs,Rt) | Rx |= (Rs & Rt);
Copy to clipboard | | Rx|=and(Rs,~Rt) | Rx |= (Rs & ~Rt);
Copy to clipboard | | Rx|=or(Rs,Rt) | Rx |= (Rs | Rt);
Copy to clipboard | | Rx|=xor(Rs,Rt) | Rx |= (Rs ^ Rt);
Copy to clipboard | | Rx=or(Ru,and(Rx,#s10)) | Rx = Ru | (Rx & apply_extension(s));
Copy to clipboard | | Rx|=and(Rs,#s10) | Rx = Rx | (Rs & apply_extension(s));
Copy to clipboard | | Rx|=or(Rs,#s10) | Rx = Rx | (Rs | apply_extension(s));
Copy to clipboard | | Rx^=and(Rs,Rt) | Rx ^= (Rs & Rt);
Copy to clipboard | | Rx^=or(Rs,Rt) | Rx ^= (Rs | Rt);
Copy to clipboard | | Rx^=and(Rs,~Rt) | Rx ^= (Rs & ~Rt);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rx^=xor(Rs,Rt)

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Rx&=and(Rs,Rt)

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Rx&=and(Rs,~Rt)

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Rx&=or(Rs,Rt)

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Rx&=xor(Rs,Rt)

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Rx|=and(Rs,Rt)

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Rx|=and(Rs,~Rt)

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Rx|=or(Rs,Rt)

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Rx|=xor(Rs,Rt)

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Rx=or(Ru,and(Rx,#s10))

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Rx|=and(Rs,#s10)

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Rx|=or(Rs,#s10)

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Rx^=and(Rs,Rt)

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Rx^=or(Rs,Rt)

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Rx^=and(Rs,~Rt)

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Intrinsics
Logical-logical words intrinsics

Rx^=xor(Rs,Rt)

Word32 Q6_R_xorxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)

Rx&=and(Rs,Rt)

Word32 Q6_R_andand_RR(Word32 Rx, Word32 Rs, Word32 Rt)

Rx&=and(Rs,~Rt)

Word32 Q6_R_andand_RnR(Word32 Rx, Word32 Rs, Word32 Rt)

Rx&=or(Rs,Rt)

Word32 Q6_R_orand_RR(Word32 Rx, Word32 Rs, Word32 Rt)

Rx&=xor(Rs,Rt)

Word32 Q6_R_xorand_RR(Word32 Rx, Word32 Rs, Word32 Rt)

Rx|=and(Rs,Rt)

Word32 Q6_R_andor_RR(Word32 Rx, Word32 Rs, Word32 Rt)

Rx|=and(Rs,~Rt)

Word32 Q6_R_andor_RnR(Word32 Rx, Word32 Rs, Word32 Rt)

Rx|=or(Rs,Rt)

Word32 Q6_R_oror_RR(Word32 Rx, Word32 Rs, Word32 Rt)

Rx|=xor(Rs,Rt)

Word32 Q6_R_xoror_RR(Word32 Rx, Word32 Rs, Word32 Rt)

Rx=or(Ru,and(Rx,#s10))

Word32 Q6_R_or_and_RRI(Word32 Ru, Word32 Rx, Word32 Is10)

Rx|=and(Rs,#s10)

Word32 Q6_R_andor_RI(Word32 Rx, Word32 Rs, Word32 Is10)

Rx|=or(Rs,#s10)

Word32 Q6_R_oror_RI(Word32 Rx, Word32 Rs, Word32 Is10)

Rx^=and(Rs,Rt)

Word32 Q6_R_andxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)

Rx^=or(Rs,Rt)

Word32 Q6_R_orxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)

Rx^=and(Rs,~Rt)

Word32 Q6_R_andxacc_RnR(Word32 Rx, Word32 Rs, Word32 Rt)
#### Maximum words Select either the signed or unsigned maximum of two source registers and place in a destination register Rdd. Maximum words instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=max(Rs,Rt) | Rd = max(Rs,Rt);
Copy to clipboard | | Rd=maxu(Rs,Rt) | Rd = max(Rs.uw[0],Rt.uw[0]);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rd=max(Rs,Rt)

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Rd=maxu(Rs,Rt)

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Intrinsics
Maximum words intrinsics

Rd=max(Rs,Rt)

Word32 Q6_R_max_RR(Word32 Rs, Word32 Rt)

Rd=maxu(Rs,Rt)

UWord32 Q6_R_maxu_RR(Word32 Rs, Word32 Rt)
#### Maximum doublewords Select either the signed or unsigned maximum of two 64-bit source registers and place in a destination register. Maximum doublewords instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=max(Rss,Rtt) | Rdd = max(Rss,Rtt);
Copy to clipboard | | Rdd=maxu(Rss,Rtt) | Rdd = max(Rss.u64,Rtt.u64);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rdd=max(Rss,Rtt)

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Rdd=maxu(Rss,Rtt)

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Intrinsics
Maximum doublewords intrinsics

Rdd=max(Rss,Rtt)

Word64 Q6_P_max_PP(Word64 Rss, Word64 Rtt)

Rdd=maxu(Rss,Rtt)

UWord64 Q6_P_maxu_PP(Word64 Rss, Word64 Rtt)
#### Minimum words Select either the signed or unsigned minimum of two source registers and place in destination register Rd. Minimum words instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=min(Rt,Rs) | Rd = min(Rt,Rs);
Copy to clipboard | | Rd=minu(Rt,Rs) | Rd = min(Rt.uw[0],Rs.uw[0]);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rd=min(Rt,Rs)

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Rd=minu(Rt,Rs)

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Intrinsics
Minimum words intrinsics

Rd=min(Rt,Rs)

Word32 Q6_R_min_RR(Word32 Rt, Word32 Rs)

Rd=minu(Rt,Rs)

UWord32 Q6_R_minu_RR(Word32 Rt, Word32 Rs)
#### Minimum doublewords Select either the signed or unsigned minimum of two 64-bit source registers and place in the destination register Rdd. Minimum doublewords instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=min(Rtt,Rss) | Rdd = min(Rtt,Rss);
Copy to clipboard | | Rdd=minu(Rtt,Rss) | Rdd = min(Rtt.u64,Rss.u64);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rdd=min(Rtt,Rss)

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Rdd=minu(Rtt,Rss)

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Intrinsics
Minimum doublewords intrinsics

Rdd=min(Rtt,Rss)

Word64 Q6_P_min_PP(Word64 Rtt, Word64 Rss)

Rdd=minu(Rtt,Rss)

UWord64 Q6_P_minu_PP(Word64 Rtt, Word64 Rss)
#### Modulo wrap Wrap the Rs value into the modulo range from 0 to Rt. If Rs is greater than or equal to Rt, wrap it to the bottom of the range by subtracting Rt. If Rs is less than zero, wrap it to the top of the range by adding Rt. Otherwise, when Rs fits within the range, no adjustment is necessary. The result is returned in register Rd. Modulo wrap instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=modwrap(Rs,Rt) | if (Rs < 0) {
Rd = Rs + Rt.uw[0];
} else if (Rs.uw[0] >= Rt.uw[0]) {
Rd = Rs - Rt.uw[0];
} else {
Rd = Rs;
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rd=modwrap(Rs,Rt)

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Intrinsics
Modulo wrap intrinsics

Rd=modwrap(Rs,Rt)

Word32 Q6_R_modwrap_RR(Word32 Rs, Word32 Rt)
#### Negate The first form of this instruction performs a negate on a 32-bit register with saturation. If the input is 0x80000000<comma> the result is saturated to 0x7fffffff. Note that the non-saturating 32-bit register negate is a ALU32-class instruction and can be executed on any slot. The second form of this instruction negates a 64-bit source register and place the result in destination Rdd. Negate instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=neg(Rs):sat | Rd = sat_32(-Rs.s64);
Copy to clipboard | | Rdd=neg(Rss) | Rdd = -Rss;
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rd=neg(Rs):sat

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Rdd=neg(Rss)

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Intrinsics
Negate intrinsics

Rd=neg(Rs):sat

Word32 Q6_R_neg_R_sat(Word32 Rs)

Rdd=neg(Rss)

Word64 Q6_P_neg_P(Word64 Rss)
#### Round Perform either arithmetic (.5 is rounded up) or convergent (.5 is rounded towards even) rounding to any bit location. Arithmetic rounding has optional saturation. In this version, the result is saturated to a 32-bit number after adding the rounding constant. After the rounding and saturation have been performed, the final result is right shifted using a sign-extending shift. Round instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=round(Rss):sat | tmp=sat64(Rss+0x080000000ULL);
Rd = tmp.w[1];
Copy to clipboard | | Rd=round(Rs,#u5) | Rd = (u==0)?(Rs):round(Rs,2**(u-1))>>u;
Copy to clipboard | | Rd=round(Rs,Rt) | Rd = (zxt_5_to_32(Rt)==0)?(Rs):round(Rs,2**(zxt_5_to_32(Rt)-1))>>zxt_5_to_32(Rt);
Copy to clipboard | | Rd=round(Rs,#u5):sat | Rd = (sat_32((u==0)?(Rs):round(Rs,2**(u-1))))>>u;
Copy to clipboard | | Rd=round(Rs,Rt):sat | Rd = (sat_32((zxt_5_to_32(Rt)==0)?(Rs):round(Rs,2**(zxt_5_to_32(Rt)-1))))>>zxt_5_to_32(Rt);
Copy to clipboard | | Rd=cround(Rs,#u5) | Rd = (u==0)?Rs:convround(Rs,2**(u-1))>>u;
Copy to clipboard | | Rd=cround(Rs,Rt) | Rd = (zxt_5_to_32(Rt)==0)?Rs:convround(Rs,2**(zxt_5_to_32(Rt)-1))>>zxt_5_to_32(Rt);
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rd=round(Rss):sat

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Rd=round(Rs,#u5)

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Rd=round(Rs,Rt)

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Rd=round(Rs,#u5):sat

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Rd=round(Rs,Rt):sat

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Rd=cround(Rs,#u5)

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Rd=cround(Rs,Rt)

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Intrinsics
Round intrinsics

Rd=round(Rss):sat

Word32 Q6_R_round_P_sat(Word64 Rss)

Rd=round(Rs,#u5)

Word32 Q6_R_round_RI(Word32 Rs, Word32 Iu5)

Rd=round(Rs,Rt)

Word32 Q6_R_round_RR(Word32 Rs, Word32 Rt)

Rd=round(Rs,#u5):sat

Word32 Q6_R_round_RI_sat(Word32 Rs, Word32 Iu5)

Rd=round(Rs,Rt):sat

Word32 Q6_R_round_RR_sat(Word32 Rs, Word32 Rt)

Rd=cround(Rs,#u5)

Word32 Q6_R_cround_RI(Word32 Rs, Word32 Iu5)

Rd=cround(Rs,Rt)

Word32 Q6_R_cround_RR(Word32 Rs, Word32 Rt)
#### Subtract doublewords Subtract the 64-bit register Rss from register Rtt. Subtract doublewords instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=sub(Rtt,Rss) | Rdd=Rtt-Rss;
Copy to clipboard | | Rd=sub(Rt,Rs):sat:deprecated | Rd=sat_32(Rt - Rs);
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rdd=sub(Rtt,Rss)

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Rd=sub(Rt,Rs):sat:deprecated

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Intrinsics
Subtract doublewords intrinsics

Rdd=sub(Rtt,Rss)

Word64 Q6_P_sub_PP(Word64 Rtt, Word64 Rss)
#### Subtract and accumulate words Subtract Rs from Rt, then add the resulting value with Rx. The result is saved in Rx. Subtract and accumulate words instructions | **Syntax** | **Behavior** | | --- | --- | | Rx+=sub(Rt,Rs) | Rx=Rx + Rt - Rs;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rx+=sub(Rt,Rs)

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Intrinsics
Subtract and accumulate words intrinsics

Rx+=sub(Rt,Rs)

Word32 Q6_R_subacc_RR(Word32 Rx, Word32 Rt, Word32 Rs)
#### Subtract halfword Perform a 16-bit subtract with optional saturation and place the result in either the upper or lower half of a register. If the result goes in the upper half, then the sources can be any high or low halfword of Rs and Rt. The lower 16 bits of the result are zeroed. If the result is to be placed in the lower 16 bits of Rd, then the Rs source can be either high or low, but the other source must be the low halfword of Rt. In this case, the upper halfword of Rd is the sign-extension of the low halfword. pic_addh Page-1 Sheet.60 Rectangle.14 Rt.L Rt.L Sheet.10 Sheet.11 Sheet.13 Sheet.27 Rt Rt Rectangle.28 Rt.H Rt.H Rectangle.6 Rs.L Rs.L Sheet.8 Rs Rs Rectangle.9 Rs.H Rs.H Rectangle.15 Result Result Rectangle.29 Sign-extend Sign-extend Sheet.30 Rd Rd Rounded rectangle.107 16-bit sub 16-bit sub Rounded rectangle.32 Saturate Saturate Sheet.1 0x8000 0x8000 Sheet.2 Sheet.3 0x7FFF 0x7FFF Rounded rectangle.4 Mux Mux Sheet.14 Sheet.16 Sheet.18 Sheet.19 Sheet.33 Rd = sub(Rt.[hl], Rs.l)[:sat] Rd = sub(Rt.[hl], Rs.l)[:sat] Rectangle.34 Rt.L Rt.L Sheet.35 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Rt Rt Rectangle.40 Rt.H Rt.H Rectangle.41 Rs.L Rs.L Sheet.42 Rs Rs Rectangle.43 Rs.H Rs.H Rectangle.44 Result Result Rectangle.45 0x0000 0x0000 Sheet.46 Rd Rd Rounded rectangle.47 16-bit sub 16-bit sub Rounded rectangle.48 Saturate Saturate Sheet.49 0x8000 0x8000 Sheet.50 Sheet.51 0x7FFF 0x7FFF Rounded rectangle.52 Mux Mux Rounded rectangle.53 Mux Mux Sheet.54 Sheet.55 Sheet.56 Sheet.57 Sheet.58 Sheet.59 Rd = sub(Rt.[hl], Rs.[hl])[:sat]:<<16 Rd = sub(Rt.[hl], Rs.[hl])[:sat]:<<16 Subtract halfword instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=sub(Rt.L,Rs.L) | Rd=sxt_16_to_32((Rt.h[0]-Rs.h[0]));
Copy to clipboard | | Rd=sub(Rt.L,Rs.H) | Rd=sxt_16_to_32((Rt.h[0]-Rs.h[1]));
Copy to clipboard | | Rd=sub(Rt.L,Rs.L):sat | Rd=sat_16(Rt.h[0]-Rs.h[0]);
Copy to clipboard | | Rd=sub(Rt.L,Rs.H):sat | Rd=sat_16(Rt.h[0]-Rs.h[1]);
Copy to clipboard | | Rd=sub(Rt.L,Rs.L):<<16 | Rd=(Rt.h[0]-Rs.h[0])<<16;
Copy to clipboard | | Rd=sub(Rt.L,Rs.H):<<16 | Rd=(Rt.h[0]-Rs.h[1])<<16;
Copy to clipboard | | Rd=sub(Rt.H,Rs.L):<<16 | Rd=(Rt.h[1]-Rs.h[0])<<16;
Copy to clipboard | | Rd=sub(Rt.H,Rs.H):<<16 | Rd=(Rt.h[1]-Rs.h[1])<<16;
Copy to clipboard | | Rd=sub(Rt.L,Rs.L):sat:<<16 | Rd=(sat_16(Rt.h[0]-Rs.h[0]))<<16;
Copy to clipboard | | Rd=sub(Rt.L,Rs.H):sat:<<16 | Rd=(sat_16(Rt.h[0]-Rs.h[1]))<<16;
Copy to clipboard | | Rd=sub(Rt.H,Rs.L):sat:<<16 | Rd=(sat_16(Rt.h[1]-Rs.h[0]))<<16;
Copy to clipboard | | Rd=sub(Rt.H,Rs.H):sat:<<16 | Rd=(sat_16(Rt.h[1]-Rs.h[1]))<<16;
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rd=sub(Rt.L,Rs.L)

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Rd=sub(Rt.L,Rs.H)

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Rd=sub(Rt.L,Rs.L):sat

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Rd=sub(Rt.L,Rs.H):sat

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Rd=sub(Rt.L,Rs.L):<<16

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Rd=sub(Rt.L,Rs.H):<<16

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Rd=sub(Rt.H,Rs.L):<<16

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Rd=sub(Rt.H,Rs.H):<<16

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Rd=sub(Rt.L,Rs.L):sat:<<16

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Rd=sub(Rt.L,Rs.H):sat:<<16

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Rd=sub(Rt.H,Rs.L):sat:<<16

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Rd=sub(Rt.H,Rs.H):sat:<<16

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Intrinsics
Subtract halfword intrinsics

Rd=sub(Rt.L,Rs.L)

Word32 Q6_R_sub_RlRl(Word32 Rt, Word32 Rs)

Rd=sub(Rt.L,Rs.H)

Word32 Q6_R_sub_RlRh(Word32 Rt, Word32 Rs)

Rd=sub(Rt.L,Rs.L):sat

Word32 Q6_R_sub_RlRl_sat(Word32 Rt, Word32 Rs)

Rd=sub(Rt.L,Rs.H):sat

Word32 Q6_R_sub_RlRh_sat(Word32 Rt, Word32 Rs)

Rd=sub(Rt.L,Rs.L):<<16

Word32 Q6_R_sub_RlRl_s16(Word32 Rt, Word32 Rs)

Rd=sub(Rt.L,Rs.H):<<16

Word32 Q6_R_sub_RlRh_s16(Word32 Rt, Word32 Rs)

Rd=sub(Rt.H,Rs.L):<<16

Word32 Q6_R_sub_RhRl_s16(Word32 Rt, Word32 Rs)

Rd=sub(Rt.H,Rs.H):<<16

Word32 Q6_R_sub_RhRh_s16(Word32 Rt, Word32 Rs)

Rd=sub(Rt.L,Rs.L):sat:<<16

Word32 Q6_R_sub_RlRl_sat_s16(Word32 Rt, Word32 Rs)

Rd=sub(Rt.L,Rs.H):sat:<<16

Word32 Q6_R_sub_RlRh_sat_s16(Word32 Rt, Word32 Rs)

Rd=sub(Rt.H,Rs.L):sat:<<16

Word32 Q6_R_sub_RhRl_sat_s16(Word32 Rt, Word32 Rs)

Rd=sub(Rt.H,Rs.H):sat:<<16

Word32 Q6_R_sub_RhRh_sat_s16(Word32 Rt, Word32 Rs)
#### Sign extend word to doubleword Sign-extend a 32-bit word to a 64-bit doubleword. Sign extend word to doubleword instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=sxtw(Rs) | Rdd = sxt_32_to_64(Rs);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rdd=sxtw(Rs)

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Intrinsics
Sign extend word to doubleword intrinsics

Rdd=sxtw(Rs)

Word64 Q6_P_sxtw_R(Word32 Rs)
#### Vector absolute value halfwords Take the absolute value of each of the four halfwords in the 64-bit source vector Rss. Place the result in Rdd. Saturation is optionally available. Vector absolute value halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vabsh(Rss) | for (i=0;i<4;i++) {
Rdd.h[i]=ABS(Rss.h[i]);
}
Copy to clipboard | | Rdd=vabsh(Rss):sat | for (i=0;i<4;i++) {
Rdd.h[i]=sat_16(ABS(Rss.h[i]));
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rdd=vabsh(Rss)

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Rdd=vabsh(Rss):sat

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Intrinsics
Vector absolute value halfwords intrinsics

Rdd=vabsh(Rss)

Word64 Q6_P_vabsh_P(Word64 Rss)

Rdd=vabsh(Rss):sat

Word64 Q6_P_vabsh_P_sat(Word64 Rss)
#### Vector absolute value words Take the absolute value of each of the two words in the 64-bit source vector Rss. Place the result in Rdd. Saturation is optionally available. Vector absolute value words instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vabsw(Rss) | for (i=0;i<2;i++) {
Rdd.w[i]=ABS(Rss.w[i]);
}
Copy to clipboard | | Rdd=vabsw(Rss):sat | for (i=0;i<2;i++) {
Rdd.w[i]=sat_32(ABS(Rss.w[i]));
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rdd=vabsw(Rss)

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Rdd=vabsw(Rss):sat

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Intrinsics
Vector absolute value words intrinsics

Rdd=vabsw(Rss)

Word64 Q6_P_vabsw_P(Word64 Rss)

Rdd=vabsw(Rss):sat

Word64 Q6_P_vabsw_P_sat(Word64 Rss)
#### Vector absolute difference bytes For each element in the source vector Rss, subtract the corresponding element in source vector Rtt. Take the absolute value of the results, and store into Rdd. Vector absolute difference bytes instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vabsdiffb(Rtt,Rss) | for (i=0;i<8;i++) {
Rdd.b[i]=ABS(Rtt.b[i] - Rss.b[i]);
}
Copy to clipboard | | Rdd=vabsdiffub(Rtt,Rss) | for (i=0;i<8;i++) {
Rdd.b[i]=ABS(Rtt.ub[i] - Rss.ub[i]);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

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Rdd=vabsdiffb(Rtt,Rss)

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Rdd=vabsdiffub(Rtt,Rss)

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Intrinsics
Vector absolute difference bytes intrinsics

Rdd=vabsdiffb(Rtt,Rss)

Word64 Q6_P_vabsdiffb_PP(Word64 Rtt, Word64 Rss)

Rdd=vabsdiffub(Rtt,Rss)

Word64 Q6_P_vabsdiffub_PP(Word64 Rtt, Word64 Rss)
#### Vector absolute difference halfwords For each element in the source vector Rss, subtract the corresponding element in source vector Rtt. Take the absolute value of the results, and store into Rdd. Vector absolute difference halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vabsdiffh(Rtt,Rss) | for (i=0;i<4;i++) {
Rdd.h[i]=ABS(Rtt.h[i] - Rss.h[i]);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

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Rdd=vabsdiffh(Rtt,Rss)

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Intrinsics
Vector absolute difference halfwords intrinsics

Rdd=vabsdiffh(Rtt,Rss)

Word64 Q6_P_vabsdiffh_PP(Word64 Rtt, Word64 Rss)
#### Vector absolute difference words For each element in the source vector Rss, subtract the corresponding element in source vector Rtt. Take the absolute value of the results, and store into Rdd. Vector absolute difference words instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vabsdiffw(Rtt,Rss) | for (i=0;i<2;i++) {
Rdd.w[i]=ABS(Rtt.w[i] - Rss.w[i]);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rdd=vabsdiffw(Rtt,Rss)

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Intrinsics
Vector absolute difference words intrinsics

Rdd=vabsdiffw(Rtt,Rss)

Word64 Q6_P_vabsdiffw_PP(Word64 Rtt, Word64 Rss)
#### Vector add compare and select maximum halfwords Add each halfword element in Rxx and Rtt, and compare the resulting sums with the corresponding differences between Rss and Rtt. Store the maximum value of each compare in Rxx, and set the corresponding bits in a predicate destination to ‘11’ if the compare result is greater, ‘00’ if not. Each sum and difference is saturated to 16 bits before the compare, and the compare operation is a signed halfword compare. pic_addh Page-1 Sheet.139 Rectangle.14 Rtt.H2 Rtt.H2 Rectangle.28 Rtt.H3 Rtt.H3 Rectangle.34 Rtt.H0 Rtt.H0 Sheet.39 Rtt Rtt Rectangle.40 Rtt.H1 Rtt.H1 Sheet.42 Rss Rss Sheet.59 Rxx, Pd = vacsh(Rss, Rtt) Rxx, Pd = vacsh(Rss, Rtt) Rectangle.4 Rss.H2 Rss.H2 Rectangle.5 Rss.H3 Rss.H3 Rectangle.6 Rss.H0 Rss.H0 Rectangle.8 Rss.H1 Rss.H1 Rectangle.9 Rxx.H2 Rxx.H2 Rectangle.12 Rxx.H3 Rxx.H3 Rectangle.13 Rxx.H0 Rxx.H0 Rectangle.14 Rxx.H1 Rxx.H1 Circle + + Dynamic connector Dynamic connector.18 Circle.20 - - Dynamic connector.21 Dynamic connector.22 Circle.23 > > Dynamic connector.24 Dynamic connector.25 Dynamic connector.26 Sheet.37 Rectangle.29 Sheet.27 Sheet.33 Sheet.35 1 1 Sheet.36 0 0 Dynamic connector.38 Dynamic connector.41 Rectangle.1 Rxx.H2 Rxx.H2 Rectangle.2 Rxx.H3 Rxx.H3 Rectangle.3 Rxx.H0 Rxx.H0 Rectangle.10 Rxx.H1 Rxx.H1 Dynamic connector.11 Circle.30 + + Dynamic connector.31 Dynamic connector.32 Circle.43 - - Dynamic connector.44 Dynamic connector.45 Circle.47 > > Dynamic connector.48 Dynamic connector.49 Sheet.51 Rectangle.29 Sheet.53 Sheet.54 Sheet.55 1 1 Sheet.56 0 0 Dynamic connector.57 Dynamic connector.58 Dynamic connector.60 Circle.15 + + Dynamic connector.19 Dynamic connector.61 Circle.63 - - Dynamic connector.64 Dynamic connector.65 Circle.66 > > Dynamic connector.67 Dynamic connector.68 Dynamic connector.69 Sheet.70 Rectangle.29 Sheet.72 Sheet.73 Sheet.74 1 1 Sheet.75 0 0 Dynamic connector.76 Dynamic connector.77 Dynamic connector.78 Circle.79 + + Dynamic connector.80 Dynamic connector.81 Circle.82 - - Dynamic connector.83 Dynamic connector.84 Circle.85 > > Dynamic connector.86 Dynamic connector.87 Dynamic connector.88 Sheet.89 Rectangle.29 Sheet.91 Sheet.92 Sheet.93 1 1 Sheet.94 0 0 Dynamic connector.95 Dynamic connector.96 Dynamic connector.97 Sheet.46 Rxx Rxx Dynamic connector.62 Dynamic connector.50 Dynamic connector.98 Dynamic connector.99 Dynamic connector.100 Dynamic connector.101 Dynamic connector.102 Dynamic connector.103 Rectangle.104 Pd Pd Dynamic connector.105 Sheet.106 Sheet.107 16 bits 16 bits Sheet.108 Sheet.109 1 bit 1 bit Rectangle.7 sat16 sat16 Rectangle.111 sat16 sat16 Rectangle.112 sat16 sat16 Rectangle.113 sat16 sat16 Rectangle.114 sat16 sat16 Rectangle.115 sat16 sat16 Rectangle.116 sat16 sat16 Rectangle.117 sat16 sat16 Sheet.118 Sheet.119 Sheet.120 Sheet.121 Sheet.122 Sheet.123 Sheet.124 Sheet.125 Sheet.126 Sheet.127 Sheet.128 Sheet.129 Sheet.130 Sheet.131 Sheet.132 Sheet.133 Sheet.134 Sheet.135 Sheet.136 Sheet.137 Sheet.138 Vector add compare and select maximum halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rxx,Pe=vacsh(Rss,Rtt) | for (i = 0; i < 4; i++) {
xv = (int) Rxx.h[i];
sv = (int) Rss.h[i];
tv = (int) Rtt.h[i];
xv = xv + tv;
sv = sv - tv;
Pe.i*2 = (xv > sv);
Pe.i*2+1 = (xv > sv);
Rxx.h[i]=sat_16(max(xv,sv));
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - The predicate generated by this instruction can not be used as a .new predicate, nor can it be automatically ANDed with another predicate. - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

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Rxx,Pe=vacsh(Rss,Rtt)

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#### Vector add halfwords Add each of the four halfwords in 64-bit vector Rss to the corresponding halfword in vector Rtt. Optionally saturate each 16-bit addition to either a signed or unsigned 16-bit value. Applying saturation to the vaddh instruction clamps the result to the signed range 0x8000 to 0x7fff, whereas applying saturation to the vadduh instruction ensures that the unsigned result falls within the range 0 to 0xffff. When saturation is not needed, the vaddh form should be used. For the 32-bit version of this vector operation, see the ALU32 instructions. Vector add halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vaddh(Rss,Rtt) | for (i=0;i<4;i++) {
Rdd.h[i]=Rss.h[i]+Rtt.h[i];
}
Copy to clipboard | | Rdd=vaddh(Rss,Rtt):sat | for (i=0;i<4;i++) {
Rdd.h[i]=sat_16(Rss.h[i]+Rtt.h[i]);
}
Copy to clipboard | | Rdd=vadduh(Rss,Rtt):sat | for (i=0;i<4;i++) {
Rdd.h[i]=usat_16(Rss.uh[i]+Rtt.uh[i]);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

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Rdd=vaddh(Rss,Rtt)

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Rdd=vaddh(Rss,Rtt):sat

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Rdd=vadduh(Rss,Rtt):sat

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Intrinsics
Vector add halfwords intrinsics

Rdd=vaddh(Rss,Rtt)

Word64 Q6_P_vaddh_PP(Word64 Rss, Word64 Rtt)

Rdd=vaddh(Rss,Rtt):sat

Word64 Q6_P_vaddh_PP_sat(Word64 Rss, Word64 Rtt)

Rdd=vadduh(Rss,Rtt):sat

Word64 Q6_P_vadduh_PP_sat(Word64 Rss, Word64 Rtt)
#### Vector add halfwords with saturate and pack to unsigned bytes Add the four 16-bit halfwords of Rss to the four 16-bit halfwords of Rtt. The results are saturated to unsigned 8-bits and packed in destination register Rd. Vector add halfwords with saturate and pack to unsigned bytes instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=vaddhub(Rss,Rtt):sat | for (i=0;i<4;i++) {
Rd.b[i]=usat_8(Rss.h[i]+Rtt.h[i]);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

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Rd=vaddhub(Rss,Rtt):sat

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Intrinsics
Vector add halfwords with saturate and pack to unsigned bytes intrinsics

Rd=vaddhub(Rss,Rtt):sat

Word32 Q6_R_vaddhub_PP_sat(Word64 Rss, Word64 Rtt)
#### Vector reduce add unsigned bytes For each byte in the source vector Rss, add the corresponding byte in the source vector Rtt. Add the four upper intermediate results and optionally the upper word of the destination. Add the four lower results and optionally the lower word of the destination. pic_addh Page-1 Sheet.65 Sheet.1 Rss Rss Rectangle.61 Sheet.3 Rtt Rtt Sheet.4 Rdd Rdd Sheet.5 Rectangle.65 Rectangle.66 Rectangle.67 Rectangle.68 Rectangle.69 Rectangle.70 Rectangle.71 Rectangle.72 Rectangle.73 Rectangle.74 Rectangle.75 Rectangle.76 Rectangle.77 Rectangle.78 Rectangle.79 Sheet.21 Sheet.22 Rounded rectangle.82 + + Sheet.24 Sheet.25 Sheet.26 Rounded rectangle.86 + + Sheet.28 Sheet.29 Sheet.30 Rounded rectangle.90 + + Sheet.32 Sheet.33 Sheet.34 Rounded rectangle.94 + + Sheet.36 Sheet.37 Sheet.38 Rounded rectangle.98 + + Sheet.40 Sheet.41 Sheet.42 Rounded rectangle.102 + + Sheet.44 Sheet.45 Sheet.46 Rounded rectangle.106 + + Sheet.48 Sheet.49 Sheet.50 Rounded rectangle.110 + + Rounded rectangle.111 32-bit add 32-bit add Rectangle.16 Sheet.54 Sheet.55 Sheet.56 Sheet.57 Rounded rectangle.59 32-bit add 32-bit add Rectangle.60 Sheet.61 Sheet.62 Sheet.63 Sheet.64 Vector reduce add unsigned bytes instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vraddub(Rss,Rtt) | Rdd = 0;
for (i=0;i<4;i++) {
Rdd.w[0]=(Rdd.w[0] + (Rss.ub[i]+Rtt.ub[i]));
}
for (i=4;i<8;i++) {
Rdd.w[1]=(Rdd.w[1] + (Rss.ub[i]+Rtt.ub[i]));
}
Copy to clipboard | | Rxx+=vraddub(Rss,Rtt) | for (i = 0; i < 4; i++) {
Rxx.w[0]=(Rxx.w[0] + (Rss.ub[i]+Rtt.ub[i]));
}
for (i = 4; i < 8; i++) {
Rxx.w[1]=(Rxx.w[1] + (Rss.ub[i]+Rtt.ub[i]));
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

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Rdd=vraddub(Rss,Rtt)

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Rxx+=vraddub(Rss,Rtt)

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Intrinsics
Vector reduce add unsigned bytes intrinsics

Rdd=vraddub(Rss,Rtt)

Word64 Q6_P_vraddub_PP(Word64 Rss, Word64 Rtt)

Rxx+=vraddub(Rss,Rtt)

Word64 Q6_P_vraddubacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
#### Vector reduce add halfwords For each halfword in the source vector Rss, add the corresponding halfword in the source vector Rtt. Add these intermediate results together, and place the result in Rd. pic_addh Page-1 Sheet.56 Sheet.1 Rss Rss Sheet.2 + + Sheet.6 Rectangle Sheet.11 Rectangle.46 Rectangle.14 Rectangle.43 Rectangle.48 Sheet.17 Rtt Rtt Rectangle.4 Rectangle.6 Rectangle.11 Rectangle.12 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.31 + + Sheet.32 Sheet.37 + + Sheet.38 Sheet.43 + + Sheet.44 Sheet.49 Sheet.50 Sheet.51 Sheet.52 Sheet.55 Rd Rd Sheet.3 + + Sheet.4 Vector reduce add halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=vraddh(Rss,Rtt) | Rd = 0;
for (i=0;i<4;i++) {
Rd += (Rss.h[i]+Rtt.h[i]);
}
Copy to clipboard | | Rd=vradduh(Rss,Rtt) | Rd = 0;
for (i=0;i<4;i++) {
Rd += (Rss.uh[i]+Rtt.uh[i]);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

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Rd=vraddh(Rss,Rtt)

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Rd=vradduh(Rss,Rtt)

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Intrinsics
Vector reduce add halfwords intrinsics

Rd=vraddh(Rss,Rtt)

Word32 Q6_R_vraddh_PP(Word64 Rss, Word64 Rtt)

Rd=vradduh(Rss,Rtt)

Word32 Q6_R_vradduh_PP(Word64 Rss, Word64 Rtt)
#### Vector add bytes Add each of the eight bytes in 64-bit vector Rss to the corresponding byte in vector Rtt. Optionally, saturate each 8-bit addition to an unsigned value between 0 and 255. The eight results are stored in destination register Rdd. Vector add bytes instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vaddub(Rss,Rtt) | for (i = 0; i < 8; i++) {
Rdd.b[i]=(Rss.ub[i]+Rtt.ub[i]);
}
Copy to clipboard | | Rdd=vaddb(Rss,Rtt) | Assembler mapped to: "Rdd=vaddub(Rss,Rtt)"
Copy to clipboard | | Rdd=vaddub(Rss,Rtt):sat | for (i = 0; i < 8; i++) {
Rdd.b[i]=usat_8(Rss.ub[i]+Rtt.ub[i]);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

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Rdd=vaddub(Rss,Rtt):sat

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Intrinsics
Vector add bytes intrinsics

Rdd=vaddub(Rss,Rtt)

Word64 Q6_P_vaddub_PP(Word64 Rss, Word64 Rtt)

Rdd=vaddb(Rss,Rtt)

Word64 Q6_P_vaddb_PP(Word64 Rss, Word64 Rtt)

Rdd=vaddub(Rss,Rtt):sat

Word64 Q6_P_vaddub_PP_sat(Word64 Rss, Word64 Rtt)
#### Vector add words Add each of the two words in 64-bit vector Rss to the corresponding word in vector Rtt. Optionally, saturate each 32-bit addition to a signed value between 0x80000000 and 0x7fffffff. The two word results are stored in destination register Rdd. Vector add words instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vaddw(Rss,Rtt) | for (i=0;i<2;i++) {
Rdd.w[i]=Rss.w[i]+Rtt.w[i];
}
Copy to clipboard | | Rdd=vaddw(Rss,Rtt):sat | for (i=0;i<2;i++) {
Rdd.w[i]=sat_32(Rss.w[i]+Rtt.w[i]);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

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Rdd=vaddw(Rss,Rtt):sat

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Intrinsics
Vector add words intrinsics

Rdd=vaddw(Rss,Rtt)

Word64 Q6_P_vaddw_PP(Word64 Rss, Word64 Rtt)

Rdd=vaddw(Rss,Rtt):sat

Word64 Q6_P_vaddw_PP_sat(Word64 Rss, Word64 Rtt)
#### Vector average halfwords Average each of the four halfwords in the 64-bit source vector Rss with the corresponding halfword in Rtt. The average operation performed on each halfword adds the two halfwords and shifts the result right by 1 bit. Unsigned average uses a logical right shift (shift in 0), whereas signed average uses an arithmetic right shift (shift in the sign bit). If the round option is used, then a 0x0001 is also added to each result before shifting. This operation does not overflow. In the case that a summation (before right shift by 1) causes an overflow of 32 bits, the value shifted in is the most-significant carry out. The signed average and negative average halfwords is available with optional convergent rounding. In convergent rounding, if the two LSBs after the addition/subtraction are 11, then a rounding constant of 1 is added, otherwise a 0 is added. This result is then shifted right by one bit. Convergent rounding accumulates less error than arithmetic rounding. Vector average halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vavguh(Rss,Rtt) | for (i=0;i<4;i++) {
Rdd.h[i]=(Rss.uh[i]+Rtt.uh[i])>>1;
}
Copy to clipboard | | Rdd=vavgh(Rss,Rtt) | for (i=0;i<4;i++) {
Rdd.h[i]=(Rss.h[i]+Rtt.h[i])>>1;
}
Copy to clipboard | | Rdd=vnavgh(Rtt,Rss) | for (i=0;i<4;i++) {
Rdd.h[i]=(Rtt.h[i]-Rss.h[i])>>1;
}
Copy to clipboard | | Rdd=vavgh(Rss,Rtt):crnd | for (i=0;i<4;i++) {
Rdd.h[i]=convround(Rss.h[i]+Rtt.h[i])>>1;
}
Copy to clipboard | | Rdd=vnavgh(Rtt,Rss):crnd:sat | for (i=0;i<4;i++) {
Rdd.h[i]=sat_16(convround(Rtt.h[i]-Rss.h[i])>>1);
}
Copy to clipboard | | Rdd=vavguh(Rss,Rtt):rnd | for (i=0;i<4;i++) {
Rdd.h[i]=(Rss.uh[i]+Rtt.uh[i]+1)>>1;
}
Copy to clipboard | | Rdd=vavgh(Rss,Rtt):rnd | for (i=0;i<4;i++) {
Rdd.h[i]=(Rss.h[i]+Rtt.h[i]+1)>>1;
}
Copy to clipboard | | Rdd=vnavgh(Rtt,Rss):rnd:sat | for (i=0;i<4;i++) {
Rdd.h[i]=sat_16((Rtt.h[i]-Rss.h[i]+1)>>1);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rdd=vavguh(Rss,Rtt)

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Rdd=vavgh(Rss,Rtt)

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Rdd=vnavgh(Rtt,Rss)

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Rdd=vavgh(Rss,Rtt):crnd

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Rdd=vnavgh(Rtt,Rss):crnd:sat

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Rdd=vavguh(Rss,Rtt):rnd

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Rdd=vavgh(Rss,Rtt):rnd

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Rdd=vnavgh(Rtt,Rss):rnd:sat

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Intrinsics
Vector average halfwords intrinsics

Rdd=vavguh(Rss,Rtt)

Word64 Q6_P_vavguh_PP(Word64 Rss, Word64 Rtt)

Rdd=vavgh(Rss,Rtt)

Word64 Q6_P_vavgh_PP(Word64 Rss, Word64 Rtt)

Rdd=vnavgh(Rtt,Rss)

Word64 Q6_P_vnavgh_PP(Word64 Rtt, Word64 Rss)

Rdd=vavgh(Rss,Rtt):crnd

Word64 Q6_P_vavgh_PP_crnd(Word64 Rss, Word64 Rtt)

Rdd=vnavgh(Rtt,Rss):crnd:sat

Word64 Q6_P_vnavgh_PP_crnd_sat(Word64 Rtt, Word64 Rss)

Rdd=vavguh(Rss,Rtt):rnd

Word64 Q6_P_vavguh_PP_rnd(Word64 Rss, Word64 Rtt)

Rdd=vavgh(Rss,Rtt):rnd

Word64 Q6_P_vavgh_PP_rnd(Word64 Rss, Word64 Rtt)

Rdd=vnavgh(Rtt,Rss):rnd:sat

Word64 Q6_P_vnavgh_PP_rnd_sat(Word64 Rtt, Word64 Rss)
#### Vector average unsigned bytes Average each of the eight unsigned bytes in the 64-bit source vector Rss with the corresponding byte in Rtt. The average operation performed on each byte is the sum of the two bytes shifted right by 1 bit. If the round option is used, then a 0x01 is also added to each result before shifting. This operation does not overflow. In the case that a summation (before right shift by 1) causes an overflow of 8 bits, the value shifted in is the most-significant carry out. Vector average unsigned bytes instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vavgub(Rss,Rtt) | for (i = 0; i < 8; i++) {
Rdd.b[i]=((Rss.ub[i] + Rtt.ub[i])>>1);
}
Copy to clipboard | | Rdd=vavgub(Rss,Rtt):rnd | for (i = 0; i < 8; i++) {
Rdd.b[i]=((Rss.ub[i]+Rtt.ub[i]+1)>>1);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rdd=vavgub(Rss,Rtt)

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Rdd=vavgub(Rss,Rtt):rnd

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Intrinsics
Vector average unsigned bytes intrinsics

Rdd=vavgub(Rss,Rtt)

Word64 Q6_P_vavgub_PP(Word64 Rss, Word64 Rtt)

Rdd=vavgub(Rss,Rtt):rnd

Word64 Q6_P_vavgub_PP_rnd(Word64 Rss, Word64 Rtt)
#### Vector average words Average each of the two words in the 64-bit source vector Rss with the corresponding word in Rtt. The average operation performed on each halfword adds the two words and shifts the result right by 1 bit. Unsigned average uses a logical right shift (shift in 0), whereas signed average uses an arithmetic right shift (shift in the sign bit). If the round option is used, then a 0x1 is also added to each result before shifting. This operation does not overflow. In the case that a summation (before right shift by 1) causes an overflow of 32 bits, the value shifted in is the most-significant carry out. The signed average and negative average words is available with optional convergent rounding. In convergent rounding, if the two LSBs after the addition/subtraction are 11, then a rounding constant of 1 is added, otherwise a 0 is added. This result is then shifted right by one bit. Convergent rounding accumulates less error than arithmetic rounding. Vector average words instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vavgw(Rss,Rtt) | for (i=0;i<2;i++) {
Rdd.w[i]=(sxt_32_to_33(Rss.w[i])+sxt_32_to_33(Rtt.w[i]))>>1;
}
Copy to clipboard | | Rdd=vnavgw(Rtt,Rss) | for (i=0;i<2;i++) {
Rdd.w[i]=(sxt_32_to_33(Rtt.w[i])-sxt_32_to_33(Rss.w[i]))>>1;
}
Copy to clipboard | | Rdd=vavgw(Rss,Rtt):rnd | for (i=0;i<2;i++) {
Rdd.w[i]=(sxt_32_to_33(Rss.w[i])+sxt_32_to_33(Rtt.w[i])+1)>>1;
}
Copy to clipboard | | Rdd=vnavgw(Rtt,Rss):rnd:sat | for (i=0;i<2;i++) {
Rdd.w[i]=sat_32((sxt_32_to_33(Rtt.w[i])-sxt_32_to_33(Rss.w[i])+1)>>1);
}
Copy to clipboard | | Rdd=vavgw(Rss,Rtt):crnd | for (i=0;i<2;i++) {
Rdd.w[i]=(convround(sxt_32_to_33(Rss.w[i])+sxt_32_to_33(Rtt.w[i]))>>1);
}
Copy to clipboard | | Rdd=vnavgw(Rtt,Rss):crnd:sat | for (i=0;i<2;i++) {
Rdd.w[i]=sat_32(convround(sxt_32_to_33(Rtt.w[i])-sxt_32_to_33(Rss.w[i]))>>1);
}
Copy to clipboard | | Rdd=vavguw(Rss,Rtt) | for (i=0;i<2;i++) {
Rdd.w[i]=(zxt_32_to_33(Rss.uw[i])+zxt_32_to_33(Rtt.uw[i]))>>1;
}
Copy to clipboard | | Rdd=vavguw(Rss,Rtt):rnd | for (i=0;i<2;i++) {
Rdd.w[i]=(zxt_32_to_33(Rss.uw[i])+zxt_32_to_33(Rtt.uw[i])+1)>>1;
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rdd=vavgw(Rss,Rtt)

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s

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t

t

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d

d

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Rdd=vnavgw(Rtt,Rss)

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Rdd=vavgw(Rss,Rtt):rnd

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d

d

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Rdd=vnavgw(Rtt,Rss):rnd:sat

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0

1

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0

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Rdd=vavgw(Rss,Rtt):crnd

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Rdd=vnavgw(Rtt,Rss):crnd:sat

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Rdd=vavguw(Rss,Rtt)

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Rdd=vavguw(Rss,Rtt):rnd

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Intrinsics
Vector average words intrinsics

Rdd=vavgw(Rss,Rtt)

Word64 Q6_P_vavgw_PP(Word64 Rss, Word64 Rtt)

Rdd=vnavgw(Rtt,Rss)

Word64 Q6_P_vnavgw_PP(Word64 Rtt, Word64 Rss)

Rdd=vavgw(Rss,Rtt):rnd

Word64 Q6_P_vavgw_PP_rnd(Word64 Rss, Word64 Rtt)

Rdd=vnavgw(Rtt,Rss):rnd:sat

Word64 Q6_P_vnavgw_PP_rnd_sat(Word64 Rtt, Word64 Rss)

Rdd=vavgw(Rss,Rtt):crnd

Word64 Q6_P_vavgw_PP_crnd(Word64 Rss, Word64 Rtt)

Rdd=vnavgw(Rtt,Rss):crnd:sat

Word64 Q6_P_vnavgw_PP_crnd_sat(Word64 Rtt, Word64 Rss)

Rdd=vavguw(Rss,Rtt)

Word64 Q6_P_vavguw_PP(Word64 Rss, Word64 Rtt)

Rdd=vavguw(Rss,Rtt):rnd

Word64 Q6_P_vavguw_PP_rnd(Word64 Rss, Word64 Rtt)
#### Vector conditional negate Based on bits in Rt, conditionally negate halves in Rss. Vector conditional negate instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vcnegh(Rss,Rt) | for (i = 0; i < 4; i++) {
if (Rt.i) {
Rdd.h[i]=sat_16(-Rss.h[i]);
} else {
Rdd.h[i]=Rss.h[i];
}
}
Copy to clipboard | | Rxx+=vrcnegh(Rss,Rt) | for (i = 0; i < 4; i++) {
if (Rt.i) {
Rxx += -Rss.h[i];
} else {
Rxx += Rss.h[i];
}
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rdd=vcnegh(Rss,Rt)

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Rxx+=vrcnegh(Rss,Rt)

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x
Intrinsics
Vector conditional negate intrinsics

Rdd=vcnegh(Rss,Rt)

Word64 Q6_P_vcnegh_PR(Word64 Rss, Word32 Rt)

Rxx+=vrcnegh(Rss,Rt)

Word64 Q6_P_vrcneghacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
#### Vector maximum bytes Compare each of the eight unsigned bytes in the 64-bit source vector Rss to the corresponding byte in Rtt. For each comparison, select the maximum of the two bytes and place that byte in the corresponding location in Rdd. Vector maximum bytes instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vmaxb(Rtt,Rss) | for (i = 0; i < 8; i++) {
Rdd.b[i]=max(Rtt.b[i],Rss.b[i]);
}
Copy to clipboard | | Rdd=vmaxub(Rtt,Rss) | for (i = 0; i < 8; i++) {
Rdd.b[i]=max(Rtt.ub[i],Rss.ub[i]);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

31

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Rdd=vmaxb(Rtt,Rss)

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Rdd=vmaxub(Rtt,Rss)

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Intrinsics
Vector maximum bytes intrinsics

Rdd=vmaxb(Rtt,Rss)

Word64 Q6_P_vmaxb_PP(Word64 Rtt, Word64 Rss)

Rdd=vmaxub(Rtt,Rss)

Word64 Q6_P_vmaxub_PP(Word64 Rtt, Word64 Rss)
#### Vector maximum halfwords Compare each of the four halfwords in the 64-bit source vector Rss to the corresponding halfword in Rtt. For each comparison, select the maximum of the two halfwords and place that halfword in the corresponding location in Rdd. Comparisons are available in both signed and unsigned form. Vector maximum halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vmaxh(Rtt,Rss) | for (i = 0; i < 4; i++) {
Rdd.h[i]=max(Rtt.h[i],Rss.h[i]);
}
Copy to clipboard | | Rdd=vmaxuh(Rtt,Rss) | for (i = 0; i < 4; i++) {
Rdd.h[i]=max(Rtt.uh[i],Rss.uh[i]);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rdd=vmaxh(Rtt,Rss)

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Rdd=vmaxuh(Rtt,Rss)

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Intrinsics
Vector maximum halfwords intrinsics

Rdd=vmaxh(Rtt,Rss)

Word64 Q6_P_vmaxh_PP(Word64 Rtt, Word64 Rss)

Rdd=vmaxuh(Rtt,Rss)

Word64 Q6_P_vmaxuh_PP(Word64 Rtt, Word64 Rss)
#### Vector reduce maximum halfwords Register Rxx contains a maximum value in the low word and the address of that maximum value in the high word. Register Rss contains a vector of four halfword values, and register Ru contains the address of this data. The instruction finds the maximum halfword between the previous maximum in Rxx[0] and the four values in Rss. The address of the new maximum is stored in Rxx[1]. Vector reduce maximum halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rxx=vrmaxh(Rss,Ru) | max = Rxx.h[0];
addr = Rxx.w[1];
for (i = 0; i < 4; i++) {
if (max < Rss.h[i]) {
max = Rss.h[i];
addr = Ru | i<<1;
}
}
Rxx.w[0]=max;
Rxx.w[1]=addr;
Copy to clipboard | | Rxx=vrmaxuh(Rss,Ru) | max = Rxx.uh[0];
addr = Rxx.w[1];
for (i = 0; i < 4; i++) {
if (max < Rss.uh[i]) {
max = Rss.uh[i];
addr = Ru | i<<1;
}
}
Rxx.w[0]=max;
Rxx.w[1]=addr;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

31

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Rxx=vrmaxh(Rss,Ru)

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Rxx=vrmaxuh(Rss,Ru)

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Intrinsics
Vector reduce maximum halfwords intrinsics

Rxx=vrmaxh(Rss,Ru)

Word64 Q6_P_vrmaxh_PR(Word64 Rxx, Word64 Rss, Word32 Ru)

Rxx=vrmaxuh(Rss,Ru)

Word64 Q6_P_vrmaxuh_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
#### Vector reduce maximum words Find the maximum word between the previous maximum in Rxx[0] and the two values in Rss. The address of the new maximum is stored in Rxx[1]. Register Rxx contains a maximum value in the low word and the address of that maximum value in the high word. Register Rss contains a vector of two word values, and register Ru contains the address of this data. Vector reduce maximum words instructions | **Syntax** | **Behavior** | | --- | --- | | Rxx=vrmaxw(Rss,Ru) | max = Rxx.w[0];
addr = Rxx.w[1];
for (i = 0; i < 2; i++) {
if (max < Rss.w[i]) {
max = Rss.w[i];
addr = Ru | i<<2;
}
}
Rxx.w[0]=max;
Rxx.w[1]=addr;
Copy to clipboard | | Rxx=vrmaxuw(Rss,Ru) | max = Rxx.uw[0];
addr = Rxx.w[1];
for (i = 0; i < 2; i++) {
if (max < Rss.uw[i]) {
max = Rss.uw[i];
addr = Ru | i<<2;
}
}
Rxx.w[0]=max;
Rxx.w[1]=addr;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rxx=vrmaxw(Rss,Ru)

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Rxx=vrmaxuw(Rss,Ru)

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Intrinsics
Vector reduce maximum words intrinsics

Rxx=vrmaxw(Rss,Ru)

Word64 Q6_P_vrmaxw_PR(Word64 Rxx, Word64 Rss, Word32 Ru)

Rxx=vrmaxuw(Rss,Ru)

Word64 Q6_P_vrmaxuw_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
#### Vector maximum words Compare each of the two words in the 64-bit source vector Rss to the corresponding word in Rtt. For each comparison, select the maximum of the two words and place that word in the corresponding location in Rdd. Comparisons are available in both signed and unsigned form. Vector maximum words instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vmaxw(Rtt,Rss) | for (i = 0; i < 2; i++) {
Rdd.w[i]=max(Rtt.w[i],Rss.w[i]);
}
Copy to clipboard | | Rdd=vmaxuw(Rtt,Rss) | for (i = 0; i < 2; i++) {
Rdd.w[i]=max(Rtt.uw[i],Rss.uw[i]);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

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Rdd=vmaxw(Rtt,Rss)

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Rdd=vmaxuw(Rtt,Rss)

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Intrinsics
Vector maximum words intrinsics

Rdd=vmaxw(Rtt,Rss)

Word64 Q6_P_vmaxw_PP(Word64 Rtt, Word64 Rss)

Rdd=vmaxuw(Rtt,Rss)

Word64 Q6_P_vmaxuw_PP(Word64 Rtt, Word64 Rss)
#### Vector minimum bytes Compare each of the eight unsigned bytes in the 64-bit source vector Rss to the corresponding byte in Rtt. For each comparison, select the minimum of the two bytes and place that byte in the corresponding location in Rdd. Vector minimum bytes instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vminb(Rtt,Rss) | for (i = 0; i < 8; i++) {
Rdd.b[i]=min(Rtt.b[i],Rss.b[i]);
}
Copy to clipboard | | Rdd=vminub(Rtt,Rss) | for (i = 0; i < 8; i++) {
Rdd.b[i]=min(Rtt.ub[i],Rss.ub[i]);
}
Copy to clipboard | | Rdd,Pe=vminub(Rtt,Rss) | for (i = 0; i < 8; i++) {
Pe.i = (Rtt.ub[i] > Rss.ub[i]);
Rdd.b[i]=min(Rtt.ub[i],Rss.ub[i]);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - The predicate generated by this instruction can not be used as a .new predicate, nor can it be automatically ANDed with another predicate.
Encodings
Bitmap

Syntax

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Rdd=vminb(Rtt,Rss)

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Rdd=vminub(Rtt,Rss)

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Rdd,Pe=vminub(Rtt,Rss)

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Intrinsics
Vector minimum bytes intrinsics

Rdd=vminb(Rtt,Rss)

Word64 Q6_P_vminb_PP(Word64 Rtt, Word64 Rss)

Rdd=vminub(Rtt,Rss)

Word64 Q6_P_vminub_PP(Word64 Rtt, Word64 Rss)
#### Vector minimum halfwords Compare each of the four halfwords in the 64-bit source vector Rss to the corresponding halfword in Rtt. For each comparison, select the minimum of the two halfwords and place that halfword in the corresponding location in Rdd. Comparisons are available in both signed and unsigned form. Vector minimum halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vminh(Rtt,Rss) | for (i = 0; i < 4; i++) {
Rdd.h[i]=min(Rtt.h[i],Rss.h[i]);
}
Copy to clipboard | | Rdd=vminuh(Rtt,Rss) | for (i = 0; i < 4; i++) {
Rdd.h[i]=min(Rtt.uh[i],Rss.uh[i]);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

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Rdd=vminh(Rtt,Rss)

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Rdd=vminuh(Rtt,Rss)

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Intrinsics
Vector minimum halfwords intrinsics

Rdd=vminh(Rtt,Rss)

Word64 Q6_P_vminh_PP(Word64 Rtt, Word64 Rss)

Rdd=vminuh(Rtt,Rss)

Word64 Q6_P_vminuh_PP(Word64 Rtt, Word64 Rss)
#### Vector reduce minimum halfwords Find the minimum halfword between the previous minimum in Rxx[0] and the four values in Rss. The address of the new minimum is stored in Rxx[1]. Register Rxx contains a minimum value in the low word and the address of that minimum value in the high word. Register Rss contains a vector of four halfword values, and register Ru contains the address of this data. Vector reduce minimum halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rxx=vrminh(Rss,Ru) | min = Rxx.h[0];
addr = Rxx.w[1];
for (i = 0; i < 4; i++) {
if (min > Rss.h[i]) {
min = Rss.h[i];
addr = Ru | i<<1;
}
}
Rxx.w[0]=min;
Rxx.w[1]=addr;
Copy to clipboard | | Rxx=vrminuh(Rss,Ru) | min = Rxx.uh[0];
addr = Rxx.w[1];
for (i = 0; i < 4; i++) {
if (min > Rss.uh[i]) {
min = Rss.uh[i];
addr = Ru | i<<1;
}
}
Rxx.w[0]=min;
Rxx.w[1]=addr;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rxx=vrminh(Rss,Ru)

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Rxx=vrminuh(Rss,Ru)

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Intrinsics
Vector reduce minimum halfwords intrinsics

Rxx=vrminh(Rss,Ru)

Word64 Q6_P_vrminh_PR(Word64 Rxx, Word64 Rss, Word32 Ru)

Rxx=vrminuh(Rss,Ru)

Word64 Q6_P_vrminuh_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
#### Vector reduce minimum words Find the minimum word between the previous minimum in Rxx[0] and the two values in Rss. The address of the new minimum is stored in Rxx[1]. Register Rxx contains a minimum value in the low word and the address of that minimum value in the high word. Register Rss contains a vector of two word values, and register Ru contains the address of this data. Vector reduce minimum words instructions | **Syntax** | **Behavior** | | --- | --- | | Rxx=vrminw(Rss,Ru) | min = Rxx.w[0];
addr = Rxx.w[1];
for (i = 0; i < 2; i++) {
if (min > Rss.w[i]) {
min = Rss.w[i];
addr = Ru | i<<2;
}
}
Rxx.w[0]=min;
Rxx.w[1]=addr;
Copy to clipboard | | Rxx=vrminuw(Rss,Ru) | min = Rxx.uw[0];
addr = Rxx.w[1];
for (i = 0; i < 2; i++) {
if (min > Rss.uw[i]) {
min = Rss.uw[i];
addr = Ru | i<<2;
}
}
Rxx.w[0]=min;
Rxx.w[1]=addr;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rxx=vrminw(Rss,Ru)

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Rxx=vrminuw(Rss,Ru)

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Intrinsics
Vector reduce minimum words intrinsics

Rxx=vrminw(Rss,Ru)

Word64 Q6_P_vrminw_PR(Word64 Rxx, Word64 Rss, Word32 Ru)

Rxx=vrminuw(Rss,Ru)

Word64 Q6_P_vrminuw_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
#### Vector minimum words Compare each of the two words in the 64-bit source vector Rss to the corresponding word in Rtt. For each comparison, select the minimum of the two words and place that word in the corresponding location in Rdd. Comparisons are available in both signed and unsigned form. Vector minimum words instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vminw(Rtt,Rss) | for (i = 0; i < 2; i++) {
Rdd.w[i]=min(Rtt.w[i],Rss.w[i]);
}
Copy to clipboard | | Rdd=vminuw(Rtt,Rss) | for (i = 0; i < 2; i++) {
Rdd.w[i]=min(Rtt.uw[i],Rss.uw[i]);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rdd=vminw(Rtt,Rss)

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Rdd=vminuw(Rtt,Rss)

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Intrinsics
Vector minimum words intrinsics

Rdd=vminw(Rtt,Rss)

Word64 Q6_P_vminw_PP(Word64 Rtt, Word64 Rss)

Rdd=vminuw(Rtt,Rss)

Word64 Q6_P_vminuw_PP(Word64 Rtt, Word64 Rss)
#### Vector sum of absolute differences unsigned bytes For each byte in the source vector Rss, subtract the corresponding byte in source vector Rtt. Take the absolute value of the intermediate results, and the upper four together and add the lower four together. Optionally, add the destination upper and lower words to these results. This instruction is useful in determining distance between two vectors, in applications such as motion estimation. pic_addh Page-1 Sheet.66 Sheet.1 Rss Rss Rectangle.61 Sheet.3 Rtt Rtt Sheet.4 Rdd Rdd Sheet.5 Rectangle.65 Rectangle.66 Rectangle.67 Rectangle.68 Rectangle.69 Rectangle.70 Rectangle.71 Rectangle.72 Rectangle.73 Rectangle.74 Rectangle.75 Rectangle.76 Rectangle.77 Rectangle.78 Rectangle.79 Sheet.21 Sheet.22 Rounded rectangle.82 sad sad Sheet.24 Sheet.25 Sheet.26 Rounded rectangle.86 sad sad Sheet.28 Sheet.29 Sheet.30 Rounded rectangle.90 sad sad Sheet.32 Sheet.33 Sheet.34 Rounded rectangle.94 sad sad Sheet.36 Sheet.37 Sheet.38 Rounded rectangle.98 sad sad Sheet.40 Sheet.41 Sheet.42 Rounded rectangle.102 sad sad Sheet.44 Sheet.45 Sheet.46 Rounded rectangle.106 sad sad Sheet.48 Sheet.49 Sheet.50 Rounded rectangle.110 sad sad Rounded rectangle.111 32-bit add 32-bit add Rectangle.16 Sheet.54 Sheet.55 Sheet.56 Sheet.57 Rounded rectangle.59 32-bit add 32-bit add Rectangle.60 Sheet.61 Sheet.62 Sheet.63 Sheet.64 Vector sum of absolute differences unsigned bytes instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vrsadub(Rss,Rtt) | Rdd = 0;
for (i = 0; i < 4; i++) {
Rdd.w[0]=(Rdd.w[0] + ABS((Rss.ub[i] - Rtt.ub[i])));
}
for (i = 4; i < 8; i++) {
Rdd.w[1]=(Rdd.w[1] + ABS((Rss.ub[i] - Rtt.ub[i])));
}
Copy to clipboard | | Rxx+=vrsadub(Rss,Rtt) | for (i = 0; i < 4; i++) {
Rxx.w[0]=(Rxx.w[0] + ABS((Rss.ub[i] - Rtt.ub[i])));
}
for (i = 4; i < 8; i++) {
Rxx.w[1]=(Rxx.w[1] + ABS((Rss.ub[i] - Rtt.ub[i])));
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rdd=vrsadub(Rss,Rtt)

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Rxx+=vrsadub(Rss,Rtt)

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Intrinsics
Vector sum of absolute differences unsigned bytes intrinsics

Rdd=vrsadub(Rss,Rtt)

Word64 Q6_P_vrsadub_PP(Word64 Rss, Word64 Rtt)

Rxx+=vrsadub(Rss,Rtt)

Word64 Q6_P_vrsadubacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
#### Vector subtract halfwords Subtract each of the four halfwords in 64-bit vector Rss from the corresponding halfword in vector Rtt. Optionally, saturate each 16-bit addition to either a signed or unsigned 16-bit value. Applying saturation to the vsubh instruction clamps the result to the signed range 0x8000 to 0x7fff, whereas applying saturation to the vsubuh instruction ensures that the unsigned result falls within the range 0 to 0xffff. When saturation is not needed, vsubh should be used. Vector subtract halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vsubh(Rtt,Rss) | for (i=0;i<4;i++) {
Rdd.h[i]=Rtt.h[i]-Rss.h[i];
}
Copy to clipboard | | Rdd=vsubh(Rtt,Rss):sat | for (i=0;i<4;i++) {
Rdd.h[i]=sat_16(Rtt.h[i]-Rss.h[i]);
}
Copy to clipboard | | Rdd=vsubuh(Rtt,Rss):sat | for (i=0;i<4;i++) {
Rdd.h[i]=usat_16(Rtt.uh[i]-Rss.uh[i]);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rdd=vsubh(Rtt,Rss)

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Rdd=vsubh(Rtt,Rss):sat

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Rdd=vsubuh(Rtt,Rss):sat

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Intrinsics
Vector subtract halfwords intrinsics

Rdd=vsubh(Rtt,Rss)

Word64 Q6_P_vsubh_PP(Word64 Rtt, Word64 Rss)

Rdd=vsubh(Rtt,Rss):sat

Word64 Q6_P_vsubh_PP_sat(Word64 Rtt, Word64 Rss)

Rdd=vsubuh(Rtt,Rss):sat

Word64 Q6_P_vsubuh_PP_sat(Word64 Rtt, Word64 Rss)
#### Vector subtract bytes Subtract each of the eight bytes in 64-bit vector Rss from the corresponding byte in vector Rtt. Optionally, saturate each 8-bit subtraction to an unsigned value between 0 and 255. The eight results are stored in destination register Rdd. Vector subtract bytes instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vsubub(Rtt,Rss) | for (i = 0; i < 8; i++) {
Rdd.b[i]=(Rtt.ub[i]-Rss.ub[i]);
}
Copy to clipboard | | Rdd=vsubb(Rss,Rtt) | Assembler mapped to: "Rdd=vsubub(Rss,Rtt)"
Copy to clipboard | | Rdd=vsubub(Rtt,Rss):sat | for (i = 0; i < 8; i++) {
Rdd.b[i]=usat_8(Rtt.ub[i]-Rss.ub[i]);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rdd=vsubub(Rtt,Rss)

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Rdd=vsubub(Rtt,Rss):sat

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Intrinsics
Vector subtract bytes intrinsics

Rdd=vsubub(Rtt,Rss)

Word64 Q6_P_vsubub_PP(Word64 Rtt, Word64 Rss)

Rdd=vsubb(Rss,Rtt)

Word64 Q6_P_vsubb_PP(Word64 Rss, Word64 Rtt)

Rdd=vsubub(Rtt,Rss):sat

Word64 Q6_P_vsubub_PP_sat(Word64 Rtt, Word64 Rss)
#### Vector subtract words Subtract each of the two words in 64-bit vector Rss from the corresponding word in vector Rtt. Optionally, saturate each 32-bit subtraction to a signed value between 0x8000\_0000 and 0x7fff\_ffff. The two word results are stored in destination register Rdd. Vector subtract words instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vsubw(Rtt,Rss) | for (i=0;i<2;i++) {
Rdd.w[i]=Rtt.w[i]-Rss.w[i];
}
Copy to clipboard | | Rdd=vsubw(Rtt,Rss):sat | for (i=0;i<2;i++) {
Rdd.w[i]=sat_32(Rtt.w[i]-Rss.w[i]);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rdd=vsubw(Rtt,Rss)

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Intrinsics
Vector subtract words intrinsics

Rdd=vsubw(Rtt,Rss)

Word64 Q6_P_vsubw_PP(Word64 Rtt, Word64 Rss)

Rdd=vsubw(Rtt,Rss):sat

Word64 Q6_P_vsubw_PP_sat(Word64 Rtt, Word64 Rss)
### BIT The XTYPE/BIT instruction subclass includes instructions for bit manipulation. #### Count leading Count leading zeros (cl0) counts the number of consecutive zeros starting with the most significant bit. Count leading ones (cl1) counts the number of consecutive ones starting with the most significant bit. Count leading bits (clb) counts both leading ones and leading zeros and then selects the maximum. The NORMAMT instruction returns the number of leading bits minus one. For a two’s-complement number, the number of leading zeros is zero for negative numbers. The number of leading ones is zero for positive numbers. The number of leading bits can be used to judge the magnitude of the value. Count leading instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=normamt(Rs) | if (Rs == 0) {
Rd = 0;
} else {
Rd = (max(count_leading_ones(Rs),count_leading_ones(~Rs)))-1;
}
Copy to clipboard | | Rd=add(clb(Rs),#s6) | Rd = (max(count_leading_ones(Rs),count_leading_ones(~Rs)))+s;
Copy to clipboard | | Rd=normamt(Rss) | if (Rss == 0) {
Rd = 0;
} else {
Rd = (max(count_leading_ones(Rss),count_leading_ones(~Rss)))-1;
}
Copy to clipboard | | Rd=add(clb(Rss),#s6) | Rd = (max(count_leading_ones(Rss),count_leading_ones(~Rss)))+s;
Copy to clipboard | | Rd=clb(Rs) | Rd = max(count_leading_ones(Rs),count_leading_ones(~Rs));
Copy to clipboard | | Rd=cl0(Rs) | Rd = count_leading_ones(~Rs);
Copy to clipboard | | Rd=cl1(Rs) | Rd = count_leading_ones(Rs);
Copy to clipboard | | Rd=clb(Rss) | Rd = max(count_leading_ones(Rss),count_leading_ones(~Rss));
Copy to clipboard | | Rd=cl0(Rss) | Rd = count_leading_ones(~Rss);
Copy to clipboard | | Rd=cl1(Rss) | Rd = count_leading_ones(Rss);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rd=normamt(Rs)

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Rd=add(clb(Rs),#s6)

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Rd=normamt(Rss)

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Rd=add(clb(Rss),#s6)

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Rd=clb(Rs)

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Rd=cl0(Rs)

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Rd=cl1(Rs)

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Rd=clb(Rss)

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Rd=cl0(Rss)

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Rd=cl1(Rss)

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Intrinsics
Count leading intrinsics

Rd=normamt(Rs)

Word32 Q6_R_normamt_R(Word32 Rs)

Rd=add(clb(Rs),#s6)

Word32 Q6_R_add_clb_RI(Word32 Rs, Word32 Is6)

Rd=normamt(Rss)

Word32 Q6_R_normamt_P(Word64 Rss)

Rd=add(clb(Rss),#s6)

Word32 Q6_R_add_clb_PI(Word64 Rss, Word32 Is6)

Rd=clb(Rs)

Word32 Q6_R_clb_R(Word32 Rs)

Rd=cl0(Rs)

Word32 Q6_R_cl0_R(Word32 Rs)

Rd=cl1(Rs)

Word32 Q6_R_cl1_R(Word32 Rs)

Rd=clb(Rss)

Word32 Q6_R_clb_P(Word64 Rss)

Rd=cl0(Rss)

Word32 Q6_R_cl0_P(Word64 Rss)

Rd=cl1(Rss)

Word32 Q6_R_cl1_P(Word64 Rss)
#### Count population Population Count (popcount) counts the number of bits in Rss that are set. Count population instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=popcount(Rss) | Rd = count_ones(Rss);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rd=popcount(Rss)

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Intrinsics
Count population intrinsics

Rd=popcount(Rss)

Word32 Q6_R_popcount_P(Word64 Rss)
#### Count trailing Count trailing zeros (ct0) counts the number of consecutive zeros starting with the least significant bit. Count trailing ones (ct1) counts the number of consecutive ones starting with the least significant bit. Count trailing instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=ct0(Rs) | Rd = count_leading_ones(~reverse_bits(Rs));
Copy to clipboard | | Rd=ct1(Rs) | Rd = count_leading_ones(reverse_bits(Rs));
Copy to clipboard | | Rd=ct0(Rss) | Rd = count_leading_ones(~reverse_bits(Rss));
Copy to clipboard | | Rd=ct1(Rss) | Rd = count_leading_ones(reverse_bits(Rss));
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

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Rd=ct0(Rs)

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Rd=ct1(Rs)

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Rd=ct0(Rss)

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Rd=ct1(Rss)

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Intrinsics
Count trailing intrinsics

Rd=ct0(Rs)

Word32 Q6_R_ct0_R(Word32 Rs)

Rd=ct1(Rs)

Word32 Q6_R_ct1_R(Word32 Rs)

Rd=ct0(Rss)

Word32 Q6_R_ct0_P(Word64 Rss)

Rd=ct1(Rss)

Word32 Q6_R_ct1_P(Word64 Rss)
#### Extract bitfield Extract a bitfield from the source register (or register pair) and deposit into the least significant bits of the destination register (or register pair). The other, more significant bits in the destination are either cleared or sign-extended, depending on the instruction. The width of the extracted field is obtained from the first immediate or from the most-significant word of Rtt. The field offset is obtained from either the second immediate or from the least-significant word of Rtt. For register-based extract, where Rtt supplies the offset and width, the offset value is treated as a signed 7-bit number. If this value is negative, the source register Rss is shifted left (the reverse direction). Width number of bits are then taken from the least-significant portion of this result. If the shift amount and/or offset captures data beyond the most significant end of the input, then these bits will be taken as zero. pic_addh Page-1 Sheet.158 Rectangle.1 Rectangle.2 Rectangle.3 Rectangle.4 Offset Offset Rectangle.5 Rectangle.6 Rectangle.7 Rectangle.41 Rectangle.42 Rectangle.43 Rectangle.44 Rectangle.12 Rectangle.13 Rectangle.14 Rectangle.48 Rectangle.49 Rectangle.17 Rectangle.18 Rectangle.19 Rectangle.20 Rectangle.21 Rectangle.55 Rectangle.23 Rectangle.24 Rectangle.58 Rectangle.59 Rectangle.60 Rectangle.61 Rectangle.62 Rectangle.63 Rectangle.64 Rectangle.65 Rectangle.66 Rectangle.67 Rectangle.35 Rectangle.36 Rectangle.120 Rectangle.121 Rectangle.122 Rectangle.40 Rectangle.124 Rectangle.125 Rectangle.126 Rectangle.127 Rectangle.45 Rectangle.46 Rectangle.47 Rectangle.131 Rectangle.132 Rectangle.50 Rectangle.51 Rectangle.52 Rectangle.53 Rectangle.54 Rectangle.138 Sheet.139 Rectangle.57 Width Width Sheet.141 Sheet.142 Sheet.143 Sheet.144 Rectangle.145 Zero extension Zero extension Rectangle.183 Rs Rs Rectangle.184 Rd Rd Rectangle.141 Rectangle.142 Rectangle.143 Rectangle.144 Rectangle.152 Rectangle.146 Rectangle.147 Rectangle.148 Rectangle.149 Rectangle.150 Extract bitfield instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=extract(Rs,#u5,#U5) | width=u;
offset=U;
Rd = sxt_width_to_32((Rs >> offset));
Copy to clipboard | | Rd=extractu(Rs,#u5,#U5) | width=u;
offset=U;
Rd = zxt_width_to_32((Rs >> offset));
Copy to clipboard | | Rdd=extract(Rss,#u6,#U6) | width=u;
offset=U;
Rdd = sxt_width_to_64((Rss >> offset));
Copy to clipboard | | Rdd=extractu(Rss,#u6,#U6) | width=u;
offset=U;
Rdd = zxt_width_to_64((Rss >> offset));
Copy to clipboard | | Rd=extract(Rs,Rtt) | width=zxt_6_to_32((Rtt.w[1]));
offset=sxt_7_to_32((Rtt.w[0]));
Rd = sxt_width_to_64((offset>0)?(zxt_32_to_64(zxt_32_to_64(Rs))>>>offset):(zxt_32_to_64(zxt_32_to_64(Rs))< Copy to clipboard | | Rd=extractu(Rs,Rtt) | width=zxt_6_to_32((Rtt.w[1]));
offset=sxt_7_to_32((Rtt.w[0]));
Rd = zxt_width_to_64((offset>0)?(zxt_32_to_64(zxt_32_to_64(Rs))>>>offset):(zxt_32_to_64(zxt_32_to_64(Rs))< Copy to clipboard | | Rdd=extract(Rss,Rtt) | width=zxt_6_to_32((Rtt.w[1]));
offset=sxt_7_to_32((Rtt.w[0]));
Rdd = sxt_width_to_64((offset>0)?(Rss>>>offset):(Rss< Copy to clipboard | | Rdd=extractu(Rss,Rtt) | width=zxt_6_to_32((Rtt.w[1]));
offset=sxt_7_to_32((Rtt.w[0]));
Rdd = zxt_width_to_64((offset>0)?(Rss>>>offset):(Rss< Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

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Rd=extract(Rs,#u5,#U5)

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Rd=extractu(Rs,#u5,#U5)

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Rdd=extract(Rss,#u6,#U6)

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Rdd=extractu(Rss,#u6,#U6)

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Rd=extract(Rs,Rtt)

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Rd=extractu(Rs,Rtt)

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Rdd=extract(Rss,Rtt)

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Rdd=extractu(Rss,Rtt)

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Intrinsics
Extract bitfield intrinsics

Rd=extract(Rs,#u5,#U5)

Word32 Q6_R_extract_RII(Word32 Rs, Word32 Iu5, Word32 IU5)

Rd=extractu(Rs,#u5,#U5)

Word32 Q6_R_extractu_RII(Word32 Rs, Word32 Iu5, Word32 IU5)

Rdd=extract(Rss,#u6,#U6)

Word64 Q6_P_extract_PII(Word64 Rss, Word32 Iu6, Word32 IU6)

Rdd=extractu(Rss,#u6,#U6)

Word64 Q6_P_extractu_PII(Word64 Rss, Word32 Iu6, Word32 IU6)

Rd=extract(Rs,Rtt)

Word32 Q6_R_extract_RP(Word32 Rs, Word64 Rtt)

Rd=extractu(Rs,Rtt)

Word32 Q6_R_extractu_RP(Word32 Rs, Word64 Rtt)

Rdd=extract(Rss,Rtt)

Word64 Q6_P_extract_PP(Word64 Rss, Word64 Rtt)

Rdd=extractu(Rss,Rtt)

Word64 Q6_P_extractu_PP(Word64 Rss, Word64 Rtt)
#### Insert bitfield Replace a bitfield in the destination register (or register pair) with bits from the least significant portion of Rs/Rss. The number of bits is obtained from the first immediate or the most-significant word of Rtt. The bits are shifted by the second immediate or the least significant word of Rtt. If register Rtt specifies the offset, then the low 7-bits of Rtt are treated as a signed 7-bit value. If this value is negative, the result is zero. Shift amounts and offsets that are too large may push bits beyond the end of the destination register, in this case the bits will not appear in the destination register. pic_addh Page-1 Sheet.161 Rectangle.56 Rectangle.2 Rectangle.3 Rectangle.4 Offset Offset Rectangle.5 Rectangle.6 Rectangle.7 Rectangle.8 Rectangle.71 Rectangle.72 Rectangle.11 Rectangle.12 Rectangle.13 Rectangle.14 Rectangle.15 Rectangle.16 Rectangle.17 Rectangle.18 Rectangle.19 Rectangle.20 Rectangle.21 Rectangle.128 Rectangle.23 Rectangle.130 Rectangle.25 Rectangle.26 Rectangle.133 Rectangle.28 Rectangle.135 Rectangle.30 Rectangle.31 Rectangle.32 Rectangle.33 Rectangle.68 Rectangle.69 Rectangle.70 Rectangle.73 Rectangle.74 Rectangle.75 Rectangle.102 Rectangle.77 Rectangle.104 Rectangle.105 Rectangle.106 Rectangle.107 Rectangle.82 Rectangle.109 Rectangle.84 Rectangle.85 Rectangle.86 Rectangle.87 Rectangle.88 Rectangle.89 Rectangle.90 Rectangle.161 Rectangle.162 Rectangle.163 Rectangle.164 Rectangle.165 Rectangle.166 Rectangle.167 Rectangle.168 Rectangle.169 Rectangle.170 Rectangle.171 Sheet.102 Rectangle.173 Width Width Sheet.104 Sheet.105 Sheet.106 Sheet.107 Rectangle.178 Unchanged Unchanged Sheet.109 Rectangle.180 Unchanged Unchanged Rectangle.181 Rs Rs Rectangle.182 Rd Rd Rectangle.185 Rectangle.186 Rectangle.187 Rectangle.188 Rectangle.189 Rectangle.190 Rectangle.191 Rectangle.192 Rectangle.193 Rectangle.194 Insert bitfield instructions | **Syntax** | **Behavior** | | --- | --- | | Rx=insert(Rs,#u5,#U5) | width=u;
offset=U;
Rx &= ~(((1< Rx |= ((Rs & ((1< Copy to clipboard | | Rxx=insert(Rss,#u6,#U6) | width=u;
offset=U;
Rxx &= ~(((1< Rxx |= ((Rss & ((1< Copy to clipboard | | Rx=insert(Rs,Rtt) | width=zxt_6_to_32((Rtt.w[1]));
offset=sxt_7_to_32((Rtt.w[0]));
mask = ((1< if (offset < 0) {
Rx = 0;
} else {
Rx &= ~(mask< Rx |= ((Rs & mask) << offset);
}
Copy to clipboard | | Rxx=insert(Rss,Rtt) | width=zxt_6_to_32((Rtt.w[1]));
offset=sxt_7_to_32((Rtt.w[0]));
mask = ((1< if (offset < 0) {
Rxx = 0;
} else {
Rxx &= ~(mask< Rxx |= ((Rss & mask) << offset);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

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Rx=insert(Rs,#u5,#U5)

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Rxx=insert(Rss,#u6,#U6)

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Rx=insert(Rs,Rtt)

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Intrinsics
Insert bitfield intrinsics

Rx=insert(Rs,#u5,#U5)

Word32 Q6_R_insert_RII(Word32 Rx, Word32 Rs, Word32 Iu5, Word32 IU5)

Rxx=insert(Rss,#u6,#U6)

Word64 Q6_P_insert_PII(Word64 Rxx, Word64 Rss, Word32 Iu6, Word32 IU6)

Rx=insert(Rs,Rtt)

Word32 Q6_R_insert_RP(Word32 Rx, Word32 Rs, Word64 Rtt)

Rxx=insert(Rss,Rtt)

Word64 Q6_P_insert_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
#### Interleave/deinterleave For interleave, bits I+32 of Rss (which are the bits from the upper source word) get placed in the odd bits (I\*2)+1 of Rdd, while bits I of Rss (which are the bits from the lower source word) get placed in the even bits (I\*2) of Rdd. For deinterleave, the even bits of the source register are placed in the even register of the result pair, and the odd bits of the source register are placed in the odd register of the result pair. Note that “r1:0 = deinterleave(r1:0)” is the inverse of “r1:0 = interleave(r1:0)”. Interleave/deinterleave instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=interleave(Rss) | Rdd = interleave(Rss.w[1],Rss.w[0]);
Copy to clipboard | | Rdd=deinterleave(Rss) | Rdd = deinterleave(ODD,EVEN);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rdd=interleave(Rss)

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Rdd=deinterleave(Rss)

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Intrinsics
Interleave/deinterleave intrinsics

Rdd=interleave(Rss)

Word64 Q6_P_interleave_P(Word64 Rss)

Rdd=deinterleave(Rss)

Word64 Q6_P_deinterleave_P(Word64 Rss)
#### Linear feedback-shift iteration Count the number of ones of the logical AND of the two source input values, and take the least significant value of that sum. The first source value is shifted right by one bit, and the parity is placed in the MSB. Linear feedback-shift iteration instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=lfs(Rss,Rtt) | Rdd = (Rss.u64 >> 1) | ((1&count_ones(Rss & Rtt)).u64<<63);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rdd=lfs(Rss,Rtt)

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Intrinsics
Linear feedback-shift iteration intrinsics

Rdd=lfs(Rss,Rtt)

Word64 Q6_P_lfs_PP(Word64 Rss, Word64 Rtt)
#### Masked parity Count the number of ones of the logical AND of the two source input values, and take the least significant bit of that sum. Masked parity instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=parity(Rs,Rt) | Rd = 1&count_ones(Rs & Rt);
Copy to clipboard | | Rd=parity(Rss,Rtt) | Rd = 1&count_ones(Rss & Rtt);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rd=parity(Rs,Rt)

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Rd=parity(Rss,Rtt)

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Intrinsics
Masked parity intrinsics

Rd=parity(Rs,Rt)

Word32 Q6_R_parity_RR(Word32 Rs, Word32 Rt)

Rd=parity(Rss,Rtt)

Word32 Q6_R_parity_PP(Word64 Rss, Word64 Rtt)
#### Bit reverse Reverse the order of bits. The most significant gets swapped with the least significant, bit 30 gets swapped with bit 1, and so on. Bit reverse instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=brev(Rs) | Rd = reverse_bits(Rs);
Copy to clipboard | | Rdd=brev(Rss) | Rdd = reverse_bits(Rss);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rd=brev(Rs)

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Rdd=brev(Rss)

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Intrinsics
Bit reverse intrinsics

Rd=brev(Rs)

Word32 Q6_R_brev_R(Word32 Rs)

Rdd=brev(Rss)

Word64 Q6_P_brev_P(Word64 Rss)
#### Set/clear/toggle bit Set (to 1), clear (to 0), or toggle a single bit in the source, and place the resulting value in the destination. The bit to be manipulated can be indicated using an immediate or register value. If a register is used to indicate the bit position, and the value of the least-significant 7 bits of Rt is out of range, then the destination register will be unchanged. Set/clear/toggle bit instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=setbit(Rs,#u5) | Rd = (Rs | (1< Copy to clipboard | | Rd=togglebit(Rs,#u5) | Rd = (Rs ^ (1< Copy to clipboard | | Rd=clrbit(Rs,#u5) | Rd = (Rs & (~(1< Copy to clipboard | | Rd=setbit(Rs,Rt) | Rd = (Rs | (sxt_7_to_32(Rt)>0)?(zxt_32_to_64(1)<>>sxt_7_to_32(Rt)));
Copy to clipboard | | Rd=togglebit(Rs,Rt) | Rd = (Rs ^ (sxt_7_to_32(Rt)>0)?(zxt_32_to_64(1)<>>sxt_7_to_32(Rt)));
Copy to clipboard | | Rd=clrbit(Rs,Rt) | Rd = (Rs & (~((sxt_7_to_32(Rt)>0)?(zxt_32_to_64(1)<>>sxt_7_to_32(Rt)))));
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rd=setbit(Rs,#u5)

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Rd=togglebit(Rs,#u5)

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Rd=clrbit(Rs,#u5)

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Rd=setbit(Rs,Rt)

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Rd=togglebit(Rs,Rt)

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Rd=clrbit(Rs,Rt)

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Intrinsics
Set/clear/toggle bit intrinsics

Rd=setbit(Rs,#u5)

Word32 Q6_R_setbit_RI(Word32 Rs, Word32 Iu5)

Rd=togglebit(Rs,#u5)

Word32 Q6_R_togglebit_RI(Word32 Rs, Word32 Iu5)

Rd=clrbit(Rs,#u5)

Word32 Q6_R_clrbit_RI(Word32 Rs, Word32 Iu5)

Rd=setbit(Rs,Rt)

Word32 Q6_R_setbit_RR(Word32 Rs, Word32 Rt)

Rd=togglebit(Rs,Rt)

Word32 Q6_R_togglebit_RR(Word32 Rs, Word32 Rt)

Rd=clrbit(Rs,Rt)

Word32 Q6_R_clrbit_RR(Word32 Rs, Word32 Rt)
#### Split bitfield Split the bitfield in a register into upper and lower parts of variable size. The lower part is placed in the lower word of a destination register pair, and the upper part is placed in the upper word of the destination. An immediate value or register Rt is used to determine the bit position of the split. pic_addh Page-1 Sheet.208 Rectangle.56 Rectangle.2 Rectangle.3 Rectangle.5 Rectangle.6 Rectangle.7 Rectangle.8 Rectangle.71 Rectangle.72 Rectangle.11 Rectangle.12 Rectangle.13 Rectangle.14 Rectangle.15 Rectangle.16 Rectangle.17 Rectangle.18 Rectangle.19 Rectangle.20 Rectangle.21 Rectangle.128 Rectangle.23 Rectangle.130 Rectangle.25 Rectangle.26 Rectangle.133 Rectangle.28 Rectangle.135 Rectangle.30 Rectangle.31 Rectangle.32 Rectangle.33 Rectangle.68 Rectangle.69 Rectangle.70 Rectangle.73 Rectangle.74 Rectangle.75 Rectangle.102 Rectangle.77 Rectangle.104 Rectangle.105 Rectangle.106 Rectangle.107 Rectangle.82 Rectangle.109 Rectangle.84 Rectangle.85 Rectangle.86 Rectangle.87 Rectangle.88 Rectangle.89 Rectangle.90 Rectangle.161 Rectangle.162 Rectangle.163 Rectangle.164 Rectangle.165 Rectangle.166 Rectangle.167 Rectangle.168 Rectangle.169 Rectangle.170 Rectangle.171 Rectangle.173 Bits Bits Sheet.104 Sheet.105 Sheet.106 Sheet.107 Rectangle.178 Zero Zero Rectangle.181 Rs Rs Rectangle.182 Rdd[0] Rdd[0] Rectangle.185 Rectangle.186 Rectangle.187 Rectangle.188 Rectangle.189 Rectangle.190 Rectangle.191 Rectangle.192 Rectangle.193 Rectangle.194 Rectangle.161 Rectangle.162 Rectangle.163 Rectangle.164 Rectangle.165 Rectangle.166 Rectangle.167 Rectangle.168 Rectangle.169 Rectangle.170 Rectangle.171 Rectangle.172 Rectangle.173 Rectangle.174 Rectangle.175 Rectangle.176 Rectangle.177 Rectangle.178 Rectangle.179 Rectangle.180 Rectangle.181 Rectangle.182 Rectangle.183 Rectangle.184 Rectangle.185 Rectangle.186 Rectangle.187 Rectangle.188 Rectangle.189 Rectangle.190 Rectangle.191 Rectangle.192 Sheet.193 Rectangle.194 Zero Zero Rectangle.195 Rdd[1] Rdd[1] Rectangle.196 Rectangle.197 Rectangle.198 Rectangle.199 Rectangle.200 Rectangle.201 Rectangle.202 Rectangle.203 Rectangle.204 Rectangle.205 Sheet.206 Sheet.207 Split bitfield instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=bitsplit(Rs,#u5) | Rdd.w[1]=(Rs>>u);
Rdd.w[0]=zxt_u_to_32(Rs);
Copy to clipboard | | Rdd=bitsplit(Rs,Rt) | shamt = zxt_5_to_32(Rt);
Rdd.w[1]=(Rs>>shamt);
Rdd.w[0]=zxt_shamt_to_32(Rs);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rdd=bitsplit(Rs,#u5)

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Rdd=bitsplit(Rs,Rt)

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Intrinsics
Split bitfield intrinsics

Rdd=bitsplit(Rs,#u5)

Word64 Q6_P_bitsplit_RI(Word32 Rs, Word32 Iu5)

Rdd=bitsplit(Rs,Rt)

Word64 Q6_P_bitsplit_RR(Word32 Rs, Word32 Rt)
#### Table index The table index instruction supports fast lookup tables where the index into the table is stored in a bit-field. The instruction forms the address of a table element by extracting the bit-field and inserting it into the appropriate bits of a pointer to the table element. Tables are defined to contain entries of bytes, halfwords, words, or doublewords. The table must be aligned to a power-of-2 size greater than or equal to the table size. For example, a 4Kbyte table should be aligned to a 4Kbyte boundary. This instruction supports tables with a maximum of 32K table entries. Register Rx contains a pointer to within the table. Register Rs contains a field to be extracted and used as a table index. This instruction first extracts the field from register Rs and then inserts it into register Rx. The insertion point is bit 0 for tables of bytes, bit 1 for tables of halfwords, bit 2 for tables of words, and bit 3 for tables of doublewords. In the assembly syntax, the width and offset values represent the field in Rs to be extracted. Unsigned constants should be used to specify the width and offsets in assembly. In the encoded instruction, however, these values are adjusted by the assembler as follows. For tableidxb, no adjustment is necessary. For tableidxh, the assembler encodes offset-1 in the signed immediate field. For tableidxw, the assembler encodes offset-2 in the signed immediate field. For tableidxd, the assembler encodes offset-3 in the signed immediate field. pic_addh Page-1 Sheet.191 Rectangle.1 Rectangle.2 Rectangle.3 Rectangle.4 Offset Offset Rectangle.5 Rectangle.6 Rectangle.7 Rectangle.41 Rectangle.42 Rectangle.43 Rectangle.44 Rectangle.12 Rectangle.13 Rectangle.14 Rectangle.48 Rectangle.49 Rectangle.17 Rectangle.18 Rectangle.19 Rectangle.20 Rectangle.21 Rectangle.55 Rectangle.23 Rectangle.24 Rectangle.58 Rectangle.59 Rectangle.60 Rectangle.61 Rectangle.62 Rectangle.63 Rectangle.64 Rectangle.65 Rectangle.66 Sheet.139 Rectangle.57 Width Width Sheet.141 Sheet.142 Sheet.143 Rectangle.145 Rx=TABLEIDXD(Rs,#width,#offset) Rx=TABLEIDXD(Rs,#width,#offset) Rectangle.183 Rs Rs Rectangle.158 Unchanged Unchanged Rectangle.175 Rectangle.178 Rectangle.179 Rectangle.180 Rx Rx Rectangle.181 Rectangle.182 Rectangle.183 Rectangle.184 Rectangle.185 Rectangle.186 Rectangle.187 Rectangle.188 Rectangle.189 Rectangle.190 Rectangle.159 Unchanged Unchanged Sheet.160 Table index instructions | **Syntax** | **Behavior** | | --- | --- | | Rx=tableidxb(Rs,#u4,#S6):raw | width=u;
offset=S;
field = Rs[(width+offset-1):offset];
Rx[(width-1+0):0]=field;
Copy to clipboard | | Rx=tableidxh(Rs,#u4,#S6):raw | width=u;
offset=S+1;
field = Rs[(width+offset-1):offset];
Rx[(width-1+1):1]=field;
Copy to clipboard | | Rx=tableidxw(Rs,#u4,#S6):raw | width=u;
offset=S+2;
field = Rs[(width+offset-1):offset];
Rx[(width-1+2):2]=field;
Copy to clipboard | | Rx=tableidxd(Rs,#u4,#S6):raw | width=u;
offset=S+3;
field = Rs[(width+offset-1):offset];
Rx[(width-1+3):3]=field;
Copy to clipboard | | Rx=tableidxb(Rs,#u4,#U5) | Assembler mapped to: "Rx=tableidxb(Rs,u4,U5):raw"
Copy to clipboard | | Rx=tableidxh(Rs,#u4,#U5) | Assembler mapped to: "Rx=tableidxh(Rs,u4,U5-1):raw"
Copy to clipboard | | Rx=tableidxw(Rs,#u4,#U5) | Assembler mapped to: "Rx=tableidxw(Rs,u4,U5-2):raw"
Copy to clipboard | | Rx=tableidxd(Rs,#u4,#U5) | Assembler mapped to: "Rx=tableidxd(Rs,u4,U5-3):raw"
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rx=tableidxb(Rs,#u4,#S6):raw

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Rx=tableidxh(Rs,#u4,#S6):raw

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Rx=tableidxw(Rs,#u4,#S6):raw

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Rx=tableidxd(Rs,#u4,#S6):raw

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Intrinsics
Table index intrinsics

Rx=tableidxb(Rs,#u4,#U5)

Word32 Q6_R_tableidxb_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5)

Rx=tableidxh(Rs,#u4,#U5)

Word32 Q6_R_tableidxh_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5)

Rx=tableidxw(Rs,#u4,#U5)

Word32 Q6_R_tableidxw_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5)

Rx=tableidxd(Rs,#u4,#U5)

Word32 Q6_R_tableidxd_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5)
### COMPLEX The XTYPE/COMPLEX instruction subclass includes instructions which are for complex math, using imaginary values. #### Complex add/sub halfwords Cross vector add-sub or sub-add used to perform X+jY and X-jY complex operations. Each 16-bit result is saturated to 16-bits. pic_addh Page-1 Sheet.144 Sheet.31 Rss Rss Rectangle.47 R R Rectangle.45 I I Sheet.55 + + Sheet.56 Sheet.1 Rdd = vxaddsubh(Rss,Rtt):sat Rdd = vxaddsubh(Rss,Rtt):sat Sheet.39 Sheet.33 Rtt Rtt Rectangle.34 R R Rectangle.46 I I Sheet.32 - - Sheet.36 Sheet.83 Sheet.47 Sheet.48 Sheet.51 Sheet.37 Sheet.38 sat16 sat16 Sheet.40 Sheet.42 sat16 sat16 Rectangle.41 R R Rectangle.43 I I Sheet.35 Sheet.49 Rdd Rdd Sheet.50 Rss Rss Rectangle.52 R R Rectangle.53 I I Sheet.54 - - Sheet.57 Sheet.58 Rdd = vxsubaddh(Rss,Rt):rnd:>>1:sat Rdd = vxsubaddh(Rss,Rt):rnd:>>1:sat Sheet.59 Sheet.60 Rtt Rtt Rectangle.61 R R Rectangle.62 I I Sheet.63 + + Sheet.64 Sheet.65 Sheet.66 Sheet.67 Sheet.68 Sheet.69 Sheet.70 sat16 sat16 Sheet.71 Sheet.72 sat16 sat16 Rectangle.73 R R Rectangle.74 I I Sheet.75 Sheet.76 Rdd Rdd Rectangle.84 R R Rectangle.85 I I Sheet.86 + + Sheet.87 Sheet.88 Rectangle.89 R R Rectangle.90 I I Sheet.91 - - Sheet.92 Sheet.93 Sheet.94 Sheet.95 Sheet.96 Sheet.97 Sheet.98 sat16 sat16 Sheet.99 Sheet.100 sat16 sat16 Rectangle.101 R R Rectangle.102 I I Sheet.103 Rectangle.104 R R Rectangle.105 I I Sheet.106 - - Sheet.107 Sheet.108 Rectangle.109 R R Rectangle.110 I I Sheet.111 + + Sheet.112 Sheet.113 Sheet.114 Sheet.115 Sheet.116 Sheet.117 Sheet.118 sat16 sat16 Sheet.119 Sheet.120 sat16 sat16 Rectangle.121 R R Rectangle.122 I I Sheet.123 Sheet.124 Sheet.128 1 1 Sheet.125 Sheet.126 1 1 Sheet.127 Sheet.129 1 1 Sheet.130 Sheet.131 1 1 Sheet.132 >>1 >>1 Sheet.133 Sheet.134 Sheet.135 Sheet.136 Sheet.137 >>1 >>1 Sheet.138 >>1 >>1 Sheet.139 >>1 >>1 Sheet.140 + + Sheet.141 + + Sheet.142 + + Sheet.143 + + Complex add/sub halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vxaddsubh(Rss,Rtt):sat | Rdd.h[0]=sat_16(Rss.h[0]+Rtt.h[1]);
Rdd.h[1]=sat_16(Rss.h[1]-Rtt.h[0]);
Rdd.h[2]=sat_16(Rss.h[2]+Rtt.h[3]);
Rdd.h[3]=sat_16(Rss.h[3]-Rtt.h[2]);
Copy to clipboard | | Rdd=vxsubaddh(Rss,Rtt):sat | Rdd.h[0]=sat_16(Rss.h[0]-Rtt.h[1]);
Rdd.h[1]=sat_16(Rss.h[1]+Rtt.h[0]);
Rdd.h[2]=sat_16(Rss.h[2]-Rtt.h[3]);
Rdd.h[3]=sat_16(Rss.h[3]+Rtt.h[2]);
Copy to clipboard | | Rdd=vxaddsubh(Rss,Rtt):rnd:>>1:sat | Rdd.h[0]=sat_16((Rss.h[0]+Rtt.h[1]+1)>>1);
Rdd.h[1]=sat_16((Rss.h[1]-Rtt.h[0]+1)>>1);
Rdd.h[2]=sat_16((Rss.h[2]+Rtt.h[3]+1)>>1);
Rdd.h[3]=sat_16((Rss.h[3]-Rtt.h[2]+1)>>1);
Copy to clipboard | | Rdd=vxsubaddh(Rss,Rtt):rnd:>>1:sat | Rdd.h[0]=sat_16((Rss.h[0]-Rtt.h[1]+1)>>1);
Rdd.h[1]=sat_16((Rss.h[1]+Rtt.h[0]+1)>>1);
Rdd.h[2]=sat_16((Rss.h[2]-Rtt.h[3]+1)>>1);
Rdd.h[3]=sat_16((Rss.h[3]+Rtt.h[2]+1)>>1);
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rdd=vxaddsubh(Rss,Rtt):sat

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Rdd=vxsubaddh(Rss,Rtt):sat

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Rdd=vxaddsubh(Rss,Rtt):rnd:>>1:sat

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Rdd=vxsubaddh(Rss,Rtt):rnd:>>1:sat

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Intrinsics
Complex add/sub halfwords intrinsics

Rdd=vxaddsubh(Rss,Rtt):sat

Word64 Q6_P_vxaddsubh_PP_sat(Word64 Rss, Word64 Rtt)

Rdd=vxsubaddh(Rss,Rtt):sat

Word64 Q6_P_vxsubaddh_PP_sat(Word64 Rss, Word64 Rtt)

Rdd=vxaddsubh(Rss,Rtt):rnd:>>1:sat

Word64 Q6_P_vxaddsubh_PP_rnd_rs1_sat(Word64 Rss, Word64 Rtt)

Rdd=vxsubaddh(Rss,Rtt):rnd:>>1:sat

Word64 Q6_P_vxsubaddh_PP_rnd_rs1_sat(Word64 Rss, Word64 Rtt)
#### Complex add/sub words Cross vector add-sub or sub-add used to perform X+jY and X-jY complex operations. Each 32-bit result is saturated to 32-bits. pic_addh Page-1 Sheet.84 Sheet.31 Rss Rss Rectangle.47 R R Rectangle.45 I I Sheet.55 + + Sheet.56 Sheet.1 Rdd = vxaddsubw(Rss,Rt):sat Rdd = vxaddsubw(Rss,Rt):sat Sheet.39 Sheet.33 Rtt Rtt Rectangle.34 R R Rectangle.46 I I Sheet.32 - - Sheet.36 Sheet.83 Sheet.47 Sheet.48 Sheet.51 Sheet.37 Sheet.38 sat32 sat32 Sheet.40 Sheet.42 sat32 sat32 Rectangle.41 R R Rectangle.43 I I Sheet.35 Sheet.49 Rdd Rdd Sheet.50 Rss Rss Rectangle.52 R R Rectangle.53 I I Sheet.54 - - Sheet.57 Sheet.58 Rdd = vxsubaddw(Rss,Rt):sat Rdd = vxsubaddw(Rss,Rt):sat Sheet.59 Sheet.60 Rtt Rtt Rectangle.61 R R Rectangle.62 I I Sheet.63 + + Sheet.64 Sheet.65 Sheet.66 Sheet.67 Sheet.68 Sheet.69 Sheet.70 sat32 sat32 Sheet.71 Sheet.72 sat32 sat32 Rectangle.73 R R Rectangle.74 I I Sheet.75 Sheet.76 Rdd Rdd Complex add/sub words instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vxaddsubw(Rss,Rtt):sat | Rdd.w[0]=sat_32(Rss.w[0]+Rtt.w[1]);
Rdd.w[1]=sat_32(Rss.w[1]-Rtt.w[0]);
Copy to clipboard | | Rdd=vxsubaddw(Rss,Rtt):sat | Rdd.w[0]=sat_32(Rss.w[0]-Rtt.w[1]);
Rdd.w[1]=sat_32(Rss.w[1]+Rtt.w[0]);
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
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Rdd=vxaddsubw(Rss,Rtt):sat

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Rdd=vxsubaddw(Rss,Rtt):sat

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Intrinsics
Complex add/sub words intrinsics

Rdd=vxaddsubw(Rss,Rtt):sat

Word64 Q6_P_vxaddsubw_PP_sat(Word64 Rss, Word64 Rtt)

Rdd=vxsubaddw(Rss,Rtt):sat

Word64 Q6_P_vxsubaddw_PP_sat(Word64 Rss, Word64 Rtt)
#### Complex multiply Multiply complex values Rs and Rt. The inputs have a real 16-bit value in the low halfword and an imaginary 16-bit value in the high halfword. Optionally, scale the result by 0-1 bits. Optionally, add a complex accumulator. Saturate the real and imaginary portions to 32-bits. The output has a real 32-bit value in the low word and an imaginary 32-bit value in the high word. The Rt input can be optionally conjugated. Another option is that the result can be subtracted from the destination rather than accumulated. pic_addh Page-1 Sheet.91 Sheet.31 Rs Rs Sheet.33 Sheet.34 Sheet.35 Add Add Rectangle Imaginary accumulation Imaginary accumulation Sheet.40 Sheet.41 Rectangle.43 I I Rectangle.47 R R Sheet.47 Rt Rt Sheet.49 * * Sheet.50 Sheet.51 Sheet.52 32 32 Rectangle.36 <<0-1 <<0-1 Sheet.54 Sheet.55 * * Sheet.56 Sheet.57 Sheet.58 32 32 Rectangle.59 <<0-1 <<0-1 Sheet.60 Sheet.69 Sheet.70 Sheet.71 Sheet.72 32 32 Sheet.73 Rxx Rxx Rectangle.1 I I Rectangle.19 R R Sheet.82 Sheet.83 Sheet.84 Sheet.85 Sheet.1 Rxx += cmpy(Rs,Rt):sat Rxx += cmpy(Rs,Rt):sat Sheet.3 Add Add Rectangle.4 Real accumulation Real accumulation Sheet.5 Rectangle.6 I I Rectangle.7 R R Sheet.9 * * Sheet.10 Sheet.11 Sheet.12 32 32 Rectangle.13 <<0-1 <<0-1 Sheet.14 Sheet.15 * * Sheet.16 Sheet.17 Sheet.18 32 32 Rectangle.19 <<0-1 <<0-1 Sheet.20 Sheet.21 Sheet.22 Rectangle.23 I I Rectangle.24 R R Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.2 Rs Rs Sheet.8 Rt Rt Sheet.29 Sheet.30 Sheet.32 32 32 Sheet.36 Sheet.37 Sheet.87 sat32 sat32 Sheet.88 sat32 sat32 Sheet.89 Sheet.90 Complex multiply instructions | **Syntax** | **Behavior** | | --- | --- | | Rxx+=cmpy(Rs,Rt):sat | Rxx.w[1]=sat_32(Rxx.w[1] + (Rs.h[1] * Rt.h[0])<<0 + (Rs.h[0] * Rt.h[1])<<0);
Rxx.w[0]=sat_32(Rxx.w[0] + (Rs.h[0] * Rt.h[0])<<0 - (Rs.h[1] * Rt.h[1])<<0);
Copy to clipboard | | Rxx+=cmpy(Rs,Rt):<<1:sat | Rxx.w[1]=sat_32(Rxx.w[1] + (Rs.h[1] * Rt.h[0])<<1 + (Rs.h[0] * Rt.h[1])<<1);
Rxx.w[0]=sat_32(Rxx.w[0] + (Rs.h[0] * Rt.h[0])<<1 - (Rs.h[1] * Rt.h[1])<<1);
Copy to clipboard | | Rxx+=cmpy(Rs,Rt\*):sat | Rxx.w[1]=sat_32(Rxx.w[1] + (Rs.h[1] * Rt.h[0])<<0 - (Rs.h[0] * Rt.h[1])<<0);
Rxx.w[0]=sat_32(Rxx.w[0] + (Rs.h[0] * Rt.h[0])<<0 + (Rs.h[1] * Rt.h[1])<<0);
Copy to clipboard | | Rxx+=cmpy(Rs,Rt\*):<<1:sat | Rxx.w[1]=sat_32(Rxx.w[1] + (Rs.h[1] * Rt.h[0])<<1 - (Rs.h[0] * Rt.h[1])<<1);
Rxx.w[0]=sat_32(Rxx.w[0] + (Rs.h[0] * Rt.h[0])<<1 + (Rs.h[1] * Rt.h[1])<<1);
Copy to clipboard | | Rdd=cmpy(Rs,Rt):sat | Rdd.w[1]=sat_32((Rs.h[1] * Rt.h[0])<<0 + (Rs.h[0] * Rt.h[1])<<0);
Rdd.w[0]=sat_32((Rs.h[0] * Rt.h[0])<<0 - (Rs.h[1] * Rt.h[1])<<0);
Copy to clipboard | | Rdd=cmpy(Rs,Rt):<<1:sat | Rdd.w[1]=sat_32((Rs.h[1] * Rt.h[0])<<1 + (Rs.h[0] * Rt.h[1])<<1);
Rdd.w[0]=sat_32((Rs.h[0] * Rt.h[0])<<1 - (Rs.h[1] * Rt.h[1])<<1);
Copy to clipboard | | Rdd=cmpy(Rs,Rt\*):sat | Rdd.w[1]=sat_32((Rs.h[1] * Rt.h[0])<<0 - (Rs.h[0] * Rt.h[1])<<0);
Rdd.w[0]=sat_32((Rs.h[0] * Rt.h[0])<<0 + (Rs.h[1] * Rt.h[1])<<0);
Copy to clipboard | | Rdd=cmpy(Rs,Rt\*):<<1:sat | Rdd.w[1]=sat_32((Rs.h[1] * Rt.h[0])<<1 - (Rs.h[0] * Rt.h[1])<<1);
Rdd.w[0]=sat_32((Rs.h[0] * Rt.h[0])<<1 + (Rs.h[1] * Rt.h[1])<<1);
Copy to clipboard | | Rxx-=cmpy(Rs,Rt):sat | Rxx.w[1]=sat_32(Rxx.w[1] - ((Rs.h[1] * Rt.h[0])<<0 + (Rs.h[0] * Rt.h[1])<<0));
Rxx.w[0]=sat_32(Rxx.w[0] - ((Rs.h[0] * Rt.h[0])<<0 - (Rs.h[1] * Rt.h[1])<<0));
Copy to clipboard | | Rxx-=cmpy(Rs,Rt):<<1:sat | Rxx.w[1]=sat_32(Rxx.w[1] - ((Rs.h[1] * Rt.h[0])<<1 + (Rs.h[0] * Rt.h[1])<<1));
Rxx.w[0]=sat_32(Rxx.w[0] - ((Rs.h[0] * Rt.h[0])<<1 - (Rs.h[1] * Rt.h[1])<<1));
Copy to clipboard | | Rxx-=cmpy(Rs,Rt\*):sat | Rxx.w[1]=sat_32(Rxx.w[1] - ((Rs.h[1] * Rt.h[0])<<0 - (Rs.h[0] * Rt.h[1])<<0));
Rxx.w[0]=sat_32(Rxx.w[0] - ((Rs.h[0] * Rt.h[0])<<0 + (Rs.h[1] * Rt.h[1])<<0));
Copy to clipboard | | Rxx-=cmpy(Rs,Rt\*):<<1:sat | Rxx.w[1]=sat_32(Rxx.w[1] - ((Rs.h[1] * Rt.h[0])<<1 - (Rs.h[0] * Rt.h[1])<<1));
Rxx.w[0]=sat_32(Rxx.w[0] - ((Rs.h[0] * Rt.h[0])<<1 + (Rs.h[1] * Rt.h[1])<<1));
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
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Rxx+=cmpy(Rs,Rt):sat

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Rxx+=cmpy(Rs,Rt):<<1:sat

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Rxx+=cmpy(Rs,Rt*):sat

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Rxx+=cmpy(Rs,Rt*):<<1:sat

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Rdd=cmpy(Rs,Rt):sat

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Rdd=cmpy(Rs,Rt):<<1:sat

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Rdd=cmpy(Rs,Rt*):sat

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Rdd=cmpy(Rs,Rt*):<<1:sat

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Rxx-=cmpy(Rs,Rt):sat

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Rxx-=cmpy(Rs,Rt):<<1:sat

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Rxx-=cmpy(Rs,Rt*):sat

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Rxx-=cmpy(Rs,Rt*):<<1:sat

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Intrinsics
Complex multiply intrinsics

Rxx+=cmpy(Rs,Rt):sat

Word64 Q6_P_cmpyacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx+=cmpy(Rs,Rt):<<1:sat

Word64 Q6_P_cmpyacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx+=cmpy(Rs,Rt*):sat

Word64 Q6_P_cmpyacc_RR_conj_sat(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx+=cmpy(Rs,Rt*):<<1:sat

Word64 Q6_P_cmpyacc_RR_conj_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)

Rdd=cmpy(Rs,Rt):sat

Word64 Q6_P_cmpy_RR_sat(Word32 Rs, Word32 Rt)

Rdd=cmpy(Rs,Rt):<<1:sat

Word64 Q6_P_cmpy_RR_s1_sat(Word32 Rs, Word32 Rt)

Rdd=cmpy(Rs,Rt*):sat

Word64 Q6_P_cmpy_RR_conj_sat(Word32 Rs, Word32 Rt)

Rdd=cmpy(Rs,Rt*):<<1:sat

Word64 Q6_P_cmpy_RR_conj_s1_sat(Word32 Rs, Word32 Rt)

Rxx-=cmpy(Rs,Rt):sat

Word64 Q6_P_cmpynac_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx-=cmpy(Rs,Rt):<<1:sat

Word64 Q6_P_cmpynac_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx-=cmpy(Rs,Rt*):sat

Word64 Q6_P_cmpynac_RR_conj_sat(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx-=cmpy(Rs,Rt*):<<1:sat

Word64 Q6_P_cmpynac_RR_conj_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
#### Complex multiply real or imaginary Multiply complex values Rs and Rt. The inputs have a real 16-bit value in the low halfword and an imaginary 16-bit value in the high halfword. Take either the real or imaginary result and optionally accumulate with a 64-bit destination. pic_addh Page-1 Sheet.86 Sheet.31 Rs Rs Sheet.33 Sheet.34 Sheet.35 Add Add Rectangle Imaginary accumulation Imaginary accumulation Sheet.40 Sheet.41 Rectangle.43 I I Rectangle.47 R R Sheet.47 Rt Rt Sheet.49 * * Sheet.50 Sheet.51 Sheet.52 32 32 Sheet.55 * * Sheet.56 Sheet.57 Sheet.58 32 32 Sheet.69 Sheet.70 Sheet.71 Sheet.72 64 64 Sheet.73 Rxx Rxx Rectangle.1 I I Rectangle.19 R R Sheet.82 Sheet.83 Sheet.84 Sheet.85 Sheet.1 Rxx+=cmpyi(Rs,Rt) Rxx+=cmpyi(Rs,Rt) Complex multiply real or imaginary instructions | **Syntax** | **Behavior** | | --- | --- | | Rxx+=cmpyi(Rs,Rt) | Rxx = Rxx + (Rs.h[1] * Rt.h[0]) + (Rs.h[0] * Rt.h[1]);
Copy to clipboard | | Rxx+=cmpyr(Rs,Rt) | Rxx = Rxx + (Rs.h[0] * Rt.h[0]) - (Rs.h[1] * Rt.h[1]);
Copy to clipboard | | Rdd=cmpyi(Rs,Rt) | Rdd = (Rs.h[1] * Rt.h[0]) + (Rs.h[0] * Rt.h[1]);
Copy to clipboard | | Rdd=cmpyr(Rs,Rt) | Rdd = (Rs.h[0] * Rt.h[0]) - (Rs.h[1] * Rt.h[1]);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
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Rxx+=cmpyi(Rs,Rt)

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Rxx+=cmpyr(Rs,Rt)

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Rdd=cmpyi(Rs,Rt)

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Rdd=cmpyr(Rs,Rt)

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Intrinsics
Complex multiply real or imaginary intrinsics

Rxx+=cmpyi(Rs,Rt)

Word64 Q6_P_cmpyiacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx+=cmpyr(Rs,Rt)

Word64 Q6_P_cmpyracc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)

Rdd=cmpyi(Rs,Rt)

Word64 Q6_P_cmpyi_RR(Word32 Rs, Word32 Rt)

Rdd=cmpyr(Rs,Rt)

Word64 Q6_P_cmpyr_RR(Word32 Rs, Word32 Rt)
#### Complex multiply with round and pack Multiply complex values Rs and Rt. The inputs have a real 16-bit value in the low halfword and an imaginary 16-bit value in the high halfword. The Rt input is optionally conjugated. The multiplier results are optionally scaled by 0-1 bits. A rounding constant is added to each real and imaginary sum. The real and imaginary parts are individually saturated to 32bits. The upper 16-bits of each 32-bit results are packed in a 32-bit destination register. pic_addh Page-1 Sheet.91 Sheet.31 Rs Rs Sheet.35 Add Add Rectangle.43 I I Rectangle.47 R R Sheet.47 Rt Rt Sheet.49 * * Sheet.50 Sheet.51 Sheet.52 32 32 Rectangle.36 <<0-1 <<0-1 Sheet.54 Sheet.55 * * Sheet.56 Sheet.57 Sheet.58 32 32 Rectangle.59 <<0-1 <<0-1 Sheet.60 Sheet.69 Sheet.70 Sheet.73 Rd Rd Rectangle.1 I I Rectangle.19 R R Sheet.82 Sheet.83 Sheet.84 Sheet.85 Sheet.1 Rd=cmpy(Rs,Rt):rnd:sat Rd=cmpy(Rs,Rt):rnd:sat Sheet.3 Add Add Sheet.5 Rectangle.6 I I Rectangle.7 R R Sheet.9 * * Sheet.10 Sheet.11 Sheet.12 32 32 Rectangle.13 <<0-1 <<0-1 Sheet.14 Sheet.15 * * Sheet.16 Sheet.17 Sheet.18 32 32 Rectangle.19 <<0-1 <<0-1 Sheet.20 Sheet.21 Sheet.22 Rectangle.23 I I Rectangle.24 R R Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.2 Rs Rs Sheet.8 Rt Rt Sheet.86 - - Sheet.87 Sheet.88 0x8000 0x8000 Sheet.89 0x8000 0x8000 Sheet.90 Sheet.29 sat32 sat32 Sheet.32 Sheet.37 sat32 sat32 Sheet.38 Sheet.40 High 16-bits High 16-bits Sheet.42 Sheet.45 High 16-bits High 16-bits Rectangle.30 I I Rectangle.36 R R Complex multiply with round and pack instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=cmpy(Rs,Rt):rnd:sat | Rd.h[1]=(sat_32((Rs.h[1] * Rt.h[0])<<0 + (Rs.h[0] * Rt.h[1])<<0 + 0x8000)).h[1];
Rd.h[0]=(sat_32((Rs.h[0] * Rt.h[0])<<0 - (Rs.h[1] * Rt.h[1])<<0 + 0x8000)).h[1];
Copy to clipboard | | Rd=cmpy(Rs,Rt):<<1:rnd:sat | Rd.h[1]=(sat_32((Rs.h[1] * Rt.h[0])<<1 + (Rs.h[0] * Rt.h[1])<<1 + 0x8000)).h[1];
Rd.h[0]=(sat_32((Rs.h[0] * Rt.h[0])<<1 - (Rs.h[1] * Rt.h[1])<<1 + 0x8000)).h[1];
Copy to clipboard | | Rd=cmpy(Rs,Rt\*):rnd:sat | Rd.h[1]=(sat_32((Rs.h[1] * Rt.h[0])<<0 - (Rs.h[0] * Rt.h[1])<<0 + 0x8000)).h[1];
Rd.h[0]=(sat_32((Rs.h[0] * Rt.h[0])<<0 + (Rs.h[1] * Rt.h[1])<<0 + 0x8000)).h[1];
Copy to clipboard | | Rd=cmpy(Rs,Rt\*):<<1:rnd:sat | Rd.h[1]=(sat_32((Rs.h[1] * Rt.h[0])<<1 - (Rs.h[0] * Rt.h[1])<<1 + 0x8000)).h[1];
Rd.h[0]=(sat_32((Rs.h[0] * Rt.h[0])<<1 + (Rs.h[1] * Rt.h[1])<<1 + 0x8000)).h[1];
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
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Rd=cmpy(Rs,Rt):rnd:sat

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Rd=cmpy(Rs,Rt):<<1:rnd:sat

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Rd=cmpy(Rs,Rt*):rnd:sat

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Rd=cmpy(Rs,Rt*):<<1:rnd:sat

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Intrinsics
Complex multiply with round and pack intrinsics

Rd=cmpy(Rs,Rt):rnd:sat

Word32 Q6_R_cmpy_RR_rnd_sat(Word32 Rs, Word32 Rt)

Rd=cmpy(Rs,Rt):<<1:rnd:sat

Word32 Q6_R_cmpy_RR_s1_rnd_sat(Word32 Rs, Word32 Rt)

Rd=cmpy(Rs,Rt*):rnd:sat

Word32 Q6_R_cmpy_RR_conj_rnd_sat(Word32 Rs, Word32 Rt)

Rd=cmpy(Rs,Rt*):<<1:rnd:sat

Word32 Q6_R_cmpy_RR_conj_s1_rnd_sat(Word32 Rs, Word32 Rt)
#### Complex multiply 32x16 Multiply 32 by 16 bit complex values Rss and Rt. The inputs have a real value in the low part of a register and the imaginary value in the upper part. The multiplier results are scaled by 1 bit and accumulated with a rounding constant. The result is saturated to 32bits. pic_addh Page-1 Sheet.115 Sheet.31 Rss Rss Sheet.32 * * Sheet.36 Sheet.37 Sheet.38 48 48 Sheet.40 Sheet.41 Rectangle.47 R R Rectangle.45 I I Sheet.47 Rt Rt Sheet.55 * * Sheet.56 Sheet.58 48 48 Sheet.68 Sheet.70 Sheet.72 Rd Rd Rectangle.1 I I Rectangle.19 R R Sheet.80 Sheet.82 Sheet.83 Sheet.84 Sheet.1 Rd = cmpyrwh(Rss,Rt):<<1:rnd:sat Rd = cmpyrwh(Rss,Rt):<<1:rnd:sat Sheet.42 Sheet.43 Add Add Rectangle.13 <<1 <<1 Rectangle.53 <<1 <<1 Sheet.57 Sheet.60 - - Rectangle.35 Real result Real result Sheet.39 Sheet.50 sat32 sat32 Sheet.46 Rss Rss Sheet.48 * * Sheet.54 Sheet.61 Sheet.62 48 48 Rectangle.65 R R Rectangle.66 I I Sheet.67 Rt Rt Sheet.69 * * Sheet.76 Sheet.77 48 48 Sheet.78 Sheet.79 Rectangle.87 I I Rectangle.88 R R Sheet.89 Sheet.90 Sheet.91 Sheet.92 Sheet.93 Rd = cmpyiwh(Rss,Rt):<<1:rnd:sat Rd = cmpyiwh(Rss,Rt):<<1:rnd:sat Sheet.94 Sheet.59 Sheet.114 0x8000 0x8000 Sheet.33 Sheet.34 Sheet.51 Rd Rd Sheet.52 Add Add Rectangle.63 <<1 <<1 Rectangle.64 <<1 <<1 Sheet.71 Rectangle.81 Imaginary result Imaginary result Sheet.85 Sheet.86 sat32 sat32 Sheet.95 Sheet.96 0x8000 0x8000 Complex multiply 32x16 instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=cmpyiwh(Rss,Rt):<<1:rnd:sat | Rd = sat_32(( (Rss.w[0] * Rt.h[1]) + (Rss.w[1] * Rt.h[0]) + 0x4000)>>15);
Copy to clipboard | | Rd=cmpyrwh(Rss,Rt):<<1:rnd:sat | Rd = sat_32(( (Rss.w[0] * Rt.h[0]) - (Rss.w[1] * Rt.h[1]) + 0x4000)>>15);
Copy to clipboard | | Rd=cmpyiwh(Rss,Rt\*):<<1:rnd:sat | Rd = sat_32(( (Rss.w[1] * Rt.h[0]) - (Rss.w[0] * Rt.h[1]) + 0x4000)>>15);
Copy to clipboard | | Rd=cmpyrwh(Rss,Rt\*):<<1:rnd:sat | Rd = sat_32(( (Rss.w[0] * Rt.h[0]) + (Rss.w[1] * Rt.h[1]) + 0x4000)>>15);
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

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Rd=cmpyiwh(Rss,Rt):<<1:rnd:sat

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Rd=cmpyrwh(Rss,Rt):<<1:rnd:sat

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Rd=cmpyiwh(Rss,Rt*):<<1:rnd:sat

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Rd=cmpyrwh(Rss,Rt*):<<1:rnd:sat

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Intrinsics
Complex multiply 32x16 intrinsics

Rd=cmpyiwh(Rss,Rt):<<1:rnd:sat

Word32 Q6_R_cmpyiwh_PR_s1_rnd_sat(Word64 Rss, Word32 Rt)

Rd=cmpyrwh(Rss,Rt):<<1:rnd:sat

Word32 Q6_R_cmpyrwh_PR_s1_rnd_sat(Word64 Rss, Word32 Rt)

Rd=cmpyiwh(Rss,Rt*):<<1:rnd:sat

Word32 Q6_R_cmpyiwh_PR_conj_s1_rnd_sat(Word64 Rss, Word32 Rt)

Rd=cmpyrwh(Rss,Rt*):<<1:rnd:sat

Word32 Q6_R_cmpyrwh_PR_conj_s1_rnd_sat(Word64 Rss, Word32 Rt)
#### Vector complex multiply real or imaginary The inputs Rss and Rtt are a vector of two complex values. Each complex value is composed of a 16-bit imaginary portion in the upper halfword and a 16-bit real portion in the lower halfword. Generate two complex results, either the real result or the imaginary result. These results are optionally shifted left by 0-1 bits, and optionally accumulated with the destination register. pic_addh Page-1 Sheet.91 Sheet.33 Sheet.34 Sheet.35 add add Rectangle Imaginary accumulation Imaginary accumulation Sheet.40 Sheet.41 Rectangle.43 I I Rectangle.47 R R Sheet.49 * * Sheet.50 Sheet.51 Sheet.52 32 32 Rectangle.36 <<0-1 <<0-1 Sheet.54 Sheet.55 * * Sheet.56 Sheet.57 Sheet.58 32 32 Rectangle.59 <<0-1 <<0-1 Sheet.60 Sheet.69 Sheet.70 Sheet.71 Sheet.72 32 32 Sheet.73 Rxx Rxx Rectangle.1 I I Rectangle.19 R R Sheet.82 Sheet.83 Sheet.84 Sheet.85 Sheet.1 Rxx += vcmpyi(Rss, Rtt):sat Rxx += vcmpyi(Rss, Rtt):sat Sheet.3 add add Rectangle.4 Imaginary accumulation Imaginary accumulation Sheet.5 Rectangle.6 I I Rectangle.7 R R Sheet.9 * * Sheet.10 Sheet.11 Sheet.12 32 32 Rectangle.13 <<0-1 <<0-1 Sheet.14 Sheet.15 * * Sheet.16 Sheet.17 Sheet.18 32 32 Rectangle.19 <<0-1 <<0-1 Sheet.20 Sheet.21 Sheet.22 Rectangle.23 I I Rectangle.24 R R Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.2 Rss Rss Sheet.8 Rtt Rtt Sheet.29 Sheet.30 Sheet.32 32 32 Sheet.36 Sheet.37 Sheet.87 sat32 sat32 Sheet.88 sat32 sat32 Sheet.89 Sheet.90 Vector complex multiply real or imaginary instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vcmpyi(Rss,Rtt):sat | Rdd.w[0]=sat_32((Rss.h[1] * Rtt.h[0]) + (Rss.h[0] * Rtt.h[1])<<0);
Rdd.w[1]=sat_32((Rss.h[3] * Rtt.h[2]) + (Rss.h[2] * Rtt.h[3])<<0);
Copy to clipboard | | Rdd=vcmpyr(Rss,Rtt):sat | Rdd.w[0]=sat_32((Rss.h[0] * Rtt.h[0]) - (Rss.h[1] * Rtt.h[1])<<0);
Rdd.w[1]=sat_32((Rss.h[2] * Rtt.h[2]) - (Rss.h[3] * Rtt.h[3])<<0);
Copy to clipboard | | Rdd=vcmpyi(Rss,Rtt):<<1:sat | Rdd.w[0]=sat_32((Rss.h[1] * Rtt.h[0]) + (Rss.h[0] * Rtt.h[1])<<1);
Rdd.w[1]=sat_32((Rss.h[3] * Rtt.h[2]) + (Rss.h[2] * Rtt.h[3])<<1);
Copy to clipboard | | Rdd=vcmpyr(Rss,Rtt):<<1:sat | Rdd.w[0]=sat_32((Rss.h[0] * Rtt.h[0]) - (Rss.h[1] * Rtt.h[1])<<1);
Rdd.w[1]=sat_32((Rss.h[2] * Rtt.h[2]) - (Rss.h[3] * Rtt.h[3])<<1);
Copy to clipboard | | Rxx+=vcmpyi(Rss,Rtt):sat | Rxx.w[0]=sat_32(Rxx.w[0] + (Rss.h[1] * Rtt.h[0]) + (Rss.h[0] * Rtt.h[1])<<0);
Rxx.w[1]=sat_32(Rxx.w[1] + (Rss.h[3] * Rtt.h[2]) + (Rss.h[2] * Rtt.h[3])<<0);
Copy to clipboard | | Rxx+=vcmpyr(Rss,Rtt):sat | Rxx.w[0]=sat_32(Rxx.w[0] + (Rss.h[0] * Rtt.h[0]) - (Rss.h[1] * Rtt.h[1])<<0);
Rxx.w[1]=sat_32(Rxx.w[1] + (Rss.h[2] * Rtt.h[2]) - (Rss.h[3] * Rtt.h[3])<<0);
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

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Rdd=vcmpyi(Rss,Rtt):sat

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Rdd=vcmpyr(Rss,Rtt):sat

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Rdd=vcmpyi(Rss,Rtt):<<1:sat

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Rdd=vcmpyr(Rss,Rtt):<<1:sat

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Rxx+=vcmpyi(Rss,Rtt):sat

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Rxx+=vcmpyr(Rss,Rtt):sat

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Intrinsics
Vector complex multiply real or imaginary intrinsics

Rdd=vcmpyi(Rss,Rtt):sat

Word64 Q6_P_vcmpyi_PP_sat(Word64 Rss, Word64 Rtt)

Rdd=vcmpyr(Rss,Rtt):sat

Word64 Q6_P_vcmpyr_PP_sat(Word64 Rss, Word64 Rtt)

Rdd=vcmpyi(Rss,Rtt):<<1:sat

Word64 Q6_P_vcmpyi_PP_s1_sat(Word64 Rss, Word64 Rtt)

Rdd=vcmpyr(Rss,Rtt):<<1:sat

Word64 Q6_P_vcmpyr_PP_s1_sat(Word64 Rss, Word64 Rtt)

Rxx+=vcmpyi(Rss,Rtt):sat

Word64 Q6_P_vcmpyiacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rxx+=vcmpyr(Rss,Rtt):sat

Word64 Q6_P_vcmpyracc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
#### Vector complex conjugate Perform a vector complex conjugate of both complex values in vector Rss. This is done by negating the imaginary halfwords, and placing the result in destination Rdd. Vector complex conjugate instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vconj(Rss):sat | Rdd.h[1]=sat_16(-Rss.h[1]);
Rdd.h[0]=Rss.h[0];
Rdd.h[3]=sat_16(-Rss.h[3]);
Rdd.h[2]=Rss.h[2];
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

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Rdd=vconj(Rss):sat

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Intrinsics
Vector complex conjugate intrinsics

Rdd=vconj(Rss):sat

Word64 Q6_P_vconj_P_sat(Word64 Rss)
#### Vector complex rotate Take the least significant bits of Rt, and use these bits to rotate each of the two complex values in the source vector a multiple of 90 degrees. Bits 0 and 1 control the rotation factor for word 0, and bits 2 and 3 control the rotation factor for word 1. If the rotation control bits are 0, the rotation is 0: the real and imaginary halves of the source appear unchanged and unmoved in the destination. If the rotation control bits are 1, the rotation is -pi/2: the real half of the destination gets the imaginary half of the source, and the imaginary half of the destination gets the negative real half of the source. If the rotation control bits are 2, the rotation is pi/2: the real half of the destination gets the negative imaginary half of the source, and the imaginary half of the destination gets the real half of the source. If the rotation control bits are 3, the rotation is pi: the real half of the destination gets the negative real half of the source, and the imaginary half of the destination gets the negative imaginary half of the source. Vector complex rotate instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vcrotate(Rss,Rt) | tmp = Rt[1:0];
if (tmp == 0) {
Rdd.h[0]=Rss.h[0];
Rdd.h[1]=Rss.h[1];
} else if (tmp == 1) {
Rdd.h[0]=Rss.h[1];
Rdd.h[1]=sat_16(-Rss.h[0]);
} else if (tmp == 2) {
Rdd.h[0]=sat_16(-Rss.h[1]);
Rdd.h[1]=Rss.h[0];
} else {
Rdd.h[0]=sat_16(-Rss.h[0]);
Rdd.h[1]=sat_16(-Rss.h[1]);
}
tmp = Rt[3:2];
if (tmp == 0) {
Rdd.h[2]=Rss.h[2];
Rdd.h[3]=Rss.h[3];
} else if (tmp == 1) {
Rdd.h[2]=Rss.h[3];
Rdd.h[3]=sat_16(-Rss.h[2]);
} else if (tmp == 2) {
Rdd.h[2]=sat_16(-Rss.h[3]);
Rdd.h[3]=Rss.h[2];
} else {
Rdd.h[2]=sat_16(-Rss.h[2]);
Rdd.h[3]=sat_16(-Rss.h[3]);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rdd=vcrotate(Rss,Rt)

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Intrinsics
Vector complex rotate intrinsics

Rdd=vcrotate(Rss,Rt)

Word64 Q6_P_vcrotate_PR(Word64 Rss, Word32 Rt)
#### Vector reduce complex multiply real or imaginary The input vectors are two packed complex values, each with a real low halfword and imaginary high halfword. Compute either the real or imaginary products, add the intermediate results together and optionally accumulate with the destination. The Rtt input is optionally conjugated (negate the imaginary portion) before multiplication. Using vrcmpyr and vrcmpyi, it is possible to sustain an average of one full complex multiply per cycle in a complex FIR, while also keeping both the real and imaginary accumulators in full precision 64-bit values. pic_addh Page-1 Sheet.86 Sheet.31 Rss Rss Sheet.32 * * Sheet.33 Sheet.34 Sheet.35 Add Add Sheet.36 Sheet.37 Sheet.38 32 32 Rectangle Imaginary Accumulation Imaginary Accumulation Sheet.40 Sheet.41 Rectangle.43 I I Rectangle.47 R R Rectangle.45 I I Rectangle.46 R R Sheet.47 Rtt Rtt Sheet.49 * * Sheet.50 Sheet.51 Sheet.52 32 32 Sheet.55 * * Sheet.56 Sheet.58 32 32 Sheet.61 * * Sheet.62 Sheet.63 Sheet.64 32 32 Sheet.67 Sheet.68 Sheet.69 Sheet.70 Sheet.71 Sheet.72 64 64 Sheet.73 Rxx Rxx Rectangle.1 I I Rectangle.19 R R Rectangle.20 I I Rectangle.21 R R Sheet.78 Sheet.79 Sheet.80 Sheet.81 Sheet.82 Sheet.83 Sheet.84 Sheet.85 Sheet.1 Rxx+=vrcmpyi(Rss,Rtt) Rxx+=vrcmpyi(Rss,Rtt) Sheet.42 Vector reduce complex multiply real or imaginary instructions | **Syntax** | **Behavior** | | --- | --- | | Rxx+=vrcmpyi(Rss,Rtt) | Rxx = Rxx + (Rss.h[1] * Rtt.h[0]) + (Rss.h[0] * Rtt.h[1]) + (Rss.h[3] * Rtt.h[2]) + (Rss.h[2] * Rtt.h[3]);
Copy to clipboard | | Rxx+=vrcmpyr(Rss,Rtt) | Rxx = Rxx + (Rss.h[0] * Rtt.h[0]) - (Rss.h[1] * Rtt.h[1]) + (Rss.h[2] * Rtt.h[2]) - (Rss.h[3] * Rtt.h[3]);
Copy to clipboard | | Rxx+=vrcmpyi(Rss,Rtt\*) | Rxx = Rxx + (Rss.h[1] * Rtt.h[0]) - (Rss.h[0] * Rtt.h[1]) + (Rss.h[3] * Rtt.h[2]) - (Rss.h[2] * Rtt.h[3]);
Copy to clipboard | | Rxx+=vrcmpyr(Rss,Rtt\*) | Rxx = Rxx + (Rss.h[0] * Rtt.h[0]) + (Rss.h[1] * Rtt.h[1]) + (Rss.h[2] * Rtt.h[2]) + (Rss.h[3] * Rtt.h[3]);
Copy to clipboard | | Rdd=vrcmpyi(Rss,Rtt) | Rdd = (Rss.h[1] * Rtt.h[0]) + (Rss.h[0] * Rtt.h[1]) + (Rss.h[3] * Rtt.h[2]) + (Rss.h[2] * Rtt.h[3]);
Copy to clipboard | | Rdd=vrcmpyr(Rss,Rtt) | Rdd = (Rss.h[0] * Rtt.h[0]) - (Rss.h[1] * Rtt.h[1]) + (Rss.h[2] * Rtt.h[2]) - (Rss.h[3] * Rtt.h[3]);
Copy to clipboard | | Rdd=vrcmpyi(Rss,Rtt\*) | Rdd = (Rss.h[1] * Rtt.h[0]) - (Rss.h[0] * Rtt.h[1]) + (Rss.h[3] * Rtt.h[2]) - (Rss.h[2] * Rtt.h[3]);
Copy to clipboard | | Rdd=vrcmpyr(Rss,Rtt\*) | Rdd = (Rss.h[0] * Rtt.h[0]) + (Rss.h[1] * Rtt.h[1]) + (Rss.h[2] * Rtt.h[2]) + (Rss.h[3] * Rtt.h[3]);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

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Rxx+=vrcmpyi(Rss,Rtt)

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Rxx+=vrcmpyr(Rss,Rtt)

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Rxx+=vrcmpyi(Rss,Rtt*)

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Rxx+=vrcmpyr(Rss,Rtt*)

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Rdd=vrcmpyi(Rss,Rtt)

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Rdd=vrcmpyr(Rss,Rtt)

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Rdd=vrcmpyi(Rss,Rtt*)

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Rdd=vrcmpyr(Rss,Rtt*)

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Intrinsics
Vector reduce complex multiply real or imaginary intrinsics

Rxx+=vrcmpyi(Rss,Rtt)

Word64 Q6_P_vrcmpyiacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rxx+=vrcmpyr(Rss,Rtt)

Word64 Q6_P_vrcmpyracc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rxx+=vrcmpyi(Rss,Rtt*)

Word64 Q6_P_vrcmpyiacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rxx+=vrcmpyr(Rss,Rtt*)

Word64 Q6_P_vrcmpyracc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rdd=vrcmpyi(Rss,Rtt)

Word64 Q6_P_vrcmpyi_PP(Word64 Rss, Word64 Rtt)

Rdd=vrcmpyr(Rss,Rtt)

Word64 Q6_P_vrcmpyr_PP(Word64 Rss, Word64 Rtt)

Rdd=vrcmpyi(Rss,Rtt*)

Word64 Q6_P_vrcmpyi_PP_conj(Word64 Rss, Word64 Rtt)

Rdd=vrcmpyr(Rss,Rtt*)

Word64 Q6_P_vrcmpyr_PP_conj(Word64 Rss, Word64 Rtt)
#### Vector reduce complex multiply by scalar Multiply a complex number by a scalar. Rss contains two complex numbers. The real portions are each multiplied by two scalars contained in register Rt, scaled, summed, optionally accumulated, saturated, and stored in the lower word of Rdd. A similar operation is done on the two imaginary portions of Rss. pic_addh Page-1 Sheet.86 Sheet.35 Add Add Rectangle.43 I I Rectangle.47 R R Sheet.47 Rt Rt Sheet.49 * * Sheet.50 Sheet.51 Sheet.52 32 32 Rectangle.36 <<1 <<1 Sheet.54 Sheet.55 * * Sheet.56 Sheet.57 Sheet.58 32 32 Rectangle.59 <<1 <<1 Sheet.60 Sheet.69 Sheet.70 Rectangle.1 b b Rectangle.19 a a Sheet.82 Sheet.83 Sheet.84 Sheet.85 Sheet.1 Rdd=vrcmpys(Rss,Rt):<<1:sat Rdd=vrcmpys(Rss,Rt):<<1:sat Sheet.3 Add Add Sheet.5 Rectangle.6 I I Rectangle.7 R R Sheet.9 * * Sheet.10 Sheet.11 Sheet.12 32 32 Rectangle.13 <<1 <<1 Sheet.14 Sheet.15 * * Sheet.16 Sheet.17 Sheet.18 32 32 Rectangle.19 <<1 <<1 Sheet.20 Sheet.21 Sheet.22 Rectangle.23 b b Rectangle.24 a a Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.2 Rss Rss Sheet.8 Rt Rt Sheet.29 Sat32 Sat32 Sheet.32 Sheet.37 Sat32 Sat32 Sheet.38 Sheet.42 Rectangle.30 I I Rectangle.31 Rectangle.33 Sheet.36 Rdd Rdd Vector reduce complex multiply by scalar instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vrcmpys(Rss,Rtt):<<1:sat:raw:hi | Rdd.w[1]=sat_32((Rss.h[1] * Rtt.w[1].h[0])<<1 + (Rss.h[3] * Rtt.w[1].h[1])<<1);
Rdd.w[0]=sat_32((Rss.h[0] * Rtt.w[1].h[0])<<1 + (Rss.h[2] * Rtt.w[1].h[1])<<1);
Copy to clipboard | | Rdd=vrcmpys(Rss,Rtt):<<1:sat:raw:lo | Rdd.w[1]=sat_32((Rss.h[1] * Rtt.w[0].h[0])<<1 + (Rss.h[3] * Rtt.w[0].h[1])<<1);
Rdd.w[0]=sat_32((Rss.h[0] * Rtt.w[0].h[0])<<1 + (Rss.h[2] * Rtt.w[0].h[1])<<1);
Copy to clipboard | | Rdd=vrcmpys(Rss,Rt):<<1:sat | if ("Rt & 1") {
Assembler mapped to: "Rdd=vrcmpys(Rss,Rtt):<<1:sat:raw:hi";
} else {
Assembler mapped to: "Rdd=vrcmpys(Rss,Rtt):<<1:sat:raw:lo";
}
Copy to clipboard | | Rxx+=vrcmpys(Rss,Rtt):<<1:sat:raw:hi | Rxx.w[1]=sat_32(Rxx.w[1] + (Rss.h[1] * Rtt.w[1].h[0])<<1 + (Rss.h[3] * Rtt.w[1].h[1])<<1);
Rxx.w[0]=sat_32(Rxx.w[0] + (Rss.h[0] * Rtt.w[1].h[0])<<1 + (Rss.h[2] * Rtt.w[1].h[1])<<1);
Copy to clipboard | | Rxx+=vrcmpys(Rss,Rtt):<<1:sat:raw:lo | Rxx.w[1]=sat_32(Rxx.w[1] + (Rss.h[1] * Rtt.w[0].h[0])<<1 + (Rss.h[3] * Rtt.w[0].h[1])<<1);
Rxx.w[0]=sat_32(Rxx.w[0] + (Rss.h[0] * Rtt.w[0].h[0])<<1 + (Rss.h[2] * Rtt.w[0].h[1])<<1);
Copy to clipboard | | Rxx+=vrcmpys(Rss,Rt):<<1:sat | if ("Rt & 1") {
Assembler mapped to: "Rxx+=vrcmpys(Rss,Rtt):<<1:sat:raw:hi";
} else {
Assembler mapped to: "Rxx+=vrcmpys(Rss,Rtt):<<1:sat:raw:lo";
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
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Rdd=vrcmpys(Rss,Rtt):<<1:sat:raw:hi

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Rdd=vrcmpys(Rss,Rtt):<<1:sat:raw:lo

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Rxx+=vrcmpys(Rss,Rtt):<<1:sat:raw:hi

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Rxx+=vrcmpys(Rss,Rtt):<<1:sat:raw:lo

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Intrinsics
Vector reduce complex multiply by scalar intrinsics

Rdd=vrcmpys(Rss,Rt):<<1:sat

Word64 Q6_P_vrcmpys_PR_s1_sat(Word64 Rss, Word32 Rt)

Rxx+=vrcmpys(Rss,Rt):<<1:sat

Word64 Q6_P_vrcmpysacc_PR_s1_sat(Word64 Rxx, Word64 Rss, Word32 Rt)
#### Vector reduce complex multiply by scalar with round and pack Multiply a complex number by scalar. Rss contains two complex numbers. The real portions are each multiplied by two scalars contained in register Rt, scaled, summed, rounded, and saturated. The upper 16bits of this result are packed in the lower halfword of Rd. A similar operation is done on the two imaginary portions of Rss. pic_addh Page-1 Sheet.91 Sheet.35 Add Add Rectangle.43 I I Rectangle.47 R R Sheet.47 Rt Rt Sheet.49 * * Sheet.50 Sheet.51 Sheet.52 32 32 Rectangle.36 <<0-1 <<0-1 Sheet.54 Sheet.55 * * Sheet.56 Sheet.57 Sheet.58 32 32 Rectangle.59 <<0-1 <<0-1 Sheet.60 Sheet.69 Sheet.70 Sheet.73 Rd Rd Rectangle.1 b b Rectangle.19 a a Sheet.82 Sheet.83 Sheet.84 Sheet.85 Sheet.1 Rd = vrcmpys(Rss,Rt):<<1:rnd:sat Rd = vrcmpys(Rss,Rt):<<1:rnd:sat Sheet.3 Add Add Sheet.5 Rectangle.6 I I Rectangle.7 R R Sheet.9 * * Sheet.10 Sheet.11 Sheet.12 32 32 Rectangle.13 <<0-1 <<0-1 Sheet.14 Sheet.15 * * Sheet.16 Sheet.17 Sheet.18 32 32 Rectangle.19 <<0-1 <<0-1 Sheet.20 Sheet.21 Sheet.22 Rectangle.23 b b Rectangle.24 a a Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.2 Rss Rss Sheet.8 Rt Rt Sheet.87 Sheet.88 0x8000 0x8000 Sheet.89 0x8000 0x8000 Sheet.90 Sheet.29 sat32 sat32 Sheet.32 Sheet.37 sat32 sat32 Sheet.38 Sheet.40 High 16 bits High 16 bits Sheet.42 Sheet.45 High 16 bits High 16 bits Rectangle.30 I I Rectangle.36 R R Vector reduce complex multiply by scalar with round and pack instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=vrcmpys(Rss,Rtt):<<1:rnd:sat:raw:hi | Rd.h[1]=sat_32((Rss.h[1] * Rtt.w[1].h[0])<<1 + (Rss.h[3] * Rtt.w[1].h[1])<<1 + 0x8000).h[1];
Rd.h[0]=sat_32((Rss.h[0] * Rtt.w[1].h[0])<<1 + (Rss.h[2] * Rtt.w[1].h[1])<<1 + 0x8000).h[1];
Copy to clipboard | | Rd=vrcmpys(Rss,Rtt):<<1:rnd:sat:raw:lo | Rd.h[1]=sat_32((Rss.h[1] * Rtt.w[0].h[0])<<1 + (Rss.h[3] * Rtt.w[0].h[1])<<1 + 0x8000).h[1];
Rd.h[0]=sat_32((Rss.h[0] * Rtt.w[0].h[0])<<1 + (Rss.h[2] * Rtt.w[0].h[1])<<1 + 0x8000).h[1];
Copy to clipboard | | Rd=vrcmpys(Rss,Rt):<<1:rnd:sat | if ("Rt & 1") {
Assembler mapped to: "Rd=vrcmpys(Rss,Rtt):<<1:rnd:sat:raw:hi";
} else {
Assembler mapped to: "Rd=vrcmpys(Rss,Rtt):<<1:rnd:sat:raw:lo";
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
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Rd=vrcmpys(Rss,Rtt):<<1:rnd:sat:raw:hi

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Rd=vrcmpys(Rss,Rtt):<<1:rnd:sat:raw:lo

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Intrinsics
Vector reduce complex multiply by scalar with round and pack intrinsics

Rd=vrcmpys(Rss,Rt):<<1:rnd:sat

Word32 Q6_R_vrcmpys_PR_s1_rnd_sat(Word64 Rss, Word32 Rt)
#### Vector reduce complex rotate This instruction is useful for CDMA despreading. An unsigned 2-bit immediate specifies a byte to use in Rt. Each of four 2-bit fields in the specified byte selects a rotation amount for one of the four complex numbers in Rss. The real and imaginary products are accumulated and stored as a 32-bit complex number in Rd. Optionally, the destination register can also be accumulated. Page-1 Rectangle.18 Rectangle.22 Rectangle.26 Re0 Re0 Rectangle.27 Im0 Im0 Rectangle.28 Re1 Re1 Rectangle.29 Im1 Im1 Rectangle.30 Re2 Re2 Rectangle.31 Im2 Im2 Rectangle.32 Re3 Re3 Rectangle.33 Im3 Im3 Dynamic connector.37 Rectangle.19 Rectangle.20 Rectangle.59 Sheet.61 Rt Rt Dynamic connector.62 Sheet.63 I I Sheet.64 R R Sheet.65 Rxx Rxx Sheet.153 Rxx += vrcrotate(Rss,Rt,#0) Rxx += vrcrotate(Rss,Rt,#0) Sheet.66 Center drag circle Rounded rectangle.98 mux mux Sheet.100 Sheet.101 Sheet.103 Sheet.104 Sheet.105 Rounded rectangle.106 1 j -1 -j 1 j -1 -j Sheet.25 Sheet.38 Rectangle.35 Dynamic connector.21 Rounded rectangle.23 mux mux Sheet.42 Sheet.75 Sheet.76 Sheet.77 Sheet.78 Rounded rectangle.79 1 j -1 -j 1 j -1 -j Sheet.80 Dynamic connector.81 Rounded rectangle.82 mux mux Sheet.83 Sheet.84 Sheet.85 Sheet.86 Sheet.87 Rounded rectangle.88 1 j -1 -j 1 j -1 -j Sheet.89 Rounded rectangle.74 mux mux Sheet.90 Sheet.91 Sheet.92 Sheet.93 Sheet.94 Rounded rectangle.95 1 j -1 -j 1 j -1 -j Sheet.96 Dynamic connector.97 Sheet.162 Sheet.163 Sheet.164 Sheet.165 Sheet.166 Sheet.167 Sheet.168 Center drag circle Sheet.51 Sheet.52 Sheet.53 Sheet.54 Sheet.55 Sheet.56 Sheet.57 Sheet.58 Sheet.169 Sheet.170 Dynamic connector.171 Dynamic connector.172 Sheet.173 Rss Rss Rectangle.1 + + Center drag circle.2 Rectangle.3 + + Rectangle.4 * * Sheet.5 Center drag circle Rectangle.7 * * Sheet.8 Center drag circle Rectangle.10 * * Sheet.11 Center drag circle Rectangle.13 * * Vector reduce complex rotate instructions | **Syntax** | **Behavior** | | --- | --- | | Rxx+=vrcrotate(Rss,Rt,#u2) | sumr = 0;
sumi = 0;
control = Rt.ub[u];
for (i = 0; i < 8; i += 2) {
tmpr = Rss.b[i];
tmpi = Rss.b[i+1];
switch (control & 3) {
case 0: sumr += tmpr;
sumi += tmpi;
break;
case 1: sumr += tmpi;
sumi -= tmpr;
break;
case 2: sumr -= tmpi;
sumi += tmpr;
break;
case 3: sumr -= tmpr;
sumi -= tmpi;
break;
}
control = control >> 2;
}
Rxx.w[0]=Rxx.w[0] + sumr;
Rxx.w[1]=Rxx.w[1] + sumi;
Copy to clipboard | | Rdd=vrcrotate(Rss,Rt,#u2) | sumr = 0;
sumi = 0;
control = Rt.ub[u];
for (i = 0; i < 8; i += 2) {
tmpr = Rss.b[i];
tmpi = Rss.b[i+1];
switch (control & 3) {
case 0: sumr += tmpr;
sumi += tmpi;
break;
case 1: sumr += tmpi;
sumi -= tmpr;
break;
case 2: sumr -= tmpi;
sumi += tmpr;
break;
case 3: sumr -= tmpr;
sumi -= tmpi;
break;
}
control = control >> 2;
}
Rdd.w[0]=sumr;
Rdd.w[1]=sumi;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
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Rxx+=vrcrotate(Rss,Rt,#u2)

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Rdd=vrcrotate(Rss,Rt,#u2)

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Intrinsics
Vector reduce complex rotate intrinsics

Rxx+=vrcrotate(Rss,Rt,#u2)

Word64 Q6_P_vrcrotateacc_PRI(Word64 Rxx, Word64 Rss, Word32 Rt, Word32 Iu2)

Rdd=vrcrotate(Rss,Rt,#u2)

Word64 Q6_P_vrcrotate_PRI(Word64 Rss, Word32 Rt, Word32 Iu2)
### FP The XTYPE FP instruction subclass includes instructions for IEEE-754 floating point math. #### Floating point addition Add two floating point values Floating point addition instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=sfadd(Rs,Rt) | Rd=Rs+Rt;
Copy to clipboard | | Rdd=dfadd(Rss,Rtt) | Rdd=Rss+Rtt;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
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Rd=sfadd(Rs,Rt)

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Rdd=dfadd(Rss,Rtt)

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Intrinsics
Floating point addition intrinsics

Rd=sfadd(Rs,Rt)

Word32 Q6_R_sfadd_RR(Word32 Rs, Word32 Rt)

Rdd=dfadd(Rss,Rtt)

Word64 Q6_P_dfadd_PP(Word64 Rss, Word64 Rtt)
#### Classify floating-point value Classify floating point values. Classes are Normal, Subnormal, Zero, NaN, or Infinity. If the number is one of the specified classes, return true. Classify floating-point value instructions | **Syntax** | **Behavior** | | --- | --- | | Pd=sfclass(Rs,#u5) | Pd = 0;
class = fpclassify(Rs);
if (u.0 && (class == FP_ZERO)) Pd = 0xff;
if (u.1 && (class == FP_NORMAL)) Pd = 0xff;
if (u.2 && (class == FP_SUBNORMAL)) Pd = 0xff;
if (u.3 && (class == FP_INFINITE)) Pd = 0xff;
if (u.4 && (class == FP_NAN)) Pd = 0xff;
cancel_flags();
Copy to clipboard | | Pd=dfclass(Rss,#u5) | Pd = 0;
class = fpclassify(Rss);
if (u.0 && (class == FP_ZERO)) Pd = 0xff;
if (u.1 && (class == FP_NORMAL)) Pd = 0xff;
if (u.2 && (class == FP_SUBNORMAL)) Pd = 0xff;
if (u.3 && (class == FP_INFINITE)) Pd = 0xff;
if (u.4 && (class == FP_NAN)) Pd = 0xff;
cancel_flags();
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
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Pd=sfclass(Rs,#u5)

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Pd=dfclass(Rss,#u5)

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Intrinsics
Classify floating-point value intrinsics

Pd=sfclass(Rs,#u5)

Byte Q6_p_sfclass_RI(Word32 Rs, Word32 Iu5)

Pd=dfclass(Rss,#u5)

Byte Q6_p_dfclass_PI(Word64 Rss, Word32 Iu5)
#### Compare floating-point value Compare floating point values. p0 returns true if at least one value is a NaN, zero otherwise. Compare floating-point value instructions | **Syntax** | **Behavior** | | --- | --- | | Pd=sfcmp.eq(Rs,Rt) | Pd=Rs==Rt ? 0xff : 0x00;
Copy to clipboard | | Pd=sfcmp.gt(Rs,Rt) | Pd=Rs>Rt ? 0xff : 0x00;
Copy to clipboard | | Pd=sfcmp.ge(Rs,Rt) | Pd=Rs>=Rt ? 0xff : 0x00;
Copy to clipboard | | Pd=sfcmp.uo(Rs,Rt) | Pd=isunordered(Rs,Rt) ? 0xff : 0x00;
Copy to clipboard | | Pd=dfcmp.eq(Rss,Rtt) | Pd=Rss==Rtt ? 0xff : 0x00;
Copy to clipboard | | Pd=dfcmp.gt(Rss,Rtt) | Pd=Rss>Rtt ? 0xff : 0x00;
Copy to clipboard | | Pd=dfcmp.ge(Rss,Rtt) | Pd=Rss>=Rtt ? 0xff : 0x00;
Copy to clipboard | | Pd=dfcmp.uo(Rss,Rtt) | Pd=isunordered(Rss,Rtt) ? 0xff : 0x00;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
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Pd=sfcmp.eq(Rs,Rt)

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Pd=sfcmp.gt(Rs,Rt)

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Pd=sfcmp.ge(Rs,Rt)

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Pd=sfcmp.uo(Rs,Rt)

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Pd=dfcmp.eq(Rss,Rtt)

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Pd=dfcmp.gt(Rss,Rtt)

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Pd=dfcmp.ge(Rss,Rtt)

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Pd=dfcmp.uo(Rss,Rtt)

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Intrinsics
Compare floating-point value intrinsics

Pd=sfcmp.eq(Rs,Rt)

Byte Q6_p_sfcmp_eq_RR(Word32 Rs, Word32 Rt)

Pd=sfcmp.gt(Rs,Rt)

Byte Q6_p_sfcmp_gt_RR(Word32 Rs, Word32 Rt)

Pd=sfcmp.ge(Rs,Rt)

Byte Q6_p_sfcmp_ge_RR(Word32 Rs, Word32 Rt)

Pd=sfcmp.uo(Rs,Rt)

Byte Q6_p_sfcmp_uo_RR(Word32 Rs, Word32 Rt)

Pd=dfcmp.eq(Rss,Rtt)

Byte Q6_p_dfcmp_eq_PP(Word64 Rss, Word64 Rtt)

Pd=dfcmp.gt(Rss,Rtt)

Byte Q6_p_dfcmp_gt_PP(Word64 Rss, Word64 Rtt)

Pd=dfcmp.ge(Rss,Rtt)

Byte Q6_p_dfcmp_ge_PP(Word64 Rss, Word64 Rtt)

Pd=dfcmp.uo(Rss,Rtt)

Byte Q6_p_dfcmp_uo_PP(Word64 Rss, Word64 Rtt)
#### Convert floating-point value to other format Convert floating point values. If rounding is required, it happens according to the rounding mode. Convert floating-point value to other format instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=convert\_sf2df(Rs) | Rdd = conv_sf_to_df(Rs);
Copy to clipboard | | Rd=convert\_df2sf(Rss) | Rd = conv_df_to_sf(Rss);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
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Rdd=convert_sf2df(Rs)

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Rd=convert_df2sf(Rss)

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Intrinsics
Convert floating-point value to other format intrinsics

Rdd=convert_sf2df(Rs)

Word64 Q6_P_convert_sf2df_R(Word32 Rs)

Rd=convert_df2sf(Rss)

Word32 Q6_R_convert_df2sf_P(Word64 Rss)
#### Convert integer to floating-point value Convert floating point values. If rounding is required, it happens according to the rounding mode unless the :chop option is specified. Convert integer to floating-point value instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=convert\_uw2sf(Rs) | Rd = conv_4u_to_sf(Rs.uw[0]);
Copy to clipboard | | Rdd=convert\_uw2df(Rs) | Rdd = conv_4u_to_df(Rs.uw[0]);
Copy to clipboard | | Rd=convert\_w2sf(Rs) | Rd = conv_4s_to_sf(Rs.s32);
Copy to clipboard | | Rdd=convert\_w2df(Rs) | Rdd = conv_4s_to_df(Rs.s32);
Copy to clipboard | | Rd=convert\_ud2sf(Rss) | Rd = conv_8u_to_sf(Rss.u64);
Copy to clipboard | | Rdd=convert\_ud2df(Rss) | Rdd = conv_8u_to_df(Rss.u64);
Copy to clipboard | | Rd=convert\_d2sf(Rss) | Rd = conv_8s_to_sf(Rss.s64);
Copy to clipboard | | Rdd=convert\_d2df(Rss) | Rdd = conv_8s_to_df(Rss.s64);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
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Rd=convert_uw2sf(Rs)

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Rdd=convert_uw2df(Rs)

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Rd=convert_w2sf(Rs)

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Rdd=convert_w2df(Rs)

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Rd=convert_ud2sf(Rss)

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Rdd=convert_ud2df(Rss)

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Rd=convert_d2sf(Rss)

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Rdd=convert_d2df(Rss)

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Intrinsics
Convert integer to floating-point value intrinsics

Rd=convert_uw2sf(Rs)

Word32 Q6_R_convert_uw2sf_R(Word32 Rs)

Rdd=convert_uw2df(Rs)

Word64 Q6_P_convert_uw2df_R(Word32 Rs)

Rd=convert_w2sf(Rs)

Word32 Q6_R_convert_w2sf_R(Word32 Rs)

Rdd=convert_w2df(Rs)

Word64 Q6_P_convert_w2df_R(Word32 Rs)

Rd=convert_ud2sf(Rss)

Word32 Q6_R_convert_ud2sf_P(Word64 Rss)

Rdd=convert_ud2df(Rss)

Word64 Q6_P_convert_ud2df_P(Word64 Rss)

Rd=convert_d2sf(Rss)

Word32 Q6_R_convert_d2sf_P(Word64 Rss)

Rdd=convert_d2df(Rss)

Word64 Q6_P_convert_d2df_P(Word64 Rss)
#### Convert floating-point value to integer Convert floating point values. If rounding is required, it happens according to the rounding mode unless the :chop option is specified. If the value is out of range of the destination integer type, the INVALID flag is raised and closest integer is chosen, including for infinite inputs. For NaN inputs, the INVALID flag is also raised, and the output value is IMPLEMENTATION DEFINED. Convert floating-point value to integer instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=convert\_sf2uw(Rs) | Rd = conv_sf_to_4u(Rs).uw[0];
Copy to clipboard | | Rd=convert\_sf2w(Rs) | Rd = conv_sf_to_4s(Rs).s32;
Copy to clipboard | | Rdd=convert\_sf2ud(Rs) | Rdd = conv_sf_to_8u(Rs).u64;
Copy to clipboard | | Rdd=convert\_sf2d(Rs) | Rdd = conv_sf_to_8s(Rs).s64;
Copy to clipboard | | Rd=convert\_df2uw(Rss) | Rd = conv_df_to_4u(Rss).uw[0];
Copy to clipboard | | Rd=convert\_df2w(Rss) | Rd = conv_df_to_4s(Rss).s32;
Copy to clipboard | | Rdd=convert\_df2ud(Rss) | Rdd = conv_df_to_8u(Rss).u64;
Copy to clipboard | | Rdd=convert\_df2d(Rss) | Rdd = conv_df_to_8s(Rss).s64;
Copy to clipboard | | Rd=convert\_sf2uw(Rs):chop | round_to_zero();
Rd = conv_sf_to_4u(Rs).uw[0];
Copy to clipboard | | Rd=convert\_sf2w(Rs):chop | round_to_zero();
Rd = conv_sf_to_4s(Rs).s32;
Copy to clipboard | | Rdd=convert\_sf2ud(Rs):chop | round_to_zero();
Rdd = conv_sf_to_8u(Rs).u64;
Copy to clipboard | | Rdd=convert\_sf2d(Rs):chop | round_to_zero();
Rdd = conv_sf_to_8s(Rs).s64;
Copy to clipboard | | Rd=convert\_df2uw(Rss):chop | round_to_zero();
Rd = conv_df_to_4u(Rss).uw[0];
Copy to clipboard | | Rd=convert\_df2w(Rss):chop | round_to_zero();
Rd = conv_df_to_4s(Rss).s32;
Copy to clipboard | | Rdd=convert\_df2ud(Rss):chop | round_to_zero();
Rdd = conv_df_to_8u(Rss).u64;
Copy to clipboard | | Rdd=convert\_df2d(Rss):chop | round_to_zero();
Rdd = conv_df_to_8s(Rss).s64;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
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Rd=convert_sf2uw(Rs)

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Rd=convert_sf2w(Rs)

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Rdd=convert_sf2ud(Rs)

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Rdd=convert_sf2d(Rs)

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Rd=convert_df2uw(Rss)

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Rd=convert_df2w(Rss)

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Rdd=convert_df2ud(Rss)

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Rdd=convert_df2d(Rss)

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Rd=convert_sf2uw(Rs):chop

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Rd=convert_sf2w(Rs):chop

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Rdd=convert_sf2ud(Rs):chop

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Rdd=convert_sf2d(Rs):chop

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Rd=convert_df2uw(Rss):chop

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Rd=convert_df2w(Rss):chop

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Rdd=convert_df2ud(Rss):chop

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Rdd=convert_df2d(Rss):chop

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Intrinsics
Convert floating-point value to integer intrinsics

Rd=convert_sf2uw(Rs)

Word32 Q6_R_convert_sf2uw_R(Word32 Rs)

Rd=convert_sf2w(Rs)

Word32 Q6_R_convert_sf2w_R(Word32 Rs)

Rdd=convert_sf2ud(Rs)

Word64 Q6_P_convert_sf2ud_R(Word32 Rs)

Rdd=convert_sf2d(Rs)

Word64 Q6_P_convert_sf2d_R(Word32 Rs)

Rd=convert_df2uw(Rss)

Word32 Q6_R_convert_df2uw_P(Word64 Rss)

Rd=convert_df2w(Rss)

Word32 Q6_R_convert_df2w_P(Word64 Rss)

Rdd=convert_df2ud(Rss)

Word64 Q6_P_convert_df2ud_P(Word64 Rss)

Rdd=convert_df2d(Rss)

Word64 Q6_P_convert_df2d_P(Word64 Rss)

Rd=convert_sf2uw(Rs):chop

Word32 Q6_R_convert_sf2uw_R_chop(Word32 Rs)

Rd=convert_sf2w(Rs):chop

Word32 Q6_R_convert_sf2w_R_chop(Word32 Rs)

Rdd=convert_sf2ud(Rs):chop

Word64 Q6_P_convert_sf2ud_R_chop(Word32 Rs)

Rdd=convert_sf2d(Rs):chop

Word64 Q6_P_convert_sf2d_R_chop(Word32 Rs)

Rd=convert_df2uw(Rss):chop

Word32 Q6_R_convert_df2uw_P_chop(Word64 Rss)

Rd=convert_df2w(Rss):chop

Word32 Q6_R_convert_df2w_P_chop(Word64 Rss)

Rdd=convert_df2ud(Rss):chop

Word64 Q6_P_convert_df2ud_P_chop(Word64 Rss)

Rdd=convert_df2d(Rss):chop

Word64 Q6_P_convert_df2d_P_chop(Word64 Rss)
#### Floating point extreme value assistance For divide and square root routines, certain values are problematic for the default routine. These instructions appropriately fix up the numerator (fixupn), denominator (fixupd), or radicand (fixupr) for proper calculations when combined with the divide or square root approximation instructions. Floating point extreme value assistance instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=sffixupn(Rs,Rt) | (Rs,Rt,Rd,adjust)=recip_common(Rs,Rt);
Rd = Rs;
Copy to clipboard | | Rd=sffixupd(Rs,Rt) | (Rs,Rt,Rd,adjust)=recip_common(Rs,Rt);
Rd = Rt;
Copy to clipboard | | Rd=sffixupr(Rs) | (Rs,Rd,adjust)=invsqrt_common(Rs);
Rd = Rs;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
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Rd=sffixupn(Rs,Rt)

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Rd=sffixupd(Rs,Rt)

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Rd=sffixupr(Rs)

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Intrinsics
Floating point extreme value assistance intrinsics

Rd=sffixupn(Rs,Rt)

Word32 Q6_R_sffixupn_RR(Word32 Rs, Word32 Rt)

Rd=sffixupd(Rs,Rt)

Word32 Q6_R_sffixupd_RR(Word32 Rs, Word32 Rt)

Rd=sffixupr(Rs)

Word32 Q6_R_sffixupr_R(Word32 Rs)
#### Floating point fused multiply-add Multiply two values, and add to (or subtract from) the accumulator. Full intermediate precision is kept. Floating point fused multiply-add instructions | **Syntax** | **Behavior** | | --- | --- | | Rx+=sfmpy(Rs,Rt) | Rx=fmaf(Rs,Rt,Rx);
Copy to clipboard | | Rx-=sfmpy(Rs,Rt) | Rx=fmaf(-Rs,Rt,Rx);
Copy to clipboard | | Rxx+=dfmpylh(Rss,Rtt) | Rxx += (Rss.uw[0] * (0x00100000 | zxt_20_to_64(Rtt.uw[1]))) << 1;
Copy to clipboard | | Rxx+=dfmpyhh(Rss,Rtt) | Rxx = Rss*Rtt with partial product Rxx;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
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Rx+=sfmpy(Rs,Rt)

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Rx-=sfmpy(Rs,Rt)

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Rxx+=dfmpylh(Rss,Rtt)

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Rxx+=dfmpyhh(Rss,Rtt)

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Intrinsics
Floating point fused multiply-add intrinsics

Rx+=sfmpy(Rs,Rt)

Word32 Q6_R_sfmpyacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=sfmpy(Rs,Rt)

Word32 Q6_R_sfmpynac_RR(Word32 Rx, Word32 Rs, Word32 Rt)

Rxx+=dfmpylh(Rss,Rtt)

Word64 Q6_P_dfmpylhacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rxx+=dfmpyhh(Rss,Rtt)

Word64 Q6_P_dfmpyhhacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
#### Floating point fused multiply-add with scaling Multiply two values, and add to (or subtract from) the accumulator. Full intermediate precision is kept. Additionally, scale the output. This instruction has special handling of corner cases. If a multiplicand source is zero and a NaN is not produced, the accumulator is left unchanged; this means the sign of a zero accumulator will not change if the product is a true zero. The scaling factor is the predicate taken as a two’s compliment number for single precision. The scaling factor is twice the predicate taken as a two’s compliment number for double precision. The implementation may change denormal accumulator values to zero for positive scale factors. Floating point fused multiply-add with scaling instructions | **Syntax** | **Behavior** | | --- | --- | | Rx+=sfmpy(Rs,Rt,Pu):scale | if (isnan(Rx) || isnan(Rs) || isnan(Rt)) Rx = NaN;
tmp=fmaf(Rs,Rt,Rx) * 2**(Pu);
if (!((Rx == 0.0) && is_true_zero(Rs*Rt))) Rx = tmp;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
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Rx+=sfmpy(Rs,Rt,Pu):scale

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Intrinsics
Floating point fused multiply-add with scaling intrinsics

Rx+=sfmpy(Rs,Rt,Pu):scale

Word32 Q6_R_sfmpyacc_RRp_scale(Word32 Rx, Word32 Rs, Word32 Rt, Byte Pu)
#### Floating point reciprocal square root approximation Provides an approximation of the reciprocal square root of the radicand (Rs), if combined with the appropriate fixup instruction. Certain values (such as infinities or zeros) in the numerator or denominator may yield values that are not reciprocal approximations, but yield the correct answer when combined with fixup instructions and the appropriate routines. For compatibility, exact results of these instructions can not be relied on. The precision of the approximation for this architecture and later is at least 6.6 bits. Floating point reciprocal square root approximation instructions | **Syntax** | **Behavior** | | --- | --- | | Rd,Pe=sfinvsqrta(Rs) | if ((Rs,Rd,adjust)=invsqrt_common(Rs)) {
Pe = adjust;
idx = (Rs >> 17) & 0x7f;
mant = (invsqrt_lut[idx] << 15);
exp = 127 - ((exponent(Rs) - 127) >> 1) - 1;
Rd = -1**Rs.31 * 1.MANT * 2**(exp-BIAS);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - This instruction provides a certain amount of accuracy. In future versions the accuracy may increase. For future compatibility, dependence on exact values must be avoided. - The predicate generated by this instruction can not be used as a .new predicate, nor can it be automatically ANDed with another predicate.
Encodings
Bitmap

Syntax

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Rd,Pe=sfinvsqrta(Rs)

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#### Floating point fused multiply-add for library routines Multiply two values, and add to (or subtract from) the accumulator. Full intermediate precision is kept. This instruction has special handling of corner cases. Addition of infinities with opposite signs, or subtraction of infinities with like signs, is defined as (positive) zero. Rounding is always Nearest-Even, except that overflows to infinity round to maximal finite values. If a multiplicand source is zero and a NaN is not produced, the accumulator is left unchanged; this means the sign of a zero accumulator will not change if the product is a true zero. Flags and Exceptions are not generated. Floating point fused multiply-add for library routines instructions | **Syntax** | **Behavior** | | --- | --- | | Rx+=sfmpy(Rs,Rt):lib | round_to_nearest();
infminusinf = ((isinf(Rx)) && (isinf(Rs*Rt)) && (Rs ^ Rx ^ Rt.31 != 0));
infinp = (isinf(Rx)) || (isinf(Rt)) || (isinf(Rs));
if (isnan(Rx) || isnan(Rs) || isnan(Rt)) Rx = NaN;
tmp=fmaf(Rs,Rt,Rx);
if (!((Rx == 0.0) && is_true_zero(Rs*Rt))) Rx = tmp;
cancel_flags();
if (isinf(Rx) && !infinp) Rx = Rx - 1;
if (infminusinf) Rx = 0;
Copy to clipboard | | Rx-=sfmpy(Rs,Rt):lib | round_to_nearest();
infminusinf = ((isinf(Rx)) && (isinf(Rs*Rt)) && (Rs ^ Rx ^ Rt.31 == 0));
infinp = (isinf(Rx)) || (isinf(Rt)) || (isinf(Rs));
if (isnan(Rx) || isnan(Rs) || isnan(Rt)) Rx = NaN;
tmp=fmaf(-Rs,Rt,Rx);
if (!((Rx == 0.0) && is_true_zero(Rs*Rt))) Rx = tmp;
cancel_flags();
if (isinf(Rx) && !infinp) Rx = Rx - 1;
if (infminusinf) Rx = 0;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rx+=sfmpy(Rs,Rt):lib

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Rx-=sfmpy(Rs,Rt):lib

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Intrinsics
Floating point fused multiply-add for library routines intrinsics

Rx+=sfmpy(Rs,Rt):lib

Word32 Q6_R_sfmpyacc_RR_lib(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=sfmpy(Rs,Rt):lib

Word32 Q6_R_sfmpynac_RR_lib(Word32 Rx, Word32 Rs, Word32 Rt)
#### Create floating-point constant Using ten bits of immediate, form a floating-point constant. Create floating-point constant instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=sfmake(#u10):pos | Rd = (127 - 6) << 23;
Rd += u << 17;
Copy to clipboard | | Rd=sfmake(#u10):neg | Rd = (127 - 6) << 23;
Rd += (u << 17);
Rd |= (1 << 31);
Copy to clipboard | | Rdd=dfmake(#u10):pos | Rdd = (1023ULL - 6) << 52;
Rdd += (u) << 46;
Copy to clipboard | | Rdd=dfmake(#u10):neg | Rdd = (1023ULL - 6) << 52;
Rdd += (u) << 46;
Rdd |= ((1ULL) << 63);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

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Rd=sfmake(#u10):pos

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Rd=sfmake(#u10):neg

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Rdd=dfmake(#u10):pos

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Rdd=dfmake(#u10):neg

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Intrinsics
Create floating-point constant intrinsics

Rd=sfmake(#u10):pos

Word32 Q6_R_sfmake_I_pos(Word32 Iu10)

Rd=sfmake(#u10):neg

Word32 Q6_R_sfmake_I_neg(Word32 Iu10)

Rdd=dfmake(#u10):pos

Word64 Q6_P_dfmake_I_pos(Word32 Iu10)

Rdd=dfmake(#u10):neg

Word64 Q6_P_dfmake_I_neg(Word32 Iu10)
#### Floating point maximum Maximum of two floating point values. If one value is a NaN, the other is chosen. Floating point maximum instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=sfmax(Rs,Rt) | Rd = fmaxf(Rs,Rt);
Copy to clipboard | | Rdd=dfmax(Rss,Rtt) | Rdd = fmax(Rss,Rtt);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rd=sfmax(Rs,Rt)

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Rdd=dfmax(Rss,Rtt)

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Intrinsics
Floating point maximum intrinsics

Rd=sfmax(Rs,Rt)

Word32 Q6_R_sfmax_RR(Word32 Rs, Word32 Rt)

Rdd=dfmax(Rss,Rtt)

Word64 Q6_P_dfmax_PP(Word64 Rss, Word64 Rtt)
#### Floating point minimum Minimum of two floating point values. If one value is a NaN, the other is chosen. Floating point minimum instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=sfmin(Rs,Rt) | Rd = fmin(Rs,Rt);
Copy to clipboard | | Rdd=dfmin(Rss,Rtt) | Rdd = fmin(Rss,Rtt);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rd=sfmin(Rs,Rt)

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Rdd=dfmin(Rss,Rtt)

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Intrinsics
Floating point minimum intrinsics

Rd=sfmin(Rs,Rt)

Word32 Q6_R_sfmin_RR(Word32 Rs, Word32 Rt)

Rdd=dfmin(Rss,Rtt)

Word64 Q6_P_dfmin_PP(Word64 Rss, Word64 Rtt)
#### Floating point multiply Multiply two floating point values Floating point multiply instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=sfmpy(Rs,Rt) | Rd=Rs*Rt;
Copy to clipboard | | Rdd=dfmpyfix(Rss,Rtt) | if (is_denormal(Rss) && (df_exponent(Rtt) >= 512) && is_normal(Rtt)) Rdd = Rss * 0x1.0p52;
else if (is_denormal(Rtt) && (df_exponent(Rss) >= 512) && is_normal(Rss)) Rdd = Rss * 0x1.0p-52;
else Rdd = Rss;
Copy to clipboard | | Rdd=dfmpyll(Rss,Rtt) | prod = (Rss.uw[0] * Rtt.uw[0]);
Rdd = (prod >> 32) << 1;
if (prod.uw[0] != 0) Rdd.0 = 1;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

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Rd=sfmpy(Rs,Rt)

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Rdd=dfmpyfix(Rss,Rtt)

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Rdd=dfmpyll(Rss,Rtt)

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Intrinsics
Floating point multiply intrinsics

Rd=sfmpy(Rs,Rt)

Word32 Q6_R_sfmpy_RR(Word32 Rs, Word32 Rt)

Rdd=dfmpyfix(Rss,Rtt)

Word64 Q6_P_dfmpyfix_PP(Word64 Rss, Word64 Rtt)

Rdd=dfmpyll(Rss,Rtt)

Word64 Q6_P_dfmpyll_PP(Word64 Rss, Word64 Rtt)
#### Floating point reciprocal approximation Provides an approximation of the reciprocal of the denominator (Rt), if combined with the appropriate fixup instructions. Certain values (such as infinities or zeros) in the numerator or denominator may yield values that are not reciprocal approximations, but yield the correct answer when combined with fixup instructions and the appropriate routines. For compatibility, exact results of these instructions can not be relied on. The precision of the approximation for this architecture and later is at least 6.6 bits. Floating point reciprocal approximation instructions | **Syntax** | **Behavior** | | --- | --- | | Rd,Pe=sfrecipa(Rs,Rt) | if ((Rs,Rt,Rd,adjust)=recip_common(Rs,Rt)) {
Pe = adjust;
idx = (Rt >> 16) & 0x7f;
mant = (recip_lut[idx] << 15) | 1;
exp = 127 - (exponent(Rt) - 127) - 1;
Rd = -1**Rt.31 * 1.MANT * 2**(exp-BIAS);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - This instruction provides a certain amount of accuracy. In future versions the accuracy may increase. For future compatibility, dependence on exact values must be avoided. - The predicate generated by this instruction can not be used as a .new predicate, nor can it be automatically ANDed with another predicate.
Encodings
Bitmap

Syntax

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Rd,Pe=sfrecipa(Rs,Rt)

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#### Floating point subtraction Subtract two floating point values Floating point subtraction instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=sfsub(Rs,Rt) | Rd=Rs-Rt;
Copy to clipboard | | Rdd=dfsub(Rss,Rtt) | Rdd=Rss-Rtt;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rd=sfsub(Rs,Rt)

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Rdd=dfsub(Rss,Rtt)

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Intrinsics
Floating point subtraction intrinsics

Rd=sfsub(Rs,Rt)

Word32 Q6_R_sfsub_RR(Word32 Rs, Word32 Rt)

Rdd=dfsub(Rss,Rtt)

Word64 Q6_P_dfsub_PP(Word64 Rss, Word64 Rtt)
### MPY The XTYPE/MPY instruction subclass includes instructions which perform multiplication. #### Multiply and use lower result Multiply the signed 32-bit integer in Rs by either the signed 32-bit integer in Rt or an unsigned immediate value. The 64-bit result is optionally accumulated with the 32-bit destination, or added to an immediate. The least-significant 32-bits of the result are written to the single destination register. This multiply produces the correct results for the ANSI C multiplication of two signed or unsigned integers with an integer result. pic_addh Page-1 Sheet.58 Sheet.5 Rx Rx Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 32 32 Sheet.31 Add Add Rectangle.7 Sheet.42 * * Sheet.43 Sheet.44 Sheet.45 64 64 Sheet.47 Rectangle.24 Sheet.53 Sheet.55 Sheet.56 Rs Rs Sheet.57 Rt /#u8 Rt /#u8 Sheet.33 Rectangle.34 Sheet.1 Low 32 bits Low 32 bits Multiply and use lower result instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=+mpyi(Rs,#u8) | apply_extension(u);
Rd=Rs*u;
Copy to clipboard | | Rd=-mpyi(Rs,#u8) | Rd=Rs*-u;
Copy to clipboard | | Rd=mpyi(Rs,#m9) | if ("((m9<0) && (m9>-256))") {
Assembler mapped to: "Rd=-mpyi(Rs,m9*(-1))";
} else {
Assembler mapped to: "Rd=+mpyi(Rs,m9)";
}
Copy to clipboard | | Rx+=mpyi(Rs,#u8) | apply_extension(u);
Rx=Rx + (Rs*u);
Copy to clipboard | | Rx-=mpyi(Rs,#u8) | apply_extension(u);
Rx=Rx - (Rs*u);
Copy to clipboard | | Rd=mpyi(Rs,Rt) | Rd=Rs*Rt;
Copy to clipboard | | Rd=mpyui(Rs,Rt) | Assembler mapped to: "Rd=mpyi(Rs,Rt)"
Copy to clipboard | | Rx+=mpyi(Rs,Rt) | Rx=Rx + Rs*Rt;
Copy to clipboard | | Rx-=mpyi(Rs,Rt) | Rx=Rx - Rs*Rt;
Copy to clipboard | | Ry=add(Ru,mpyi(Ry,Rs)) | Ry = Ru + Rs*Ry;
Copy to clipboard | | Rd=add(Ru,mpyi(#u6:2,Rs)) | Rd = Ru + Rs*u;
Copy to clipboard | | Rd=add(Ru,mpyi(Rs,#u6)) | apply_extension(u);
Rd = Ru + Rs*u;
Copy to clipboard | | Rd=add(#u6,mpyi(Rs,#U6)) | apply_extension(u);
Rd = u + Rs*U;
Copy to clipboard | | Rd=add(#u6,mpyi(Rs,Rt)) | apply_extension(u);
Rd = u + Rs*Rt;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rd=+mpyi(Rs,#u8)

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Rd=-mpyi(Rs,#u8)

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Rx+=mpyi(Rs,#u8)

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Rx-=mpyi(Rs,#u8)

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Rd=mpyi(Rs,Rt)

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Rx+=mpyi(Rs,Rt)

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Rx-=mpyi(Rs,Rt)

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Ry=add(Ru,mpyi(Ry,Rs))

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Rd=add(Ru,mpyi(#u6:2,Rs))

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Rd=add(Ru,mpyi(Rs,#u6))

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Rd=add(#u6,mpyi(Rs,#U6))

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Rd=add(#u6,mpyi(Rs,Rt))

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Intrinsics
Multiply and use lower result intrinsics

Rd=mpyi(Rs,#m9)

Word32 Q6_R_mpyi_RI(Word32 Rs, Word32 Im9)

Rx+=mpyi(Rs,#u8)

Word32 Q6_R_mpyiacc_RI(Word32 Rx, Word32 Rs, Word32 Iu8)

Rx-=mpyi(Rs,#u8)

Word32 Q6_R_mpyinac_RI(Word32 Rx, Word32 Rs, Word32 Iu8)

Rd=mpyi(Rs,Rt)

Word32 Q6_R_mpyi_RR(Word32 Rs, Word32 Rt)

Rd=mpyui(Rs,Rt)

Word32 Q6_R_mpyui_RR(Word32 Rs, Word32 Rt)

Rx+=mpyi(Rs,Rt)

Word32 Q6_R_mpyiacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpyi(Rs,Rt)

Word32 Q6_R_mpyinac_RR(Word32 Rx, Word32 Rs, Word32 Rt)

Ry=add(Ru,mpyi(Ry,Rs))

Word32 Q6_R_add_mpyi_RRR(Word32 Ru, Word32 Ry, Word32 Rs)

Rd=add(Ru,mpyi(#u6:2,Rs))

Word32 Q6_R_add_mpyi_RIR(Word32 Ru, Word32 Iu6_2, Word32 Rs)

Rd=add(Ru,mpyi(Rs,#u6))

Word32 Q6_R_add_mpyi_RRI(Word32 Ru, Word32 Rs, Word32 Iu6)

Rd=add(#u6,mpyi(Rs,#U6))

Word32 Q6_R_add_mpyi_IRI(Word32 Iu6, Word32 Rs, Word32 IU6)

Rd=add(#u6,mpyi(Rs,Rt))

Word32 Q6_R_add_mpyi_IRR(Word32 Iu6, Word32 Rs, Word32 Rt)
#### Vector multiply word by signed half (32x16) Perform mixed precision vector multiply operations. A 32-bit word from vector Rss is multiplied by a 16-bit halfword (either even or odd) from vector Rtt. The multiplication is performed as a signed 32x16, which produces a 48-bit result. This result is optionally scaled left by one bit. This result is then shifted right by 16 bits, optionally accumulated and then saturated to 32-bits. This operation is available in vector form (vmpyweh/vmpywoh) and non-vector form (multiply and use upper result). pic_addh Page-1 Sheet.101 Sheet.33 Sheet.34 Sheet.35 Add Add Rectangle Sheet.40 Sheet.41 Rectangle.47 s32 s32 Sheet.49 * * Sheet.50 Sheet.51 Sheet.52 48 48 Rectangle.36 <<0-1 <<0-1 Sheet.54 Sheet.69 Sheet.71 Sheet.72 32 32 Sheet.73 Rxx Rxx Rectangle.19 s16 s16 Sheet.83 Sheet.3 Add Add Rectangle.4 Sheet.5 Rectangle.7 s32 s32 Sheet.9 * * Sheet.10 Rectangle.24 s16 s16 Sheet.26 Sheet.2 Rss Rss Sheet.8 Rtt Rtt Sheet.29 Sheet.30 Sheet.32 32 32 Sheet.36 Sheet.37 Sheet.87 sat32 sat32 Sheet.88 sat32 sat32 Sheet.89 Sheet.90 Rectangle.1 s16 s16 Rectangle.18 s16 s16 Sheet.85 Sheet.27 Rounded rectangle mux mux Sheet.20 Rounded rectangle.22 mux mux Sheet.23 Sheet.25 Sheet.28 Sheet.91 Add Add Sheet.92 Sheet.93 Sheet.96 0x8000 0x8000 Rounded rectangle.97 mux mux Sheet.98 0x0 0x0 Sheet.99 Sheet.100 Sheet.11 Sheet.12 48 48 Rectangle.13 <<0-1 <<0-1 Sheet.14 Sheet.31 Add Add Sheet.38 Sheet.45 Sheet.46 0x8000 0x8000 Rounded rectangle.47 mux mux Sheet.48 0x0 0x0 Sheet.55 Sheet.56 Sheet.6 >>16 >>16 Sheet.15 Sheet.16 Sheet.17 >>16 >>16 Sheet.21 Vector multiply word by signed half (32x16) instructions | **Syntax** | **Behavior** | | --- | --- | | Rxx+=vmpyweh(Rss,Rtt):sat | Rxx.w[1]=sat_32(Rxx.w[1] + (((Rss.w[1] * Rtt.h[2])<<0)>>16));
Rxx.w[0]=sat_32(Rxx.w[0] + (((Rss.w[0] * Rtt.h[0])<<0)>>16));
Copy to clipboard | | Rxx+=vmpyweh(Rss,Rtt):<<1:sat | Rxx.w[1]=sat_32(Rxx.w[1] + (((Rss.w[1] * Rtt.h[2])<<1)>>16));
Rxx.w[0]=sat_32(Rxx.w[0] + (((Rss.w[0] * Rtt.h[0])<<1)>>16));
Copy to clipboard | | Rxx+=vmpywoh(Rss,Rtt):sat | Rxx.w[1]=sat_32(Rxx.w[1] + (((Rss.w[1] * Rtt.h[3])<<0)>>16));
Rxx.w[0]=sat_32(Rxx.w[0] + (((Rss.w[0] * Rtt.h[1])<<0)>>16 ));
Copy to clipboard | | Rxx+=vmpywoh(Rss,Rtt):<<1:sat | Rxx.w[1]=sat_32(Rxx.w[1] + (((Rss.w[1] * Rtt.h[3])<<1)>>16));
Rxx.w[0]=sat_32(Rxx.w[0] + (((Rss.w[0] * Rtt.h[1])<<1)>>16 ));
Copy to clipboard | | Rdd=vmpyweh(Rss,Rtt):sat | Rdd.w[1]=sat_32(((Rss.w[1] * Rtt.h[2])<<0)>>16);
Rdd.w[0]=sat_32(((Rss.w[0] * Rtt.h[0])<<0)>>16);
Copy to clipboard | | Rdd=vmpyweh(Rss,Rtt):<<1:sat | Rdd.w[1]=sat_32(((Rss.w[1] * Rtt.h[2])<<1)>>16);
Rdd.w[0]=sat_32(((Rss.w[0] * Rtt.h[0])<<1)>>16);
Copy to clipboard | | Rdd=vmpywoh(Rss,Rtt):sat | Rdd.w[1]=sat_32(((Rss.w[1] * Rtt.h[3])<<0)>>16);
Rdd.w[0]=sat_32(((Rss.w[0] * Rtt.h[1])<<0)>>16);
Copy to clipboard | | Rdd=vmpywoh(Rss,Rtt):<<1:sat | Rdd.w[1]=sat_32(((Rss.w[1] * Rtt.h[3])<<1)>>16);
Rdd.w[0]=sat_32(((Rss.w[0] * Rtt.h[1])<<1)>>16);
Copy to clipboard | | Rxx+=vmpyweh(Rss,Rtt):rnd:sat | Rxx.w[1]=sat_32(Rxx.w[1] + (((Rss.w[1] * Rtt.h[2])<<0+0x8000)>>16));
Rxx.w[0]=sat_32(Rxx.w[0] + (((Rss.w[0] * Rtt.h[0])<<0+0x8000)>>16));
Copy to clipboard | | Rxx+=vmpyweh(Rss,Rtt):<<1:rnd:sat | Rxx.w[1]=sat_32(Rxx.w[1] + (((Rss.w[1] * Rtt.h[2])<<1+0x8000)>>16));
Rxx.w[0]=sat_32(Rxx.w[0] + (((Rss.w[0] * Rtt.h[0])<<1+0x8000)>>16));
Copy to clipboard | | Rxx+=vmpywoh(Rss,Rtt):rnd:sat | Rxx.w[1]=sat_32(Rxx.w[1] + (((Rss.w[1] * Rtt.h[3])<<0+0x8000)>>16));
Rxx.w[0]=sat_32(Rxx.w[0] + (((Rss.w[0] * Rtt.h[1])<<0+0x8000)>>16 ));
Copy to clipboard | | Rxx+=vmpywoh(Rss,Rtt):<<1:rnd:sat | Rxx.w[1]=sat_32(Rxx.w[1] + (((Rss.w[1] * Rtt.h[3])<<1+0x8000)>>16));
Rxx.w[0]=sat_32(Rxx.w[0] + (((Rss.w[0] * Rtt.h[1])<<1+0x8000)>>16 ));
Copy to clipboard | | Rdd=vmpyweh(Rss,Rtt):rnd:sat | Rdd.w[1]=sat_32(((Rss.w[1] * Rtt.h[2])<<0+0x8000)>>16);
Rdd.w[0]=sat_32(((Rss.w[0] * Rtt.h[0])<<0+0x8000)>>16);
Copy to clipboard | | Rdd=vmpyweh(Rss,Rtt):<<1:rnd:sat | Rdd.w[1]=sat_32(((Rss.w[1] * Rtt.h[2])<<1+0x8000)>>16);
Rdd.w[0]=sat_32(((Rss.w[0] * Rtt.h[0])<<1+0x8000)>>16);
Copy to clipboard | | Rdd=vmpywoh(Rss,Rtt):rnd:sat | Rdd.w[1]=sat_32(((Rss.w[1] * Rtt.h[3])<<0+0x8000)>>16);
Rdd.w[0]=sat_32(((Rss.w[0] * Rtt.h[1])<<0+0x8000)>>16);
Copy to clipboard | | Rdd=vmpywoh(Rss,Rtt):<<1:rnd:sat | Rdd.w[1]=sat_32(((Rss.w[1] * Rtt.h[3])<<1+0x8000)>>16);
Rdd.w[0]=sat_32(((Rss.w[0] * Rtt.h[1])<<1+0x8000)>>16);
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
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Rxx+=vmpyweh(Rss,Rtt):sat

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Rxx+=vmpyweh(Rss,Rtt):<<1:sat

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Rxx+=vmpywoh(Rss,Rtt):sat

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Rxx+=vmpywoh(Rss,Rtt):<<1:sat

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Rdd=vmpyweh(Rss,Rtt):sat

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Rdd=vmpyweh(Rss,Rtt):<<1:sat

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Rdd=vmpywoh(Rss,Rtt):sat

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Rdd=vmpywoh(Rss,Rtt):<<1:sat

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Rxx+=vmpyweh(Rss,Rtt):rnd:sat

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Rxx+=vmpyweh(Rss,Rtt):<<1:rnd:sat

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Rxx+=vmpywoh(Rss,Rtt):rnd:sat

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Rxx+=vmpywoh(Rss,Rtt):<<1:rnd:sat

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Rdd=vmpyweh(Rss,Rtt):rnd:sat

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Rdd=vmpyweh(Rss,Rtt):<<1:rnd:sat

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Rdd=vmpywoh(Rss,Rtt):rnd:sat

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Rdd=vmpywoh(Rss,Rtt):<<1:rnd:sat

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Intrinsics
Vector multiply word by signed half (32x16) intrinsics

Rxx+=vmpyweh(Rss,Rtt):sat

Word64 Q6_P_vmpywehacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rxx+=vmpyweh(Rss,Rtt):<<1:sat

Word64 Q6_P_vmpywehacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rxx+=vmpywoh(Rss,Rtt):sat

Word64 Q6_P_vmpywohacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rxx+=vmpywoh(Rss,Rtt):<<1:sat

Word64 Q6_P_vmpywohacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rdd=vmpyweh(Rss,Rtt):sat

Word64 Q6_P_vmpyweh_PP_sat(Word64 Rss, Word64 Rtt)

Rdd=vmpyweh(Rss,Rtt):<<1:sat

Word64 Q6_P_vmpyweh_PP_s1_sat(Word64 Rss, Word64 Rtt)

Rdd=vmpywoh(Rss,Rtt):sat

Word64 Q6_P_vmpywoh_PP_sat(Word64 Rss, Word64 Rtt)

Rdd=vmpywoh(Rss,Rtt):<<1:sat

Word64 Q6_P_vmpywoh_PP_s1_sat(Word64 Rss, Word64 Rtt)

Rxx+=vmpyweh(Rss,Rtt):rnd:sat

Word64 Q6_P_vmpywehacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rxx+=vmpyweh(Rss,Rtt):<<1:rnd:sat

Word64 Q6_P_vmpywehacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rxx+=vmpywoh(Rss,Rtt):rnd:sat

Word64 Q6_P_vmpywohacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rxx+=vmpywoh(Rss,Rtt):<<1:rnd:sat

Word64 Q6_P_vmpywohacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rdd=vmpyweh(Rss,Rtt):rnd:sat

Word64 Q6_P_vmpyweh_PP_rnd_sat(Word64 Rss, Word64 Rtt)

Rdd=vmpyweh(Rss,Rtt):<<1:rnd:sat

Word64 Q6_P_vmpyweh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)

Rdd=vmpywoh(Rss,Rtt):rnd:sat

Word64 Q6_P_vmpywoh_PP_rnd_sat(Word64 Rss, Word64 Rtt)

Rdd=vmpywoh(Rss,Rtt):<<1:rnd:sat

Word64 Q6_P_vmpywoh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
#### Vector multiply word by unsigned half (32x16) Perform mixed precision vector multiply operations. A 32-bit signed word from vector Rss is multiplied by a 16-bit unsigned halfword (either odd or even) from vector Rtt. This multiplication produces a 48-bit result. This result is optionally scaled left by one bit, and then a rounding constant is optionally added to the lower 16-bits. This result is then shifted right by 16 bits, optionally accumulated and then saturated to 32-bits. This is a dual vector operation and is performed for both high and low word of Rss. pic_addh Page-1 Sheet.101 Sheet.33 Sheet.34 Sheet.35 Add Add Rectangle Sheet.40 Sheet.41 Rectangle.47 s32 s32 Sheet.49 * * Sheet.50 Sheet.51 Sheet.52 48 48 Rectangle.36 <<0-1 <<0-1 Sheet.54 Sheet.69 Sheet.71 Sheet.72 32 32 Sheet.73 Rxx Rxx Rectangle.19 u16 u16 Sheet.83 Sheet.3 Add Add Rectangle.4 Sheet.5 Rectangle.7 s32 s32 Sheet.9 * * Sheet.10 Rectangle.24 u16 u16 Sheet.26 Sheet.2 Rss Rss Sheet.8 Rtt Rtt Sheet.29 Sheet.30 Sheet.32 32 32 Sheet.36 Sheet.37 Sheet.87 sat32 sat32 Sheet.88 sat32 sat32 Sheet.89 Sheet.90 Rectangle.1 u16 u16 Rectangle.18 u16 u16 Sheet.85 Sheet.27 Rounded rectangle mux mux Sheet.20 Rounded rectangle.22 mux mux Sheet.23 Sheet.25 Sheet.28 Sheet.91 Add Add Sheet.92 Sheet.93 Sheet.96 0x8000 0x8000 Rounded rectangle.97 mux mux Sheet.98 0x0 0x0 Sheet.99 Sheet.100 Sheet.11 Sheet.12 48 48 Rectangle.13 <<0-1 <<0-1 Sheet.14 Sheet.31 Add Add Sheet.38 Sheet.45 Sheet.46 0x8000 0x8000 Rounded rectangle.47 mux mux Sheet.48 0x0 0x0 Sheet.55 Sheet.56 Sheet.6 >>16 >>16 Sheet.15 Sheet.16 Sheet.17 >>16 >>16 Sheet.21 Vector multiply word by unsigned half (32x16) instructions | **Syntax** | **Behavior** | | --- | --- | | Rxx+=vmpyweuh(Rss,Rtt):sat | Rxx.w[1]=sat_32(Rxx.w[1] + (((Rss.w[1] * Rtt.uh[2])<<0)>>16));
Rxx.w[0]=sat_32(Rxx.w[0] + (((Rss.w[0] * Rtt.uh[0])<<0)>>16));
Copy to clipboard | | Rxx+=vmpyweuh(Rss,Rtt):<<1:sat | Rxx.w[1]=sat_32(Rxx.w[1] + (((Rss.w[1] * Rtt.uh[2])<<1)>>16));
Rxx.w[0]=sat_32(Rxx.w[0] + (((Rss.w[0] * Rtt.uh[0])<<1)>>16));
Copy to clipboard | | Rxx+=vmpywouh(Rss,Rtt):sat | Rxx.w[1]=sat_32(Rxx.w[1] + (((Rss.w[1] * Rtt.uh[3])<<0)>>16));
Rxx.w[0]=sat_32(Rxx.w[0] + (((Rss.w[0] * Rtt.uh[1])<<0)>>16 ));
Copy to clipboard | | Rxx+=vmpywouh(Rss,Rtt):<<1:sat | Rxx.w[1]=sat_32(Rxx.w[1] + (((Rss.w[1] * Rtt.uh[3])<<1)>>16));
Rxx.w[0]=sat_32(Rxx.w[0] + (((Rss.w[0] * Rtt.uh[1])<<1)>>16 ));
Copy to clipboard | | Rdd=vmpyweuh(Rss,Rtt):sat | Rdd.w[1]=sat_32(((Rss.w[1] * Rtt.uh[2])<<0)>>16);
Rdd.w[0]=sat_32(((Rss.w[0] * Rtt.uh[0])<<0)>>16);
Copy to clipboard | | Rdd=vmpyweuh(Rss,Rtt):<<1:sat | Rdd.w[1]=sat_32(((Rss.w[1] * Rtt.uh[2])<<1)>>16);
Rdd.w[0]=sat_32(((Rss.w[0] * Rtt.uh[0])<<1)>>16);
Copy to clipboard | | Rdd=vmpywouh(Rss,Rtt):sat | Rdd.w[1]=sat_32(((Rss.w[1] * Rtt.uh[3])<<0)>>16);
Rdd.w[0]=sat_32(((Rss.w[0] * Rtt.uh[1])<<0)>>16);
Copy to clipboard | | Rdd=vmpywouh(Rss,Rtt):<<1:sat | Rdd.w[1]=sat_32(((Rss.w[1] * Rtt.uh[3])<<1)>>16);
Rdd.w[0]=sat_32(((Rss.w[0] * Rtt.uh[1])<<1)>>16);
Copy to clipboard | | Rxx+=vmpyweuh(Rss,Rtt):rnd:sat | Rxx.w[1]=sat_32(Rxx.w[1] + (((Rss.w[1] * Rtt.uh[2])<<0+0x8000)>>16));
Rxx.w[0]=sat_32(Rxx.w[0] + (((Rss.w[0] * Rtt.uh[0])<<0+0x8000)>>16));
Copy to clipboard | | Rxx+=vmpyweuh(Rss,Rtt):<<1:rnd:sat | Rxx.w[1]=sat_32(Rxx.w[1] + (((Rss.w[1] * Rtt.uh[2])<<1+0x8000)>>16));
Rxx.w[0]=sat_32(Rxx.w[0] + (((Rss.w[0] * Rtt.uh[0])<<1+0x8000)>>16));
Copy to clipboard | | Rxx+=vmpywouh(Rss,Rtt):rnd:sat | Rxx.w[1]=sat_32(Rxx.w[1] + (((Rss.w[1] * Rtt.uh[3])<<0+0x8000)>>16));
Rxx.w[0]=sat_32(Rxx.w[0] + (((Rss.w[0] * Rtt.uh[1])<<0+0x8000)>>16 ));
Copy to clipboard | | Rxx+=vmpywouh(Rss,Rtt):<<1:rnd:sat | Rxx.w[1]=sat_32(Rxx.w[1] + (((Rss.w[1] * Rtt.uh[3])<<1+0x8000)>>16));
Rxx.w[0]=sat_32(Rxx.w[0] + (((Rss.w[0] * Rtt.uh[1])<<1+0x8000)>>16 ));
Copy to clipboard | | Rdd=vmpyweuh(Rss,Rtt):rnd:sat | Rdd.w[1]=sat_32(((Rss.w[1] * Rtt.uh[2])<<0+0x8000)>>16);
Rdd.w[0]=sat_32(((Rss.w[0] * Rtt.uh[0])<<0+0x8000)>>16);
Copy to clipboard | | Rdd=vmpyweuh(Rss,Rtt):<<1:rnd:sat | Rdd.w[1]=sat_32(((Rss.w[1] * Rtt.uh[2])<<1+0x8000)>>16);
Rdd.w[0]=sat_32(((Rss.w[0] * Rtt.uh[0])<<1+0x8000)>>16);
Copy to clipboard | | Rdd=vmpywouh(Rss,Rtt):rnd:sat | Rdd.w[1]=sat_32(((Rss.w[1] * Rtt.uh[3])<<0+0x8000)>>16);
Rdd.w[0]=sat_32(((Rss.w[0] * Rtt.uh[1])<<0+0x8000)>>16);
Copy to clipboard | | Rdd=vmpywouh(Rss,Rtt):<<1:rnd:sat | Rdd.w[1]=sat_32(((Rss.w[1] * Rtt.uh[3])<<1+0x8000)>>16);
Rdd.w[0]=sat_32(((Rss.w[0] * Rtt.uh[1])<<1+0x8000)>>16);
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
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Rxx+=vmpyweuh(Rss,Rtt):sat

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Rxx+=vmpyweuh(Rss,Rtt):<<1:sat

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Rxx+=vmpywouh(Rss,Rtt):sat

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Rxx+=vmpywouh(Rss,Rtt):<<1:sat

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Rdd=vmpyweuh(Rss,Rtt):sat

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s

s

s

P

P

0

t

t

t

t

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1

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1

d

d

d

d

d

Rdd=vmpyweuh(Rss,Rtt):<<1:sat

1

1

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0

0

0

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P

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Rdd=vmpywouh(Rss,Rtt):sat

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Rdd=vmpywouh(Rss,Rtt):<<1:sat

1

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0

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0

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s

s

s

P

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1

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1

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Rxx+=vmpyweuh(Rss,Rtt):rnd:sat

1

1

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0

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0

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s

s

P

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x

x

Rxx+=vmpyweuh(Rss,Rtt):<<1:rnd:sat

1

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P

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Rxx+=vmpywouh(Rss,Rtt):rnd:sat

1

1

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s

P

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x

Rxx+=vmpywouh(Rss,Rtt):<<1:rnd:sat

1

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P

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x

Rdd=vmpyweuh(Rss,Rtt):rnd:sat

1

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1

0

0

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s

s

s

s

P

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d

Rdd=vmpyweuh(Rss,Rtt):<<1:rnd:sat

1

1

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Rdd=vmpywouh(Rss,Rtt):rnd:sat

1

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Rdd=vmpywouh(Rss,Rtt):<<1:rnd:sat

1

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d

d

d

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d
Intrinsics
Vector multiply word by unsigned half (32x16) intrinsics

Rxx+=vmpyweuh(Rss,Rtt):sat

Word64 Q6_P_vmpyweuhacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rxx+=vmpyweuh(Rss,Rtt):<<1:sat

Word64 Q6_P_vmpyweuhacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rxx+=vmpywouh(Rss,Rtt):sat

Word64 Q6_P_vmpywouhacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rxx+=vmpywouh(Rss,Rtt):<<1:sat

Word64 Q6_P_vmpywouhacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rdd=vmpyweuh(Rss,Rtt):sat

Word64 Q6_P_vmpyweuh_PP_sat(Word64 Rss, Word64 Rtt)

Rdd=vmpyweuh(Rss,Rtt):<<1:sat

Word64 Q6_P_vmpyweuh_PP_s1_sat(Word64 Rss, Word64 Rtt)

Rdd=vmpywouh(Rss,Rtt):sat

Word64 Q6_P_vmpywouh_PP_sat(Word64 Rss, Word64 Rtt)

Rdd=vmpywouh(Rss,Rtt):<<1:sat

Word64 Q6_P_vmpywouh_PP_s1_sat(Word64 Rss, Word64 Rtt)

Rxx+=vmpyweuh(Rss,Rtt):rnd:sat

Word64 Q6_P_vmpyweuhacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rxx+=vmpyweuh(Rss,Rtt):<<1:rnd:sat

Word64 Q6_P_vmpyweuhacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rxx+=vmpywouh(Rss,Rtt):rnd:sat

Word64 Q6_P_vmpywouhacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rxx+=vmpywouh(Rss,Rtt):<<1:rnd:sat

Word64 Q6_P_vmpywouhacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rdd=vmpyweuh(Rss,Rtt):rnd:sat

Word64 Q6_P_vmpyweuh_PP_rnd_sat(Word64 Rss, Word64 Rtt)

Rdd=vmpyweuh(Rss,Rtt):<<1:rnd:sat

Word64 Q6_P_vmpyweuh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)

Rdd=vmpywouh(Rss,Rtt):rnd:sat

Word64 Q6_P_vmpywouh_PP_rnd_sat(Word64 Rss, Word64 Rtt)

Rdd=vmpywouh(Rss,Rtt):<<1:rnd:sat

Word64 Q6_P_vmpywouh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
#### Multiply signed halfwords Multiply two signed halfwords. Optionally shift the multiplier result by 1 bit. This result can be accumulated or rounded. The destination/accumulator can be either 32 or 64-bits. For 32-bit results, saturation is optional. pic_addh Page-1 Sheet.80 Sheet.1 Rs Rs Rectangle.3 Sheet.4 Rt Rt Rectangle.6 Sheet.8 Sheet.10 Sheet.19 Sheet.20 32 32 Rectangle.27 <<0-1 <<0-1 Sheet.22 Sheet.26 Rx Rx Sheet.24 Rx+=mpy(Rs.[HL],Rt.[HL])[:<<1][:sat] Rx+=mpy(Rs.[HL],Rt.[HL])[:<<1][:sat] Rectangle.2 Rounded rectangle.20 32-bit add/sub 32-bit add/sub Sheet.9 Sheet.13 Sheet.14 Rounded rectangle.2 Optional sat to 32 bits Optional sat to 32 bits Sheet.18 Rectangle.5 Rectangle.17 Rounded rectangle.23 mux mux Sheet.27 Sheet.28 Rounded rectangle.29 mux mux Rounded rectangle.11 16 × 16 16 × 16 Sheet.12 Sheet.30 Sheet.15 Sheet.25 Sheet.31 Rs Rs Rectangle.32 Sheet.33 Rt Rt Rectangle.34 Sheet.35 Sheet.36 Sheet.37 Sheet.38 32 32 Rectangle.39 <<0-1 <<0-1 Sheet.40 Sheet.41 Rxx Rxx Sheet.42 Rxx+=mpy(Rs.[HL],Rt.[HL])[:<<1] Rxx+=mpy(Rs.[HL],Rt.[HL])[:<<1] Rounded rectangle.44 64-bit add/sub 64-bit add/sub Sheet.45 Sheet.47 Rectangle.50 Rectangle.51 Rounded rectangle.52 mux mux Sheet.53 Sheet.54 Rounded rectangle.55 mux mux Rounded rectangle.56 16 ×16 16 ×16 Sheet.57 Sheet.58 Sheet.60 Rectangle.48 Rounded rectangle.43 mux mux Sheet.49 Sheet.61 0x8000 0x8000 Sheet.62 Sheet.63 Rd = mpy(Rs.[HL],Rt.[HL])[:<<1][:rnd][:sat] Rd = mpy(Rs.[HL],Rt.[HL])[:<<1][:rnd][:sat] Sheet.46 Rdd = mpy(Rs.[HL],Rt.[HL])[:<<1][:rnd] Rdd = mpy(Rs.[HL],Rt.[HL])[:<<1][:rnd] Sheet.70 Sheet.71 0x0 0x0 Sheet.72 Sheet.73 Rounded rectangle.74 mux mux Sheet.75 Sheet.76 0x8000 0x8000 Sheet.77 Sheet.78 Sheet.79 0x0 0x0 Multiply signed halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rx+=mpy(Rs.H,Rt.H) | Rx=Rx+ (Rs.h[1] * Rt.h[1]);
Copy to clipboard | | Rx+=mpy(Rs.H,Rt.H):<<1 | Rx=Rx+ (Rs.h[1] * Rt.h[1])<<1;
Copy to clipboard | | Rx+=mpy(Rs.H,Rt.L) | Rx=Rx+ (Rs.h[1] * Rt.h[0]);
Copy to clipboard | | Rx+=mpy(Rs.H,Rt.L):<<1 | Rx=Rx+ (Rs.h[1] * Rt.h[0])<<1;
Copy to clipboard | | Rx+=mpy(Rs.L,Rt.H) | Rx=Rx+ (Rs.h[0] * Rt.h[1]);
Copy to clipboard | | Rx+=mpy(Rs.L,Rt.H):<<1 | Rx=Rx+ (Rs.h[0] * Rt.h[1])<<1;
Copy to clipboard | | Rx+=mpy(Rs.L,Rt.L) | Rx=Rx+ (Rs.h[0] * Rt.h[0]);
Copy to clipboard | | Rx+=mpy(Rs.L,Rt.L):<<1 | Rx=Rx+ (Rs.h[0] * Rt.h[0])<<1;
Copy to clipboard | | Rx-=mpy(Rs.H,Rt.H) | Rx=Rx- (Rs.h[1] * Rt.h[1]);
Copy to clipboard | | Rx-=mpy(Rs.H,Rt.H):<<1 | Rx=Rx- (Rs.h[1] * Rt.h[1])<<1;
Copy to clipboard | | Rx-=mpy(Rs.H,Rt.L) | Rx=Rx- (Rs.h[1] * Rt.h[0]);
Copy to clipboard | | Rx-=mpy(Rs.H,Rt.L):<<1 | Rx=Rx- (Rs.h[1] * Rt.h[0])<<1;
Copy to clipboard | | Rx-=mpy(Rs.L,Rt.H) | Rx=Rx- (Rs.h[0] * Rt.h[1]);
Copy to clipboard | | Rx-=mpy(Rs.L,Rt.H):<<1 | Rx=Rx- (Rs.h[0] * Rt.h[1])<<1;
Copy to clipboard | | Rx-=mpy(Rs.L,Rt.L) | Rx=Rx- (Rs.h[0] * Rt.h[0]);
Copy to clipboard | | Rx-=mpy(Rs.L,Rt.L):<<1 | Rx=Rx- (Rs.h[0] * Rt.h[0])<<1;
Copy to clipboard | | Rx+=mpy(Rs.H,Rt.H):sat | Rx=sat_32(Rx+ (Rs.h[1] * Rt.h[1]));
Copy to clipboard | | Rx+=mpy(Rs.H,Rt.H):<<1:sat | Rx=sat_32(Rx+ (Rs.h[1] * Rt.h[1])<<1);
Copy to clipboard | | Rx+=mpy(Rs.H,Rt.L):sat | Rx=sat_32(Rx+ (Rs.h[1] * Rt.h[0]));
Copy to clipboard | | Rx+=mpy(Rs.H,Rt.L):<<1:sat | Rx=sat_32(Rx+ (Rs.h[1] * Rt.h[0])<<1);
Copy to clipboard | | Rx+=mpy(Rs.L,Rt.H):sat | Rx=sat_32(Rx+ (Rs.h[0] * Rt.h[1]));
Copy to clipboard | | Rx+=mpy(Rs.L,Rt.H):<<1:sat | Rx=sat_32(Rx+ (Rs.h[0] * Rt.h[1])<<1);
Copy to clipboard | | Rx+=mpy(Rs.L,Rt.L):sat | Rx=sat_32(Rx+ (Rs.h[0] * Rt.h[0]));
Copy to clipboard | | Rx+=mpy(Rs.L,Rt.L):<<1:sat | Rx=sat_32(Rx+ (Rs.h[0] * Rt.h[0])<<1);
Copy to clipboard | | Rx-=mpy(Rs.H,Rt.H):sat | Rx=sat_32(Rx- (Rs.h[1] * Rt.h[1]));
Copy to clipboard | | Rx-=mpy(Rs.H,Rt.H):<<1:sat | Rx=sat_32(Rx- (Rs.h[1] * Rt.h[1])<<1);
Copy to clipboard | | Rx-=mpy(Rs.H,Rt.L):sat | Rx=sat_32(Rx- (Rs.h[1] * Rt.h[0]));
Copy to clipboard | | Rx-=mpy(Rs.H,Rt.L):<<1:sat | Rx=sat_32(Rx- (Rs.h[1] * Rt.h[0])<<1);
Copy to clipboard | | Rx-=mpy(Rs.L,Rt.H):sat | Rx=sat_32(Rx- (Rs.h[0] * Rt.h[1]));
Copy to clipboard | | Rx-=mpy(Rs.L,Rt.H):<<1:sat | Rx=sat_32(Rx- (Rs.h[0] * Rt.h[1])<<1);
Copy to clipboard | | Rx-=mpy(Rs.L,Rt.L):sat | Rx=sat_32(Rx- (Rs.h[0] * Rt.h[0]));
Copy to clipboard | | Rx-=mpy(Rs.L,Rt.L):<<1:sat | Rx=sat_32(Rx- (Rs.h[0] * Rt.h[0])<<1);
Copy to clipboard | | Rd=mpy(Rs.H,Rt.H) | Rd=(Rs.h[1] * Rt.h[1]);
Copy to clipboard | | Rd=mpy(Rs.H,Rt.H):<<1 | Rd=(Rs.h[1] * Rt.h[1])<<1;
Copy to clipboard | | Rd=mpy(Rs.H,Rt.L) | Rd=(Rs.h[1] * Rt.h[0]);
Copy to clipboard | | Rd=mpy(Rs.H,Rt.L):<<1 | Rd=(Rs.h[1] * Rt.h[0])<<1;
Copy to clipboard | | Rd=mpy(Rs.L,Rt.H) | Rd=(Rs.h[0] * Rt.h[1]);
Copy to clipboard | | Rd=mpy(Rs.L,Rt.H):<<1 | Rd=(Rs.h[0] * Rt.h[1])<<1;
Copy to clipboard | | Rd=mpy(Rs.L,Rt.L) | Rd=(Rs.h[0] * Rt.h[0]);
Copy to clipboard | | Rd=mpy(Rs.L,Rt.L):<<1 | Rd=(Rs.h[0] * Rt.h[0])<<1;
Copy to clipboard | | Rd=mpy(Rs.H,Rt.H):sat | Rd=sat_32((Rs.h[1] * Rt.h[1]));
Copy to clipboard | | Rd=mpy(Rs.H,Rt.H):<<1:sat | Rd=sat_32((Rs.h[1] * Rt.h[1])<<1);
Copy to clipboard | | Rd=mpy(Rs.H,Rt.L):sat | Rd=sat_32((Rs.h[1] * Rt.h[0]));
Copy to clipboard | | Rd=mpy(Rs.H,Rt.L):<<1:sat | Rd=sat_32((Rs.h[1] * Rt.h[0])<<1);
Copy to clipboard | | Rd=mpy(Rs.L,Rt.H):sat | Rd=sat_32((Rs.h[0] * Rt.h[1]));
Copy to clipboard | | Rd=mpy(Rs.L,Rt.H):<<1:sat | Rd=sat_32((Rs.h[0] * Rt.h[1])<<1);
Copy to clipboard | | Rd=mpy(Rs.L,Rt.L):sat | Rd=sat_32((Rs.h[0] * Rt.h[0]));
Copy to clipboard | | Rd=mpy(Rs.L,Rt.L):<<1:sat | Rd=sat_32((Rs.h[0] * Rt.h[0])<<1);
Copy to clipboard | | Rd=mpy(Rs.H,Rt.H):rnd | Rd=round((Rs.h[1] * Rt.h[1]));
Copy to clipboard | | Rd=mpy(Rs.H,Rt.H):<<1:rnd | Rd=round((Rs.h[1] * Rt.h[1])<<1);
Copy to clipboard | | Rd=mpy(Rs.H,Rt.L):rnd | Rd=round((Rs.h[1] * Rt.h[0]));
Copy to clipboard | | Rd=mpy(Rs.H,Rt.L):<<1:rnd | Rd=round((Rs.h[1] * Rt.h[0])<<1);
Copy to clipboard | | Rd=mpy(Rs.L,Rt.H):rnd | Rd=round((Rs.h[0] * Rt.h[1]));
Copy to clipboard | | Rd=mpy(Rs.L,Rt.H):<<1:rnd | Rd=round((Rs.h[0] * Rt.h[1])<<1);
Copy to clipboard | | Rd=mpy(Rs.L,Rt.L):rnd | Rd=round((Rs.h[0] * Rt.h[0]));
Copy to clipboard | | Rd=mpy(Rs.L,Rt.L):<<1:rnd | Rd=round((Rs.h[0] * Rt.h[0])<<1);
Copy to clipboard | | Rd=mpy(Rs.H,Rt.H):rnd:sat | Rd=sat_32(round((Rs.h[1] * Rt.h[1])));
Copy to clipboard | | Rd=mpy(Rs.H,Rt.H):<<1:rnd:sat | Rd=sat_32(round((Rs.h[1] * Rt.h[1])<<1));
Copy to clipboard | | Rd=mpy(Rs.H,Rt.L):rnd:sat | Rd=sat_32(round((Rs.h[1] * Rt.h[0])));
Copy to clipboard | | Rd=mpy(Rs.H,Rt.L):<<1:rnd:sat | Rd=sat_32(round((Rs.h[1] * Rt.h[0])<<1));
Copy to clipboard | | Rd=mpy(Rs.L,Rt.H):rnd:sat | Rd=sat_32(round((Rs.h[0] * Rt.h[1])));
Copy to clipboard | | Rd=mpy(Rs.L,Rt.H):<<1:rnd:sat | Rd=sat_32(round((Rs.h[0] * Rt.h[1])<<1));
Copy to clipboard | | Rd=mpy(Rs.L,Rt.L):rnd:sat | Rd=sat_32(round((Rs.h[0] * Rt.h[0])));
Copy to clipboard | | Rd=mpy(Rs.L,Rt.L):<<1:rnd:sat | Rd=sat_32(round((Rs.h[0] * Rt.h[0])<<1));
Copy to clipboard | | Rxx+=mpy(Rs.H,Rt.H) | Rxx=Rxx+ (Rs.h[1] * Rt.h[1]);
Copy to clipboard | | Rxx+=mpy(Rs.H,Rt.H):<<1 | Rxx=Rxx+ (Rs.h[1] * Rt.h[1])<<1;
Copy to clipboard | | Rxx+=mpy(Rs.H,Rt.L) | Rxx=Rxx+ (Rs.h[1] * Rt.h[0]);
Copy to clipboard | | Rxx+=mpy(Rs.H,Rt.L):<<1 | Rxx=Rxx+ (Rs.h[1] * Rt.h[0])<<1;
Copy to clipboard | | Rxx+=mpy(Rs.L,Rt.H) | Rxx=Rxx+ (Rs.h[0] * Rt.h[1]);
Copy to clipboard | | Rxx+=mpy(Rs.L,Rt.H):<<1 | Rxx=Rxx+ (Rs.h[0] * Rt.h[1])<<1;
Copy to clipboard | | Rxx+=mpy(Rs.L,Rt.L) | Rxx=Rxx+ (Rs.h[0] * Rt.h[0]);
Copy to clipboard | | Rxx+=mpy(Rs.L,Rt.L):<<1 | Rxx=Rxx+ (Rs.h[0] * Rt.h[0])<<1;
Copy to clipboard | | Rxx-=mpy(Rs.H,Rt.H) | Rxx=Rxx- (Rs.h[1] * Rt.h[1]);
Copy to clipboard | | Rxx-=mpy(Rs.H,Rt.H):<<1 | Rxx=Rxx- (Rs.h[1] * Rt.h[1])<<1;
Copy to clipboard | | Rxx-=mpy(Rs.H,Rt.L) | Rxx=Rxx- (Rs.h[1] * Rt.h[0]);
Copy to clipboard | | Rxx-=mpy(Rs.H,Rt.L):<<1 | Rxx=Rxx- (Rs.h[1] * Rt.h[0])<<1;
Copy to clipboard | | Rxx-=mpy(Rs.L,Rt.H) | Rxx=Rxx- (Rs.h[0] * Rt.h[1]);
Copy to clipboard | | Rxx-=mpy(Rs.L,Rt.H):<<1 | Rxx=Rxx- (Rs.h[0] * Rt.h[1])<<1;
Copy to clipboard | | Rxx-=mpy(Rs.L,Rt.L) | Rxx=Rxx- (Rs.h[0] * Rt.h[0]);
Copy to clipboard | | Rxx-=mpy(Rs.L,Rt.L):<<1 | Rxx=Rxx- (Rs.h[0] * Rt.h[0])<<1;
Copy to clipboard | | Rdd=mpy(Rs.H,Rt.H) | Rdd=(Rs.h[1] * Rt.h[1]);
Copy to clipboard | | Rdd=mpy(Rs.H,Rt.H):<<1 | Rdd=(Rs.h[1] * Rt.h[1])<<1;
Copy to clipboard | | Rdd=mpy(Rs.H,Rt.L) | Rdd=(Rs.h[1] * Rt.h[0]);
Copy to clipboard | | Rdd=mpy(Rs.H,Rt.L):<<1 | Rdd=(Rs.h[1] * Rt.h[0])<<1;
Copy to clipboard | | Rdd=mpy(Rs.L,Rt.H) | Rdd=(Rs.h[0] * Rt.h[1]);
Copy to clipboard | | Rdd=mpy(Rs.L,Rt.H):<<1 | Rdd=(Rs.h[0] * Rt.h[1])<<1;
Copy to clipboard | | Rdd=mpy(Rs.L,Rt.L) | Rdd=(Rs.h[0] * Rt.h[0]);
Copy to clipboard | | Rdd=mpy(Rs.L,Rt.L):<<1 | Rdd=(Rs.h[0] * Rt.h[0])<<1;
Copy to clipboard | | Rdd=mpy(Rs.H,Rt.H):rnd | Rdd=round((Rs.h[1] * Rt.h[1]));
Copy to clipboard | | Rdd=mpy(Rs.H,Rt.H):<<1:rnd | Rdd=round((Rs.h[1] * Rt.h[1])<<1);
Copy to clipboard | | Rdd=mpy(Rs.H,Rt.L):rnd | Rdd=round((Rs.h[1] * Rt.h[0]));
Copy to clipboard | | Rdd=mpy(Rs.H,Rt.L):<<1:rnd | Rdd=round((Rs.h[1] * Rt.h[0])<<1);
Copy to clipboard | | Rdd=mpy(Rs.L,Rt.H):rnd | Rdd=round((Rs.h[0] * Rt.h[1]));
Copy to clipboard | | Rdd=mpy(Rs.L,Rt.H):<<1:rnd | Rdd=round((Rs.h[0] * Rt.h[1])<<1);
Copy to clipboard | | Rdd=mpy(Rs.L,Rt.L):rnd | Rdd=round((Rs.h[0] * Rt.h[0]));
Copy to clipboard | | Rdd=mpy(Rs.L,Rt.L):<<1:rnd | Rdd=round((Rs.h[0] * Rt.h[0])<<1);
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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30

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0

Rx+=mpy(Rs.H,Rt.H)

1

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0

1

1

1

0

0

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0

s

s

s

s

s

P

P

-

t

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t

t

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1

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x

Rx+=mpy(Rs.H,Rt.H):<<1

1

1

1

0

1

1

1

0

1

0

0

s

s

s

s

s

P

P

-

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t

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t

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1

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x

Rx+=mpy(Rs.H,Rt.L)

1

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0

1

1

1

0

0

0

0

s

s

s

s

s

P

P

-

t

t

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t

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x

Rx+=mpy(Rs.H,Rt.L):<<1

1

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0

1

1

1

0

1

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0

s

s

s

s

s

P

P

-

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Rx+=mpy(Rs.L,Rt.H)

1

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0

1

1

1

0

0

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0

s

s

s

s

s

P

P

-

t

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x

x

x

x

x

Rx+=mpy(Rs.L,Rt.H):<<1

1

1

1

0

1

1

1

0

1

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

1

x

x

x

x

x

Rx+=mpy(Rs.L,Rt.L)

1

1

1

0

1

1

1

0

0

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

0

x

x

x

x

x

Rx+=mpy(Rs.L,Rt.L):<<1

1

1

1

0

1

1

1

0

1

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

0

x

x

x

x

x

Rx-=mpy(Rs.H,Rt.H)

1

1

1

0

1

1

1

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

1

1

x

x

x

x

x

Rx-=mpy(Rs.H,Rt.H):<<1

1

1

1

0

1

1

1

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

1

1

x

x

x

x

x

Rx-=mpy(Rs.H,Rt.L)

1

1

1

0

1

1

1

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

1

0

x

x

x

x

x

Rx-=mpy(Rs.H,Rt.L):<<1

1

1

1

0

1

1

1

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

1

0

x

x

x

x

x

Rx-=mpy(Rs.L,Rt.H)

1

1

1

0

1

1

1

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

1

x

x

x

x

x

Rx-=mpy(Rs.L,Rt.H):<<1

1

1

1

0

1

1

1

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

1

x

x

x

x

x

Rx-=mpy(Rs.L,Rt.L)

1

1

1

0

1

1

1

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

0

x

x

x

x

x

Rx-=mpy(Rs.L,Rt.L):<<1

1

1

1

0

1

1

1

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

0

x

x

x

x

x

Rx+=mpy(Rs.H,Rt.H):sat

1

1

1

0

1

1

1

0

0

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

1

1

1

x

x

x

x

x

Rx+=mpy(Rs.H,Rt.H):<<1:sat

1

1

1

0

1

1

1

0

1

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

1

1

1

x

x

x

x

x

Rx+=mpy(Rs.H,Rt.L):sat

1

1

1

0

1

1

1

0

0

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

1

1

0

x

x

x

x

x

Rx+=mpy(Rs.H,Rt.L):<<1:sat

1

1

1

0

1

1

1

0

1

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

1

1

0

x

x

x

x

x

Rx+=mpy(Rs.L,Rt.H):sat

1

1

1

0

1

1

1

0

0

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

1

0

1

x

x

x

x

x

Rx+=mpy(Rs.L,Rt.H):<<1:sat

1

1

1

0

1

1

1

0

1

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

1

0

1

x

x

x

x

x

Rx+=mpy(Rs.L,Rt.L):sat

1

1

1

0

1

1

1

0

0

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

1

0

0

x

x

x

x

x

Rx+=mpy(Rs.L,Rt.L):<<1:sat

1

1

1

0

1

1

1

0

1

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

1

0

0

x

x

x

x

x

Rx-=mpy(Rs.H,Rt.H):sat

1

1

1

0

1

1

1

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

1

1

1

x

x

x

x

x

Rx-=mpy(Rs.H,Rt.H):<<1:sat

1

1

1

0

1

1

1

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

1

1

1

x

x

x

x

x

Rx-=mpy(Rs.H,Rt.L):sat

1

1

1

0

1

1

1

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

1

1

0

x

x

x

x

x

Rx-=mpy(Rs.H,Rt.L):<<1:sat

1

1

1

0

1

1

1

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

1

1

0

x

x

x

x

x

Rx-=mpy(Rs.L,Rt.H):sat

1

1

1

0

1

1

1

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

1

0

1

x

x

x

x

x

Rx-=mpy(Rs.L,Rt.H):<<1:sat

1

1

1

0

1

1

1

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

1

0

1

x

x

x

x

x

Rx-=mpy(Rs.L,Rt.L):sat

1

1

1

0

1

1

1

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

1

0

0

x

x

x

x

x

Rx-=mpy(Rs.L,Rt.L):<<1:sat

1

1

1

0

1

1

1

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

1

0

0

x

x

x

x

x

Rd=mpy(Rs.H,Rt.H)

1

1

1

0

1

1

0

0

0

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

0

1

1

d

d

d

d

d

Rd=mpy(Rs.H,Rt.H):<<1

1

1

1

0

1

1

0

0

1

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

0

1

1

d

d

d

d

d

Rd=mpy(Rs.H,Rt.L)

1

1

1

0

1

1

0

0

0

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

0

1

0

d

d

d

d

d

Rd=mpy(Rs.H,Rt.L):<<1

1

1

1

0

1

1

0

0

1

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

0

1

0

d

d

d

d

d

Rd=mpy(Rs.L,Rt.H)

1

1

1

0

1

1

0

0

0

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

1

d

d

d

d

d

Rd=mpy(Rs.L,Rt.H):<<1

1

1

1

0

1

1

0

0

1

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

1

d

d

d

d

d

Rd=mpy(Rs.L,Rt.L)

1

1

1

0

1

1

0

0

0

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

0

d

d

d

d

d

Rd=mpy(Rs.L,Rt.L):<<1

1

1

1

0

1

1

0

0

1

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

0

d

d

d

d

d

Rd=mpy(Rs.H,Rt.H):sat

1

1

1

0

1

1

0

0

0

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

1

1

1

d

d

d

d

d

Rd=mpy(Rs.H,Rt.H):<<1:sat

1

1

1

0

1

1

0

0

1

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

1

1

1

d

d

d

d

d

Rd=mpy(Rs.H,Rt.L):sat

1

1

1

0

1

1

0

0

0

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

1

1

0

d

d

d

d

d

Rd=mpy(Rs.H,Rt.L):<<1:sat

1

1

1

0

1

1

0

0

1

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

1

1

0

d

d

d

d

d

Rd=mpy(Rs.L,Rt.H):sat

1

1

1

0

1

1

0

0

0

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

1

0

1

d

d

d

d

d

Rd=mpy(Rs.L,Rt.H):<<1:sat

1

1

1

0

1

1

0

0

1

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

1

0

1

d

d

d

d

d

Rd=mpy(Rs.L,Rt.L):sat

1

1

1

0

1

1

0

0

0

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

1

0

0

d

d

d

d

d

Rd=mpy(Rs.L,Rt.L):<<1:sat

1

1

1

0

1

1

0

0

1

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

1

0

0

d

d

d

d

d

Rd=mpy(Rs.H,Rt.H):rnd

1

1

1

0

1

1

0

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

1

1

d

d

d

d

d

Rd=mpy(Rs.H,Rt.H):<<1:rnd

1

1

1

0

1

1

0

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

1

1

d

d

d

d

d

Rd=mpy(Rs.H,Rt.L):rnd

1

1

1

0

1

1

0

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

1

0

d

d

d

d

d

Rd=mpy(Rs.H,Rt.L):<<1:rnd

1

1

1

0

1

1

0

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

1

0

d

d

d

d

d

Rd=mpy(Rs.L,Rt.H):rnd

1

1

1

0

1

1

0

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

1

d

d

d

d

d

Rd=mpy(Rs.L,Rt.H):<<1:rnd

1

1

1

0

1

1

0

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

1

d

d

d

d

d

Rd=mpy(Rs.L,Rt.L):rnd

1

1

1

0

1

1

0

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

0

d

d

d

d

d

Rd=mpy(Rs.L,Rt.L):<<1:rnd

1

1

1

0

1

1

0

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

0

d

d

d

d

d

Rd=mpy(Rs.H,Rt.H):rnd:sat

1

1

1

0

1

1

0

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

1

1

1

d

d

d

d

d

Rd=mpy(Rs.H,Rt.H):<<1:rnd:sat

1

1

1

0

1

1

0

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

1

1

1

d

d

d

d

d

Rd=mpy(Rs.H,Rt.L):rnd:sat

1

1

1

0

1

1

0

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

1

1

0

d

d

d

d

d

Rd=mpy(Rs.H,Rt.L):<<1:rnd:sat

1

1

1

0

1

1

0

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

1

1

0

d

d

d

d

d

Rd=mpy(Rs.L,Rt.H):rnd:sat

1

1

1

0

1

1

0

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

1

0

1

d

d

d

d

d

Rd=mpy(Rs.L,Rt.H):<<1:rnd:sat

1

1

1

0

1

1

0

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

1

0

1

d

d

d

d

d

Rd=mpy(Rs.L,Rt.L):rnd:sat

1

1

1

0

1

1

0

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

1

0

0

d

d

d

d

d

Rd=mpy(Rs.L,Rt.L):<<1:rnd:sat

1

1

1

0

1

1

0

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

1

0

0

d

d

d

d

d

Rxx+=mpy(Rs.H,Rt.H)

1

1

1

0

0

1

1

0

0

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

0

1

1

x

x

x

x

x

Rxx+=mpy(Rs.H,Rt.H):<<1

1

1

1

0

0

1

1

0

1

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

0

1

1

x

x

x

x

x

Rxx+=mpy(Rs.H,Rt.L)

1

1

1

0

0

1

1

0

0

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

0

1

0

x

x

x

x

x

Rxx+=mpy(Rs.H,Rt.L):<<1

1

1

1

0

0

1

1

0

1

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

0

1

0

x

x

x

x

x

Rxx+=mpy(Rs.L,Rt.H)

1

1

1

0

0

1

1

0

0

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

1

x

x

x

x

x

Rxx+=mpy(Rs.L,Rt.H):<<1

1

1

1

0

0

1

1

0

1

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

1

x

x

x

x

x

Rxx+=mpy(Rs.L,Rt.L)

1

1

1

0

0

1

1

0

0

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

0

x

x

x

x

x

Rxx+=mpy(Rs.L,Rt.L):<<1

1

1

1

0

0

1

1

0

1

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

0

x

x

x

x

x

Rxx-=mpy(Rs.H,Rt.H)

1

1

1

0

0

1

1

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

1

1

x

x

x

x

x

Rxx-=mpy(Rs.H,Rt.H):<<1

1

1

1

0

0

1

1

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

1

1

x

x

x

x

x

Rxx-=mpy(Rs.H,Rt.L)

1

1

1

0

0

1

1

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

1

0

x

x

x

x

x

Rxx-=mpy(Rs.H,Rt.L):<<1

1

1

1

0

0

1

1

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

1

0

x

x

x

x

x

Rxx-=mpy(Rs.L,Rt.H)

1

1

1

0

0

1

1

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

1

x

x

x

x

x

Rxx-=mpy(Rs.L,Rt.H):<<1

1

1

1

0

0

1

1

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

1

x

x

x

x

x

Rxx-=mpy(Rs.L,Rt.L)

1

1

1

0

0

1

1

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

0

x

x

x

x

x

Rxx-=mpy(Rs.L,Rt.L):<<1

1

1

1

0

0

1

1

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

0

x

x

x

x

x

Rdd=mpy(Rs.H,Rt.H)

1

1

1

0

0

1

0

0

0

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

-

1

1

d

d

d

d

d

Rdd=mpy(Rs.H,Rt.H):<<1

1

1

1

0

0

1

0

0

1

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

-

1

1

d

d

d

d

d

Rdd=mpy(Rs.H,Rt.L)

1

1

1

0

0

1

0

0

0

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

-

1

0

d

d

d

d

d

Rdd=mpy(Rs.H,Rt.L):<<1

1

1

1

0

0

1

0

0

1

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

-

1

0

d

d

d

d

d

Rdd=mpy(Rs.L,Rt.H)

1

1

1

0

0

1

0

0

0

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

-

0

1

d

d

d

d

d

Rdd=mpy(Rs.L,Rt.H):<<1

1

1

1

0

0

1

0

0

1

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

-

0

1

d

d

d

d

d

Rdd=mpy(Rs.L,Rt.L)

1

1

1

0

0

1

0

0

0

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

-

0

0

d

d

d

d

d

Rdd=mpy(Rs.L,Rt.L):<<1

1

1

1

0

0

1

0

0

1

0

0

s

s

s

s

s

P

P

-

t

t

t

t

t

-

0

0

d

d

d

d

d

Rdd=mpy(Rs.H,Rt.H):rnd

1

1

1

0

0

1

0

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

-

1

1

d

d

d

d

d

Rdd=mpy(Rs.H,Rt.H):<<1:rnd

1

1

1

0

0

1

0

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

-

1

1

d

d

d

d

d

Rdd=mpy(Rs.H,Rt.L):rnd

1

1

1

0

0

1

0

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

-

1

0

d

d

d

d

d

Rdd=mpy(Rs.H,Rt.L):<<1:rnd

1

1

1

0

0

1

0

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

-

1

0

d

d

d

d

d

Rdd=mpy(Rs.L,Rt.H):rnd

1

1

1

0

0

1

0

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

-

0

1

d

d

d

d

d

Rdd=mpy(Rs.L,Rt.H):<<1:rnd

1

1

1

0

0

1

0

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

-

0

1

d

d

d

d

d

Rdd=mpy(Rs.L,Rt.L):rnd

1

1

1

0

0

1

0

0

0

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

-

0

0

d

d

d

d

d

Rdd=mpy(Rs.L,Rt.L):<<1:rnd

1

1

1

0

0

1

0

0

1

0

1

s

s

s

s

s

P

P

-

t

t

t

t

t

-

0

0

d

d

d

d

d
Intrinsics
Multiply signed halfwords intrinsics

Rx+=mpy(Rs.H,Rt.H)

Word32 Q6_R_mpyacc_RhRh(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=mpy(Rs.H,Rt.H):<<1

Word32 Q6_R_mpyacc_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=mpy(Rs.H,Rt.L)

Word32 Q6_R_mpyacc_RhRl(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=mpy(Rs.H,Rt.L):<<1

Word32 Q6_R_mpyacc_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=mpy(Rs.L,Rt.H)

Word32 Q6_R_mpyacc_RlRh(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=mpy(Rs.L,Rt.H):<<1

Word32 Q6_R_mpyacc_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=mpy(Rs.L,Rt.L)

Word32 Q6_R_mpyacc_RlRl(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=mpy(Rs.L,Rt.L):<<1

Word32 Q6_R_mpyacc_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpy(Rs.H,Rt.H)

Word32 Q6_R_mpynac_RhRh(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpy(Rs.H,Rt.H):<<1

Word32 Q6_R_mpynac_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpy(Rs.H,Rt.L)

Word32 Q6_R_mpynac_RhRl(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpy(Rs.H,Rt.L):<<1

Word32 Q6_R_mpynac_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpy(Rs.L,Rt.H)

Word32 Q6_R_mpynac_RlRh(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpy(Rs.L,Rt.H):<<1

Word32 Q6_R_mpynac_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpy(Rs.L,Rt.L)

Word32 Q6_R_mpynac_RlRl(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpy(Rs.L,Rt.L):<<1

Word32 Q6_R_mpynac_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=mpy(Rs.H,Rt.H):sat

Word32 Q6_R_mpyacc_RhRh_sat(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=mpy(Rs.H,Rt.H):<<1:sat

Word32 Q6_R_mpyacc_RhRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=mpy(Rs.H,Rt.L):sat

Word32 Q6_R_mpyacc_RhRl_sat(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=mpy(Rs.H,Rt.L):<<1:sat

Word32 Q6_R_mpyacc_RhRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=mpy(Rs.L,Rt.H):sat

Word32 Q6_R_mpyacc_RlRh_sat(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=mpy(Rs.L,Rt.H):<<1:sat

Word32 Q6_R_mpyacc_RlRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=mpy(Rs.L,Rt.L):sat

Word32 Q6_R_mpyacc_RlRl_sat(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=mpy(Rs.L,Rt.L):<<1:sat

Word32 Q6_R_mpyacc_RlRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpy(Rs.H,Rt.H):sat

Word32 Q6_R_mpynac_RhRh_sat(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpy(Rs.H,Rt.H):<<1:sat

Word32 Q6_R_mpynac_RhRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpy(Rs.H,Rt.L):sat

Word32 Q6_R_mpynac_RhRl_sat(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpy(Rs.H,Rt.L):<<1:sat

Word32 Q6_R_mpynac_RhRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpy(Rs.L,Rt.H):sat

Word32 Q6_R_mpynac_RlRh_sat(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpy(Rs.L,Rt.H):<<1:sat

Word32 Q6_R_mpynac_RlRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpy(Rs.L,Rt.L):sat

Word32 Q6_R_mpynac_RlRl_sat(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpy(Rs.L,Rt.L):<<1:sat

Word32 Q6_R_mpynac_RlRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)

Rd=mpy(Rs.H,Rt.H)

Word32 Q6_R_mpy_RhRh(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.H,Rt.H):<<1

Word32 Q6_R_mpy_RhRh_s1(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.H,Rt.L)

Word32 Q6_R_mpy_RhRl(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.H,Rt.L):<<1

Word32 Q6_R_mpy_RhRl_s1(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.L,Rt.H)

Word32 Q6_R_mpy_RlRh(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.L,Rt.H):<<1

Word32 Q6_R_mpy_RlRh_s1(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.L,Rt.L)

Word32 Q6_R_mpy_RlRl(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.L,Rt.L):<<1

Word32 Q6_R_mpy_RlRl_s1(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.H,Rt.H):sat

Word32 Q6_R_mpy_RhRh_sat(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.H,Rt.H):<<1:sat

Word32 Q6_R_mpy_RhRh_s1_sat(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.H,Rt.L):sat

Word32 Q6_R_mpy_RhRl_sat(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.H,Rt.L):<<1:sat

Word32 Q6_R_mpy_RhRl_s1_sat(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.L,Rt.H):sat

Word32 Q6_R_mpy_RlRh_sat(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.L,Rt.H):<<1:sat

Word32 Q6_R_mpy_RlRh_s1_sat(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.L,Rt.L):sat

Word32 Q6_R_mpy_RlRl_sat(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.L,Rt.L):<<1:sat

Word32 Q6_R_mpy_RlRl_s1_sat(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.H,Rt.H):rnd

Word32 Q6_R_mpy_RhRh_rnd(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.H,Rt.H):<<1:rnd

Word32 Q6_R_mpy_RhRh_s1_rnd(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.H,Rt.L):rnd

Word32 Q6_R_mpy_RhRl_rnd(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.H,Rt.L):<<1:rnd

Word32 Q6_R_mpy_RhRl_s1_rnd(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.L,Rt.H):rnd

Word32 Q6_R_mpy_RlRh_rnd(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.L,Rt.H):<<1:rnd

Word32 Q6_R_mpy_RlRh_s1_rnd(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.L,Rt.L):rnd

Word32 Q6_R_mpy_RlRl_rnd(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.L,Rt.L):<<1:rnd

Word32 Q6_R_mpy_RlRl_s1_rnd(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.H,Rt.H):rnd:sat

Word32 Q6_R_mpy_RhRh_rnd_sat(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.H,Rt.H):<<1:rnd:sat

Word32 Q6_R_mpy_RhRh_s1_rnd_sat(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.H,Rt.L):rnd:sat

Word32 Q6_R_mpy_RhRl_rnd_sat(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.H,Rt.L):<<1:rnd:sat

Word32 Q6_R_mpy_RhRl_s1_rnd_sat(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.L,Rt.H):rnd:sat

Word32 Q6_R_mpy_RlRh_rnd_sat(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.L,Rt.H):<<1:rnd:sat

Word32 Q6_R_mpy_RlRh_s1_rnd_sat(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.L,Rt.L):rnd:sat

Word32 Q6_R_mpy_RlRl_rnd_sat(Word32 Rs, Word32 Rt)

Rd=mpy(Rs.L,Rt.L):<<1:rnd:sat

Word32 Q6_R_mpy_RlRl_s1_rnd_sat(Word32 Rs, Word32 Rt)

Rxx+=mpy(Rs.H,Rt.H)

Word64 Q6_P_mpyacc_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx+=mpy(Rs.H,Rt.H):<<1

Word64 Q6_P_mpyacc_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx+=mpy(Rs.H,Rt.L)

Word64 Q6_P_mpyacc_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx+=mpy(Rs.H,Rt.L):<<1

Word64 Q6_P_mpyacc_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx+=mpy(Rs.L,Rt.H)

Word64 Q6_P_mpyacc_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx+=mpy(Rs.L,Rt.H):<<1

Word64 Q6_P_mpyacc_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx+=mpy(Rs.L,Rt.L)

Word64 Q6_P_mpyacc_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx+=mpy(Rs.L,Rt.L):<<1

Word64 Q6_P_mpyacc_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx-=mpy(Rs.H,Rt.H)

Word64 Q6_P_mpynac_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx-=mpy(Rs.H,Rt.H):<<1

Word64 Q6_P_mpynac_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx-=mpy(Rs.H,Rt.L)

Word64 Q6_P_mpynac_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx-=mpy(Rs.H,Rt.L):<<1

Word64 Q6_P_mpynac_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx-=mpy(Rs.L,Rt.H)

Word64 Q6_P_mpynac_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx-=mpy(Rs.L,Rt.H):<<1

Word64 Q6_P_mpynac_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx-=mpy(Rs.L,Rt.L)

Word64 Q6_P_mpynac_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx-=mpy(Rs.L,Rt.L):<<1

Word64 Q6_P_mpynac_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)

Rdd=mpy(Rs.H,Rt.H)

Word64 Q6_P_mpy_RhRh(Word32 Rs, Word32 Rt)

Rdd=mpy(Rs.H,Rt.H):<<1

Word64 Q6_P_mpy_RhRh_s1(Word32 Rs, Word32 Rt)

Rdd=mpy(Rs.H,Rt.L)

Word64 Q6_P_mpy_RhRl(Word32 Rs, Word32 Rt)

Rdd=mpy(Rs.H,Rt.L):<<1

Word64 Q6_P_mpy_RhRl_s1(Word32 Rs, Word32 Rt)

Rdd=mpy(Rs.L,Rt.H)

Word64 Q6_P_mpy_RlRh(Word32 Rs, Word32 Rt)

Rdd=mpy(Rs.L,Rt.H):<<1

Word64 Q6_P_mpy_RlRh_s1(Word32 Rs, Word32 Rt)

Rdd=mpy(Rs.L,Rt.L)

Word64 Q6_P_mpy_RlRl(Word32 Rs, Word32 Rt)

Rdd=mpy(Rs.L,Rt.L):<<1

Word64 Q6_P_mpy_RlRl_s1(Word32 Rs, Word32 Rt)

Rdd=mpy(Rs.H,Rt.H):rnd

Word64 Q6_P_mpy_RhRh_rnd(Word32 Rs, Word32 Rt)

Rdd=mpy(Rs.H,Rt.H):<<1:rnd

Word64 Q6_P_mpy_RhRh_s1_rnd(Word32 Rs, Word32 Rt)

Rdd=mpy(Rs.H,Rt.L):rnd

Word64 Q6_P_mpy_RhRl_rnd(Word32 Rs, Word32 Rt)

Rdd=mpy(Rs.H,Rt.L):<<1:rnd

Word64 Q6_P_mpy_RhRl_s1_rnd(Word32 Rs, Word32 Rt)

Rdd=mpy(Rs.L,Rt.H):rnd

Word64 Q6_P_mpy_RlRh_rnd(Word32 Rs, Word32 Rt)

Rdd=mpy(Rs.L,Rt.H):<<1:rnd

Word64 Q6_P_mpy_RlRh_s1_rnd(Word32 Rs, Word32 Rt)

Rdd=mpy(Rs.L,Rt.L):rnd

Word64 Q6_P_mpy_RlRl_rnd(Word32 Rs, Word32 Rt)

Rdd=mpy(Rs.L,Rt.L):<<1:rnd

Word64 Q6_P_mpy_RlRl_s1_rnd(Word32 Rs, Word32 Rt)
#### Multiply unsigned halfwords Multiply two unsigned halfwords. Scale the result by 0-3 bits. Optionally, add or subtract the result from the accumulator. pic_addh Page-1 Sheet.80 Sheet.1 Rs Rs Rectangle.3 Sheet.4 Rt Rt Rectangle.6 Sheet.8 Sheet.10 Sheet.19 Sheet.20 32 32 Rectangle.27 <<0-1 <<0-1 Sheet.22 Sheet.26 Rx Rx Sheet.24 Rx+=mpyu(Rs.[HL],Rt.[HL])[:<<1] Rx+=mpyu(Rs.[HL],Rt.[HL])[:<<1] Rectangle.2 Rounded rectangle.20 32-bit add/sub 32-bit add/sub Sheet.9 Sheet.13 Sheet.14 Rectangle.5 Rectangle.17 Rounded rectangle.23 mux mux Sheet.27 Sheet.28 Rounded rectangle.29 mux mux Rounded rectangle.11 16 × 16 16 × 16 Sheet.12 Sheet.30 Sheet.15 Sheet.25 Sheet.31 Rs Rs Rectangle.32 Sheet.33 Rt Rt Rectangle.34 Sheet.35 Sheet.36 Sheet.37 Sheet.38 32 32 Rectangle.39 <<0-1 <<0-1 Sheet.40 Sheet.41 Rxx Rxx Sheet.42 Rxx+=mpyu(Rs.[HL],Rt.[HL])[:<<1] Rxx+=mpyu(Rs.[HL],Rt.[HL])[:<<1] Rounded rectangle.44 64-bit add/sub 64-bit add/sub Sheet.45 Sheet.47 Rectangle.50 Rectangle.51 Rounded rectangle.52 mux mux Sheet.53 Sheet.54 Rounded rectangle.55 mux mux Rounded rectangle.56 16 × 16 16 × 16 Sheet.57 Sheet.58 Sheet.60 Rectangle.48 Rounded rectangle.43 mux mux Sheet.62 Sheet.63 Rd = mpyu(Rs.[HL],Rt.[HL])[:<<1] Rd = mpyu(Rs.[HL],Rt.[HL])[:<<1] Sheet.46 Rdd = mpyu(Rs.[HL],Rt.[HL])[:<<1] Rdd = mpyu(Rs.[HL],Rt.[HL])[:<<1] Sheet.70 Sheet.71 0x0 0x0 Sheet.72 Sheet.73 Rounded rectangle.74 mux mux Sheet.77 Sheet.78 Sheet.79 0x0 0x0 Sheet.16 Multiply unsigned halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rx+=mpyu(Rs.H,Rt.H) | Rx=Rx+ (Rs.uh[1] * Rt.uh[1]);
Copy to clipboard | | Rx+=mpyu(Rs.H,Rt.H):<<1 | Rx=Rx+ (Rs.uh[1] * Rt.uh[1])<<1;
Copy to clipboard | | Rx+=mpyu(Rs.H,Rt.L) | Rx=Rx+ (Rs.uh[1] * Rt.uh[0]);
Copy to clipboard | | Rx+=mpyu(Rs.H,Rt.L):<<1 | Rx=Rx+ (Rs.uh[1] * Rt.uh[0])<<1;
Copy to clipboard | | Rx+=mpyu(Rs.L,Rt.H) | Rx=Rx+ (Rs.uh[0] * Rt.uh[1]);
Copy to clipboard | | Rx+=mpyu(Rs.L,Rt.H):<<1 | Rx=Rx+ (Rs.uh[0] * Rt.uh[1])<<1;
Copy to clipboard | | Rx+=mpyu(Rs.L,Rt.L) | Rx=Rx+ (Rs.uh[0] * Rt.uh[0]);
Copy to clipboard | | Rx+=mpyu(Rs.L,Rt.L):<<1 | Rx=Rx+ (Rs.uh[0] * Rt.uh[0])<<1;
Copy to clipboard | | Rx-=mpyu(Rs.H,Rt.H) | Rx=Rx- (Rs.uh[1] * Rt.uh[1]);
Copy to clipboard | | Rx-=mpyu(Rs.H,Rt.H):<<1 | Rx=Rx- (Rs.uh[1] * Rt.uh[1])<<1;
Copy to clipboard | | Rx-=mpyu(Rs.H,Rt.L) | Rx=Rx- (Rs.uh[1] * Rt.uh[0]);
Copy to clipboard | | Rx-=mpyu(Rs.H,Rt.L):<<1 | Rx=Rx- (Rs.uh[1] * Rt.uh[0])<<1;
Copy to clipboard | | Rx-=mpyu(Rs.L,Rt.H) | Rx=Rx- (Rs.uh[0] * Rt.uh[1]);
Copy to clipboard | | Rx-=mpyu(Rs.L,Rt.H):<<1 | Rx=Rx- (Rs.uh[0] * Rt.uh[1])<<1;
Copy to clipboard | | Rx-=mpyu(Rs.L,Rt.L) | Rx=Rx- (Rs.uh[0] * Rt.uh[0]);
Copy to clipboard | | Rx-=mpyu(Rs.L,Rt.L):<<1 | Rx=Rx- (Rs.uh[0] * Rt.uh[0])<<1;
Copy to clipboard | | Rd=mpyu(Rs.H,Rt.H) | Rd=(Rs.uh[1] * Rt.uh[1]);
Copy to clipboard | | Rd=mpyu(Rs.H,Rt.H):<<1 | Rd=(Rs.uh[1] * Rt.uh[1])<<1;
Copy to clipboard | | Rd=mpyu(Rs.H,Rt.L) | Rd=(Rs.uh[1] * Rt.uh[0]);
Copy to clipboard | | Rd=mpyu(Rs.H,Rt.L):<<1 | Rd=(Rs.uh[1] * Rt.uh[0])<<1;
Copy to clipboard | | Rd=mpyu(Rs.L,Rt.H) | Rd=(Rs.uh[0] * Rt.uh[1]);
Copy to clipboard | | Rd=mpyu(Rs.L,Rt.H):<<1 | Rd=(Rs.uh[0] * Rt.uh[1])<<1;
Copy to clipboard | | Rd=mpyu(Rs.L,Rt.L) | Rd=(Rs.uh[0] * Rt.uh[0]);
Copy to clipboard | | Rd=mpyu(Rs.L,Rt.L):<<1 | Rd=(Rs.uh[0] * Rt.uh[0])<<1;
Copy to clipboard | | Rxx+=mpyu(Rs.H,Rt.H) | Rxx=Rxx+ (Rs.uh[1] * Rt.uh[1]);
Copy to clipboard | | Rxx+=mpyu(Rs.H,Rt.H):<<1 | Rxx=Rxx+ (Rs.uh[1] * Rt.uh[1])<<1;
Copy to clipboard | | Rxx+=mpyu(Rs.H,Rt.L) | Rxx=Rxx+ (Rs.uh[1] * Rt.uh[0]);
Copy to clipboard | | Rxx+=mpyu(Rs.H,Rt.L):<<1 | Rxx=Rxx+ (Rs.uh[1] * Rt.uh[0])<<1;
Copy to clipboard | | Rxx+=mpyu(Rs.L,Rt.H) | Rxx=Rxx+ (Rs.uh[0] * Rt.uh[1]);
Copy to clipboard | | Rxx+=mpyu(Rs.L,Rt.H):<<1 | Rxx=Rxx+ (Rs.uh[0] * Rt.uh[1])<<1;
Copy to clipboard | | Rxx+=mpyu(Rs.L,Rt.L) | Rxx=Rxx+ (Rs.uh[0] * Rt.uh[0]);
Copy to clipboard | | Rxx+=mpyu(Rs.L,Rt.L):<<1 | Rxx=Rxx+ (Rs.uh[0] * Rt.uh[0])<<1;
Copy to clipboard | | Rxx-=mpyu(Rs.H,Rt.H) | Rxx=Rxx- (Rs.uh[1] * Rt.uh[1]);
Copy to clipboard | | Rxx-=mpyu(Rs.H,Rt.H):<<1 | Rxx=Rxx- (Rs.uh[1] * Rt.uh[1])<<1;
Copy to clipboard | | Rxx-=mpyu(Rs.H,Rt.L) | Rxx=Rxx- (Rs.uh[1] * Rt.uh[0]);
Copy to clipboard | | Rxx-=mpyu(Rs.H,Rt.L):<<1 | Rxx=Rxx- (Rs.uh[1] * Rt.uh[0])<<1;
Copy to clipboard | | Rxx-=mpyu(Rs.L,Rt.H) | Rxx=Rxx- (Rs.uh[0] * Rt.uh[1]);
Copy to clipboard | | Rxx-=mpyu(Rs.L,Rt.H):<<1 | Rxx=Rxx- (Rs.uh[0] * Rt.uh[1])<<1;
Copy to clipboard | | Rxx-=mpyu(Rs.L,Rt.L) | Rxx=Rxx- (Rs.uh[0] * Rt.uh[0]);
Copy to clipboard | | Rxx-=mpyu(Rs.L,Rt.L):<<1 | Rxx=Rxx- (Rs.uh[0] * Rt.uh[0])<<1;
Copy to clipboard | | Rdd=mpyu(Rs.H,Rt.H) | Rdd=(Rs.uh[1] * Rt.uh[1]);
Copy to clipboard | | Rdd=mpyu(Rs.H,Rt.H):<<1 | Rdd=(Rs.uh[1] * Rt.uh[1])<<1;
Copy to clipboard | | Rdd=mpyu(Rs.H,Rt.L) | Rdd=(Rs.uh[1] * Rt.uh[0]);
Copy to clipboard | | Rdd=mpyu(Rs.H,Rt.L):<<1 | Rdd=(Rs.uh[1] * Rt.uh[0])<<1;
Copy to clipboard | | Rdd=mpyu(Rs.L,Rt.H) | Rdd=(Rs.uh[0] * Rt.uh[1]);
Copy to clipboard | | Rdd=mpyu(Rs.L,Rt.H):<<1 | Rdd=(Rs.uh[0] * Rt.uh[1])<<1;
Copy to clipboard | | Rdd=mpyu(Rs.L,Rt.L) | Rdd=(Rs.uh[0] * Rt.uh[0]);
Copy to clipboard | | Rdd=mpyu(Rs.L,Rt.L):<<1 | Rdd=(Rs.uh[0] * Rt.uh[0])<<1;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rx+=mpyu(Rs.H,Rt.H)

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Rx+=mpyu(Rs.H,Rt.H):<<1

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Rx+=mpyu(Rs.H,Rt.L)

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Rx+=mpyu(Rs.H,Rt.L):<<1

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P

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Rx+=mpyu(Rs.L,Rt.H)

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P

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Rx+=mpyu(Rs.L,Rt.H):<<1

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P

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Rx+=mpyu(Rs.L,Rt.L)

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P

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Rx+=mpyu(Rs.L,Rt.L):<<1

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Rx-=mpyu(Rs.H,Rt.H)

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Rx-=mpyu(Rs.H,Rt.H):<<1

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Rx-=mpyu(Rs.H,Rt.L)

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Rx-=mpyu(Rs.H,Rt.L):<<1

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Rx-=mpyu(Rs.L,Rt.H)

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Rx-=mpyu(Rs.L,Rt.H):<<1

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Rx-=mpyu(Rs.L,Rt.L)

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Rx-=mpyu(Rs.L,Rt.L):<<1

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Rd=mpyu(Rs.H,Rt.H)

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Rd=mpyu(Rs.H,Rt.H):<<1

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Rd=mpyu(Rs.H,Rt.L)

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Rd=mpyu(Rs.H,Rt.L):<<1

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Rd=mpyu(Rs.L,Rt.H)

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Rd=mpyu(Rs.L,Rt.H):<<1

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Rd=mpyu(Rs.L,Rt.L)

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Rd=mpyu(Rs.L,Rt.L):<<1

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Rxx+=mpyu(Rs.H,Rt.H)

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Rxx+=mpyu(Rs.H,Rt.H):<<1

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Rxx+=mpyu(Rs.H,Rt.L)

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Rxx+=mpyu(Rs.H,Rt.L):<<1

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Rxx+=mpyu(Rs.L,Rt.H)

1

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s

s

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P

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Rxx+=mpyu(Rs.L,Rt.H):<<1

1

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s

s

s

s

P

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x

Rxx+=mpyu(Rs.L,Rt.L)

1

1

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0

0

1

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0

0

1

0

s

s

s

s

s

P

P

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x

x

x

x

Rxx+=mpyu(Rs.L,Rt.L):<<1

1

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0

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P

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Rxx-=mpyu(Rs.H,Rt.H)

1

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s

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P

P

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x

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x

Rxx-=mpyu(Rs.H,Rt.H):<<1

1

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1

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s

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Rxx-=mpyu(Rs.H,Rt.L)

1

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x

x

Rxx-=mpyu(Rs.H,Rt.L):<<1

1

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1

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1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

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x

x

x

x

x

Rxx-=mpyu(Rs.L,Rt.H)

1

1

1

0

0

1

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0

1

1

s

s

s

s

s

P

P

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t

t

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0

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1

x

x

x

x

x

Rxx-=mpyu(Rs.L,Rt.H):<<1

1

1

1

0

0

1

1

0

1

1

1

s

s

s

s

s

P

P

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t

t

t

t

t

0

0

1

x

x

x

x

x

Rxx-=mpyu(Rs.L,Rt.L)

1

1

1

0

0

1

1

0

0

1

1

s

s

s

s

s

P

P

-

t

t

t

t

t

0

0

0

x

x

x

x

x

Rxx-=mpyu(Rs.L,Rt.L):<<1

1

1

1

0

0

1

1

0

1

1

1

s

s

s

s

s

P

P

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t

t

t

t

t

0

0

0

x

x

x

x

x

Rdd=mpyu(Rs.H,Rt.H)

1

1

1

0

0

1

0

0

0

1

0

s

s

s

s

s

P

P

-

t

t

t

t

t

-

1

1

d

d

d

d

d

Rdd=mpyu(Rs.H,Rt.H):<<1

1

1

1

0

0

1

0

0

1

1

0

s

s

s

s

s

P

P

-

t

t

t

t

t

-

1

1

d

d

d

d

d

Rdd=mpyu(Rs.H,Rt.L)

1

1

1

0

0

1

0

0

0

1

0

s

s

s

s

s

P

P

-

t

t

t

t

t

-

1

0

d

d

d

d

d

Rdd=mpyu(Rs.H,Rt.L):<<1

1

1

1

0

0

1

0

0

1

1

0

s

s

s

s

s

P

P

-

t

t

t

t

t

-

1

0

d

d

d

d

d

Rdd=mpyu(Rs.L,Rt.H)

1

1

1

0

0

1

0

0

0

1

0

s

s

s

s

s

P

P

-

t

t

t

t

t

-

0

1

d

d

d

d

d

Rdd=mpyu(Rs.L,Rt.H):<<1

1

1

1

0

0

1

0

0

1

1

0

s

s

s

s

s

P

P

-

t

t

t

t

t

-

0

1

d

d

d

d

d

Rdd=mpyu(Rs.L,Rt.L)

1

1

1

0

0

1

0

0

0

1

0

s

s

s

s

s

P

P

-

t

t

t

t

t

-

0

0

d

d

d

d

d

Rdd=mpyu(Rs.L,Rt.L):<<1

1

1

1

0

0

1

0

0

1

1

0

s

s

s

s

s

P

P

-

t

t

t

t

t

-

0

0

d

d

d

d

d
Intrinsics
Multiply unsigned halfwords intrinsics

Rx+=mpyu(Rs.H,Rt.H)

Word32 Q6_R_mpyuacc_RhRh(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=mpyu(Rs.H,Rt.H):<<1

Word32 Q6_R_mpyuacc_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=mpyu(Rs.H,Rt.L)

Word32 Q6_R_mpyuacc_RhRl(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=mpyu(Rs.H,Rt.L):<<1

Word32 Q6_R_mpyuacc_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=mpyu(Rs.L,Rt.H)

Word32 Q6_R_mpyuacc_RlRh(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=mpyu(Rs.L,Rt.H):<<1

Word32 Q6_R_mpyuacc_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=mpyu(Rs.L,Rt.L)

Word32 Q6_R_mpyuacc_RlRl(Word32 Rx, Word32 Rs, Word32 Rt)

Rx+=mpyu(Rs.L,Rt.L):<<1

Word32 Q6_R_mpyuacc_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpyu(Rs.H,Rt.H)

Word32 Q6_R_mpyunac_RhRh(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpyu(Rs.H,Rt.H):<<1

Word32 Q6_R_mpyunac_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpyu(Rs.H,Rt.L)

Word32 Q6_R_mpyunac_RhRl(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpyu(Rs.H,Rt.L):<<1

Word32 Q6_R_mpyunac_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpyu(Rs.L,Rt.H)

Word32 Q6_R_mpyunac_RlRh(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpyu(Rs.L,Rt.H):<<1

Word32 Q6_R_mpyunac_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpyu(Rs.L,Rt.L)

Word32 Q6_R_mpyunac_RlRl(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpyu(Rs.L,Rt.L):<<1

Word32 Q6_R_mpyunac_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)

Rd=mpyu(Rs.H,Rt.H)

UWord32 Q6_R_mpyu_RhRh(Word32 Rs, Word32 Rt)

Rd=mpyu(Rs.H,Rt.H):<<1

UWord32 Q6_R_mpyu_RhRh_s1(Word32 Rs, Word32 Rt)

Rd=mpyu(Rs.H,Rt.L)

UWord32 Q6_R_mpyu_RhRl(Word32 Rs, Word32 Rt)

Rd=mpyu(Rs.H,Rt.L):<<1

UWord32 Q6_R_mpyu_RhRl_s1(Word32 Rs, Word32 Rt)

Rd=mpyu(Rs.L,Rt.H)

UWord32 Q6_R_mpyu_RlRh(Word32 Rs, Word32 Rt)

Rd=mpyu(Rs.L,Rt.H):<<1

UWord32 Q6_R_mpyu_RlRh_s1(Word32 Rs, Word32 Rt)

Rd=mpyu(Rs.L,Rt.L)

UWord32 Q6_R_mpyu_RlRl(Word32 Rs, Word32 Rt)

Rd=mpyu(Rs.L,Rt.L):<<1

UWord32 Q6_R_mpyu_RlRl_s1(Word32 Rs, Word32 Rt)

Rxx+=mpyu(Rs.H,Rt.H)

Word64 Q6_P_mpyuacc_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx+=mpyu(Rs.H,Rt.H):<<1

Word64 Q6_P_mpyuacc_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx+=mpyu(Rs.H,Rt.L)

Word64 Q6_P_mpyuacc_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx+=mpyu(Rs.H,Rt.L):<<1

Word64 Q6_P_mpyuacc_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx+=mpyu(Rs.L,Rt.H)

Word64 Q6_P_mpyuacc_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx+=mpyu(Rs.L,Rt.H):<<1

Word64 Q6_P_mpyuacc_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx+=mpyu(Rs.L,Rt.L)

Word64 Q6_P_mpyuacc_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx+=mpyu(Rs.L,Rt.L):<<1

Word64 Q6_P_mpyuacc_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx-=mpyu(Rs.H,Rt.H)

Word64 Q6_P_mpyunac_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx-=mpyu(Rs.H,Rt.H):<<1

Word64 Q6_P_mpyunac_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx-=mpyu(Rs.H,Rt.L)

Word64 Q6_P_mpyunac_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx-=mpyu(Rs.H,Rt.L):<<1

Word64 Q6_P_mpyunac_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx-=mpyu(Rs.L,Rt.H)

Word64 Q6_P_mpyunac_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx-=mpyu(Rs.L,Rt.H):<<1

Word64 Q6_P_mpyunac_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx-=mpyu(Rs.L,Rt.L)

Word64 Q6_P_mpyunac_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx-=mpyu(Rs.L,Rt.L):<<1

Word64 Q6_P_mpyunac_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)

Rdd=mpyu(Rs.H,Rt.H)

UWord64 Q6_P_mpyu_RhRh(Word32 Rs, Word32 Rt)

Rdd=mpyu(Rs.H,Rt.H):<<1

UWord64 Q6_P_mpyu_RhRh_s1(Word32 Rs, Word32 Rt)

Rdd=mpyu(Rs.H,Rt.L)

UWord64 Q6_P_mpyu_RhRl(Word32 Rs, Word32 Rt)

Rdd=mpyu(Rs.H,Rt.L):<<1

UWord64 Q6_P_mpyu_RhRl_s1(Word32 Rs, Word32 Rt)

Rdd=mpyu(Rs.L,Rt.H)

UWord64 Q6_P_mpyu_RlRh(Word32 Rs, Word32 Rt)

Rdd=mpyu(Rs.L,Rt.H):<<1

UWord64 Q6_P_mpyu_RlRh_s1(Word32 Rs, Word32 Rt)

Rdd=mpyu(Rs.L,Rt.L)

UWord64 Q6_P_mpyu_RlRl(Word32 Rs, Word32 Rt)

Rdd=mpyu(Rs.L,Rt.L):<<1

UWord64 Q6_P_mpyu_RlRl_s1(Word32 Rs, Word32 Rt)
#### Polynomial multiply words Perform a 32x32 carryless polynomial multiply using 32-bit source registers Rs and Rt. The 64-bit result is optionally accumulated (XORed) with the destination register. Finite field multiply instructions are useful for many algorithms including scramble code generation, cryptographic algorithms, convolutional, and Reed Solomon codes. Page-1 Sheet.141 Rectangle Rectangle.2 Dynamic connector Sheet.7 Center drag circle Center drag circle.5 Sheet.4 * * Sheet.9 Rs Rs Sheet.10 Rt Rt Dynamic connector.8 Rectangle.11 Dynamic connector.12 Rounded rectangle XOR XOR Dynamic connector.14 Dynamic connector.15 Sheet.16 32 × 32 carryless polynomial mpy 32 × 32 carrylesspolynomial mpy Sheet.17 Rxx Rxx Sheet.140 Rxx += pmpyw(Rs,Rt) Rxx += pmpyw(Rs,Rt) Polynomial multiply words instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=pmpyw(Rs,Rt) | x = Rs.uw[0];
y = Rt.uw[0];
prod = 0;
for(i=0; i < 32; i++) {
if((y >> i) & 1) prod ^= (x << i);
}
Rdd = prod;
Copy to clipboard | | Rxx^=pmpyw(Rs,Rt) | x = Rs.uw[0];
y = Rt.uw[0];
prod = 0;
for(i=0; i < 32; i++) {
if((y >> i) & 1) prod ^= (x << i);
}
Rxx ^= prod;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rdd=pmpyw(Rs,Rt)

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Rxx^=pmpyw(Rs,Rt)

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Intrinsics
Polynomial multiply words intrinsics

Rdd=pmpyw(Rs,Rt)

Word64 Q6_P_pmpyw_RR(Word32 Rs, Word32 Rt)

Rxx^=pmpyw(Rs,Rt)

Word64 Q6_P_pmpywxacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
#### Vector reduce multiply word by signed half (32x16) Perform mixed precision vector multiply operations and accumulate the results. A 32-bit word from vector Rss is multiplied by a 16-bit halfword (either even or odd) from vector Rtt. The multiplication is performed as a signed 32x16, which produces a 48-bit result. This result is optionally scaled left by one bit. A similar operation is performed for both words in Rss, and the two results are accumulated. The final result is optionally accumulated with Rxx. pic_addh Page-1 Sheet.91 Sheet.33 Sheet.34 Sheet.40 Rectangle.47 s32 s32 Sheet.49 * * Sheet.50 Sheet.51 Sheet.52 48 48 Rectangle.36 <<0-1 <<0-1 Sheet.54 Sheet.73 Rxx Rxx Rectangle.19 s16 s16 Sheet.83 Sheet.3 Add Add Rectangle.4 Rectangle.7 s32 s32 Sheet.9 * * Sheet.10 Rectangle.24 s16 s16 Sheet.26 Sheet.2 Rss Rss Sheet.8 Rtt Rtt Sheet.90 Rectangle.1 s16 s16 Rectangle.18 s16 s16 Sheet.85 Sheet.27 Rounded rectangle mux mux Sheet.20 Rounded rectangle.22 mux mux Sheet.23 Sheet.25 Sheet.28 Sheet.11 Sheet.12 48 48 Rectangle.13 <<0-1 <<0-1 Sheet.14 Sheet.5 Sheet.6 Vector reduce multiply word by signed half (32x16) instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vrmpyweh(Rss,Rtt) | Rdd = (Rss.w[1] * Rtt.h[2])<<0 + (Rss.w[0] * Rtt.h[0])<<0;
Copy to clipboard | | Rdd=vrmpyweh(Rss,Rtt):<<1 | Rdd = (Rss.w[1] * Rtt.h[2])<<1 + (Rss.w[0] * Rtt.h[0])<<1;
Copy to clipboard | | Rxx+=vrmpyweh(Rss,Rtt) | Rxx += (Rss.w[1] * Rtt.h[2])<<0 + (Rss.w[0] * Rtt.h[0])<<0;
Copy to clipboard | | Rxx+=vrmpyweh(Rss,Rtt):<<1 | Rxx += (Rss.w[1] * Rtt.h[2])<<1 + (Rss.w[0] * Rtt.h[0])<<1;
Copy to clipboard | | Rdd=vrmpywoh(Rss,Rtt) | Rdd = (Rss.w[1] * Rtt.h[3])<<0 + (Rss.w[0] * Rtt.h[1])<<0;
Copy to clipboard | | Rdd=vrmpywoh(Rss,Rtt):<<1 | Rdd = (Rss.w[1] * Rtt.h[3])<<1 + (Rss.w[0] * Rtt.h[1])<<1;
Copy to clipboard | | Rxx+=vrmpywoh(Rss,Rtt) | Rxx += (Rss.w[1] * Rtt.h[3])<<0 + (Rss.w[0] * Rtt.h[1])<<0;
Copy to clipboard | | Rxx+=vrmpywoh(Rss,Rtt):<<1 | Rxx += (Rss.w[1] * Rtt.h[3])<<1 + (Rss.w[0] * Rtt.h[1])<<1;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rdd=vrmpyweh(Rss,Rtt)

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Rdd=vrmpyweh(Rss,Rtt):<<1

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Rxx+=vrmpyweh(Rss,Rtt)

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Rxx+=vrmpyweh(Rss,Rtt):<<1

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Rdd=vrmpywoh(Rss,Rtt)

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Rdd=vrmpywoh(Rss,Rtt):<<1

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Rxx+=vrmpywoh(Rss,Rtt)

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Rxx+=vrmpywoh(Rss,Rtt):<<1

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Intrinsics
Vector reduce multiply word by signed half (32x16) intrinsics

Rdd=vrmpyweh(Rss,Rtt)

Word64 Q6_P_vrmpyweh_PP(Word64 Rss, Word64 Rtt)

Rdd=vrmpyweh(Rss,Rtt):<<1

Word64 Q6_P_vrmpyweh_PP_s1(Word64 Rss, Word64 Rtt)

Rxx+=vrmpyweh(Rss,Rtt)

Word64 Q6_P_vrmpywehacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rxx+=vrmpyweh(Rss,Rtt):<<1

Word64 Q6_P_vrmpywehacc_PP_s1(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rdd=vrmpywoh(Rss,Rtt)

Word64 Q6_P_vrmpywoh_PP(Word64 Rss, Word64 Rtt)

Rdd=vrmpywoh(Rss,Rtt):<<1

Word64 Q6_P_vrmpywoh_PP_s1(Word64 Rss, Word64 Rtt)

Rxx+=vrmpywoh(Rss,Rtt)

Word64 Q6_P_vrmpywohacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rxx+=vrmpywoh(Rss,Rtt):<<1

Word64 Q6_P_vrmpywohacc_PP_s1(Word64 Rxx, Word64 Rss, Word64 Rtt)
#### Multiply and use upper result Multiply two signed or unsigned 32-bit words. Take the upper 32-bits of this results store to a single destination register. Optional rounding is available. pic_addh Page-1 Sheet.27 Sheet.1 Rs Rs Rectangle.3 Sheet.4 Rt Rt Rectangle.6 Sheet.8 Sheet.10 Sheet.11 32×32 32×32 Sheet.12 Sheet.19 Sheet.20 64 64 Sheet.22 Sheet.26 Rd Rd Sheet.15 Rectangle.21 Rectangle.23 Rectangle.2 Multiply and use upper result instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=mpy(Rs,Rt) | Rd=(Rs * Rt)>>32;
Copy to clipboard | | Rd=mpy(Rs,Rt):<<1 | Rd=(Rs * Rt)>>31;
Copy to clipboard | | Rd=mpy(Rs,Rt):<<1:sat | Rd=sat_32((Rs * Rt)>>31);
Copy to clipboard | | Rd=mpyu(Rs,Rt) | Rd=(Rs.uw[0] * Rt.uw[0])>>32;
Copy to clipboard | | Rd=mpysu(Rs,Rt) | Rd=(Rs * Rt.uw[0])>>32;
Copy to clipboard | | Rd=mpy(Rs,Rt):rnd | Rd=((Rs * Rt)+0x80000000)>>32;
Copy to clipboard | | Rx+=mpy(Rs,Rt):<<1:sat | Rx=sat_32((Rx) + ((Rs * Rt)>>31));
Copy to clipboard | | Rx-=mpy(Rs,Rt):<<1:sat | Rx=sat_32((Rx) - ((Rs * Rt)>>31));
Copy to clipboard | | Rd=mpy(Rs,Rt.L):<<1:rnd:sat | Rd = sat_32(((Rs * Rt.h[0])<<1+0x8000)>>16);
Copy to clipboard | | Rd=mpy(Rs,Rt.H):<<1:rnd:sat | Rd = sat_32(((Rs * Rt.h[1])<<1+0x8000)>>16);
Copy to clipboard | | Rd=mpy(Rs,Rt.L):<<1:sat | Rd = sat_32(((Rs * Rt.h[0])<<1)>>16);
Copy to clipboard | | Rd=mpy(Rs,Rt.H):<<1:sat | Rd = sat_32(((Rs * Rt.h[1])<<1)>>16);
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rd=mpy(Rs,Rt)

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Rd=mpy(Rs,Rt):<<1

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Rd=mpy(Rs,Rt):<<1:sat

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Rd=mpyu(Rs,Rt)

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Rd=mpysu(Rs,Rt)

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Rd=mpy(Rs,Rt):rnd

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Rx+=mpy(Rs,Rt):<<1:sat

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Rx-=mpy(Rs,Rt):<<1:sat

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Rd=mpy(Rs,Rt.L):<<1:rnd:sat

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Rd=mpy(Rs,Rt.H):<<1:rnd:sat

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Rd=mpy(Rs,Rt.L):<<1:sat

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Rd=mpy(Rs,Rt.H):<<1:sat

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Intrinsics
Multiply and use upper result intrinsics

Rd=mpy(Rs,Rt)

Word32 Q6_R_mpy_RR(Word32 Rs, Word32 Rt)

Rd=mpy(Rs,Rt):<<1

Word32 Q6_R_mpy_RR_s1(Word32 Rs, Word32 Rt)

Rd=mpy(Rs,Rt):<<1:sat

Word32 Q6_R_mpy_RR_s1_sat(Word32 Rs, Word32 Rt)

Rd=mpyu(Rs,Rt)

UWord32 Q6_R_mpyu_RR(Word32 Rs, Word32 Rt)

Rd=mpysu(Rs,Rt)

Word32 Q6_R_mpysu_RR(Word32 Rs, Word32 Rt)

Rd=mpy(Rs,Rt):rnd

Word32 Q6_R_mpy_RR_rnd(Word32 Rs, Word32 Rt)

Rx+=mpy(Rs,Rt):<<1:sat

Word32 Q6_R_mpyacc_RR_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)

Rx-=mpy(Rs,Rt):<<1:sat

Word32 Q6_R_mpynac_RR_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)

Rd=mpy(Rs,Rt.L):<<1:rnd:sat

Word32 Q6_R_mpy_RRl_s1_rnd_sat(Word32 Rs, Word32 Rt)

Rd=mpy(Rs,Rt.H):<<1:rnd:sat

Word32 Q6_R_mpy_RRh_s1_rnd_sat(Word32 Rs, Word32 Rt)

Rd=mpy(Rs,Rt.L):<<1:sat

Word32 Q6_R_mpy_RRl_s1_sat(Word32 Rs, Word32 Rt)

Rd=mpy(Rs,Rt.H):<<1:sat

Word32 Q6_R_mpy_RRh_s1_sat(Word32 Rs, Word32 Rt)
#### Multiply and use full result Multiply two signed or unsigned 32-bit words. Optionally, add or subtract this value from the 64-bit accumulator. The result is a full-precision 64-bit value. pic_addh Page-1 Sheet.27 Sheet.1 Rs Rs Rectangle.3 Sheet.4 Rt Rt Rectangle.6 Sheet.8 Sheet.10 Sheet.11 32 × 32 32 × 32 Sheet.12 Sheet.19 Sheet.20 64 64 Sheet.22 Sheet.26 Rxx Rxx Rectangle.2 Rounded rectangle.20 64-bit add/sub 64-bit add/sub Sheet.9 Sheet.13 Sheet.14 Sheet.15 Multiply and use full result instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=mpy(Rs,Rt) | Rdd=(Rs * Rt);
Copy to clipboard | | Rxx+=mpy(Rs,Rt) | Rxx= Rxx + (Rs * Rt);
Copy to clipboard | | Rxx-=mpy(Rs,Rt) | Rxx= Rxx - (Rs * Rt);
Copy to clipboard | | Rdd=mpyu(Rs,Rt) | Rdd=(Rs.uw[0] * Rt.uw[0]);
Copy to clipboard | | Rxx+=mpyu(Rs,Rt) | Rxx= Rxx + (Rs.uw[0] * Rt.uw[0]);
Copy to clipboard | | Rxx-=mpyu(Rs,Rt) | Rxx= Rxx - (Rs.uw[0] * Rt.uw[0]);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rdd=mpy(Rs,Rt)

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Rxx+=mpy(Rs,Rt)

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Rxx-=mpy(Rs,Rt)

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Rdd=mpyu(Rs,Rt)

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Rxx+=mpyu(Rs,Rt)

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Rxx-=mpyu(Rs,Rt)

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Intrinsics
Multiply and use full result intrinsics

Rdd=mpy(Rs,Rt)

Word64 Q6_P_mpy_RR(Word32 Rs, Word32 Rt)

Rxx+=mpy(Rs,Rt)

Word64 Q6_P_mpyacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx-=mpy(Rs,Rt)

Word64 Q6_P_mpynac_RR(Word64 Rxx, Word32 Rs, Word32 Rt)

Rdd=mpyu(Rs,Rt)

UWord64 Q6_P_mpyu_RR(Word32 Rs, Word32 Rt)

Rxx+=mpyu(Rs,Rt)

Word64 Q6_P_mpyuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx-=mpyu(Rs,Rt)

Word64 Q6_P_mpyunac_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
#### Vector dual multiply Multiply four 16-bit halfwords in Rss by the corresponding 16-bit halfwords in Rtt. The two lower results are scaled and added. The lower word of the accumulator is optionally added. This result is saturated to 32-bits and stored in the lower word of the accumulator. The same operation is performed on the upper two products using the upper word of the accumulator. pic_addh Page-1 Sheet.91 Sheet.33 Sheet.34 Sheet.35 Add Add Rectangle High accumulation High accumulation Sheet.40 Sheet.41 Rectangle.43 Rectangle.47 Sheet.49 * * Sheet.50 Sheet.51 Sheet.52 32 32 Rectangle.36 <<0-1 <<0-1 Sheet.54 Sheet.55 * * Sheet.56 Sheet.57 Sheet.58 32 32 Rectangle.59 <<0-1 <<0-1 Sheet.60 Sheet.69 Sheet.70 Sheet.71 Sheet.72 32 32 Sheet.73 Rxx Rxx Rectangle.1 Rectangle.19 Sheet.82 Sheet.83 Sheet.84 Sheet.85 Sheet.1 Rxx+=vdmpy(Rss,Rtt):sat Rxx+=vdmpy(Rss,Rtt):sat Sheet.3 Add Add Rectangle.4 Low accumulation Low accumulation Sheet.5 Rectangle.6 Rectangle.7 Sheet.9 * * Sheet.10 Sheet.11 Sheet.12 32 32 Rectangle.13 <<0-1 <<0-1 Sheet.14 Sheet.15 * * Sheet.16 Sheet.17 Sheet.18 32 32 Rectangle.19 <<0-1 <<0-1 Sheet.20 Sheet.21 Sheet.22 Rectangle.23 Rectangle.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.2 Rss Rss Sheet.8 Rtt Rtt Sheet.29 Sheet.30 Sheet.32 32 32 Sheet.36 Sheet.37 Sheet.87 Sat_32 Sat_32 Sheet.88 Sat_32 Sat_32 Sheet.89 Sheet.90 Vector dual multiply instructions | **Syntax** | **Behavior** | | --- | --- | | Rxx+=vdmpy(Rss,Rtt):sat | Rxx.w[0]=sat_32(Rxx.w[0] + (Rss.h[0] * Rtt.h[0])<<0 + (Rss.h[1] * Rtt.h[1])<<0);
Rxx.w[1]=sat_32(Rxx.w[1] + (Rss.h[2] * Rtt.h[2])<<0 + (Rss.h[3] * Rtt.h[3])<<0);
Copy to clipboard | | Rxx+=vdmpy(Rss,Rtt):<<1:sat | Rxx.w[0]=sat_32(Rxx.w[0] + (Rss.h[0] * Rtt.h[0])<<1 + (Rss.h[1] * Rtt.h[1])<<1);
Rxx.w[1]=sat_32(Rxx.w[1] + (Rss.h[2] * Rtt.h[2])<<1 + (Rss.h[3] * Rtt.h[3])<<1);
Copy to clipboard | | Rdd=vdmpy(Rss,Rtt):sat | Rdd.w[0]=sat_32((Rss.h[0] * Rtt.h[0])<<0 + (Rss.h[1] * Rtt.h[1])<<0);
Rdd.w[1]=sat_32((Rss.h[2] * Rtt.h[2])<<0 + (Rss.h[3] * Rtt.h[3])<<0);
Copy to clipboard | | Rdd=vdmpy(Rss,Rtt):<<1:sat | Rdd.w[0]=sat_32((Rss.h[0] * Rtt.h[0])<<1 + (Rss.h[1] * Rtt.h[1])<<1);
Rdd.w[1]=sat_32((Rss.h[2] * Rtt.h[2])<<1 + (Rss.h[3] * Rtt.h[3])<<1);
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
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Rxx+=vdmpy(Rss,Rtt):sat

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Rxx+=vdmpy(Rss,Rtt):<<1:sat

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Rdd=vdmpy(Rss,Rtt):sat

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Rdd=vdmpy(Rss,Rtt):<<1:sat

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Intrinsics
Vector dual multiply intrinsics

Rxx+=vdmpy(Rss,Rtt):sat

Word64 Q6_P_vdmpyacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rxx+=vdmpy(Rss,Rtt):<<1:sat

Word64 Q6_P_vdmpyacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rdd=vdmpy(Rss,Rtt):sat

Word64 Q6_P_vdmpy_PP_sat(Word64 Rss, Word64 Rtt)

Rdd=vdmpy(Rss,Rtt):<<1:sat

Word64 Q6_P_vdmpy_PP_s1_sat(Word64 Rss, Word64 Rtt)
#### Vector dual multiply with round and pack Multiply four 16-bit halfwords in Rss by the corresponding 16-bit halfwords in Rtt. The two lower results are scaled and added together with a rounding constant. This result is saturated to 32-bits, and the upper 16-bits of this result are stored in the lower 16-bits of the destination register. The same operation is performed on the upper two products and the result is stored in the upper 16-bit halfword of the destination. pic_addh Page-1 Sheet.91 Sheet.35 Add Add Rectangle.43 Rectangle.47 Sheet.49 * * Sheet.50 Sheet.51 Sheet.52 32 32 Rectangle.36 <<0-1 <<0-1 Sheet.54 Sheet.55 * * Sheet.56 Sheet.57 Sheet.58 32 32 Rectangle.59 <<0-1 <<0-1 Sheet.60 Sheet.69 Sheet.70 Sheet.73 Rd Rd Rectangle.1 Rectangle.19 Sheet.82 Sheet.83 Sheet.84 Sheet.85 Sheet.1 Rd=vdmpy(Rss,Rtt):rnd:sat Rd=vdmpy(Rss,Rtt):rnd:sat Sheet.3 Add Add Sheet.5 Rectangle.6 Rectangle.7 Sheet.9 * * Sheet.10 Sheet.11 Sheet.12 32 32 Rectangle.13 <<0-1 <<0-1 Sheet.14 Sheet.15 * * Sheet.16 Sheet.17 Sheet.18 32 32 Rectangle.19 <<0-1 <<0-1 Sheet.20 Sheet.21 Sheet.22 Rectangle.23 Rectangle.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.2 Rss Rss Sheet.8 Rtt Rtt Sheet.87 Sheet.88 0x8000 0x8000 Sheet.89 0x8000 0x8000 Sheet.90 Sheet.29 Sat32 Sat32 Sheet.32 Sheet.37 Sat32 Sat32 Sheet.38 Sheet.40 High 16 bits High 16 bits Sheet.42 Sheet.45 High 16 bits High 16 bits Rectangle.30 Rectangle.36 Vector dual multiply with round and pack instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=vdmpy(Rss,Rtt):rnd:sat | Rd.h[0]=(sat_32((Rss.h[0] * Rtt.h[0])<<0 + (Rss.h[1] * Rtt.h[1])<<0 + 0x8000)).h[1];
Rd.h[1]=(sat_32((Rss.h[2] * Rtt.h[2])<<0 + (Rss.h[3] * Rtt.h[3])<<0 + 0x8000)).h[1];
Copy to clipboard | | Rd=vdmpy(Rss,Rtt):<<1:rnd:sat | Rd.h[0]=(sat_32((Rss.h[0] * Rtt.h[0])<<1 + (Rss.h[1] * Rtt.h[1])<<1 + 0x8000)).h[1];
Rd.h[1]=(sat_32((Rss.h[2] * Rtt.h[2])<<1 + (Rss.h[3] * Rtt.h[3])<<1 + 0x8000)).h[1];
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

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Rd=vdmpy(Rss,Rtt):rnd:sat

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Rd=vdmpy(Rss,Rtt):<<1:rnd:sat

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Intrinsics
Vector dual multiply with round and pack intrinsics

Rd=vdmpy(Rss,Rtt):rnd:sat

Word32 Q6_R_vdmpy_PP_rnd_sat(Word64 Rss, Word64 Rtt)

Rd=vdmpy(Rss,Rtt):<<1:rnd:sat

Word32 Q6_R_vdmpy_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
#### Vector reduce multiply bytes Multiply eight 8-bit bytes in Rss by the corresponding 8-bit bytes in Rtt. The four lower results are accumulated. The lower word of the accumulator is optionally added. This result is stored in the lower 32-bits of the accumulator. The same operation is performed on the upper four products using the upper word of the accumulator. The eight bytes of Rss can be treated as either signed or unsigned. pic_addh Page-1 Sheet.94 Sheet.33 Sheet.34 Sheet.35 Add Add Rectangle High accumulation High accumulation Sheet.40 Sheet.41 Rectangle.43 Sheet.49 * * Sheet.50 Sheet.51 Sheet.52 16 16 Sheet.54 Sheet.71 Sheet.72 32 32 Sheet.73 Rxx Rxx Sheet.82 Sheet.83 Sheet.84 Sheet.85 Rectangle.4 Low accumulation Low accumulation Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.2 Rss Rss Sheet.8 Rtt Rtt Sheet.29 Sheet.30 Sheet.32 32 32 Sheet.36 Sheet.37 Rectangle.6 Rectangle.7 Rectangle.13 Rectangle.19 Rectangle.21 Rectangle.22 Rectangle.23 Sheet.9 * * Sheet.10 Sheet.11 Sheet.12 16 16 Sheet.14 Sheet.15 * * Sheet.16 Sheet.17 Sheet.18 16 16 Sheet.20 Sheet.24 * * Sheet.31 Sheet.38 Sheet.42 16 16 Sheet.44 Sheet.3 Add Add Sheet.5 Rectangle.45 Sheet.46 * * Sheet.47 Sheet.48 Sheet.53 16 16 Sheet.55 Sheet.56 Sheet.57 Sheet.58 Sheet.59 Sheet.60 Sheet.61 Sheet.62 Sheet.63 Rectangle.64 Rectangle.65 Rectangle.66 Rectangle.67 Rectangle.68 Rectangle.69 Rectangle.70 Sheet.74 * * Sheet.75 Sheet.76 Sheet.77 16 16 Sheet.78 Sheet.79 * * Sheet.80 Sheet.81 Sheet.86 16 16 Sheet.87 Sheet.88 * * Sheet.89 Sheet.90 Sheet.91 16 16 Sheet.92 Vector reduce multiply bytes instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vrmpybu(Rss,Rtt) | Rdd.w[0]=((Rss.ub[0] * Rtt.ub[0]) + (Rss.ub[1] * Rtt.ub[1]) + (Rss.ub[2] * Rtt.ub[2]) + (Rss.ub[3] * Rtt.ub[3]));
Rdd.w[1]=((Rss.ub[4] * Rtt.ub[4]) + (Rss.ub[5] * Rtt.ub[5]) + (Rss.ub[6] * Rtt.ub[6]) + (Rss.ub[7] * Rtt.ub[7]));
Copy to clipboard | | Rxx+=vrmpybu(Rss,Rtt) | Rxx.w[0]=(Rxx.w[0] + (Rss.ub[0] * Rtt.ub[0]) + (Rss.ub[1] * Rtt.ub[1]) + (Rss.ub[2] * Rtt.ub[2]) + (Rss.ub[3] * Rtt.ub[3]));
Rxx.w[1]=(Rxx.w[1] + (Rss.ub[4] * Rtt.ub[4]) + (Rss.ub[5] * Rtt.ub[5]) + (Rss.ub[6] * Rtt.ub[6]) + (Rss.ub[7] * Rtt.ub[7]));
Copy to clipboard | | Rdd=vrmpybsu(Rss,Rtt) | Rdd.w[0]=((Rss.b[0] * Rtt.ub[0]) + (Rss.b[1] * Rtt.ub[1]) + (Rss.b[2] * Rtt.ub[2]) + (Rss.b[3] * Rtt.ub[3]));
Rdd.w[1]=((Rss.b[4] * Rtt.ub[4]) + (Rss.b[5] * Rtt.ub[5]) + (Rss.b[6] * Rtt.ub[6]) + (Rss.b[7] * Rtt.ub[7]));
Copy to clipboard | | Rxx+=vrmpybsu(Rss,Rtt) | Rxx.w[0]=(Rxx.w[0] + (Rss.b[0] * Rtt.ub[0]) + (Rss.b[1] * Rtt.ub[1]) + (Rss.b[2] * Rtt.ub[2]) + (Rss.b[3] * Rtt.ub[3]));
Rxx.w[1]=(Rxx.w[1] + (Rss.b[4] * Rtt.ub[4]) + (Rss.b[5] * Rtt.ub[5]) + (Rss.b[6] * Rtt.ub[6]) + (Rss.b[7] * Rtt.ub[7]));
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
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Rdd=vrmpybu(Rss,Rtt)

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Rxx+=vrmpybu(Rss,Rtt)

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Rdd=vrmpybsu(Rss,Rtt)

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Rxx+=vrmpybsu(Rss,Rtt)

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Intrinsics
Vector reduce multiply bytes intrinsics

Rdd=vrmpybu(Rss,Rtt)

Word64 Q6_P_vrmpybu_PP(Word64 Rss, Word64 Rtt)

Rxx+=vrmpybu(Rss,Rtt)

Word64 Q6_P_vrmpybuacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rdd=vrmpybsu(Rss,Rtt)

Word64 Q6_P_vrmpybsu_PP(Word64 Rss, Word64 Rtt)

Rxx+=vrmpybsu(Rss,Rtt)

Word64 Q6_P_vrmpybsuacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
#### Vector dual multiply signed by unsigned bytes Multiply eight 8-bit signed bytes in Rss by the corresponding 8-bit unsigned bytes in Rtt. Add the results in pairs, and optionally add the accumulator. The results are saturated to signed 16-bits and stored in the four halfwords of the destination register. pic_addh Page-1 Sheet.109 Sheet.35 Add Add Rectangle.43 Sheet.49 * * Sheet.50 Sheet.51 Sheet.52 16 16 Sheet.54 Sheet.73 Rxx Rxx Sheet.82 Sheet.83 Sheet.84 Sheet.85 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.2 Rss Rss Sheet.8 Rtt Rtt Rectangle.6 Rectangle.7 Rectangle.13 Rectangle.19 Rectangle.21 Rectangle.22 Rectangle.23 Sheet.9 * * Sheet.10 Sheet.11 Sheet.12 16 16 Sheet.14 Sheet.15 * * Sheet.16 Sheet.17 Sheet.18 16 16 Sheet.20 Sheet.24 * * Sheet.31 Sheet.38 Sheet.42 16 16 Sheet.44 Sheet.5 Rectangle.45 Sheet.46 * * Sheet.47 Sheet.56 Sheet.57 Sheet.58 Sheet.59 Sheet.60 Sheet.61 Sheet.62 Sheet.63 Rectangle.64 Rectangle.65 Rectangle.66 Rectangle.67 Rectangle.68 Rectangle.69 Rectangle.70 Sheet.74 * * Sheet.75 Sheet.79 * * Sheet.80 Sheet.88 * * Sheet.89 Sheet.93 Add Add Rectangle.95 Rectangle.96 Rectangle.4 Rectangle.39 Sheet.3 Add Add Sheet.48 Sheet.53 16 16 Sheet.55 Sheet.76 Sheet.77 16 16 Sheet.78 Sheet.81 Sheet.86 16 16 Sheet.87 Sheet.90 Sheet.91 16 16 Sheet.92 Sheet.94 Add Add Sheet.32 Sheet.99 Sheet.33 Sheet.34 Sheet.40 Sheet.71 Sheet.30 Sheet.100 Sheet.103 Sat16 Sat16 Sheet.101 Sat16 Sat16 Sheet.102 Sat16 Sat16 Sheet.104 Sat16 Sat16 Sheet.41 Sheet.72 Sheet.97 Sheet.98 Sheet.105 Sheet.106 Sheet.107 Vector dual multiply signed by unsigned bytes instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vdmpybsu(Rss,Rtt):sat | Rdd.h[0]=sat_16(((Rss.b[0] * Rtt.ub[0]) + (Rss.b[1] * Rtt.ub[1])));
Rdd.h[1]=sat_16(((Rss.b[2] * Rtt.ub[2]) + (Rss.b[3] * Rtt.ub[3])));
Rdd.h[2]=sat_16(((Rss.b[4] * Rtt.ub[4]) + (Rss.b[5] * Rtt.ub[5])));
Rdd.h[3]=sat_16(((Rss.b[6] * Rtt.ub[6]) + (Rss.b[7] * Rtt.ub[7])));
Copy to clipboard | | Rxx+=vdmpybsu(Rss,Rtt):sat | Rxx.h[0]=sat_16((Rxx.h[0] + (Rss.b[0] * Rtt.ub[0]) + (Rss.b[1] * Rtt.ub[1])));
Rxx.h[1]=sat_16((Rxx.h[1] + (Rss.b[2] * Rtt.ub[2]) + (Rss.b[3] * Rtt.ub[3])));
Rxx.h[2]=sat_16((Rxx.h[2] + (Rss.b[4] * Rtt.ub[4]) + (Rss.b[5] * Rtt.ub[5])));
Rxx.h[3]=sat_16((Rxx.h[3] + (Rss.b[6] * Rtt.ub[6]) + (Rss.b[7] * Rtt.ub[7])));
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rdd=vdmpybsu(Rss,Rtt):sat

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Rxx+=vdmpybsu(Rss,Rtt):sat

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Intrinsics
Vector dual multiply signed by unsigned bytes intrinsics

Rdd=vdmpybsu(Rss,Rtt):sat

Word64 Q6_P_vdmpybsu_PP_sat(Word64 Rss, Word64 Rtt)

Rxx+=vdmpybsu(Rss,Rtt):sat

Word64 Q6_P_vdmpybsuacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
#### Vector multiply even halfwords Multiply the even 16-bit halfwords from Rss and Rtt separately. Optionally accumulate with the low and high words of the destination register pair and optionally saturate. pic_addh Page-1 Sheet.73 Sheet.1 Rss Rss Rectangle.2 Rectangle.3 Sheet.4 Rtt Rtt Rectangle.4 Rectangle.6 Sheet.7 Sheet.9 Sheet.10 Sheet.11 * * Sheet.12 Sheet.13 Sheet.14 32 32 Rectangle.15 <<0-1 <<0-1 Sheet.16 Sheet.17 * * Sheet.18 Sheet.19 Sheet.20 32 32 Rectangle.27 <<0-1 <<0-1 Sheet.22 Sheet.23 Sheet.25 Sheet.24 Rxx+=vmpyeh(Rss,Rtt):sat Rxx+=vmpyeh(Rss,Rtt):sat Sheet.48 Sheet.49 Sheet.50 Add Add Rectangle High accumulation High accumulation Sheet.52 Sheet.53 Sheet.54 Sheet.55 32 32 Sheet.56 Rxx Rxx Sheet.57 Add Add Rectangle.58 Low accumulation Low accumulation Sheet.59 Sheet.60 Sheet.61 Sheet.62 32 32 Sheet.63 Sheet.64 Sheet.65 Sat32 Sat32 Sheet.66 Sat32 Sat32 Sheet.67 Sheet.68 Rectangle.69 Rectangle.70 Rectangle.71 Rectangle.72 Sheet.8 Vector multiply even halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vmpyeh(Rss,Rtt):sat | Rdd.w[0]=sat_32((Rss.h[0] * Rtt.h[0])<<0);
Rdd.w[1]=sat_32((Rss.h[2] * Rtt.h[2])<<0);
Copy to clipboard | | Rdd=vmpyeh(Rss,Rtt):<<1:sat | Rdd.w[0]=sat_32((Rss.h[0] * Rtt.h[0])<<1);
Rdd.w[1]=sat_32((Rss.h[2] * Rtt.h[2])<<1);
Copy to clipboard | | Rxx+=vmpyeh(Rss,Rtt):sat | Rxx.w[0]=sat_32(Rxx.w[0] + (Rss.h[0] * Rtt.h[0])<<0);
Rxx.w[1]=sat_32(Rxx.w[1] + (Rss.h[2] * Rtt.h[2])<<0);
Copy to clipboard | | Rxx+=vmpyeh(Rss,Rtt):<<1:sat | Rxx.w[0]=sat_32(Rxx.w[0] + (Rss.h[0] * Rtt.h[0])<<1);
Rxx.w[1]=sat_32(Rxx.w[1] + (Rss.h[2] * Rtt.h[2])<<1);
Copy to clipboard | | Rxx+=vmpyeh(Rss,Rtt) | Rxx.w[0]=Rxx.w[0] + (Rss.h[0] * Rtt.h[0]);
Rxx.w[1]=Rxx.w[1] + (Rss.h[2] * Rtt.h[2]);
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rdd=vmpyeh(Rss,Rtt):sat

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Rdd=vmpyeh(Rss,Rtt):<<1:sat

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Rxx+=vmpyeh(Rss,Rtt):sat

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Rxx+=vmpyeh(Rss,Rtt):<<1:sat

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Rxx+=vmpyeh(Rss,Rtt)

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Intrinsics
Vector multiply even halfwords intrinsics

Rdd=vmpyeh(Rss,Rtt):sat

Word64 Q6_P_vmpyeh_PP_sat(Word64 Rss, Word64 Rtt)

Rdd=vmpyeh(Rss,Rtt):<<1:sat

Word64 Q6_P_vmpyeh_PP_s1_sat(Word64 Rss, Word64 Rtt)

Rxx+=vmpyeh(Rss,Rtt):sat

Word64 Q6_P_vmpyehacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rxx+=vmpyeh(Rss,Rtt):<<1:sat

Word64 Q6_P_vmpyehacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rxx+=vmpyeh(Rss,Rtt)

Word64 Q6_P_vmpyehacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
#### Vector multiply halfwords Multiply two 16-bit halfwords separately, and optionally accumulate with the low and high words of the destination. Optionally saturate, and store the results back to the destination register pair. pic_addh Page-1 Sheet.69 Sheet.1 Rs Rs Rectangle.2 Rectangle.3 Sheet.4 Rt Rt Rectangle.4 Rectangle.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 * * Sheet.12 Sheet.13 Sheet.14 32 32 Rectangle.15 <<0-1 <<0-1 Sheet.16 Sheet.17 * * Sheet.18 Sheet.19 Sheet.20 32 32 Rectangle.27 <<0-1 <<0-1 Sheet.22 Sheet.23 Sheet.25 Sheet.24 Rxx+=vmpyh(Rs,Rt):sat Rxx+=vmpyh(Rs,Rt):sat Sheet.48 Sheet.49 Sheet.50 Add Add Rectangle High accumulation High accumulation Sheet.52 Sheet.53 Sheet.54 Sheet.55 32 32 Sheet.56 Rxx Rxx Sheet.57 Add Add Rectangle.58 Low accumulation Low accumulation Sheet.59 Sheet.60 Sheet.61 Sheet.62 32 32 Sheet.63 Sheet.64 Sheet.65 Sat32 Sat32 Sheet.66 Sat32 Sat32 Sheet.67 Sheet.68 Vector multiply halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vmpyh(Rs,Rt):sat | Rdd.w[0]=sat_32((Rs.h[0] * Rt.h[0])<<0);
Rdd.w[1]=sat_32((Rs.h[1] * Rt.h[1])<<0);
Copy to clipboard | | Rdd=vmpyh(Rs,Rt):<<1:sat | Rdd.w[0]=sat_32((Rs.h[0] * Rt.h[0])<<1);
Rdd.w[1]=sat_32((Rs.h[1] * Rt.h[1])<<1);
Copy to clipboard | | Rxx+=vmpyh(Rs,Rt):sat | Rxx.w[0]=sat_32(Rxx.w[0] + (Rs.h[0] * Rt.h[0])<<0);
Rxx.w[1]=sat_32(Rxx.w[1] + (Rs.h[1] * Rt.h[1])<<0);
Copy to clipboard | | Rxx+=vmpyh(Rs,Rt):<<1:sat | Rxx.w[0]=sat_32(Rxx.w[0] + (Rs.h[0] * Rt.h[0])<<1);
Rxx.w[1]=sat_32(Rxx.w[1] + (Rs.h[1] * Rt.h[1])<<1);
Copy to clipboard | | Rxx+=vmpyh(Rs,Rt) | Rxx.w[0]=Rxx.w[0] + (Rs.h[0] * Rt.h[0]);
Rxx.w[1]=Rxx.w[1] + (Rs.h[1] * Rt.h[1]);
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rdd=vmpyh(Rs,Rt):sat

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Rdd=vmpyh(Rs,Rt):<<1:sat

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Rxx+=vmpyh(Rs,Rt):sat

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Rxx+=vmpyh(Rs,Rt):<<1:sat

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Rxx+=vmpyh(Rs,Rt)

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Intrinsics
Vector multiply halfwords intrinsics

Rdd=vmpyh(Rs,Rt):sat

Word64 Q6_P_vmpyh_RR_sat(Word32 Rs, Word32 Rt)

Rdd=vmpyh(Rs,Rt):<<1:sat

Word64 Q6_P_vmpyh_RR_s1_sat(Word32 Rs, Word32 Rt)

Rxx+=vmpyh(Rs,Rt):sat

Word64 Q6_P_vmpyhacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx+=vmpyh(Rs,Rt):<<1:sat

Word64 Q6_P_vmpyhacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx+=vmpyh(Rs,Rt)

Word64 Q6_P_vmpyhacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
#### Vector multiply halfwords with round and pack Multiply two 16-bit halfwords separately. Round the results, and store the high halfwords packed in a single register destination. pic_addh Page-1 Sheet.71 Sheet.1 Rs Rs Rectangle.2 Rectangle.3 Sheet.4 Rt Rt Rectangle.4 Rectangle.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 * * Sheet.12 Sheet.13 Sheet.14 32 32 Rectangle.15 <<0-1 <<0-1 Sheet.16 Sheet.17 * * Sheet.18 Sheet.19 Sheet.20 32 32 Rectangle.27 <<0-1 <<0-1 Sheet.22 Sheet.23 Sheet.25 Sheet.24 Rd=vmpyh(Rs,Rt):rnd:sat Rd=vmpyh(Rs,Rt):rnd:sat Sheet.50 Add Add Sheet.53 Sheet.57 Add Add Sheet.59 Sheet.65 Sat32 Sat32 Sheet.66 Sat32 Sat32 Sheet.67 Sheet.68 Sheet.69 Sheet.70 0x8000 0x8000 Sheet.26 Sheet.27 0x8000 0x8000 Sheet.28 Rd Rd Rectangle.29 Rectangle.30 Sheet.31 High 16 bits High 16 bits Sheet.32 High 16 bits High 16 bits Vector multiply halfwords with round and pack instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=vmpyh(Rs,Rt):rnd:sat | Rd.h[1]=(sat_32((Rs.h[1] * Rt.h[1])<<0 + 0x8000)).h[1];
Rd.h[0]=(sat_32((Rs.h[0] * Rt.h[0])<<0 + 0x8000)).h[1];
Copy to clipboard | | Rd=vmpyh(Rs,Rt):<<1:rnd:sat | Rd.h[1]=(sat_32((Rs.h[1] * Rt.h[1])<<1 + 0x8000)).h[1];
Rd.h[0]=(sat_32((Rs.h[0] * Rt.h[0])<<1 + 0x8000)).h[1];
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rd=vmpyh(Rs,Rt):rnd:sat

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Rd=vmpyh(Rs,Rt):<<1:rnd:sat

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Intrinsics
Vector multiply halfwords with round and pack intrinsics

Rd=vmpyh(Rs,Rt):rnd:sat

Word32 Q6_R_vmpyh_RR_rnd_sat(Word32 Rs, Word32 Rt)

Rd=vmpyh(Rs,Rt):<<1:rnd:sat

Word32 Q6_R_vmpyh_RR_s1_rnd_sat(Word32 Rs, Word32 Rt)
#### Vector multiply halfwords, signed by unsigned Multiply two 16-bit halfwords. Rs is considered signed, Ru unsigned. Vector multiply halfwords, signed by unsigned instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vmpyhsu(Rs,Rt):sat | Rdd.w[0]=sat_32((Rs.h[0] * Rt.uh[0])<<0);
Rdd.w[1]=sat_32((Rs.h[1] * Rt.uh[1])<<0);
Copy to clipboard | | Rdd=vmpyhsu(Rs,Rt):<<1:sat | Rdd.w[0]=sat_32((Rs.h[0] * Rt.uh[0])<<1);
Rdd.w[1]=sat_32((Rs.h[1] * Rt.uh[1])<<1);
Copy to clipboard | | Rxx+=vmpyhsu(Rs,Rt):sat | Rxx.w[0]=sat_32(Rxx.w[0] + (Rs.h[0] * Rt.uh[0])<<0);
Rxx.w[1]=sat_32(Rxx.w[1] + (Rs.h[1] * Rt.uh[1])<<0);
Copy to clipboard | | Rxx+=vmpyhsu(Rs,Rt):<<1:sat | Rxx.w[0]=sat_32(Rxx.w[0] + (Rs.h[0] * Rt.uh[0])<<1);
Rxx.w[1]=sat_32(Rxx.w[1] + (Rs.h[1] * Rt.uh[1])<<1);
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rdd=vmpyhsu(Rs,Rt):sat

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Rdd=vmpyhsu(Rs,Rt):<<1:sat

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Rxx+=vmpyhsu(Rs,Rt):sat

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Rxx+=vmpyhsu(Rs,Rt):<<1:sat

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Intrinsics
Vector multiply halfwords, signed by unsigned intrinsics

Rdd=vmpyhsu(Rs,Rt):sat

Word64 Q6_P_vmpyhsu_RR_sat(Word32 Rs, Word32 Rt)

Rdd=vmpyhsu(Rs,Rt):<<1:sat

Word64 Q6_P_vmpyhsu_RR_s1_sat(Word32 Rs, Word32 Rt)

Rxx+=vmpyhsu(Rs,Rt):sat

Word64 Q6_P_vmpyhsuacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx+=vmpyhsu(Rs,Rt):<<1:sat

Word64 Q6_P_vmpyhsuacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
#### Vector reduce multiply halfwords Multiply each halfword of Rss by the corresponding halfword in Rtt. Add the intermediate products together and then optionally add the accumulator. Store the full 64-bit result in the destination register pair. This instruction is affectionately known as “big mac”. pic_addh Page-1 Sheet.1 Rss Rss Sheet.2 * * Sheet.3 Sheet.4 Sheet.5 Add Add Sheet.6 Sheet.7 Sheet.8 32 32 Rectangle 64-bit register pair 64-bit register pair Sheet.11 Rectangle.46 Rectangle.14 Rectangle.43 Rectangle.48 Sheet.17 Rtt Rtt Rectangle.4 Rectangle.6 Rectangle.11 Rectangle.12 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 * * Sheet.32 Sheet.33 Sheet.34 32 32 Sheet.36 Sheet.37 * * Sheet.38 Sheet.39 Sheet.40 32 32 Sheet.42 Sheet.43 * * Sheet.44 Sheet.45 Sheet.46 32 32 Sheet.48 Sheet.53 Sheet.54 64 64 Sheet.55 Rdd Rdd Sheet.10 Vector reduce multiply halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rxx+=vrmpyh(Rss,Rtt) | Rxx = Rxx + (Rss.h[0] * Rtt.h[0]) + (Rss.h[1] * Rtt.h[1]) + (Rss.h[2] * Rtt.h[2]) + (Rss.h[3] * Rtt.h[3]);
Copy to clipboard | | Rdd=vrmpyh(Rss,Rtt) | Rdd = (Rss.h[0] * Rtt.h[0]) + (Rss.h[1] * Rtt.h[1]) + (Rss.h[2] * Rtt.h[2]) + (Rss.h[3] * Rtt.h[3]);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rxx+=vrmpyh(Rss,Rtt)

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Rdd=vrmpyh(Rss,Rtt)

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Intrinsics
Vector reduce multiply halfwords intrinsics

Rxx+=vrmpyh(Rss,Rtt)

Word64 Q6_P_vrmpyhacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)

Rdd=vrmpyh(Rss,Rtt)

Word64 Q6_P_vrmpyh_PP(Word64 Rss, Word64 Rtt)
#### Vector multiply bytes Four 8-bit bytes from register Rs are multiplied by four 8-bit bytes from Rt. The product is optionally accumulated with the 16-bit value from the destination register. The 16-bit results are packed in the destination register pair. The bytes of Rs can be treated as either signed or unsigned. pic_addh Page-1 Sheet.103 Rectangle.43 Sheet.49 * * Sheet.50 Sheet.54 Sheet.82 Sheet.83 Sheet.84 Sheet.85 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.2 Rs Rs Sheet.8 Rt Rt Rectangle.6 Rectangle.7 Rectangle.13 Rectangle.19 Rectangle.21 Rectangle.22 Rectangle.23 Sheet.9 * * Sheet.10 Sheet.14 Sheet.15 * * Sheet.16 Sheet.20 Sheet.24 * * Sheet.31 Sheet.44 Rectangle Sheet.94 Rxx Rxx Sheet.96 Sheet.99 Sheet.100 Sheet.101 Add Add Sheet.102 Rectangle.1 Sheet.3 Sheet.4 Sheet.5 Sheet.11 Add Add Sheet.12 Rectangle.17 Sheet.18 Sheet.29 Sheet.30 Sheet.32 Add Add Sheet.33 Rectangle.34 Sheet.35 Sheet.36 Sheet.37 Sheet.38 Add Add Sheet.39 Vector multiply bytes instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vmpybu(Rs,Rt) | Rdd.h[0]=((Rs.ub[0] * Rt.ub[0]));
Rdd.h[1]=((Rs.ub[1] * Rt.ub[1]));
Rdd.h[2]=((Rs.ub[2] * Rt.ub[2]));
Rdd.h[3]=((Rs.ub[3] * Rt.ub[3]));
Copy to clipboard | | Rdd=vmpybsu(Rs,Rt) | Rdd.h[0]=((Rs.b[0] * Rt.ub[0]));
Rdd.h[1]=((Rs.b[1] * Rt.ub[1]));
Rdd.h[2]=((Rs.b[2] * Rt.ub[2]));
Rdd.h[3]=((Rs.b[3] * Rt.ub[3]));
Copy to clipboard | | Rxx+=vmpybu(Rs,Rt) | Rxx.h[0]=(Rxx.h[0]+(Rs.ub[0] * Rt.ub[0]));
Rxx.h[1]=(Rxx.h[1]+(Rs.ub[1] * Rt.ub[1]));
Rxx.h[2]=(Rxx.h[2]+(Rs.ub[2] * Rt.ub[2]));
Rxx.h[3]=(Rxx.h[3]+(Rs.ub[3] * Rt.ub[3]));
Copy to clipboard | | Rxx+=vmpybsu(Rs,Rt) | Rxx.h[0]=(Rxx.h[0]+(Rs.b[0] * Rt.ub[0]));
Rxx.h[1]=(Rxx.h[1]+(Rs.b[1] * Rt.ub[1]));
Rxx.h[2]=(Rxx.h[2]+(Rs.b[2] * Rt.ub[2]));
Rxx.h[3]=(Rxx.h[3]+(Rs.b[3] * Rt.ub[3]));
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rdd=vmpybu(Rs,Rt)

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Rdd=vmpybsu(Rs,Rt)

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Rxx+=vmpybu(Rs,Rt)

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Rxx+=vmpybsu(Rs,Rt)

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Intrinsics
Vector multiply bytes intrinsics

Rdd=vmpybu(Rs,Rt)

Word64 Q6_P_vmpybu_RR(Word32 Rs, Word32 Rt)

Rdd=vmpybsu(Rs,Rt)

Word64 Q6_P_vmpybsu_RR(Word32 Rs, Word32 Rt)

Rxx+=vmpybu(Rs,Rt)

Word64 Q6_P_vmpybuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)

Rxx+=vmpybsu(Rs,Rt)

Word64 Q6_P_vmpybsuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
#### Vector polynomial multiply halfwords Perform a vector 16x16 carryless polynomial multiply using 32-bit source registers Rs and Rt. The 64-bit result is stored in packed H,H,L,L format in the destination register. The destination register can also be optionally accumulated (XORed). Finite field multiply instructions are useful for many algorithms including scramble code generation, cryptographic algorithms, convolutional, and Reed Solomon codes. Page-1 Sheet.153 Rectangle.114 Rectangle.115 Dynamic connector.116 Sheet.117 Center drag circle Center drag circle.5 Sheet.120 * * Sheet.121 Rs Rs Sheet.122 Rt Rt Dynamic connector.123 Rectangle.124 Dynamic connector.125 Rounded rectangle.126 XOR XOR Dynamic connector.127 Dynamic connector.128 Sheet.129 16 × 16 carryless polynomial mpy 16 × 16carrylesspolynomial mpy Sheet.130 Rxx Rxx Dynamic connector.131 Dynamic connector.132 Rectangle.133 Rectangle.134 Dynamic connector.135 Sheet.136 Center drag circle Center drag circle.5 Sheet.139 * * Dynamic connector.142 Dynamic connector.143 Rounded rectangle.144 XOR XOR Dynamic connector.145 Dynamic connector.146 Sheet.147 16 × 16 carryless polynomial mpy 16 × 16carrylesspolynomial mpy Dynamic connector.148 Dynamic connector.149 Dynamic connector.150 Dynamic connector.151 Dynamic connector.152 Sheet.141 Rxx += vpmpyh(Rs,Rt) Rxx += vpmpyh(Rs,Rt) Vector polynomial multiply halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vpmpyh(Rs,Rt) | x0 = Rs.uh[0];
x1 = Rs.uh[1];
y0 = Rt.uh[0];
y1 = Rt.uh[1];
prod0 = prod1 = 0;
for(i=0; i < 16; i++) {
if((y0 >> i) & 1) prod0 ^= (x0 << i);
if((y1 >> i) & 1) prod1 ^= (x1 << i);
}
Rdd.h[0]=prod0.uh[0];
Rdd.h[1]=prod1.uh[0];
Rdd.h[2]=prod0.uh[1];
Rdd.h[3]=prod1.uh[1];
Copy to clipboard | | Rxx^=vpmpyh(Rs,Rt) | x0 = Rs.uh[0];
x1 = Rs.uh[1];
y0 = Rt.uh[0];
y1 = Rt.uh[1];
prod0 = prod1 = 0;
for(i=0; i < 16; i++) {
if((y0 >> i) & 1) prod0 ^= (x0 << i);
if((y1 >> i) & 1) prod1 ^= (x1 << i);
}
Rxx.h[0]=Rxx.uh[0] ^ prod0.uh[0];
Rxx.h[1]=Rxx.uh[1] ^ prod1.uh[0];
Rxx.h[2]=Rxx.uh[2] ^ prod0.uh[1];
Rxx.h[3]=Rxx.uh[3] ^ prod1.uh[1];
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rdd=vpmpyh(Rs,Rt)

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Rxx^=vpmpyh(Rs,Rt)

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Intrinsics
Vector polynomial multiply halfwords intrinsics

Rdd=vpmpyh(Rs,Rt)

Word64 Q6_P_vpmpyh_RR(Word32 Rs, Word32 Rt)

Rxx^=vpmpyh(Rs,Rt)

Word64 Q6_P_vpmpyhxacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
### PERM The XTYPE/PERM instruction subclass includes instructions which perform permutations. #### CABAC decode bin This is a special-purpose instruction to support H.264 Context Adaptive Binary Arithmetic Coding (CABAC). See Section X.X for a complete description. CABAC decode bin instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=decbin(Rss,Rtt) | state = Rtt.w[1][5:0];
valMPS = Rtt.w[1][8:8];
bitpos = Rtt.w[0][4:0];
range = Rss.w[0];
offset = Rss.w[1];
range <<= bitpos;
offset <<= bitpos;
rLPS = rLPS_table_64x4[state][ (range >>29)&3];
rLPS = rLPS << 23;
rMPS= (range&0xff800000) - rLPS;
if (offset < rMPS) {
Rdd = AC_next_state_MPS_64[state];
Rdd[8:8]=valMPS;
Rdd[31:23]=(rMPS>>23);
Rdd.w[1]=offset;
P0=valMPS;
} else {
Rdd = AC_next_state_LPS_64[state];
Rdd[8:8]=((!state)?(1-valMPS):(valMPS));
Rdd[31:23]=(rLPS>>23);
Rdd.w[1]=(offset-rMPS);
P0=(valMPS^1);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - The predicate generated by this instruction can not be used as a .new predicate, nor can it be automatically ANDed with another predicate.
Encodings
Bitmap

Syntax

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Rdd=decbin(Rss,Rtt)

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#### Saturate Saturate a single scalar value. sath saturates a signed 32-bit number to a signed 16-bit number, which is sign-extended back to 32 bits and placed in the destination register. The minimum negative value of the result is 0xffff8000 and the maximum positive value is 0x00007fff. satuh saturates a signed 32-bit number to an unsigned 16-bit number, which is zero-extended back to 32 bits and placed in the destination register. The minimum value of the result is 0 and the maximum value is 0x0000ffff. satb saturates a signed 32-bit number to an signed 8-bit number, which is sign-extended back to 32 bits and placed in the destination register. The minimum value of the result is 0xffffff80 and the maximum value is 0x0000007f. satub saturates a signed 32-bit number to an unsigned 8-bit number, which is zero-extended back to 32 bits and placed in the destination register. The minimum value of the result is 0 and the maximum value is 0x000000ff. Saturate instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=sat(Rss) | Rd = sat_32(Rss);
Copy to clipboard | | Rd=sath(Rs) | Rd = sat_16(Rs);
Copy to clipboard | | Rd=satuh(Rs) | Rd = usat_16(Rs);
Copy to clipboard | | Rd=satub(Rs) | Rd = usat_8(Rs);
Copy to clipboard | | Rd=satb(Rs) | Rd = sat_8(Rs);
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rd=sat(Rss)

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Rd=sath(Rs)

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Rd=satuh(Rs)

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Rd=satub(Rs)

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Rd=satb(Rs)

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Intrinsics
Saturate intrinsics

Rd=sat(Rss)

Word32 Q6_R_sat_P(Word64 Rss)

Rd=sath(Rs)

Word32 Q6_R_sath_R(Word32 Rs)

Rd=satuh(Rs)

Word32 Q6_R_satuh_R(Word32 Rs)

Rd=satub(Rs)

Word32 Q6_R_satub_R(Word32 Rs)

Rd=satb(Rs)

Word32 Q6_R_satb_R(Word32 Rs)
#### Swizzle bytes Swizzle the bytes of a word. This instruction is useful in converting between little and big endian formats. pic_addh Page-1 Sheet.61 Rectangle.39 Rectangle.40 Rectangle.41 Rectangle.22 Sheet.43 Sheet.44 Sheet.45 Sheet.46 Sheet.48 Sheet.59 Rd Rd Sheet.60 Rs Rs Rectangle.1 Rectangle.2 Rectangle.3 Rectangle.4 Sheet.5 Sheet.6 Rd = swiz(Rs) Rd = swiz(Rs) Swizzle bytes instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=swiz(Rs) | Rd.b[0]=Rs.b[3];
Rd.b[1]=Rs.b[2];
Rd.b[2]=Rs.b[1];
Rd.b[3]=Rs.b[0];
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rd=swiz(Rs)

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Intrinsics
Swizzle bytes intrinsics

Rd=swiz(Rs)

Word32 Q6_R_swiz_R(Word32 Rs)
#### Vector align Align a vector. Use the immediate amount, or the least significant 3 bits of a Predicate register, as the number of bytes to align. Shift the Rss register pair right by this number of bytes. Fill the vacated positions with the least significant elements from Rtt. pic_addh Page-1 Sheet.34 Sheet.1 Rss Rss Rectangle.74 Sheet.3 Rtt Rtt Rectangle.32 Sheet.5 Rectangle.60 Rectangle.61 Rectangle.62 Rectangle.63 Rectangle.64 Rectangle.65 Rectangle.7 Rectangle.8 Rectangle.9 Rectangle.10 Rectangle.11 Rectangle.12 Rectangle.13 Rectangle.14 Rectangle.15 Rectangle.16 Rectangle.17 Rectangle.18 Rectangle.19 Rectangle.20 Rectangle.66 Rectangle.67 Sheet.28 Sheet.29 Sheet.30 Sheet.31 Rdd Rdd Sheet.32 Sheet.33 #u3/P #u3/P Vector align instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=valignb(Rtt,Rss,#u3) | Rdd = (Rss >>> u*8)|(Rtt << ((8-u)*8));
Copy to clipboard | | Rdd=valignb(Rtt,Rss,Pu) | Rdd = Rss >>> (Pu&0x7)*8|(Rtt << (8-(Pu&0x7))*8);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Rdd=valignb(Rtt,Rss,#u3)

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Rdd=valignb(Rtt,Rss,Pu)

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Intrinsics
Vector align intrinsics

Rdd=valignb(Rtt,Rss,#u3)

Word64 Q6_P_valignb_PPI(Word64 Rtt, Word64 Rss, Word32 Iu3)

Rdd=valignb(Rtt,Rss,Pu)

Word64 Q6_P_valignb_PPp(Word64 Rtt, Word64 Rss, Byte Pu)
#### Vector round and pack Add the constant 0x00008000 to each word in the 64-bit source vector Rss. Optionally saturate this addition to 32bits. Pack the high halfwords of the result into the corresponding halfword of the 32-bit destination register. pic_addh Page-1 Sheet.32 Sheet.10 Sheet.11 Sheet.12 Sheet.13 Sheet.27 Rss Rss Rectangle.28 Rss.w[1] Rss.w[1] Sheet.30 Rd Rd Rounded rectangle.107 32-bit Add 32-bit Add Sheet.1 0x8000 0x8000 Sheet.14 Rectangle.5 Rss.w[0] Rss.w[0] Rectangle.8 Rectangle.9 Sheet.2 Sheet.3 Sheet.4 Rounded rectangle.6 32-bit Add 32-bit Add Sheet.15 0x8000 0x8000 Rectangle.16 Rectangle.17 Rectangle.18 Rd.h[1] Rd.h[1] Rectangle.19 Rd.h[0] Rd.h[0] Vector round and pack instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=vrndwh(Rss) | for (i=0;i<2;i++) {
Rd.h[i]=(Rss.w[i]+0x08000).h[1];
}
Copy to clipboard | | Rd=vrndwh(Rss):sat | for (i=0;i<2;i++) {
Rd.h[i]=sat_32(Rss.w[i]+0x08000).h[1];
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rd=vrndwh(Rss)

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Rd=vrndwh(Rss):sat

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Intrinsics
Vector round and pack intrinsics

Rd=vrndwh(Rss)

Word32 Q6_R_vrndwh_P(Word64 Rss)

Rd=vrndwh(Rss):sat

Word32 Q6_R_vrndwh_P_sat(Word64 Rss)
#### Vector saturate and pack For each element in the vector, saturate the value to the next smaller size. VSATHUB saturates signed halfwords to unsigned bytes, while VSATHB saturates signed halfwords to signed bytes. pic_addh Page-1 Sheet.81 Rectangle.59 s16 s16 Rectangle.61 s16 s16 Rectangle.62 s16 s16 Rectangle.63 s16 s16 Rectangle.65 u8 u8 Rectangle.66 u8 u8 Rectangle.67 u8 u8 Rectangle.69 u8 u8 Sheet.9 Sheet.10 Sheet.11 Sheet.12 Rss Rss Sheet.13 Rd Rd Rounded rectangle.107 sat_u8 sat_u8 Sheet.15 Rounded rectangle.58 sat_u8 sat_u8 Sheet.17 Sheet.18 Sheet.19 Rounded rectangle.76 sat_u8 sat_u8 Sheet.21 Sheet.22 Rounded rectangle.79 sat_u8 sat_u8 Sheet.24 Rd = vsathub(Rss) Rd = vsathub(Rss) Rectangle.25 s16 s16 Rectangle.26 s16 s16 Rectangle.27 s16 s16 Rectangle.28 s16 s16 Rectangle.29 s8 s8 Rectangle.30 s8 s8 Rectangle.31 s8 s8 Rectangle.32 s8 s8 Sheet.33 Sheet.34 Sheet.35 Sheet.36 Rss Rss Sheet.37 Rd Rd Rounded rectangle.38 sat_s8 sat_s8 Sheet.39 Rounded rectangle.40 sat_s8 sat_s8 Sheet.41 Sheet.42 Sheet.43 Rounded rectangle.44 sat_s8 sat_s8 Sheet.45 Sheet.46 Rounded rectangle.47 sat_s8 sat_s8 Sheet.48 Rd = vsathb(Rss) Rd = vsathb(Rss) Rectangle.51 s16 s16 Rectangle.52 s16 s16 Rectangle.53 0 0 Rectangle.54 0 0 Rectangle.55 u8 u8 Rectangle.56 u8 u8 Sheet.60 Rs Rs Sheet.61 Rd Rd Sheet.66 Sheet.67 Rounded rectangle.68 sat_u8 sat_u8 Sheet.69 Sheet.70 Rounded rectangle.71 sat_u8 sat_u8 Sheet.72 Rd = vsathub(Rs) Rd = vsathub(Rs) Rectangle.49 s16 s16 Rectangle.50 s16 s16 Rectangle.57 0 0 Rectangle.58 0 0 Rectangle.62 s8 s8 Rectangle.63 s8 s8 Sheet.65 Rs Rs Sheet.73 Rd Rd Sheet.74 Sheet.75 Rounded rectangle.76 sat_s8 sat_s8 Sheet.77 Sheet.78 Rounded rectangle.79 sat_s8 sat_s8 Sheet.80 Rd = vsathb(Rs) Rd = vsathb(Rs) VSATWH saturates signed words to signed halfwords, while VSATWUH saturates signed words to unsigned halfwords. The resulting values are packed together into destination register Rd. pic_addh Page-1 Sheet.29 Rectangle.59 s32 s32 Rectangle.62 s32 s32 Rectangle.65 s16 s16 Sheet.9 Sheet.10 Sheet.11 Sheet.12 Rss Rss Sheet.13 Rd Rd Rounded rectangle.107 Sat_s16 Sat_s16 Sheet.21 Sheet.22 Rounded rectangle.79 Sat_s16 Sat_s16 Sheet.24 Rd=vsathwh(Rss) Rd=vsathwh(Rss) Rectangle.2 s16 s16 Rectangle.4 s32 s32 Rectangle.6 s32 s32 Rectangle.7 u16 u16 Sheet.8 Sheet.15 Sheet.16 Sheet.17 Rss Rss Sheet.18 Rd Rd Rounded rectangle.19 Sat_u16 Sat_u16 Sheet.20 Sheet.25 Rounded rectangle.26 Sat_u16 Sat_u16 Sheet.27 Rd=vsathwuh(Rss) Rd=vsathwuh(Rss) Rectangle.28 u16 u16 Vector saturate and pack instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=vsathub(Rss) | for (i=0;i<4;i++) {
Rd.b[i]=usat_8(Rss.h[i]);
}
Copy to clipboard | | Rd=vsathub(Rs) | Rd.b[0]=usat_8(Rs.h[0]);
Rd.b[1]=usat_8(Rs.h[1]);
Rd.b[2]=0;
Rd.b[3]=0;
Copy to clipboard | | Rd=vsathb(Rs) | Rd.b[0]=sat_8(Rs.h[0]);
Rd.b[1]=sat_8(Rs.h[1]);
Rd.b[2]=0;
Rd.b[3]=0;
Copy to clipboard | | Rd=vsathb(Rss) | for (i=0;i<4;i++) {
Rd.b[i]=sat_8(Rss.h[i]);
}
Copy to clipboard | | Rd=vsatwh(Rss) | for (i=0;i<2;i++) {
Rd.h[i]=sat_16(Rss.w[i]);
}
Copy to clipboard | | Rd=vsatwuh(Rss) | for (i=0;i<2;i++) {
Rd.h[i]=usat_16(Rss.w[i]);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rd=vsathub(Rss)

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Rd=vsathub(Rs)

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Rd=vsathb(Rs)

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Rd=vsathb(Rss)

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Rd=vsatwh(Rss)

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Rd=vsatwuh(Rss)

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Intrinsics
Vector saturate and pack intrinsics

Rd=vsathub(Rss)

Word32 Q6_R_vsathub_P(Word64 Rss)

Rd=vsathub(Rs)

Word32 Q6_R_vsathub_R(Word32 Rs)

Rd=vsathb(Rs)

Word32 Q6_R_vsathb_R(Word32 Rs)

Rd=vsathb(Rss)

Word32 Q6_R_vsathb_P(Word64 Rss)

Rd=vsatwh(Rss)

Word32 Q6_R_vsatwh_P(Word64 Rss)

Rd=vsatwuh(Rss)

Word32 Q6_R_vsatwuh_P(Word64 Rss)
#### Vector saturate without pack Saturate each element of source vector Rss to the next smaller size. VSATHUB saturates signed halfwords to unsigned bytes. VSATWH saturates signed words to signed halfwords, and VSATWUH saturates signed words to unsigned halfwords. The resulting values are placed in destination register Rdd in unpacked form. pic_addh Page-1 Sheet.63 Rectangle.59 s16 s16 Rectangle.61 s16 s16 Rectangle.62 s16 s16 Rectangle.63 s16 s16 Sheet.9 Sheet.10 Sheet.12 Rss Rss Sheet.13 Rdd Rdd Rounded rectangle.107 Sat_u8 Sat_u8 Sheet.15 Rounded rectangle.58 Sat_u8 Sat_u8 Sheet.17 Sheet.18 Sheet.19 Rounded rectangle.76 Sat_u8 Sat_u8 Sheet.21 Sheet.22 Rounded rectangle.79 Sat_u8 Sat_u8 Sheet.24 Rdd=vsathub(Rss) Rdd=vsathub(Rss) Rectangle.5 0 0 Rectangle.11 u8 u8 Rectangle.6 0 0 Rectangle.7 u8 u8 Rectangle.8 0 0 Rectangle.25 u8 u8 Rectangle.26 0 0 Rectangle.27 u8 u8 Rectangle.28 s16 s16 Rectangle.29 s16 s16 Rectangle.30 s16 s16 Rectangle.31 s16 s16 Sheet.32 Sheet.33 Sheet.34 Rss Rss Sheet.35 Rdd Rdd Rounded rectangle.36 Sat_s8 Sat_s8 Sheet.37 Rounded rectangle.38 Sat_s8 Sat_s8 Sheet.39 Sheet.40 Sheet.41 Rounded rectangle.42 Sat_s8 Sat_s8 Sheet.43 Sheet.44 Rounded rectangle.45 Sat_s8 Sat_s8 Sheet.46 Rdd=vsathb(Rss) Rdd=vsathb(Rss) Rectangle.47 Rectangle.48 s8 s8 Rectangle.50 s8 s8 Rectangle.52 s8 s8 Rectangle.54 s8 s8 Sheet.55 Sheet.56 se se Rectangle.49 Sheet.57 Sheet.58 se se Rectangle.51 Sheet.53 Sheet.59 se se Rectangle.60 Sheet.61 Sheet.62 se se Vector saturate without pack instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vsathub(Rss) | for (i=0;i<4;i++) {
Rdd.h[i]=usat_8(Rss.h[i]);
}
Copy to clipboard | | Rdd=vsathb(Rss) | for (i=0;i<4;i++) {
Rdd.h[i]=sat_8(Rss.h[i]);
}
Copy to clipboard | | Rdd=vsatwh(Rss) | for (i=0;i<2;i++) {
Rdd.w[i]=sat_16(Rss.w[i]);
}
Copy to clipboard | | Rdd=vsatwuh(Rss) | for (i=0;i<2;i++) {
Rdd.w[i]=usat_16(Rss.w[i]);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)** Note - If saturation occurs during execution of this instruction (a result is clamped to either maximum or minimum values), then the OVF bit in the Status Register is set. OVF will remain set until explicitly cleared by a transfer to SR.
Encodings
Bitmap

Syntax

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Rdd=vsathub(Rss)

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Rdd=vsathb(Rss)

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Rdd=vsatwh(Rss)

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Rdd=vsatwuh(Rss)

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Intrinsics
Vector saturate without pack intrinsics

Rdd=vsathub(Rss)

Word64 Q6_P_vsathub_P(Word64 Rss)

Rdd=vsathb(Rss)

Word64 Q6_P_vsathb_P(Word64 Rss)

Rdd=vsatwh(Rss)

Word64 Q6_P_vsatwh_P(Word64 Rss)

Rdd=vsatwuh(Rss)

Word64 Q6_P_vsatwuh_P(Word64 Rss)
#### Vector shuffle Shuffle odd halfwords (shuffoh) takes the odd halfwords from Rtt and the odd halfwords from Rss and merges them together into vector Rdd. Shuffle even halfwords (shuffeh) performs the same operation on every even halfword in Rss and Rtt. The same operation is available for odd and even bytes. pic_addh Page-1 Sheet.131 Sheet.30 Rtt Rtt Rectangle.8 Rectangle.7 Rectangle.20 Rectangle.21 Rectangle.22 Rectangle.23 Rectangle.24 Rectangle.25 Rectangle.26 Rectangle.29 Rectangle.32 Rectangle.33 Sheet.13 Sheet.34 Rss Rss Sheet.35 Rdd Rdd Sheet.36 Sheet.37 shuffoh shuffoh Sheet.38 Sheet.39 Sheet.28 Rss Rss Rectangle.40 Rectangle.41 Rectangle.42 Rectangle.43 Rectangle.44 Rectangle.45 Rectangle.46 Rectangle.47 Rectangle.48 Rectangle.49 Rectangle.50 Rectangle.51 Sheet.52 Sheet.53 Rtt Rtt Sheet.54 Rdd Rdd Sheet.55 Sheet.56 Sheet.57 Sheet.58 shuffeh shuffeh Rectangle.59 Rectangle.60 Rectangle.61 Rectangle.62 Rectangle.63 Rectangle.64 Rectangle.65 Rectangle.66 Rectangle.67 Rectangle.68 Rectangle.69 Rectangle.70 Rectangle.71 Rectangle.72 Rectangle.73 Rectangle.74 Rectangle.75 Rectangle.76 Rectangle.77 Rectangle.78 Rectangle.79 Rectangle.80 Rectangle.81 Rectangle.82 Sheet.83 Sheet.84 Sheet.85 Sheet.86 Sheet.87 Sheet.88 Sheet.89 Sheet.90 Sheet.91 Rtt Rtt Sheet.92 Rss Rss Sheet.93 Rdd Rdd Sheet.94 shuffob shuffob Rectangle.95 Rectangle.96 Rectangle.97 Rectangle.98 Rectangle.99 Rectangle.100 Rectangle.101 Rectangle.102 Rectangle.103 Rectangle.104 Rectangle.105 Rectangle.106 Rectangle.107 Rectangle.108 Rectangle.109 Rectangle.110 Rectangle.111 Rectangle.112 Rectangle.113 Rectangle.114 Rectangle.115 Rectangle.116 Rectangle.117 Rectangle.118 Sheet.119 Sheet.120 Sheet.121 Sheet.122 Sheet.123 Sheet.124 Sheet.125 Sheet.126 Sheet.127 Rss Rss Sheet.128 Rtt Rtt Sheet.129 Rdd Rdd Sheet.130 shuffeb shuffeb Vector shuffle instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=shuffob(Rtt,Rss) | for (i=0;i<4;i++) {
Rdd.b[i*2]=Rss.b[i*2+1];
Rdd.b[i*2+1]=Rtt.b[i*2+1];
}
Copy to clipboard | | Rdd=shuffeb(Rss,Rtt) | for (i=0;i<4;i++) {
Rdd.b[i*2]=Rtt.b[i*2];
Rdd.b[i*2+1]=Rss.b[i*2];
}
Copy to clipboard | | Rdd=shuffoh(Rtt,Rss) | for (i=0;i<2;i++) {
Rdd.h[i*2]=Rss.h[i*2+1];
Rdd.h[i*2+1]=Rtt.h[i*2+1];
}
Copy to clipboard | | Rdd=shuffeh(Rss,Rtt) | for (i=0;i<2;i++) {
Rdd.h[i*2]=Rtt.h[i*2];
Rdd.h[i*2+1]=Rss.h[i*2];
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

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Rdd=shuffob(Rtt,Rss)

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Rdd=shuffeb(Rss,Rtt)

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Rdd=shuffoh(Rtt,Rss)

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Rdd=shuffeh(Rss,Rtt)

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Intrinsics
Vector shuffle intrinsics

Rdd=shuffob(Rtt,Rss)

Word64 Q6_P_shuffob_PP(Word64 Rtt, Word64 Rss)

Rdd=shuffeb(Rss,Rtt)

Word64 Q6_P_shuffeb_PP(Word64 Rss, Word64 Rtt)

Rdd=shuffoh(Rtt,Rss)

Word64 Q6_P_shuffoh_PP(Word64 Rtt, Word64 Rss)

Rdd=shuffeh(Rss,Rtt)

Word64 Q6_P_shuffeh_PP(Word64 Rss, Word64 Rtt)
#### Vector splat bytes Replicate the low 8-bits from register Rs into each of the four bytes of destination register Rd. pic_addh Page-1 Sheet.29 Rectangle.59 Rectangle.61 Rectangle.62 Rectangle.63 Sheet.12 Rd Rd Sheet.13 Rs Rs Sheet.21 Sheet.24 Rd=vsplatb(Rs) Rd=vsplatb(Rs) Rectangle.25 Rectangle.26 Sheet.5 Sheet.6 Sheet.7 Rectangle.27 Rectangle.28 Vector splat bytes instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=vsplatb(Rs) | for (i=0;i<4;i++) {
Rd.b[i]=Rs.b[0];
}
Copy to clipboard | | Rdd=vsplatb(Rs) | for (i=0;i<8;i++) {
Rdd.b[i]=Rs.b[0];
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

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Rd=vsplatb(Rs)

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Rdd=vsplatb(Rs)

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Intrinsics
Vector splat bytes intrinsics

Rd=vsplatb(Rs)

Word32 Q6_R_vsplatb_R(Word32 Rs)

Rdd=vsplatb(Rs)

Word64 Q6_P_vsplatb_R(Word32 Rs)
#### Vector splat halfwords Replicate the low 16-bits from register Rs into each of the four halfwords of destination Rdd. pic_addh Page-1 Sheet.27 Rectangle.59 Rectangle.61 Rectangle.62 Rectangle.63 Sheet.12 Rdd Rdd Sheet.13 Rs Rs Sheet.21 Sheet.24 Rdd=vsplath(Rs) Rdd=vsplath(Rs) Rectangle.25 Rectangle.26 Sheet.5 Sheet.6 Sheet.7 Vector splat halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vsplath(Rs) | for (i=0;i<4;i++) {
Rdd.h[i]=Rs.h[0];
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

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Rdd=vsplath(Rs)

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Intrinsics
Vector splat halfwords intrinsics

Rdd=vsplath(Rs)

Word64 Q6_P_vsplath_R(Word32 Rs)
#### Vector splice Concatenate the low (8-N) bytes of vector Rtt with the low N bytes of vector Rss. This instruction is helpful to vectorize unaligned stores. pic_addh Page-1 Sheet.34 Sheet.1 Rtt Rtt Rectangle.74 Sheet.3 Rss Rss Rectangle.32 Sheet.5 Rectangle.60 Rectangle.61 Rectangle.62 Rectangle.63 Rectangle.64 Rectangle.65 Rectangle.7 Rectangle.8 Rectangle.9 Rectangle.10 Rectangle.11 Rectangle.12 Rectangle.13 Rectangle.14 Rectangle.15 Rectangle.16 Rectangle.17 Rectangle.18 Rectangle.19 Rectangle.20 Rectangle.66 Rectangle.67 Sheet.28 Sheet.29 Sheet.30 Sheet.31 Rdd Rdd Sheet.32 Sheet.33 #u3/P #u3/P Vector splice instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vspliceb(Rss,Rtt,#u3) | Rdd = Rtt << u*8 | zxt_u*8_to_64(Rss);
Copy to clipboard | | Rdd=vspliceb(Rss,Rtt,Pu) | Rdd = Rtt << (Pu&7)*8 | zxt_(Pu&7)*8_to_64(Rss);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

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Rdd=vspliceb(Rss,Rtt,#u3)

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Rdd=vspliceb(Rss,Rtt,Pu)

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Intrinsics
Vector splice intrinsics

Rdd=vspliceb(Rss,Rtt,#u3)

Word64 Q6_P_vspliceb_PPI(Word64 Rss, Word64 Rtt, Word32 Iu3)

Rdd=vspliceb(Rss,Rtt,Pu)

Word64 Q6_P_vspliceb_PPp(Word64 Rss, Word64 Rtt, Byte Pu)
#### Vector sign extend vsxtbh sign-extends each byte of a single register source to halfwords, and places the result in the destination register pair. vsxthw sign-extends each halfword of a single register source to words, and places the result in the destination register pair. pic_addh Page-1 Sheet.88 Rectangle.34 Rectangle.35 Rectangle.36 Rectangle.37 Rectangle.79 Rectangle.39 Rectangle.40 Rectangle.41 Rectangle.22 Sheet.43 Sheet.44 Sheet.45 Sheet.46 Sheet.47 Sheet.48 Sheet.49 sign sign Rectangle.50 Sheet.51 Sheet.52 sign sign Rectangle.47 Sheet.54 Sheet.55 sign sign Rectangle.51 Sheet.57 Sheet.58 sign sign Sheet.59 Rdd Rdd Sheet.60 Rs Rs Rectangle.62 Rectangle.63 Rectangle.64 Rectangle.65 Rectangle.66 Rectangle.68 Sheet.71 Sheet.73 Sheet.75 Sheet.81 Sheet.82 sign sign Sheet.86 Rdd Rdd Sheet.87 Rs Rs Sheet.61 Sheet.67 sign sign Sheet.69 Rdd = vsxthw(Rs) Rdd = vsxthw(Rs) Sheet.70 Rdd = vsxtbh(Rs) Rdd = vsxtbh(Rs) Vector sign extend instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vsxtbh(Rs) | for (i=0;i<4;i++) {
Rdd.h[i]=Rs.b[i];
}
Copy to clipboard | | Rdd=vsxthw(Rs) | for (i=0;i<2;i++) {
Rdd.w[i]=Rs.h[i];
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

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Rdd=vsxtbh(Rs)

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Rdd=vsxthw(Rs)

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Intrinsics
Vector sign extend intrinsics

Rdd=vsxtbh(Rs)

Word64 Q6_P_vsxtbh_R(Word32 Rs)

Rdd=vsxthw(Rs)

Word64 Q6_P_vsxthw_R(Word32 Rs)
#### Vector truncate In vtrunehb, for each halfword in a vector, take the even (lower) byte and ignore the other byte. The resulting values are packed into destination register Rd. vtrunohb takes each odd byte of the source vector. vtrunewh uses two source register pairs, Rss and Rtt. The even (lower) halfwords of Rss are packed in the upper word of Rdd, while the lower halfwords of Rtt are packed in the lower word of Rdd. vtrunowh performs the same operation as vtrunewh, but uses the odd (upper) halfwords of the source vectors instead. pic_addh Page-1 Sheet.110 Sheet.24 Rd = vtrunehb(Rss) Rd = vtrunehb(Rss) Rectangle.88 Rectangle.89 Rectangle.90 Rectangle.91 Rectangle.92 Rectangle.93 Rectangle.94 Rectangle.95 Rectangle.96 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Rss Rss Sheet.42 Rd Rd Rectangle.104 Rectangle.105 Rectangle.106 Sheet.46 Rd = vtrunohb(Rss) Rd = vtrunohb(Rss) Rectangle.47 Rectangle.48 Rectangle.49 Rectangle.50 Rectangle.51 Rectangle.52 Rectangle.53 Rectangle.54 Rectangle.55 Sheet.56 Sheet.57 Sheet.58 Sheet.59 Sheet.60 Sheet.61 Rss Rss Sheet.62 Rd Rd Rectangle.63 Rectangle.64 Rectangle.65 Rectangle.66 Rectangle.71 Rectangle.73 Sheet.76 Sheet.78 Sheet.79 Sheet.80 Rss Rss Sheet.81 Rdd Rdd Rectangle.82 Rectangle.83 Rectangle.84 Rectangle.67 Rectangle.68 Sheet.69 Rectangle.70 Rectangle.72 Rectangle.74 Rectangle.75 Sheet.77 Rtt Rtt Sheet.85 Sheet.86 Sheet.87 Rdd = vtrunewh(Rss,Rtt) Rdd = vtrunewh(Rss,Rtt) Rectangle.88 Rectangle.89 Rectangle.90 Sheet.91 Sheet.92 Sheet.93 Sheet.94 Rss Rss Sheet.95 Rdd Rdd Rectangle.96 Rectangle.97 Rectangle.98 Rectangle.99 Rectangle.100 Sheet.101 Rectangle.102 Rectangle.103 Rectangle.104 Rectangle.105 Sheet.106 Rtt Rtt Sheet.107 Sheet.108 Sheet.109 Rdd = vtrunowh(Rss,Rtt) Rdd = vtrunowh(Rss,Rtt) Vector truncate instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=vtrunohb(Rss) | for (i=0;i<4;i++) {
Rd.b[i]=Rss.b[i*2+1];
}
Copy to clipboard | | Rdd=vtrunewh(Rss,Rtt) | Rdd.h[0]=Rtt.h[0];
Rdd.h[1]=Rtt.h[2];
Rdd.h[2]=Rss.h[0];
Rdd.h[3]=Rss.h[2];
Copy to clipboard | | Rdd=vtrunowh(Rss,Rtt) | Rdd.h[0]=Rtt.h[1];
Rdd.h[1]=Rtt.h[3];
Rdd.h[2]=Rss.h[1];
Rdd.h[3]=Rss.h[3];
Copy to clipboard | | Rd=vtrunehb(Rss) | for (i=0;i<4;i++) {
Rd.b[i]=Rss.b[i*2];
}
Copy to clipboard | | Rdd=vtrunehb(Rss,Rtt) | for (i=0;i<4;i++) {
Rdd.b[i]=Rtt.b[i*2];
Rdd.b[i+4]=Rss.b[i*2];
}
Copy to clipboard | | Rdd=vtrunohb(Rss,Rtt) | for (i=0;i<4;i++) {
Rdd.b[i]=Rtt.b[i*2+1];
Rdd.b[i+4]=Rss.b[i*2+1];
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

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Rd=vtrunohb(Rss)

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Rdd=vtrunewh(Rss,Rtt)

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Rdd=vtrunowh(Rss,Rtt)

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Rd=vtrunehb(Rss)

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Rdd=vtrunehb(Rss,Rtt)

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Rdd=vtrunohb(Rss,Rtt)

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Intrinsics
Vector truncate intrinsics

Rd=vtrunohb(Rss)

Word32 Q6_R_vtrunohb_P(Word64 Rss)

Rdd=vtrunewh(Rss,Rtt)

Word64 Q6_P_vtrunewh_PP(Word64 Rss, Word64 Rtt)

Rdd=vtrunowh(Rss,Rtt)

Word64 Q6_P_vtrunowh_PP(Word64 Rss, Word64 Rtt)

Rd=vtrunehb(Rss)

Word32 Q6_R_vtrunehb_P(Word64 Rss)

Rdd=vtrunehb(Rss,Rtt)

Word64 Q6_P_vtrunehb_PP(Word64 Rss, Word64 Rtt)

Rdd=vtrunohb(Rss,Rtt)

Word64 Q6_P_vtrunohb_PP(Word64 Rss, Word64 Rtt)
#### Vector zero extend vzxtbh zero-extends each byte of a single register source to halfwords, and places the result in the destination register pair. vzxthw zero-extends each halfword of a single register source to words, and places the result in the destination register pair. pic_addh Page-1 Sheet.78 Rectangle.34 Rectangle.35 Rectangle.36 Rectangle.37 Rectangle.79 Rectangle.39 Rectangle.40 Rectangle.41 Rectangle.22 Sheet.43 Sheet.44 Sheet.45 Sheet.46 Sheet.47 Sheet.48 Sheet.49 zero zero Rectangle.50 Sheet.51 Sheet.52 zero zero Rectangle.47 Sheet.54 Sheet.55 zero zero Rectangle.51 Sheet.57 Sheet.58 zero zero Sheet.59 Rdd Rdd Sheet.60 Rs Rs Rectangle.61 Rectangle.62 Rectangle.63 Rectangle.64 Rectangle.65 Rectangle.68 Sheet.67 Sheet.68 Sheet.69 Sheet.70 Sheet.71 zero zero Sheet.72 Rdd Rdd Sheet.73 Rs Rs Sheet.74 Sheet.75 zero zero Sheet.76 Rdd = vzxthw(Rs) Rdd = vzxthw(Rs) Sheet.77 Rdd = vzxtbh(Rs) Rdd = vzxtbh(Rs) Vector zero extend instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=vzxtbh(Rs) | for (i=0;i<4;i++) {
Rdd.h[i]=Rs.ub[i];
}
Copy to clipboard | | Rdd=vzxthw(Rs) | for (i=0;i<2;i++) {
Rdd.w[i]=Rs.uh[i];
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

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Rdd=vzxthw(Rs)

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Intrinsics
Vector zero extend intrinsics

Rdd=vzxtbh(Rs)

Word64 Q6_P_vzxtbh_R(Word32 Rs)

Rdd=vzxthw(Rs)

Word64 Q6_P_vzxthw_R(Word32 Rs)
### PRED The XTYPE/PRED instruction subclass includes instructions which perform miscellaneous operations on predicates, including mask generation, predicate transfers, and the Viterbi pack operation. #### Bounds check Determine if Rs falls in the range defined by Rtt. Rtt.w0 is set by the user to the lower bound, and Rtt.w1 is set by the user to the upper bound. All bits of the destination predicate are set if the value falls within the range, or all cleared otherwise. Bounds check instructions | **Syntax** | **Behavior** | | --- | --- | | Pd=boundscheck(Rss,Rtt):raw:hi | src = Rss.uw[1];
Pd = (src.uw[0] >= Rtt.uw[0]) && (src.uw[0] < Rtt.uw[1]) ? 0xff : 0x00;
Copy to clipboard | | Pd=boundscheck(Rss,Rtt):raw:lo | src = Rss.uw[0];
Pd = (src.uw[0] >= Rtt.uw[0]) && (src.uw[0] < Rtt.uw[1]) ? 0xff : 0x00;
Copy to clipboard | | Pd=boundscheck(Rs,Rtt) | if ("Rs & 1") {
Assembler mapped to: "Pd=boundscheck(Rss,Rtt):raw:hi";
} else {
Assembler mapped to: "Pd=boundscheck(Rss,Rtt):raw:lo";
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

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Pd=boundscheck(Rss,Rtt):raw:hi

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Pd=boundscheck(Rss,Rtt):raw:lo

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Intrinsics
Bounds check intrinsics

Pd=boundscheck(Rs,Rtt)

Byte Q6_p_boundscheck_RP(Word32 Rs, Word64 Rtt)
#### Compare byte These instructions sign- or zero-extend the low 8-bits of the source registers and perform 32-bit comparisons on the result. In the case of an extended 32-bit immediate operand, the full 32 immediate bits are used for the comparison. Compare byte instructions | **Syntax** | **Behavior** | | --- | --- | | Pd=cmpb.eq(Rs,Rt) | Pd=Rs.b[0] == Rt.b[0] ? 0xff : 0x00;
Copy to clipboard | | Pd=cmpb.eq(Rs,#u8) | Pd=Rs.ub[0] == u ? 0xff : 0x00;
Copy to clipboard | | Pd=cmpb.gtu(Rs,Rt) | Pd=Rs.ub[0] > Rt.ub[0] ? 0xff : 0x00;
Copy to clipboard | | Pd=cmpb.gtu(Rs,#u7) | apply_extension(u);
Pd=Rs.ub[0] > u.uw[0] ? 0xff : 0x00;
Copy to clipboard | | Pd=cmpb.gt(Rs,Rt) | Pd=Rs.b[0] > Rt.b[0] ? 0xff : 0x00;
Copy to clipboard | | Pd=cmpb.gt(Rs,#s8) | Pd=Rs.b[0] > s ? 0xff : 0x00;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Pd=cmpb.eq(Rs,Rt)

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Pd=cmpb.eq(Rs,#u8)

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Pd=cmpb.gtu(Rs,Rt)

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Pd=cmpb.gtu(Rs,#u7)

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Pd=cmpb.gt(Rs,Rt)

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Pd=cmpb.gt(Rs,#s8)

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Intrinsics
Compare byte intrinsics

Pd=cmpb.eq(Rs,Rt)

Byte Q6_p_cmpb_eq_RR(Word32 Rs, Word32 Rt)

Pd=cmpb.eq(Rs,#u8)

Byte Q6_p_cmpb_eq_RI(Word32 Rs, Word32 Iu8)

Pd=cmpb.gtu(Rs,Rt)

Byte Q6_p_cmpb_gtu_RR(Word32 Rs, Word32 Rt)

Pd=cmpb.gtu(Rs,#u7)

Byte Q6_p_cmpb_gtu_RI(Word32 Rs, Word32 Iu7)

Pd=cmpb.gt(Rs,Rt)

Byte Q6_p_cmpb_gt_RR(Word32 Rs, Word32 Rt)

Pd=cmpb.gt(Rs,#s8)

Byte Q6_p_cmpb_gt_RI(Word32 Rs, Word32 Is8)
#### Compare half These instructions sign- or zero-extend the low 16-bits of the source registers and perform 32-bit comparisons on the result. In the case of an extended 32-bit immediate operand, the full 32 immediate bits are used for the comparison. Compare half instructions | **Syntax** | **Behavior** | | --- | --- | | Pd=cmph.eq(Rs,Rt) | Pd=Rs.h[0] == Rt.h[0] ? 0xff : 0x00;
Copy to clipboard | | Pd=cmph.gt(Rs,Rt) | Pd=Rs.h[0] > Rt.h[0] ? 0xff : 0x00;
Copy to clipboard | | Pd=cmph.gtu(Rs,Rt) | Pd=Rs.uh[0] > Rt.uh[0] ? 0xff : 0x00;
Copy to clipboard | | Pd=cmph.eq(Rs,#s8) | apply_extension(s);
Pd=Rs.h[0] == s ? 0xff : 0x00;
Copy to clipboard | | Pd=cmph.gt(Rs,#s8) | apply_extension(s);
Pd=Rs.h[0] > s ? 0xff : 0x00;
Copy to clipboard | | Pd=cmph.gtu(Rs,#u7) | apply_extension(u);
Pd=Rs.uh[0] > u.uw[0] ? 0xff : 0x00;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Pd=cmph.eq(Rs,Rt)

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Pd=cmph.gt(Rs,Rt)

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Pd=cmph.gtu(Rs,Rt)

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Pd=cmph.eq(Rs,#s8)

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Pd=cmph.gt(Rs,#s8)

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Pd=cmph.gtu(Rs,#u7)

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Intrinsics
Compare half intrinsics

Pd=cmph.eq(Rs,Rt)

Byte Q6_p_cmph_eq_RR(Word32 Rs, Word32 Rt)

Pd=cmph.gt(Rs,Rt)

Byte Q6_p_cmph_gt_RR(Word32 Rs, Word32 Rt)

Pd=cmph.gtu(Rs,Rt)

Byte Q6_p_cmph_gtu_RR(Word32 Rs, Word32 Rt)

Pd=cmph.eq(Rs,#s8)

Byte Q6_p_cmph_eq_RI(Word32 Rs, Word32 Is8)

Pd=cmph.gt(Rs,#s8)

Byte Q6_p_cmph_gt_RI(Word32 Rs, Word32 Is8)

Pd=cmph.gtu(Rs,#u7)

Byte Q6_p_cmph_gtu_RI(Word32 Rs, Word32 Iu7)
#### Compare doublewords Compare two 64-bit register pairs for unsigned greater than, greater than, or equal. The 8-bit predicate register Pd is set to all 1’s or all 0’s depending on the result. Compare doublewords instructions | **Syntax** | **Behavior** | | --- | --- | | Pd=cmp.eq(Rss,Rtt) | Pd=Rss==Rtt ? 0xff : 0x00;
Copy to clipboard | | Pd=cmp.gt(Rss,Rtt) | Pd=Rss>Rtt ? 0xff : 0x00;
Copy to clipboard | | Pd=cmp.gtu(Rss,Rtt) | Pd=Rss.u64>Rtt.u64 ? 0xff : 0x00;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Pd=cmp.eq(Rss,Rtt)

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Pd=cmp.gt(Rss,Rtt)

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Pd=cmp.gtu(Rss,Rtt)

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Intrinsics
Compare doublewords intrinsics

Pd=cmp.eq(Rss,Rtt)

Byte Q6_p_cmp_eq_PP(Word64 Rss, Word64 Rtt)

Pd=cmp.gt(Rss,Rtt)

Byte Q6_p_cmp_gt_PP(Word64 Rss, Word64 Rtt)

Pd=cmp.gtu(Rss,Rtt)

Byte Q6_p_cmp_gtu_PP(Word64 Rss, Word64 Rtt)
#### Compare bit mask If all the bits in the mask in Rt or a short immediate are set (BITSSET) or clear (BITSCLEAR) in Rs, set the Pd to true. Otherwise, set the bits in Pd to false. Compare bit mask instructions | **Syntax** | **Behavior** | | --- | --- | | Pd=bitsset(Rs,Rt) | Pd=(Rs&Rt)==Rt ? 0xff : 0x00;
Copy to clipboard | | Pd=bitsclr(Rs,Rt) | Pd=(Rs&Rt)==0 ? 0xff : 0x00;
Copy to clipboard | | Pd=!bitsset(Rs,Rt) | Pd=(Rs&Rt)!=Rt ? 0xff : 0x00;
Copy to clipboard | | Pd=!bitsclr(Rs,Rt) | Pd=(Rs&Rt)!=0 ? 0xff : 0x00;
Copy to clipboard | | Pd=bitsclr(Rs,#u6) | Pd=(Rs&u)==0 ? 0xff : 0x00;
Copy to clipboard | | Pd=!bitsclr(Rs,#u6) | Pd=(Rs&u)!=0 ? 0xff : 0x00;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Pd=bitsset(Rs,Rt)

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Pd=bitsclr(Rs,Rt)

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Pd=!bitsset(Rs,Rt)

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Pd=!bitsclr(Rs,Rt)

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Pd=bitsclr(Rs,#u6)

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Pd=!bitsclr(Rs,#u6)

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Intrinsics
Compare bit mask intrinsics

Pd=bitsset(Rs,Rt)

Byte Q6_p_bitsset_RR(Word32 Rs, Word32 Rt)

Pd=bitsclr(Rs,Rt)

Byte Q6_p_bitsclr_RR(Word32 Rs, Word32 Rt)

Pd=!bitsset(Rs,Rt)

Byte Q6_p_not_bitsset_RR(Word32 Rs, Word32 Rt)

Pd=!bitsclr(Rs,Rt)

Byte Q6_p_not_bitsclr_RR(Word32 Rs, Word32 Rt)

Pd=bitsclr(Rs,#u6)

Byte Q6_p_bitsclr_RI(Word32 Rs, Word32 Iu6)

Pd=!bitsclr(Rs,#u6)

Byte Q6_p_not_bitsclr_RI(Word32 Rs, Word32 Iu6)
#### Mask generate from predicate For each of the low 8 bits in predicate register Pt, if the bit is set then set the corresponding byte in 64-bit register pair Rdd to 0xff, otherwise, set the corresponding byte to 0x00. pic_addh Page-1 Sheet.71 Sheet.1 Pt Pt Rectangle.163 1 1 Rectangle.164 0 0 Rectangle.165 1 1 Rectangle.166 0 0 Rectangle.167 1 1 Rectangle.168 0 0 Rectangle.169 1 1 Rectangle.170 0 0 Sheet.18 0 0 Sheet.19 7 7 Sheet.20 Rdd Rdd Rectangle.130 0xFF 0xFF Rectangle.22 0x00 0x00 Rectangle.134 0xFF 0xFF Rectangle.24 0x00 0x00 Rectangle.136 0xFF 0xFF Rectangle.137 0x00 0x00 Rectangle.30 0xFF 0xFF Rectangle.31 0x00 0x00 Sheet.29 Sheet.30 Sheet.31 Sheet.32 Sheet.33 Sheet.68 Sheet.69 Sheet.70 Mask generate from predicate instructions | **Syntax** | **Behavior** | | --- | --- | | Rdd=mask(Pt) | for (i = 0; i < 8; i++) {
Rdd.b[i]=(Pt.i?(0xff):(0x00));
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

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Rdd=mask(Pt)

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Intrinsics
Mask generate from predicate intrinsics

Rdd=mask(Pt)

Word64 Q6_P_mask_p(Byte Pt)
#### Predicate transfer Pd=Rs transfers a predicate to the 8 least-significant bits of a general register and zeros the other bits. Rd=Ps transfers the 8 least-significant bits of a general register to a predicate. Predicate transfer instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=Ps | Rd = zxt_8_to_32(Ps);
Copy to clipboard | | Pd=Rs | Pd = Rs.ub[0];
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Pd=Rs

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Intrinsics
Predicate transfer intrinsics

Rd=Ps

Word32 Q6_R_equals_p(Byte Ps)

Pd=Rs

Byte Q6_p_equals_R(Word32 Rs)
#### Test bit Extract a bit from a register. If the bit is true (1), set all the bits of the predicate register destination to 1. If the bit is false (0), set all the bits of the predicate register destination to 0. The bit to be tested can be indicated using an immediate or register value. If a register is used to indicate the bit to test, and the value specified is out of range, the predicate result is zero. Test bit instructions | **Syntax** | **Behavior** | | --- | --- | | Pd=tstbit(Rs,#u5) | Pd = (Rs & (1< Copy to clipboard | | Pd=!tstbit(Rs,#u5) | Pd = (Rs & (1< Copy to clipboard | | Pd=tstbit(Rs,Rt) | Pd = (zxt_32_to_64(Rs) & (sxt_7_to_32(Rt)>0)?(zxt_32_to_64(1)<>>sxt_7_to_32(Rt))) != 0 ? 0xff : 0x00;
Copy to clipboard | | Pd=!tstbit(Rs,Rt) | Pd = (zxt_32_to_64(Rs) & (sxt_7_to_32(Rt)>0)?(zxt_32_to_64(1)<>>sxt_7_to_32(Rt))) == 0 ? 0xff : 0x00;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Pd=!tstbit(Rs,#u5)

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Pd=tstbit(Rs,Rt)

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Pd=!tstbit(Rs,Rt)

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Intrinsics
Test bit intrinsics

Pd=tstbit(Rs,#u5)

Byte Q6_p_tstbit_RI(Word32 Rs, Word32 Iu5)

Pd=!tstbit(Rs,#u5)

Byte Q6_p_not_tstbit_RI(Word32 Rs, Word32 Iu5)

Pd=tstbit(Rs,Rt)

Byte Q6_p_tstbit_RR(Word32 Rs, Word32 Rt)

Pd=!tstbit(Rs,Rt)

Byte Q6_p_not_tstbit_RR(Word32 Rs, Word32 Rt)
#### Vector compare halfwords Compare each of four 16-bit halfwords in two 64-bit vectors and set the corresponding bits in a predicate destination to ‘11’ if true, ‘00’ if false. Halfword comparisons can be for equal, signed greater than, or unsigned greater than. pic_vcmpub Page-1 Sheet.1 Rss Rss Rectangle.72 Rectangle.73 Rectangle.74 Rectangle.75 Sheet.6 Rtt Rtt Rectangle.50 Rectangle.51 Rectangle.52 Rectangle.80 Sheet.11 Sheet.12 Sheet.13 Sheet.14 Sheet.15 Sheet.16 Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Rectangle.119 1 1 Rectangle.120 1 1 Rectangle.121 0 0 Rectangle.122 0 0 Rectangle.123 1 1 Rectangle.124 1 1 Rectangle.125 0 0 Rectangle.126 0 0 Sheet.39 0 0 Sheet.41 7 7 Sheet.42 Sheet.43 Sheet.44 Sheet.45 Rounded rectangle.62 cmp cmp Rounded rectangle.63 cmp cmp Rounded rectangle.64 cmp cmp Rounded rectangle.65 cmp cmp Sheet.50 Pd Pd Vector compare halfwords instructions | **Syntax** | **Behavior** | | --- | --- | | Pd=vcmph.eq(Rss,Rtt) | for (i = 0; i < 4; i++) {
Pd.i*2 = (Rss.h[i] == Rtt.h[i]);
Pd.i*2+1 = (Rss.h[i] == Rtt.h[i]);
}
Copy to clipboard | | Pd=vcmph.gt(Rss,Rtt) | for (i = 0; i < 4; i++) {
Pd.i*2 = (Rss.h[i] > Rtt.h[i]);
Pd.i*2+1 = (Rss.h[i] > Rtt.h[i]);
}
Copy to clipboard | | Pd=vcmph.gtu(Rss,Rtt) | for (i = 0; i < 4; i++) {
Pd.i*2 = (Rss.uh[i] > Rtt.uh[i]);
Pd.i*2+1 = (Rss.uh[i] > Rtt.uh[i]);
}
Copy to clipboard | | Pd=vcmph.eq(Rss,#s8) | for (i = 0; i < 4; i++) {
Pd.i*2 = (Rss.h[i] == s);
Pd.i*2+1 = (Rss.h[i] == s);
}
Copy to clipboard | | Pd=vcmph.gt(Rss,#s8) | for (i = 0; i < 4; i++) {
Pd.i*2 = (Rss.h[i] > s);
Pd.i*2+1 = (Rss.h[i] > s);
}
Copy to clipboard | | Pd=vcmph.gtu(Rss,#u7) | for (i = 0; i < 4; i++) {
Pd.i*2 = (Rss.uh[i] > u);
Pd.i*2+1 = (Rss.uh[i] > u);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Pd=vcmph.eq(Rss,Rtt)

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Pd=vcmph.gt(Rss,Rtt)

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Pd=vcmph.gtu(Rss,Rtt)

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Pd=vcmph.eq(Rss,#s8)

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Pd=vcmph.gt(Rss,#s8)

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Pd=vcmph.gtu(Rss,#u7)

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Intrinsics
Vector compare halfwords intrinsics

Pd=vcmph.eq(Rss,Rtt)

Byte Q6_p_vcmph_eq_PP(Word64 Rss, Word64 Rtt)

Pd=vcmph.gt(Rss,Rtt)

Byte Q6_p_vcmph_gt_PP(Word64 Rss, Word64 Rtt)

Pd=vcmph.gtu(Rss,Rtt)

Byte Q6_p_vcmph_gtu_PP(Word64 Rss, Word64 Rtt)

Pd=vcmph.eq(Rss,#s8)

Byte Q6_p_vcmph_eq_PI(Word64 Rss, Word32 Is8)

Pd=vcmph.gt(Rss,#s8)

Byte Q6_p_vcmph_gt_PI(Word64 Rss, Word32 Is8)

Pd=vcmph.gtu(Rss,#u7)

Byte Q6_p_vcmph_gtu_PI(Word64 Rss, Word32 Iu7)
#### Vector compare bytes for any match Compare each byte in two 64-bit source vectors and set a predicate if any of the 8 bytes are equal. This instruction can be used to quickly find the null terminator in a string. Vector compare bytes for any match instructions | **Syntax** | **Behavior** | | --- | --- | | Pd=any8(vcmpb.eq(Rss,Rtt)) | Pd = 0;
for (i = 0; i < 8; i++) {
if (Rss.b[i] == Rtt.b[i]) Pd = 0xff;
}
Copy to clipboard | | Pd=!any8(vcmpb.eq(Rss,Rtt)) | Pd = 0;
for (i = 0; i < 8; i++) {
if (Rss.b[i] == Rtt.b[i]) Pd = 0xff;
}
Pd = ~Pd;
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Pd=any8(vcmpb.eq(Rss,Rtt))

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Pd=!any8(vcmpb.eq(Rss,Rtt))

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Intrinsics
Vector compare bytes for any match intrinsics

Pd=any8(vcmpb.eq(Rss,Rtt))

Byte Q6_p_any8_vcmpb_eq_PP(Word64 Rss, Word64 Rtt)

Pd=!any8(vcmpb.eq(Rss,Rtt))

Byte Q6_p_not_any8_vcmpb_eq_PP(Word64 Rss, Word64 Rtt)
#### Vector compare bytes Compare each of eight bytes in two 64-bit vectors and set the corresponding bit in a predicate destination to 1 if true, 0 if false. Byte comparisons can be for equal or for unsigned greater than. In the following example, every other comparison is true. pic_vcmpub Page-1 Sheet.1 Pd Pd Rectangle.163 1 1 Rectangle.164 0 0 Rectangle.165 1 1 Rectangle.166 0 0 Rectangle.167 1 1 Rectangle.168 0 0 Rectangle.169 1 1 Rectangle.170 0 0 Sheet.18 0 0 Sheet.20 7 7 Sheet.21 Rss Rss Rectangle.130 Sheet.23 Rtt Rtt Sheet.24 Rectangle.25 Rectangle.134 Rectangle.27 Rectangle.136 Rectangle.137 Rectangle.30 Rectangle.31 Rectangle.140 Rectangle.141 Rectangle.142 Rectangle.143 Rectangle.36 Rectangle.37 Rectangle.38 Rectangle.39 Sheet.40 Sheet.41 Rounded rectangle cmp cmp Sheet.43 Sheet.44 Sheet.45 Rounded rectangle.16 cmp cmp Sheet.47 Sheet.48 Sheet.49 Rounded rectangle.21 cmp cmp Sheet.51 Sheet.52 Sheet.53 Rounded rectangle.30 cmp cmp Sheet.55 Sheet.56 Sheet.57 Rounded rectangle.44 cmp cmp Sheet.59 Sheet.60 Sheet.61 Rounded rectangle.48 cmp cmp Sheet.63 Sheet.64 Sheet.65 Rounded rectangle.52 cmp cmp Sheet.67 Sheet.68 Sheet.69 Rounded rectangle.56 cmp cmp Vector compare bytes instructions | **Syntax** | **Behavior** | | --- | --- | | Pd=vcmpb.eq(Rss,Rtt) | for (i = 0; i < 8; i++) {
Pd.i = (Rss.b[i] == Rtt.b[i]);
}
Copy to clipboard | | Pd=vcmpb.eq(Rss,#u8) | for (i = 0; i < 8; i++) {
Pd.i = (Rss.ub[i] == u);
}
Copy to clipboard | | Pd=vcmpb.gtu(Rss,Rtt) | for (i = 0; i < 8; i++) {
Pd.i = (Rss.ub[i] > Rtt.ub[i]);
}
Copy to clipboard | | Pd=vcmpb.gtu(Rss,#u7) | for (i = 0; i < 8; i++) {
Pd.i = (Rss.ub[i] > u);
}
Copy to clipboard | | Pd=vcmpb.gt(Rss,Rtt) | for (i = 0; i < 8; i++) {
Pd.i = (Rss.b[i] > Rtt.b[i]);
}
Copy to clipboard | | Pd=vcmpb.gt(Rss,#s8) | for (i = 0; i < 8; i++) {
Pd.i = (Rss.b[i] > s);
}
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Pd=vcmpb.eq(Rss,Rtt)

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Pd=vcmpb.gtu(Rss,Rtt)

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Pd=vcmpb.gt(Rss,Rtt)

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Pd=vcmpb.gt(Rss,#s8)

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Intrinsics
Vector compare bytes intrinsics

Pd=vcmpb.eq(Rss,Rtt)

Byte Q6_p_vcmpb_eq_PP(Word64 Rss, Word64 Rtt)

Pd=vcmpb.eq(Rss,#u8)

Byte Q6_p_vcmpb_eq_PI(Word64 Rss, Word32 Iu8)

Pd=vcmpb.gtu(Rss,Rtt)

Byte Q6_p_vcmpb_gtu_PP(Word64 Rss, Word64 Rtt)

Pd=vcmpb.gtu(Rss,#u7)

Byte Q6_p_vcmpb_gtu_PI(Word64 Rss, Word32 Iu7)

Pd=vcmpb.gt(Rss,Rtt)

Byte Q6_p_vcmpb_gt_PP(Word64 Rss, Word64 Rtt)

Pd=vcmpb.gt(Rss,#s8)

Byte Q6_p_vcmpb_gt_PI(Word64 Rss, Word32 Is8)
#### Vector compare words Compare each of two 32-bit words in two 64-bit vectors and set the corresponding bits in a predicate destination to ‘1111’ if true, ‘0000’ if false. Word comparisons can be for equal, signed greater than, or unsigned greater than. pic_addh Page-1 Sheet.50 Sheet.1 Rss Rss Rectangle.73 Rectangle.74 Sheet.6 Rtt Rtt Rectangle.51 Rectangle.52 Sheet.12 Sheet.14 Sheet.15 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Rectangle.119 1 1 Rectangle.120 1 1 Rectangle.121 1 1 Rectangle.122 1 1 Rectangle.123 0 0 Rectangle.124 0 0 Rectangle.125 0 0 Rectangle.126 0 0 Sheet.39 0 0 Sheet.41 7 7 Sheet.42 Sheet.43 Sheet.45 Rounded rectangle.63 cmp cmp Rounded rectangle.65 cmp cmp Sheet.2 Sheet.5 Pd Pd Vector compare words instructions | **Syntax** | **Behavior** | | --- | --- | | Pd=vcmpw.eq(Rss,Rtt) | Pd[3:0] = (Rss.w[0]==Rtt.w[0]);
Pd[7:4] = (Rss.w[1]==Rtt.w[1]);
Copy to clipboard | | Pd=vcmpw.gt(Rss,Rtt) | Pd[3:0] = (Rss.w[0]>Rtt.w[0]);
Pd[7:4] = (Rss.w[1]>Rtt.w[1]);
Copy to clipboard | | Pd=vcmpw.gtu(Rss,Rtt) | Pd[3:0] = (Rss.uw[0]>Rtt.uw[0]);
Pd[7:4] = (Rss.uw[1]>Rtt.uw[1]);
Copy to clipboard | | Pd=vcmpw.eq(Rss,#s8) | Pd[3:0] = (Rss.w[0]==s);
Pd[7:4] = (Rss.w[1]==s);
Copy to clipboard | | Pd=vcmpw.gt(Rss,#s8) | Pd[3:0] = (Rss.w[0]>s);
Pd[7:4] = (Rss.w[1]>s);
Copy to clipboard | | Pd=vcmpw.gtu(Rss,#u7) | Pd[3:0] = (Rss.uw[0]>u.uw[0]);
Pd[7:4] = (Rss.uw[1]>u.uw[0]);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Pd=vcmpw.eq(Rss,Rtt)

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Pd=vcmpw.gtu(Rss,Rtt)

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Pd=vcmpw.gtu(Rss,#u7)

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Intrinsics
Vector compare words intrinsics

Pd=vcmpw.eq(Rss,Rtt)

Byte Q6_p_vcmpw_eq_PP(Word64 Rss, Word64 Rtt)

Pd=vcmpw.gt(Rss,Rtt)

Byte Q6_p_vcmpw_gt_PP(Word64 Rss, Word64 Rtt)

Pd=vcmpw.gtu(Rss,Rtt)

Byte Q6_p_vcmpw_gtu_PP(Word64 Rss, Word64 Rtt)

Pd=vcmpw.eq(Rss,#s8)

Byte Q6_p_vcmpw_eq_PI(Word64 Rss, Word32 Is8)

Pd=vcmpw.gt(Rss,#s8)

Byte Q6_p_vcmpw_gt_PI(Word64 Rss, Word32 Is8)

Pd=vcmpw.gtu(Rss,#u7)

Byte Q6_p_vcmpw_gtu_PI(Word64 Rss, Word32 Iu7)
#### Viterbi pack even and odd predicate bits Pack the even and odd bits of two predicate registers into a single destination register. A variant of this instruction is the R3:2 |= vitpack(P1,P0). This places the packed predicate bits into the lower 8bits of the register pair which has been preshifted by 8bits. - This instruction is useful in Viterbi decoding. Repeated use of the push version enables - a history to be stored for traceback, purposes. pic_vcmpub Page-1 Sheet.75 Rectangle.119 Rectangle.120 Rectangle.121 Rectangle.122 Rectangle.123 Rectangle.124 Rectangle.125 Rectangle.126 Sheet.39 0 0 Sheet.50 Rd Rd Rectangle.2 Rectangle.3 Rectangle.4 Rectangle.5 Rectangle.7 Rectangle.8 Rectangle.9 Rectangle.10 Sheet.11 0 0 Sheet.12 7 7 Sheet.13 Ps Ps Rectangle.60 0 0 Sheet.19 7 7 Sheet.20 8 8 Sheet.22 31 31 Rectangle.27 Rectangle.28 Rectangle.29 Rectangle.30 Rectangle.40 Rectangle.41 Rectangle.42 Rectangle.43 Sheet.46 Pt Pt Sheet.70 Sheet.72 Sheet.74 Sheet.1 Sheet.6 Sheet.14 Sheet.15 Sheet.21 Viterbi pack even and odd predicate bits instructions | **Syntax** | **Behavior** | | --- | --- | | Rd=vitpack(Ps,Pt) | Rd = (Ps&0x55) | (Pt&0xAA);
Copy to clipboard | **Class: XTYPE (slots 2,3)**
Encodings
Bitmap

Syntax

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Intrinsics
Viterbi pack even and odd predicate bits intrinsics

Rd=vitpack(Ps,Pt)

Word32 Q6_R_vitpack_pp(Byte Ps, Byte Pt)
#### Vector mux Perform an element-wise byte selection between two vectors. For each of the low 8 bits of predicate register Pu, if the bit is set, then the corresponding byte in Rdd is set to the corresponding byte from Rss. Otherwise, set the byte in Rdd to the byte from Rtt. pic_addh Page-1 Sheet.1 Rss Rss Rectangle.22 Sheet.3 Rtt Rtt Sheet.4 Rectangle.25 Rectangle.26 Rectangle.27 Rectangle.28 Rectangle.29 Rectangle.30 Rectangle.31 Rectangle.32 Rectangle.33 Rectangle.34 Rectangle.15 Rectangle.16 Rectangle.37