# PMU events

The Hexagon processor can collect execution statistics on the
applications it executes. The statistics summarize the types of
Hexagon processor events that occur while the application runs.

Execution statistics are collected in hardware or software:

- Statistics are collected in hardware with the performance monitor
unit (PMU), which is defined as part of the Hexagon processor
architecture.
- Statistics are collected in software that uses the Hexagon simulator.
The simulator statistics are presented in the same format used by the
PMU.

Execution statistics are expressed in terms of processor events. This
chapter defines the event symbols, along with their associated
numeric codes.

Note

Because the types of execution events vary across the
Hexagon processor versions, different types of statistics are
collected for each version. This chapter lists the event symbols
defined for version V79.

## V79 processor event symbols

[V79 processor event symbols](https://docs.qualcomm.com/doc/80-N2040-60/topic/pmu-events.html#tbl-v79-q6-processor-event-symbols)
defines the symbols that represent processor events for the
V79 Hexagon processor.

q6 v79 processor event symbols

| **Event** | **Symbol** | **Definition** | **Maskable** |
| --- | --- | --- | --- |
| 0x1 | COUNTER0\_OVERFLOW | Can be used as the event detected by counter1 to build an effective 64-bit counter. | Maskable |
| 0x2 | COUNTER2\_OVERFLOW | Can be used as the event detected by counter3 to build an effective 64-bit counter. | Maskable |
| 0x3 | COMMITTED\_PKT\_ANY | Number of packets that are committed by any thread. Packets are executed. | Maskable |
| 0x4 | COMMITTED\_PKT\_BSB | Number of packets that are committed two cycles after an earlier packet in the same thread. | Not maskable |
| 0x5 | COUNTER4\_OVERFLOW | Can be used as the event detected by counter5 to build an effective 64-bit counter. | Maskable |
| 0x6 | COUNTER6\_OVERFLOW | Can be used as the event detected by counter7 to build an effective 64-bit counter. | Maskable |
| 0x7 | COMMITTED\_PKT\_B2B | Number of packets that are committed one cycle after the earlier packet in the same thread. | Not maskable |
| 0x8 | COMMITTED\_PKT\_SMT | Number of packets that are committed on the SMT threads. Includes the second, third, and fourth packets that are committed in one cycle. | Not maskable |
| 0xa | CYCLES\_5\_THREAD\_RUNNING | Processor cycles that exactly five threads are running. Running means the threads are not in the Wait or Stop state. | Not maskable |
| 0xb | CYCLES\_6\_THREAD\_RUNNING | Processor cycles that exactly six threads are running. Running means the threads are not in the Wait or Stop state. | Not maskable |
| 0xc | COMMITTED\_PKT\_T0 | Number of packets that are committed by thread 0. Packets are executed. | Not maskable |
| 0xd | COMMITTED\_PKT\_T1 | Number of packets that are committed by thread 1. Packets are executed. | Not maskable |
| 0xe | COMMITTED\_PKT\_T2 | Number of packets that are committed by thread 2. Packets are executed. | Not maskable |
| 0xf | COMMITTED\_PKT\_T3 | Number of packets that are committed by thread 3. Packets are executed. | Not maskable |
| 0x10 | COMMITTED\_PKT\_T4 | Number of packets that are committed by thread 4. Packets are executed. | Not maskable |
| 0x11 | COMMITTED\_PKT\_T5 | Number of packets that are committed by thread 5. Packets are executed. | Not maskable |
| 0x12 | ICACHE\_DEMAND\_MISS | Number of I-cache cacheable demand primary or secondary misses. Includes secondary misses. | Not maskable |
| 0x13 | DCACHE\_DEMAND\_MISS | Number of D-cache cacheable demand primary or secondary misses. Includes dczero stalls. Excludes uncacheables, prefetches, and no-allocate store misses. | Not maskable |
| 0x14 | DCACHE\_STORE\_MISS | Number of D-cache cacheable store misses. | Maskable |
| 0x15 | COMMITTED\_PKT\_T6 | Thread 6 committed a packet. Packets are executed. | Not maskable |
| 0x16 | COMMITTED\_PKT\_T7 | Thread 7 committed a packet. Packets are executed. | Not maskable |
| 0x17 | CU\_PKT\_READY\_NOT\_DISPATCHED | Packets were ready at the CU scheduler but were not scheduled because either the scheduler’s thread was not picked or there was an inter-cluster resource conflict. | Not maskable |
| 0x18 | COMMITTED\_PKT\_5\_THREAD\_RUNNING | Number of committed packets with five threads running. Running means the threads are not in Wait or Stop mode. | Maskable |
| 0x19 | COMMITTED\_PKT\_6\_THREAD\_RUNNING | Number of committed packets with six threads running. Running means the threads are not in Wait or Stop mode. | Maskable |
| 0x1a | COMMITTED\_PKT\_7\_THREAD\_RUNNING | Number of committed packets with seven threads running. Running means the threads are not in Wait or Stop mode. | Maskable |
| 0x1b | COMMITTED\_PKT\_8\_THREAD\_RUNNING | Number of committed packets with eight threads running. Running means the threads are not in Wait or Stop mode. | Maskable |
| 0x1c | IU\_L1S\_ACCESS | Number of IU L1S loads. Includes demands or prefetches. | Not maskable |
| 0x1d | IU\_L1S\_PREFETCH | Number of IU L1S prefetches. | Not maskable |
| 0x1e | IU\_L1S\_AXIS\_STALL | Number of IU L1S stalls due to an AXI slave. | Not maskable |
| 0x1f | IU\_L1S\_NO\_GRANT | IU request to L1S, and no grant from the vector unit. | Not maskable |
| 0x20 | ANY\_IU\_REPLAY | Any IU stall other than an I-cache miss. Includes a jump register stall, fetchcross stall, ITLB miss stall, and so on. Excludes a CU replay. | Not maskable |
| 0x21 | ANY\_DU\_REPLAY | Any DU replay. Includes a bank conflict, store buffer full, and so on. Excludes a stall due to a cache miss. | Not maskable |
| 0x22 | CYCLES\_7\_THREAD\_RUNNING | Processor cycles that exactly seven threads are running. Running means the threads are not in Wait or Stop mode. | Not maskable |
| 0x23 | ISSUED\_PACKETS | Speculatively issued packets were delivered from an IU. | Not maskable |
| 0x25 | COMMITTED\_PKT\_1\_THREAD\_RUNNING | Number of committed packets with one thread running. Running means the thread is not in Wait or Stop mode. | Maskable |
| 0x26 | COMMITTED\_PKT\_2\_THREAD\_RUNNING | Number of committed packets with two threads running. Running means the threads are not in Wait or Stop mode. | Maskable |
| 0x27 | COMMITTED\_PKT\_3\_THREAD\_RUNNING | Number of committed packets with three threads running. Running means the threads are not in Wait or Stop mode. | Maskable |
| 0x28 | THREAD\_LMH\_THROTTLE | For a specific thread, the sustained power exceeds the limits management threshold and limits budget threshold. Results in throttling that is based on thread priority. | Not maskable |
| 0x29 | LMH\_THROTTLE | Throttling is based on the value of the peak current that is over the current limits of LMH. | Not maskable |
| 0x2a | COMMITTED\_INSTS | Number of committed instructions. Increments by up to eight per cycle. Duplex of two instructions counts as two instructions. Does not include end loops. | Maskable |
| 0x2b | COMMITTED\_TC1\_INSTS | Number of committed TC1 class instructions. Increments by up to eight per cycle. Duplex of two TC1 instructions counts as two separate TC1 instructions. Does not include NOPs. | Maskable |
| 0x2c | COMMITTED\_PRIVATE\_INSTS | Number of committed instructions that have per-cluster (private) execution resources. Increments by up to eight per cycle. Duplex of two private instructions counts as two private instructions. | Maskable |
| 0x2d | GLOBAL\_POWERLIMITS\_OVER | Sustained global power that exceeds the overall global limits management threshold and limits the budget threshold. Causes the thread-specific LMH to engage. | Not maskable |
| 0x2e | CYCLES\_8\_THREAD\_RUNNING | Processor cycles that exactly eight threads are running. Running means the threads are not in Wait or Stop mode. | Not maskable |
| 0x2f | COMMITTED\_PKT\_4\_THREAD\_RUNNING | Number of committed packets with four threads running. Running means the threads are not in Stop or Wait mode. | Maskable |
| 0x30 | COMMITTED\_LOADS | Number of committed load instructions. Includes cached and uncached. Increments by two for dual loads. Excludes prefetches, memory operations, and coprocessor loads. | Maskable |
| 0x31 | COMMITTED\_STORES | Number of committed store instructions. Includes cached and uncached. Increments by two for dual stores. Excludes memory operations and coprocessor stores. | Maskable |
| 0x32 | COMMITTED\_MEMOPS | Number of committed memory operations instructions. Cached or uncached. | Maskable |
| 0x33 | COMMITTED\_NOPS | Number of committed NOPs. | Maskable |
| 0x34 | ISSUED\_INSTS | Speculatively issued instructions delivered from the IU. | Maskable |
| 0x35 | DISPATCHED\_PACKETS | Number of packets that the CU dispatched. NOPs instructions are squashed. | Not maskable |
| 0x36 | DISPATCHED\_INSTS | Number of instructions that the CU dispatched. | Maskable |
| 0x37 | COMMITTED\_PROGRAM\_FLOW\_INSTS | Number of committed packets that contain a program flow instruction. Includes CR jumps, endloop, J, JR, dealloc\_return, system/trap, superset of event 56. Dual jumps count as two jumps. | Maskable |
| 0x38 | COMMITTED\_PKT\_CHANGED\_FLOW | Number of committed packets that resulted in a change of flow. Any taken jump. Includes endloop and dealloc\_return. | Maskable |
| 0x39 | COMMITTED\_PKT\_ENDLOOP | Number of committed packets containing an end loop that was taken. | Maskable |
| 0x3a | PST\_USED\_P0P1BUSY | Number of times a store port was used when p0 and p1 were both occupied. Only increments when store port is present. | Maskable |
| 0x3b | CYCLES\_1\_THREAD\_RUNNING | Processor cycles that exactly one thread is running. Running means the thread is not in Wait or Stop mode. | Not maskable |
| 0x3c | CYCLES\_2\_THREAD\_RUNNING | Processor cycles that exactly two threads are running. Running means the threads are not in Wait or Stop mode. | Not maskable |
| 0x3d | CYCLES\_3\_THREAD\_RUNNING | Processor cycles that exactly three threads are running. Running means the threads are not in Wait or Stop mode. | Not maskable |
| 0x3e | CYCLES\_4\_THREAD\_RUNNING | Processor cycles that exactly four threads are running. Running means the threads are not in Wait or Stop mode. | Not maskable |
| 0x3f | AXI\_LINE128\_READ\_REQUEST | Number of 128-byte line read requests issued by the primary AXI master. Includes all interleaved requests. | Not maskable |
| 0x40 | AXI\_READ\_REQUEST | All read requests issued by the primary AXI master. Includes full lines, partial lines, and all interleaved requests. | Not maskable |
| 0x41 | AXI\_LINE32\_READ\_REQUEST | Number of 32-byte line read requests issued by the primary AXI master. Includes all interleaved requests. | Not maskable |
| 0x42 | AXI\_WRITE\_REQUEST | All write requests issued by the primary AXI master. Includes full lines, partial lines, and all interleaved requests. | Not maskable |
| 0x43 | AXI\_LINE32\_WRITE\_REQUEST | Number of 32-byte line write requests issued by the primary AXI master. Includes all interleaved requests. All bytes are valid. | Not maskable |
| 0x44 | AHB\_READ\_REQUEST | Number of read requests issued by the AHB master. | Not maskable |
| 0x45 | AHB\_WRITE\_REQUEST | Number of write requests issued by the AHB master. | Not maskable |
| 0x46 | AXI\_LINE128\_WRITE\_REQUEST | Number of 128-byte line write requests issued by the primary AXI master. Includes all interleaved requests. All bytes are valid. | Not maskable |
| 0x47 | AXI\_SLAVE\_MULTI\_BEAT\_ACCESS | Number of AXI slave multi-beat accesses. | Not maskable |
| 0x48 | AXI\_SLAVE\_SINGLE\_BEAT\_ACCESS | Number of AXI slave single-beat accesses. | Not maskable |
| 0x49 | AXI2\_READ\_REQUEST | All read requests issued by the secondary AXI master. Includes full lines and partial lines. | Not maskable |
| 0x4a | AXI2\_LINE32\_READ\_REQUEST | Number of 32-byte line read requests issued by the secondary AXI master. | Not maskable |
| 0x4b | AXI2\_WRITE\_REQUEST | All write requests issued by the secondary AXI master. Includes full lines and partial lines. | Not maskable |
| 0x4c | AXI2\_LINE32\_WRITE\_REQUEST | Number of 32-byte line write requests issued by the secondary AXI master. | Not maskable |
| 0x4d | AXI2\_CONGESTION | Secondary AXI command or data queue is full. An operation is stuck at the head of the secondary AXI master command queue. | Not maskable |
| 0x50 | COMMITTED\_FPS | Number of committed floating point instructions. Increments by two for dual floating-point operations. Excludes conversions. | Maskable |
| 0x51 | REDIRECT\_BIMODAL\_MISPREDICT | Mispredicted bimodal branch direction caused a control flow redirect. | Not maskable |
| 0x52 | REDIRECT\_TARGET\_MISPREDICT | Mispredicted branch target caused a control flow redirect. Includes an RAS mispredict, and HintJR mispredict. Excludes indirect jumps and calls other than JUMPR R31 returns. Excludes direction mispredicts. | Not maskable |
| 0x53 | REDIRECT\_LOOP\_MISPREDICT | Mispredicted hardware loop end caused a control flow redirect. Can only happen when the loop has few packets and the loop count is 2 or less. | Not maskable |
| 0x54 | REDIRECT\_MISC | Control flow is redirected for a reason other than events 81, 82, and 83. Includes exceptions, traps, interrupts, non-R31 jumps, multiple initialization loops in flight, and so on. | Not maskable |
| 0x55 | AXI\_LINE256\_WRITE\_REQUEST | Number of 256-byte line write requests issued by the AXI master. All bytes are valid. | Not maskable |
| 0x56 | NUM\_PACKET\_CRACKED | Number of packets that cracked. | Maskable |
| 0x58 | JTLB\_MISS | Instruction or data address translation request was missed in the JTLB. | Maskable |
| 0x5a | COMMITTED\_PKT\_RETURN | Number of committed return instructions. Includes canceled returns. | Maskable |
| 0x5b | COMMITTED\_PKT\_INDIRECT\_JUMP | Number of committed indirect jumps or call instructions. Includes canceled instructions. Does not include JUMPR R31 returns. | Maskable |
| 0x5c | COMMITTED\_BIMODAL\_BRANCH\_INSTS | Number of committed bimodal branches. Includes \*.old and \*.new. Increments by two for dual jumps. | Maskable |
| 0x5f | VTCM\_FIFO\_FULL\_CYCLES | Cycles cluster can be issued if the VTCM FIFO queue is full. | Not maskable |
| 0x61 | DU\_L1S\_LOAD\_ACCESS | Number of scalar load accesses to L1S. | Not maskable |
| 0x62 | ICACHE\_ACCESS | Number of I-cacheline fetches. | Not maskable |
| 0x63 | BTB\_HIT | Number of branch target buffer hits. | Not maskable |
| 0x64 | BTB\_MISS | Number of branch target buffer misses. | Not maskable |
| 0x65 | IU\_DEMAND\_SECONDARY\_MISS | Number of I-cache secondary misses. | Not maskable |
| 0x67 | FAST\_FETCH\_KILLED | Number of fast fetches that were killed (after an I-cache access). | Not maskable |
| 0x69 | FETCHED\_PACKETS\_DROPPED | Number of packets that are dropped because the IU cannot deliver them to the CU. | Not maskable |
| 0x6b | IU\_PREFETCHES\_SENT\_TO\_L2 | Number of IU prefetches sent to the L2 cache. Includes cachelines not dropped by the L2 cache. Excludes replayed prefetches and only counts prefetches the L2 accepts. Excludes IU prefetches that are sent to L2 ITCM. | Maskable |
| 0x6c | ITLB\_MISS | Number of ITLB misses that go to JTLB. | Maskable |
| 0x72 | FETCH\_2\_CYCLE | Number of two-cycle fetches in an IU (returns, loop end, fall through, BTB). | Not maskable |
| 0x73 | FETCH\_3\_CYCLE | Number of three-cycle fetches in an IU. | Not maskable |
| 0x75 | L2\_IU\_SECONDARY\_MISS | Number of L2 secondary misses from an IU. | Maskable |
| 0x76 | L2\_IU\_ACCESS | Number of L2 cacheable access from an IU. Includes any access to the L2 cache that was the result of an IU command, either demand or L1 prefetch access. Excludes any prefetches generated in the L2 cache. Excludes L2fetch, TCM accesses, and uncacheables. Address must target the primary AXI master. | Maskable |
| 0x77 | L2\_IU\_MISS | Number of L2 misses from an IU. Of the events qualified by 0x76,  the event that resulted in an L2 miss (demand miss or L1 prefetch miss). An L2 miss is any condition that prevents the immediate return of data to the IU, excluding pipeline conflicts. | Maskable |
| 0x78 | L2\_IU\_PREFETCH\_ACCESS | Number of prefetches from an IU to the L2 cache. Any IU prefetch access sent to the L2 cache. Access must be L2 cacheable and target the primary AXI. Does not include L2 fetch-generated accesses. | Maskable |
| 0x79 | L2\_IU\_PREFETCH\_MISS | Number of L2 misses that were IU prefetches. Of the events qualified by 0x78, the events that resulted in an L2 miss. | Maskable |
| 0x7a | L2\_IU\_BRANCH\_CACHE\_WRITE\_REQUEST | Number of requests sent from the IU to the L2 cache to write the bimodal bits of instructions in L2. Includes all requests, regardless of the target. | Not maskable |
| 0x7b | L2\_IU\_BRANCH\_CACHE\_WRITE | Number of writes to the bimodal bits of instructions in the L2 cache. This event is the number of event 122 requests that completed by updating memory in the L2 cache or TCM. | Not maskable |
| 0x7c | L2\_DU\_READ\_ACCESS | Number of L2 cacheable read accesses from a DU. Any read access from the DU that might cause a lookup in the L2 cache. Includes loads, L1 prefetches, dcfetches. Excludes the initial L2fetch command, uncacheables, TCM accesses, and coprocessor loads. Must target the primary AXI master. | Maskable |
| 0x7d | L2\_DU\_READ\_MISS | Number of L2 read misses from a DU. Of the events qualified by 0x7C, any event that results in an L2 miss (that is, the line was not previously allocated in the L2 cache and is fetched from the backing memory). | Maskable |
| 0x7e | L2FETCH\_ACCESS | Number of L2 fetch accesses from a DU. Any access to the L2 cache from the L2 prefetch engine initiated by programming the L2fetch engine. | Maskable |
| 0x7f | L2FETCH\_MISS | Number of L2 fetch misses from a programmed inquiry. Of the events qualified by 0x7E, the event that results in an L2 miss (that is, the line was not previously allocated in the L2 cache and is fetched from the backing memory). | Maskable |
| 0x81 | L2\_ACCESS | All requests to the L2 cache. Does not include internally generated accesses like L2 fetch, however the programming of the L2Fetch engine is counted. All accesses to odd interleave or even interleave are counted. Can be L2 cacheable or TCM. | Maskable |
| 0x82 | L2\_PIPE\_CONFLICT\_STALL | Request is not taken by the L2 cache due to a pipe conflict. The conflict can be a tag bank, data bank, or other pipeline conflict. | Maskable |
| 0x83 | L2\_TAG\_ARRAY\_CONFLICT | Of the items in event 130, the items caused by a conflict with the tag array. | Maskable |
| 0x87 | TCM\_DU\_ACCESS | Number of TCM accesses from a DU. DU access to the L2 TCM space. Excludes HVX requests. | Maskable |
| 0x88 | TCM\_DU\_READ\_ACCESS | Number of TCM read accesses from a DU. DU read access to the L2 TCM space. Includes HVX requests. | Maskable |
| 0x89 | TCM\_IU\_ACCESS | Number of TCM accesses from an IU. IU access to the L2 TCM space. | Maskable |
| 0x8a | L2\_CASTOUT | L2 cache evicts a dirty line due to an allocation. This event is not triggered on cache operations. | Not maskable |
| 0x8b | L2\_DU\_STORE\_ACCESS | Number of L2 cacheable store access from a DU. Any store access from the DU that might cause a lookup in the L2 cache. Excludes cache operations, uncacheables, TCM, and coprocessor stores. Must target the primary AXI master. | Maskable |
| 0x8c | L2\_DU\_STORE\_MISS | Number of L2 misses from a DU. Of the events qualified by 0x8B, the events that resulted in a miss. Specifically, the cases where the line is not in the cache or a coalesce buffer. | Maskable |
| 0x8d | L2\_DU\_PREFETCH\_ACCESS | Number of L2 prefetch accesses from a DU. Of the events qualified by 0x7C, the events that are dcfetch and dhwprefetch. These L2 cacheable events target the primary AXI master. | Maskable |
| 0x8e | L2\_DU\_PREFETCH\_MISS | Number of L2 prefetch misses from a DU. Of the events qualified by 0x8D, the events that missed the L2 cache. | Maskable |
| 0x90 | L2\_DU\_LOAD\_SECONDARY\_MISS | Number of L2 load secondary misses from a DU. Hit a busy line in the scoreboard, which prevented a return. A busy condition can include pipeline bubbles caused by back-to-back loads, like L1 UC loads. | Maskable |
| 0x91 | L2FETCH\_COMMAND | Number of L2fetch commands. Excludes L2 fetch stop commands. | Not maskable |
| 0x92 | L2FETCH\_COMMAND\_KILLED | L2 fetch command was killed because a stop command was issued. Increments once for each L2 fetch command that is killed. If multiple commands are queued to the L2Fetch engine, the kill of each command is recorded. | Maskable |
| 0x93 | L2FETCH\_COMMAND\_OVERWRITE | L2 fetch command was overwritten. Kills an old L2 fetch command and replaces it with a new command. | Not maskable |
| 0x94 | L2FETCH\_ACCESS\_CREDIT\_FAIL | L2 fetch access could not get a credit. L2 fetch was blocked due to a missing L2 fetch or L2 evict credit. | Not maskable |
| 0x95 | AXI\_SLAVE\_READ\_BUSY | AXI slave read access hit a busy line. | Not maskable |
| 0x96 | AXI\_SLAVE\_WRITE\_BUSY | AXI slave write access hit a busy line. | Not maskable |
| 0x97 | L2\_ACCESS\_EVEN | Of the events in 0x81, number of accesses made to the even L2 cache. | Maskable |
| 0x98 | CLADE\_HIGH\_PRIO\_L2\_ACCESS | Number of IU or DU requests for a high-priority CLADE region. Not counted for an L2 fetch. | Maskable |
| 0x99 | CLADE\_LOW\_PRIO\_L2\_ACCESS | Number of IU or DU requests for a low-priority CLADE region. Not counted for an L2 fetch. | Maskable |
| 0x9a | CLADE\_HIGH\_PRIO\_L2\_MISS | Number of CLADE high-priority L2 accesses that missed in the L2 cache. | Maskable |
| 0x9b | CLADE\_LOW\_PRIO\_L2\_MISS | Number of CLADE low-priority L2 accesses that missed in the L2 cache. | Maskable |
| 0x9c | CLADE\_HIGH\_PRIO\_EXCEPTION | CLADE high-priority decode that had an exception. | Not maskable |
| 0x9d | CLADE\_LOW\_PRIO\_EXCEPTION | CLADE low-priority decode that had an exception. | Not maskable |
| 0x9e | AXI2\_SLAVE\_READ\_BUSY | AXI secondary slave read access hit a busy line. | Not maskable |
| 0x9f | AXI2\_SLAVE\_WRITE\_BUSY | AXI secondary slave write access hit a busy line. | Not maskable |
| 0xa0 | ANY\_DU\_STALL | Any DU stall. Increments once when the thread has a DU stall (D-cache miss or DTLB miss). | Not maskable |
| 0xa1 | DU\_BANK\_CONFLICT\_REPLAY | DU bank conflict replay. Dual memory access to same bank, but different lines. | Maskable |
| 0xa2 | DU\_CREDIT\_REPLAY | Number of times a packet took a replay because insufficient QoS DU credits were available. | Maskable |
| 0xa3 | L2\_FIFO\_FULL\_REPLAY | Number of L2 even or odd FIFO full replays. | Maskable |
| 0xa4 | DU\_STORE\_BUFFER\_FULL\_REPLAY | Number of DU replays because a demand load access hit in the store buffer. | Maskable |
| 0xa7 | DU\_SNOOP\_REQUEST | Number of DU snoop requests that were accepted. | Not maskable |
| 0xa8 | DU\_FILL\_REPLAY | Fill has an index conflict with an instruction from the same thread in the pipeline. Fills and demands might be from different threads if there is a prefetch from the deferral queue, or if a fill has not be acknowledged for very long and forces itself into the pipeline. | Maskable |
| 0xac | DU\_READ\_TO\_L2 | Number of DU reads to L2 cache. Total of everything that brings data from the L2 array. Includes prefetches (dcfetch and hwprefetch). Excludes coprocessor loads. | Not maskable |
| 0xad | DU\_WRITE\_TO\_L2 | Number of DU writes to L2 cache. Total of everything that is written out of the DU to the L2 array. Includes dczeroa. Excludes dcclean, dccleaninv, tag writes, and coprocessor stores. | Not maskable |
| 0xaf | DCZERO\_COMMITTED | Dczeroa instruction was committed. | Maskable |
| 0xb0 | L2ITCM\_IU\_READ | Number of ITCM accesses from an IU. Includes IU demand fetches and IU prefetches. This event is not included in any other L2 events. | Not maskable |
| 0xb1 | L2ITCM\_DU\_READ | Number of L2 ITCM read accesses from a DU. Includes all demands and prefetches. This event is not included in any other L2 events. | Not maskable |
| 0xb2 | L2ITCM\_DU\_WRITE | Number of L2 ITCM write accesses from a DU. Includes stores and dczeroa events. Does not include any cache operations. This event is not included in any other L2 events. | Not maskable |
| 0xb3 | DTLB\_MISS | DTLB miss that goes to JTLB. When both slots miss to different pages, increments by two. When both slots miss to the same page, only counts S1 because S1 goes first and fills for S0. | Maskable |
| 0xb4 | L2ITCM\_BIMODAL\_WRITES\_SUCCESS | Number of successful bimodal writes into L2 ITCM. | Not maskable |
| 0xb6 | STORE\_BUFFER\_HIT\_REPLAY | Store buffer hit is replayed because a packet with two stores goes to the same bank but different cachelines, followed by a load from an address pushed into the store buffer. | Maskable |
| 0xb7 | STORE\_BUFFER\_FORCE\_REPLAY | Store buffer must drain, forcing the current packet to replay. Typically occurs on a cache index match between the current packet and store buffer. Can also a store buffer timeout. | Maskable |
| 0xb8 | TAG\_WRITE\_CONFLICT\_REPLAY | Number of inter-cluster tag write conflicts. | Maskable |
| 0xb9 | SMT\_BANK\_CONFLICT | Number of inter-thread SMT bank conflicts. | Not maskable |
| 0xba | PORT\_CONFLICT\_REPLAY | Number of all port conflict replays, including the same cluster replays caused by high-priority fills and store buffer force drains. Includes inter-cluster replays. | Maskable |
| 0xbb | L2ITCM\_BIMODAL\_WRITES\_DROPPED | Number of bimodal writes into L2 ITCM that were dropped. | Not maskable |
| 0xbc | L2ITCM\_IU\_PREFETCH\_READ | Number of ITCM accesses from IU prefetches. Includes only prefetches from an IU. This event is included in event 176. It is not included in any other L2 events. | Not maskable |
| 0xbd | PAGE\_CROSS\_REPLAY | Page cross from a valid packet that caused a replay. Excludes pdkill packets. Counts twice if both slots cause a page cross. | Maskable |
| 0xbe | PST\_STORE\_SENTON\_OTHPORT | Number of times a slot 0 store was sent to the other store buffer because the other cluster had a slot 1 store or memop. Only increments when store port is present. | Maskable |
| 0xbf | DU\_DEMAND\_SECONDARY\_MISS | Number of DU demand secondary misses. | Maskable |
| 0xc0 | DU\_MISC\_REPLAY | All DU replays not counted by other replay events. This event counts every time ANY\_DU\_REPLAY counts and no other DU replay event counts. | Maskable |
| 0xc2 | DU\_STATE\_REPLAY | Number of times an access replayed because the access one cycle ahead of it allocates or invalidates a way in the same index. | Maskable |
| 0xc3 | DCFETCH\_COMMITTED | Number of dcfetches committed. Includes hits and drops. Does not include convert-to-prefetches. | Maskable |
| 0xc4 | DCFETCH\_HIT | Number of dcfetch hits in D-cache. Includes hitting valid or reserved lines. | Maskable |
| 0xc5 | DCFETCH\_MISS | Number of dcfetches missed in L1 cache. Counts the dcfetches issued to L2 FIFO. | Maskable |
| 0xc8 | DU\_LOAD\_UNCACHEABLE | Load instructions with addresses uncacheable in the L1 cache. | Maskable |
| 0xc9 | DU\_DUAL\_LOAD\_UNCACHEABLE | Packets where both loads have addresses uncacheable in the L1 cache | Maskable |
| 0xca | DU\_STORE\_UNCACHEABLE | Store instructions with addresses uncacheable in the L1 cache. | Maskable |
| 0xcb | DU\_STORE\_RELEASE\_CREDIT\_STALL | Stall occurs because there are not enough credits from the store release. | Maskable |
| 0xcd | AXI\_LINE256\_READ\_REQUEST | Number of 256-byte line read requests issued by the AXI master. All bytes are valid. | Not maskable |
| 0xce | AXI\_LINE64\_READ\_REQUEST | Number of 64-byte line read requests issued by the primary AXI master. Includes all interleaved requests. | Not maskable |
| 0xcf | AXI\_LINE64\_WRITE\_REQUEST | Number of 64-byte line write requests issued by the primary AXI master. Includes all interleaved requests. All bytes are valid. | Not maskable |
| 0xd1 | AHB\_8\_READ\_REQUEST | Number of 8-byte read requests issued by the AHB. | Not maskable |
| 0xd3 | L2FETCH\_COMMAND\_PAGE\_TERMINATION | L2fetch command terminated because it could not get a page translation from VA to PA. Includes terminations due to permission errors. That is, an address translation can fail because the VA to PA is not in the TLB, or the properties in the translation are not acceptable and the command terminates. | Not maskable |
| 0xd5 | L2\_DU\_STORE\_COALESCE | Number of events from 139 that were coalesced | Maskable |
| 0xd6 | L2\_STORE\_LINK | Number of times a new store links to something else in the scoreboard. | Maskable |
| 0xd7 | L2\_SCOREBOARD\_70\_PERCENT\_FULL | Increments by one for every cycle where the L2 scoreboard is at least 70% full. For a 32-entry scoreboard, 23 or more entries are consumed. This event continues to count even if the scoreboard is more than 80% full. For more than one interleave, this event considers only the scoreboard that has the most entries consumed. | Not maskable |
| 0xd8 | L2\_SCOREBOARD\_80\_PERCENT\_FULL | Increments by one for every cycle where the L2 scoreboard is at least 80% full. For a 32-entry scoreboard, 26 or more entries are consumed. This event continues to count even if the scoreboard is more than 90% full. For more than one interleave, this event considers only the scoreboard that has the most entries consumed. | Not maskable |
| 0xd9 | L2\_SCOREBOARD\_90\_PERCENT\_FULL | Increments by one for every cycle where the L2 scoreboard is at least 90% full. For a 32-entry scoreboard, 29 or more entries are consumed. For more than one interleave, this event considers only the scoreboard that has the most entries consumed. | Not maskable |
| 0xda | L2\_SCOREBOARD\_FULL\_REJECT | L2 scoreboard is too full to accept a selector request, and the selector has a request. | Not maskable |
| 0xdc | L2\_EVICTION\_BUFFERS\_FULL | Counts every cycle when all eviction buffers in any interleave are occupied. | Not maskable |
| 0xdd | AHB\_MULTI\_BEAT\_READ\_REQUEST | Number of 32-byte multi-beat read requests issued by the AHB. | Not maskable |
| 0xdf | L2\_DU\_LOAD\_SECONDARY\_MISS\_ON\_SW\_PREFETCH | Of the events in 0x90, the events where the primary miss was a DC fetch or L2 fetch. | Maskable |
| 0xe0 | L2FETCH\_DROP | L2 fetch data dropped because a previous eviction has not completed. | Not maskable |
| 0xe5 | THREAD\_IDLE\_PVIEW\_CYCLES | Cycles cluster cannot commit because a thread is in the Off , Wait state or in pause. | Maskable |
| 0xe6 | ARCH\_LOCK\_PVIEW\_CYCLES | Cycles cluster cannot commit due to a kernel lock or TLB lock. | Maskable |
| 0xe7 | REDIRECT\_PVIEW\_CYCLES | Cycles cluster cannot commit because of redirects such as branch mispredicts. | Maskable |
| 0xe8 | IU\_NO\_PKT\_PVIEW\_CYCLES | Cycles cluster cannot commit because the issue queue is empty. | Maskable |
| 0xe9 | DU\_CACHE\_MISS\_PVIEW\_CYCLES | Cycles cluster cannot commit due to a D-cache cacheable miss. | Maskable |
| 0xea | DU\_BUSY\_OTHER\_PVIEW\_CYCLES | Cycles cluster cannot commit due to a DU replay, DU bubble, or DTLB miss. | Maskable |
| 0xeb | CU\_BUSY\_PVIEW\_CYCLES | Cycles cluster cannot commit due to a register interlock, register port conflict, bubbles due to a timing class such as tc\_3stall, no B2B HVX, or HVX FIFO is full. | Maskable |
| 0xec | DU\_CONFLICT\_PVIEW\_CYCLES | Cycles cluster cannot commit due to a DU resource conflict. | Maskable |
| 0xed | COPROC\_BUSY\_PVIEW\_CYCLES | Cycles cluster cannot commit because the coprocessor is busy. | Maskable |
| 0xee | DU\_UNCACHED\_PVIEW\_CYCLES | Cycles cluster cannot commit due to a D-cache uncacheable access. | Maskable |
| 0xef | SYSTEM\_BUSY\_PVIEW\_CYCLES | Cycles cluster cannot commit due to system level stalls, including DMA synchronization, ETM is full, Qtimer read is not ready, AXI bus is busy, and global cache operations synchronization. | Maskable |
| 0xf1 | AXI\_LINE128\_READ\_REQUEST\_EVEN | Number of 128-byte line read requests issued by the even interleaved AXI master. | Not maskable |
| 0xf2 | AXI\_READ\_REQUEST\_EVEN | All read requests issued by the even interleaved AXI master. | Not maskable |
| 0xf3 | AXI\_LINE32\_READ\_REQUEST\_EVEN | Number of 32-byte line read requests issued by the even-interleaved AXI master. | Not maskable |
| 0xf4 | AXI\_WRITE\_REQUEST\_EVEN | All write requests issued by the even-interleaved AXI master. | Not maskable |
| 0xf5 | AXI\_LINE32\_WRITE\_REQUEST\_EVEN | Number of 32-byte line write requests issued by the even-interleaved AXI master. All bytes are valid. | Not maskable |
| 0xf6 | AXI\_LINE128\_WRITE\_REQUEST\_EVEN | Number of 128-byte line write requests issued by the even-interleaved AXI master. All bytes are valid. | Not maskable |
| 0xf8 | AXI\_LINE64\_READ\_REQUEST\_EVEN | Number of 64-byte line read requests issued by the even-interleaved AXI master. | Not maskable |
| 0xf9 | AXI\_LINE64\_WRITE\_REQUEST\_EVEN | Number of 64-byte line write requests issued by the even-interleaved AXI master. All bytes are valid. | Not maskable |
| 0xfa | AXI\_WR\_CONGESTION\_EVEN | Even-interleaved AXI write command or data queue is full, and an operation is stuck at the head of the even interleaved AXI master command queue. | Not maskable |
| 0xfb | AXI\_INCOMPLETE\_WRITE\_REQUEST\_EVEN | L2 line-sized write was made to the even-interleaved AXI master, but not all bytes were valid. Includes segmented writes. Excludes WT stores. This event captures the number of writes coalesced at a line level. | Not maskable |
| 0xfc | AXI\_LINE256\_READ\_REQUEST\_EVEN | Number of 256-byte line read requests issued by an even-interleaved AXI master. All bytes are valid. | Not maskable |
| 0xfd | AXI\_LINE256\_WRITE\_REQUEST\_EVEN | Number of 256-byte line write requests issued by an even-interleaved AXI master. All bytes are valid. | Not maskable |
| 0xfe | CYCLES\_3\_COPROC\_THREADS\_ONE\_CLUSTER | Number of processor cycles during which a cluster has three threads in Run mode with the coprocessor bit (SSR.XE) enabled. | Maskable |
| 0x2fa | L2\_CLEAN\_CASTOUT | Number of clean line evictions from L2 cache. Triggers when L2 cache evicts a line due to an allocation. Not triggered on cache operations. | Maskable |
| 0x2fb | AXI3\_READ\_REQUEST | All read requests issued by the tertiary AXI master. Includes full lines and partial lines. | Not maskable |
| 0x2fc | AXI3\_LINE32\_READ\_REQUEST | Number of 32-byte line read requests issued by the tertiary AXI master. | Not maskable |
| 0x2fd | AXI3\_WRITE\_REQUEST | All write requests issued by the tertiary AXI master. Includes full lines and partial lines. | Not maskable |
| 0x2fe | AXI3\_LINE32\_WRITE\_REQUEST | Number of 32-byte line write requests issued by the tertiary AXI master. | Not maskable |
| 0x2ff | AXI3\_RD\_CONGESTION | Tertiary AXI read command queue is full, and an operation is stuck at the head of the primary AXI master command queue. Includes all interleaved requests. | Not maskable |
| 0x300 | CYCLES\_1\_PACKET\_COMMITTED | Number of cycles when one packet is committed. | Not maskable |
| 0x301 | CYCLES\_2\_PACKET\_COMMITTED | Number of cycles when two packets are committed. | Not maskable |
| 0x302 | CYCLES\_3\_PACKET\_COMMITTED | Number of cycles when three packets are committed. | Not maskable |
| 0x303 | CYCLES\_4\_PACKET\_COMMITTED | Number of cycles when four packets are committed. | Not maskable |
| 0x304 | SMT\_CLUSTER0 | Number of cycles when more than one packet is committed in cluster 0. | Not maskable |
| 0x305 | SMT\_CLUSTER1 | Number of cycles when more than one packet is committed in cluster 1. | Not maskable |
| 0x306 | SMT\_INTERCLUSTER | Number of cycles when packets are committed on both clusters. | Not maskable |
| 0x307 | SMT\_CONFLICT\_FOR\_REG\_READ\_OR\_CU\_FWD | Number of cases when a packet is SMT-able without slot resource conflicts, but it cannot go due to s0/s1 register read/CU forwarding. | Maskable |
| 0x308 | COMMITTED\_PKT\_2\_THREAD\_RUNNING\_2T\_PLUS\_0T | Number of committed packets with two threads running on the same cluster. Running means the threads are not in the Wait or Stop state. | Not maskable |
| 0x309 | COMMITTED\_PKT\_2\_THREAD\_RUNNING\_1T\_PLUS\_1T | Number of committed packets with two threads running on the different cluster. Running means the threads are not in the Wait or Stop state. | Not maskable |
| 0x30a | COMMITTED\_PKT\_3\_THREAD\_RUNNING\_3T\_PLUS\_0T | Number of committed packets with three threads running on the same cluster. Running means the threads are not in the Wait or Stop state. | Not maskable |
| 0x30b | COMMITTED\_PKT\_3\_THREAD\_RUNNING\_2T\_PLUS\_1T | Number of committed packets with three threads running, two threads on one cluster and 1 on another cluster. Running means the threads are not in the Wait or Stop state. | Not maskable |
| 0x30c | COMMITTED\_PKT\_4\_THREAD\_RUNNING\_4T\_PLUS\_0T | Number of committed packets with four threads running on same cluster. Running means the threads are not in the Wait or Stop state. | Not maskable |
| 0x30d | COMMITTED\_PKT\_4\_THREAD\_RUNNING\_3T\_PLUS\_1T | Number of committed packets with four threads running, three threads on one cluster and one thread running on another cluster. Running means the threads are not in the Wait or Stop state. | Not maskable |
| 0x30e | COMMITTED\_PKT\_4\_THREAD\_RUNNING\_2T\_PLUS\_2T | Number of committed packets with four threads running, two threads on one cluster and two threads running on another cluster. Running means the threads are not in the Wait or Stop state. | Not maskable |
| 0x30f | COMMITTED\_PKT\_5\_THREAD\_RUNNING\_4T\_PLUS\_1T | Number of committed packets with five threads running, four threads on one cluster and one thread running on another cluster. Running means the threads are not in the Wait or Stop state. | Not maskable |
| 0x310 | COMMITTED\_PKT\_5\_THREAD\_RUNNING\_3T\_PLUS\_2T | Number of committed packets with five threads running, three threads on one cluster and two threads running on another cluster. Running means the threads are not in the Wait or Stop state. | Not maskable |
| 0x311 | COMMITTED\_PKT\_6\_THREAD\_RUNNING\_4T\_PLUS\_2T | Number of committed packets with six threads running, four threads on one cluster and two threads running on another cluster. Running means the threads are not in the Wait or Stop state. | Not maskable |
| 0x312 | COMMITTED\_PKT\_6\_THREAD\_RUNNING\_3T\_PLUS\_3T | Number of committed packets with six threads running, three threads on one cluster and three threads running on another cluster. Running means the threads are not in the Wait or Stop state. | Not maskable |
| 0x313 | ICACHE\_DEMAND\_MISS\_PREFETCH\_MISS | Number of iprfetches initiated on demand misses. | Not maskable |
| 0x314 | SIMPLE\_PACKET | Number of committed simple packets, which can be dispatched on in-cluster SMT threads. Includes eligible packets that are committed on both primary and in-cluster SMT threads. | Not maskable |
| 0x315 | AXI3\_LINE64\_WRITE\_REQUEST | Number of 64-byte line write requests issued by the primary AXI3 master. Includes all interleaved requests. All bytes are valid. | Not maskable |
| 0x316 | AXI3\_LINE64\_READ\_REQUEST | Number of 64-byte line read requests issued by the primary AXI3 master. Includes all interleaved requests | Not maskable |
| 0x317 | AXI3\_WR\_CONGESTION | Tertiary AXI write command or data queue is full, and an operation is stuck at the head of the primary AXI3 master command queue. Includes all interleaved requests. | Not maskable |
| 0x318 | AXI3\_INCOMPLETE\_WRITE\_REQUEST | L2 line-sized write was made to the AXI3 master, but not all bytes were valid. Includes segmented writes. Excludes WT stores. | Not maskable |
| 0x319 | ICACHE\_DATA\_REPLAY | Number of I-cache data replays due to incorrect way predictions. | Not maskable |
| 0x31c | SMT\_PKT\_PICKED\_BUT\_NOT\_DISP | In-cluster SMT thread is picked, but not committed. | Not maskable |
| 0x322 | CLADE2\_EB\_FULL | CLADE2 can use up to two eviction buffer entries. Indicates that both entries are used and CLADE2 is congested. | Not maskable |
| 0x323 | CLADE2\_RD\_REQ | Number of L2 cache read requests in the CLADE2 region. | Maskable |
| 0x324 | CLADE2\_RDCACHE\_MISS | Number of L2 cache read request misses in the CLADE2 region. | Maskable |
| 0x325 | CLADE2\_WR\_REQ | Number of L2 cache write requests in the CLADE2 region. | Maskable |
| 0x326 | CLADE2\_WRCACHE\_MISS | Number of L2 cache write request misses in the CLADE2 region. | Maskable |
| 0x327 | AXI\_EWD\_REQUEST | L2 cache eviction of clean data to the AXI master bus. | Not maskable |
| 0x328 | AXI\_EWD\_REQUEST\_EVEN | L2 cache eviction of clean data to the even interleaved AXI master bus. | Not maskable |
| 0x329 | AXI\_CMO\_REQUEST | Cache maintenance operation request from the QDSP6 core to AXIM. | Not maskable |
| 0x32a | AXI\_CMO\_REQUEST\_EVEN | Cache maintenance operation request from the QDSP6 core to AXIM Interleave0. | Not maskable |
| 0x32d | TAGE\_TABLE\_ALLOC | Number of allocations in the TAGE branch predictor due to mispredicting branches. | Not maskable |
| 0x32e | TAGE\_TABLE\_HIT | Number of hits in the TAGE branch predictor table. | Not maskable |
| 0x32f | TAGE\_BRANCH\_OVERRIDE | Number of times the TAGE branch predictor overrode the bimodal prediction for a branch instruction. | Not maskable |
| 0x333 | DU\_SPF\_DTLBPGCROSS | Number of stopping prefetching due to page cross. | Not maskable |
| 0x334 | DU\_SPF\_DCACHE\_HIT | Number of prefetch requests that hit in L1D$ | Not maskable |
| 0x335 | DU\_SPF\_DCACHE\_MISS | Number of prefetch requests missing in L1D$ | Not maskable |
| 0x336 | DU\_SPF\_L2FIFOFULL\_RETRY | Number of prefetch retry on L2FIFO queue full | Not maskable |
| 0x337 | DU\_SPF\_L2BUFFULL\_RETRY | Number of prefetch retry on L2 credits/AQoS busy | Not maskable |
| 0x338 | DU\_SPF\_CONFLICT\_RETRY | Number of cycles that prefetches losing arbitration | Not maskable |
| 0x340 | DPM\_AVG\_COMPRESSED | Representation of relative DPM value(obtained using the DPM weights) produced every cycle. Computed absolute average power (mW) = (DPM\_AVG\_COMPRESSED count \* max DPM value from DPM weights \* scaling factor)/execution time (ns). A value of 1 represents an overflow event from a local DPM accumulator.  The overflow may be counted to give a representation of power over the count period. | Not maskable |
| 0x351 | DU\_WAY\_PRED\_REPLAYS | Number of times DU replayed due to way misprediction | Maskable |
| 0x387 | CU\_BANK\_CONFLICT\_BLOCK | Number of dispatch blocks due to a inter cluster bank conflict prediction on one thread | Not maskable |
| 0x388 | CU\_BANK\_CONFLICT\_FLUSH | Number of flushes due to incorect inter cluster bank conflict prediction per thread | Not maskable |
| 0x389 | CU\_BANK\_CONFLICT\_PREDICTION | Number of valid bank conflict predictions for a given thread | Not maskable |

Last Published: Jan 16, 2025

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