# Introduction This document describes the Qualcomm® Hexagon™ Vector eXtensions (HVX) instruction set architecture. These extensions are implemented in an optional coprocessor. This document assumes that the reader is familiar with the Hexagon architecture. For a full description of the architecture, refer to the Qualcomm Hexagon Programmer’s Reference Manual ## SIMD coprocessor HVX instructions are primarily implemented in a single instruction multiple data (SIMD) coprocessor block that includes vector registers, vector compute elements, and dedicated memory. This extends the baseline Hexagon architecture to enable high-performance computer vision, image processing, or other workloads that can map to SIMD parallel processing. Page-1 Rectangle.15 Hexagon core Hexagon core Rectangle.4 SIMD coprocessor SIMD coprocessor Rectangle.18 L2$/L2-TCM L2$/L2-TCM Rectangle.41 I$ I$ Rectangle.75 R0-R31 P0-P3 R0-R31P0-P3 Rectangle.76 S0 S0 Rectangle.77 D$ D$ Rectangle.78 S1 S1 Rectangle.79 S2 S2 Rectangle.80 S3 S3 Rectangle.81 R0-R31 P0-P3 R0-R31P0-P3 Rectangle.82 S0 S0 Rectangle.83 S1 S1 Rectangle.84 S2 S2 Rectangle.85 S3 S3 Rectangle.86 Mem Mem Rectangle.87 scat gath scatgath Rectangle.88 VTCM VTCM Dynamic connector Dynamic connector.90 Sheet.93 Sheet.94 Sheet.95 Sheet.97 **Hexagon core with attached SIMD coprocessor** The Hexagon instruction set architecture (ISA) is extended with HVX instructions. These instructions use HVX compute resources and can freely mix with normal Hexagon instructions in a very long instruction word (VLIW) packet. HVX instructions can also use scalar source operands from the core. ## HVX features HVX adds very wide SIMD capability to the Hexagon ISA. SIMD operations execute on vector registers (currently up to 1024 bits each), and multiple SIMD instructions can execute in parallel. ### Vector length HVX supports 1024-bit vectors (128 byte). To minimize porting effort, software should strive to treat vector length as an arbitrary constant power of two. Page-1 Rectangle.39 Vector context 0 Vector context 0 Rectangle.31 1024-bit 1024-bit Rectangle.20 . . . . . . Rectangle.43 1024-bit 1024-bit Sheet.5 V0 V0 Sheet.6 V31 V31 Rectangle.68 128-bit 128-bit Rectangle.69 . . . . . . Rectangle.70 128-bit 128-bit Sheet.10 Q0 Q0 Sheet.11 Q3 Q3 **Registers using 128 byte with a vector length of 1024 bits** ### Vector contexts A vector context consists of a vector register file, vector predicate file, and the ability to execute instructions using this state. Scalar core hardware threads dynamically attach to a vector context; this enables the thread to execute HVX instructions. Multiple hardware threads can execute in parallel, each with a different vector context. The number of supported vector contexts is implementation-defined. The scalar core can contain any number of hardware threads greater or equal to the number of vector contexts. The scalar hardware thread is assignable to a vector context through per-thread SSR.XA programming, as follows: - SSR.XA = 0: HVX instructions use vector context 0. - SSR.XA = 1: HVX instructions use vector context 1, if it is available. - SSR.XA = 2: HVX instructions use vector context 2, if it is available. - SSR.XA = 3: HVX instructions use vector context 3, if it is available. - SSR.XA = 4: HVX instructions use vector context 4, if it is available. - SSR.XA = 5: HVX instructions use vector context 5, if it is available. - SSR.XA = 6: HVX instructions use vector context 6, if it is available. - SSR.XA = 7: HVX instructions use vector context 7, if it is available. [Hardware threads](https://docs.qualcomm.com/doc/80-N2040-61/topic/introduction.html#v79-fig-hardware-threads) shows a vector context configuration with four hardware threads, but with two of the threads configured to use 128 byte vectors. In this configuration, two of the threads can execute 128 byte vector instructions, while the other two threads can execute scalar-only instructions. Page-1 Rectangle.15 Hexagon Hexagon Rectangle.4 SIMD coprocessor SIMD coprocessor Rectangle.18 L2$/L2-TCM L2$/L2-TCM Rectangle.41 I$ I$ Rectangle.77 D$ D$ Rectangle.80 GRF thread0 GRF thread0 Rectangle.81 GRF thread2 GRF thread2 Rectangle.82 GRF thread1 GRF thread1 Rectangle.83 GRF thread3 GRF thread3 Rectangle.39 Vector context 0 Vector context 0 Rectangle.31 1024-bit 1024-bit Rectangle.20 . . . . . . Rectangle.43 1024-bit 1024-bit Sheet.88 V0 V0 Sheet.89 V31 V31 Rectangle.68 128-bit 128-bit Rectangle.69 . . . . . . Rectangle.70 128-bit 128-bit Sheet.93 Q0 Q0 Sheet.94 Q3 Q3 Rectangle.95 Vector context 1 Vector context 1 Rectangle.96 1024-bit 1024-bit Rectangle.97 . . . . . . Rectangle.98 1024-bit 1024-bit Sheet.99 V0 V0 Sheet.100 V31 V31 Rectangle.101 128-bit 128-bit Rectangle.102 . . . . . . Rectangle.103 128-bit 128-bit Sheet.104 Q0 Q0 Sheet.105 Q3 Q3 Sheet.106 Coprocessor instruction port Coprocessor instruction port Sheet.107 Sheet.108 Sheet.109 Sheet.111 **Four hardware threads (two HVX-enabled threads and two scalar-only threads)** ### Memory access The HVX memory instructions (referred to as VMEM instructions) use the Hexagon general registers (R0 through R31) to form addresses that access memory. The memory access size of these instructions is the vector length or the size of a vector register. VMEM loads and stores share a 32-bit virtual address space as normal scalar load/stores. VMEM load/stores are coherent with scalar load/stores and hardware maintains coherency. ### Vector registers HVX has two sets of registers: - Data registers consist of 32 vector length registers. Certain operations can access a pair of registers to effectively double the vector length for the operand. - Predicate registers consist of four registers, each with one bit per byte of vector length. These registers provide operands to compare, mux, and other special instructions. The vector registers are partitioned into lanes that operate in SIMD fashion. For example, with 1024-bit (128 byte) vector length, each vector register can contain any of the following items: - 32 words (32-bit elements) - 64 halfwords (16-bit elements) - 128 bytes (8-bit elements) Element ordering is little-endian with the lowest byte in the least-significant position, as shown in [1024-bit SIMD register](https://docs.qualcomm.com/doc/80-N2040-61/topic/introduction.html#v79-fig-1024-bit-simd-reg). Page-1 Sheet.2 . . . . . . Rectangle.15 127 127 Sheet.28 Byte Byte Sheet.32 Halfword Halfword Sheet.33 Word Word Rectangle.45 63 63 Rectangle.46 63 63 Rectangle.47 31 31 Rectangle.48 126 126 Rectangle.49 125 125 Rectangle.50 124 124 Rectangle.51 7 7 Rectangle.52 6 6 Rectangle.53 5 5 Rectangle.54 4 4 Rectangle.55 3 3 Rectangle.56 2 2 Rectangle.57 1 1 Rectangle.58 0 0 Rectangle.65 3 3 Rectangle.91 2 2 Rectangle.92 1 1 Rectangle.93 0 0 Rectangle.94 1 1 Rectangle.95 0 0 **1024-bit SIMD register** ### Vector compute instructions Vector instructions process vector register data in SIMD fashion. The operation is performed on each vector lane in parallel. For example, the following instruction performs a signed ADD operation over each halfword: V2.h = VADD(V3.h,V4.h) Copy to clipboard In this instruction, the halfwords in V3 are summed with the corresponding halfwords in V4, and the results stored in V2. When vectors are specified in instructions, the element type is also usually specified: - .b for signed byte - .ub for unsigned byte - .h for signed halfword - .uh for unsigned halfword - .w for signed word - .uw for unsigned word - .qf16 for 16-bit HVX floating point - .qf32 for 32-bit HVX floating point - .hf for half precision - .sf for single precision For example: v0.b = vadd(v1.b,v2.b) // Add vectors of bytes v1:0.b = vadd(v3:2.b, v5:4.b) // Add vector pairs of bytes v1:0.h = vadd(v3:2.h, v5:4.h) // Add vector pairs of halfwords v5:4.w = vmpy(v0.h,v1.h) // Widening vector 16 x 16 to 32 // multiplies: halfword inputs, // word outputs Copy to clipboard For operations with mixed element sizes, each operand with the smaller element size uses a single vector register and each operand with the larger element size (double the smaller) uses a vector register pair. One vector in a pair contains even elements and the other odd elements. Last Published: Jan 16, 2025 [Next Topic HVX Revision history](https://docs.qualcomm.com/bundle/publicresource/80-N2040-61/topics/hvx-revision.md)