# C-PHY (DSI and CSI) routing constraints

Source: [https://docs.qualcomm.com/doc/80-PV086-5P/topic/C-PHY (DSI and CSI) routing constraints.html](https://docs.qualcomm.com/doc/80-PV086-5P/topic/C-PHY%20%28DSI%20and%20CSI%29%20routing%20constraints.html)

To interpret the following table, use the 1.5 Gsps/lane as an example. If the cable insertion loss is -0.9 dB or better, the trace length needs to be ≤ 250 mm. If cable insertion loss is between -0.9 dB and -1.8 dB, the trace length needs to be ≤ 165 mm. If cable insertion loss is worse than -1.8 dB, a higher-quality flex cable is needed as a replacement, which reduces insertion loss.

The single-ended impedance targets are relaxed from the legacy 50 Ω single-ended targets to better reflect design limitations of an ultra-thin PCB. This has been verified by simulation.

| Metrics | Metrics | Guidance | Guidance | Guidance | Guidance | Guidance | Guidance | Guidance | Guidance | Guidance | Guidance | Guidance | Guidance | Guidance | Guidance | Guidance |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| Data rate | Data rate | 1.5 Gsps/lane | 1.5 Gsps/lane | 1.5 Gsps/lane | 2.1 Gsps/lane | 2.1 Gsps/lane | 2.1 Gsps/lane | 2.5 Gsps/lane | 2.5 Gsps/lane | 2.5 Gsps/lane | 3.5 Gsps/lane | 3.5 Gsps/lane | 3.5 Gsps/lane | 4.5 Gsps/lane | 4.5 Gsps/lane | 4.5 Gsps/lane |
| Flex cable length (in inches) [^1^](https://docs.qualcomm.com/doc/80-PV086-5P/topic/C-PHY%20%28DSI%20and%20CSI%29%20routing%20constraints.html#fntarg_1) | Flex cable length (in inches) [^1^](https://docs.qualcomm.com/doc/80-PV086-5P/topic/C-PHY%20%28DSI%20and%20CSI%29%20routing%20constraints.html#fntarg_1) | 1ʺ | 3ʺ | 6ʺ | 1ʺ | 3ʺ | 6ʺ | 1ʺ | 3ʺ | 6ʺ | 1" | 3" | 6" | 1" | 3" | 6" |
| Flex cable insertion loss [^2^](https://docs.qualcomm.com/doc/80-PV086-5P/topic/C-PHY%20%28DSI%20and%20CSI%29%20routing%20constraints.html#fntarg_2) | Flex cable insertion loss [^2^](https://docs.qualcomm.com/doc/80-PV086-5P/topic/C-PHY%20%28DSI%20and%20CSI%29%20routing%20constraints.html#fntarg_2) | -0.4 dB | -0.9 dB | -1.8 dB | -0.5 dB | -1.3 dB | -2.3 dB | -0.48 dB | -1.4 dB | -2.5 dB | -0.71 dB | -1,46 dB | -3.12 dB | -0.48 dB | -1.72 dB | -3.8 dB |
| Maximum PCB trace length | Maximum PCB trace length | 280 mm | 220 mm | 140 mm | 225 mm | 150 mm | 85 mm | 200 mm | 130 mm | 40 mm | 208 mm | 188 mm | 152 mm | 168 mm | 132 mm | 88 mm |
| Maximum PCB IL – Estimated | Maximum PCB IL – Estimated | -2.5 dB | -2.0 dB | -1.3 dB | -2.5 dB | -1.7 dB | -1.0 dB | -2.2 dB | -1.4 dB | -0.5 dB | -3.69 dB | -3.34 dB | -2.08 dB | -3.46 dB | -2.88 dB | -1.1 dB |
| Impedance | Single-ended [^3^](https://docs.qualcomm.com/doc/80-PV086-5P/topic/C-PHY%20%28DSI%20and%20CSI%29%20routing%20constraints.html#fntarg_3) | 36 to 52 Ω | 36 to 52 Ω | 36 to 52 Ω | 36 to 52 Ω | 36 to 52 Ω | 36 to 52 Ω | 36 to 52 Ω | 36 to 52 Ω | 36 to 52 Ω | 36 to 52 Ω | 36 to 52 Ω | 36 to 52 Ω | 36 to 52 Ω | 36 to 52 Ω | 36 to 52 Ω |
| Length match | Intralane (within a trio) | 0.7 mm | 0.7 mm | 0.7 mm | 0.7 mm | 0.7 mm | 0.7 mm | 0.7 mm | 0.7 mm | 0.7 mm | 0.7 mm | 0.7 mm | 0.7 mm | 0.7 mm | 0.7 mm | 0.7 mm |
| Length match | Interlane (trio-to-trio) | 4.2 mm | 4.2 mm | 4.2 mm | 4.2 mm | 4.2 mm | 4.2 mm | 4.2 mm | 4.2 mm | 4.2 mm | 4.2 mm | 4.2 mm | 4.2 mm | 4.2 mm | 4.2 mm | 4.2 mm |
| Spacing | To all other signals | 3 × line width | 3 × line width | 3 × line width | 3 × line width | 3 × line width | 3 × line width | 3 × line width | 3 × line width | 3 × line width | 3 × line width | 3 × line width | 3 × line width | 3 × line width | 3 × line width | 3 × line width |
| Spacing | Intralane (within a trio) | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width |
| Spacing | Interlane (trio to trio) | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width | 1.5 × line width |
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[^1^](https://docs.qualcomm.com/doc/80-PV086-5P/topic/C-PHY%20%28DSI%20and%20CSI%29%20routing%20constraints.html#fnsrc_1)  The flex cable
                length used in this table is an example with specified insertion loss.

[^2^](https://docs.qualcomm.com/doc/80-PV086-5P/topic/C-PHY%20%28DSI%20and%20CSI%29%20routing%20constraints.html#fnsrc_2)  The insertion loss is
                measured at 0.5 × data rate (in Gsps) in GHz. Flex cable insertion loss can be
                measured using a vector signal analyzer or obtained from the flex-cable datasheet.
                Cable insertion loss on the design should be no worse than what is listed
                above.

[^3^](https://docs.qualcomm.com/doc/80-PV086-5P/topic/C-PHY%20%28DSI%20and%20CSI%29%20routing%20constraints.html#fnsrc_3)  The range of PCB impedance includes manufacturing variation. The
                PCB designer is responsible for working with their PCB vendor to ensure each design
                falls within the published impedance range.

**Parent Topic:** [PCB layout guidelines](https://docs.qualcomm.com/doc/80-PV086-5P/topic/pcb-layout-guidelines.html)

Last Published: Jul 07, 2023