# PCIe layout guidelines

Source: [https://docs.qualcomm.com/doc/80-PV086-5P/topic/PCIe layout guidelines.html](https://docs.qualcomm.com/doc/80-PV086-5P/topic/PCIe%20layout%20guidelines.html)

The following are the general PCIe routing guidelines:

- All other sensitive/high-speed signals and circuits must be protected from PCIe
                corruption.
- PCIe signals must be protected from noisy signals (clocks, SMPS, and so forth).
- Pay extra attention to crosstalk, ISI, and intralane skew and impedance
                discontinuities.
- For a single-board design, PCIe Tx AC coupling capacitors can be anywhere along the
                line, but better be placed close to source or receiver side to keep good SI of main
                route on PCB.
- Each trace needs to be adjacent to a ground plane.
- To maintain impedance balance, maintain positive and negative traces as balanced as
                possible in terms of the signal and its return path.
- Avoid broadside coupling and routing a signal trace directly over another signal
                trace.
- To reduce the probability for layer-to-layer manufacturing variation, minimize layer
                transitions on the main route (in other words, apply layer transitions only at
                QRB5165 device breakouts and connectors to ensure minimum layer transitions on the
                main route).

**Additional layout guidelines**

- The trace length matching between the reference clock, Tx, and Rx pairs are not
                required. The trace serpentines are not required.
- Ensure not to stagger the capacitors. This can affect the differential integrity of
                the design and can create EMI.
- In the case of serpentines, one line of a differential pair must be routed to make
                up a length delta, then it must be routed at the source (breakout) – this ensures
                that lines stay differential thereafter.

The following table lists the PCIe routing constraints.

| Metrics | Metrics | Metrics | Guidance | Guidance |
| --- | --- | --- | --- | --- |
| Data rate | Data rate | Data rate | 8 Gbps (Gen 3.0) | 5 Gbps (Gen 2.0) |
| Channel differential insertion<br>                            loss | Channel differential insertion<br>                            loss | Channel differential insertion<br>                            loss | -10 dB at 4 GHz | -6 dB at 2.5 GHz |
| Bus length | Bus length | Bus length | 300 mm | 250 mm |
| Impedance [^1^](https://docs.qualcomm.com/doc/80-PV086-5P/topic/PCIe%20layout%20guidelines.html#fntarg_1) | Differential | Field route | 70 to 100 Ω | 70 to 100 Ω |
| Length match | Intralane length match | Intralane length match | 5 ps (0.7 mm) | 5 ps (0.7 mm) |
| Spacing | To all other signals | Field route | 4 × line width | 4 × line width |
| Spacing | Rx-to-Tx | Field route | 4 × line width | 3 × line width |
| Component | AC capacitor | AC capacitor | 176 to 265 nF | 75 to 265 nF |
|  |  |  |  |  |

[^1^](https://docs.qualcomm.com/doc/80-PV086-5P/topic/PCIe%20layout%20guidelines.html#fnsrc_1)  The range of PCB impedance includes manufacturing
                                variation. The PCB designer is responsible for working with their
                                PCB vendor to ensure each design falls within the published
                                impedance range.

**Parent Topic:** [PCB layout guidelines](https://docs.qualcomm.com/doc/80-PV086-5P/topic/pcb-layout-guidelines.html)

Last Published: Jul 07, 2023