# QRB5165 features Source: [https://docs.qualcomm.com/doc/80-PV086-5P/topic/QRB5165-features.html](https://docs.qualcomm.com/doc/80-PV086-5P/topic/QRB5165-features.html) The following table lists all the features and QRB5165 capabilities. Note: Some of the hardware features integrated within the QRB5165 must be enabled by software. See the latest revision of the applicable software release notes to identify the enabled QRB5165 features. | Feature | QRB5165 capability | | --- | --- | | ***Processors*** | ***Processors*** | | Applications | Kryo 585 – 64-bit applications processor with a 4 MB L3 cache




| | Digital signal processing | Compute Hexagon DSP with quad Hexagon Vector eXtensions (quad-HVX) and Hexagon Coprocessor (Hexagon CP) 2.0





Audio Hexagon DSP dedicated to an audio subsystem.



Sensor Hexagon DSP in the Qualcomm^®^Sensing Hub to support always-on, low-power use cases.



All Hexagon DSP are cache-based processors with full access to DDR memory for large memory requirements. | | Always-on system | Always-on subsystem with always-on processor.



Hardware-based resource and power management (RPMh) with hardware accelerators for voltage control and regulation, clock management, and resource communication. | | Artificial intelligence | Qualcomm NPU230 dedicated neural processing unit for performance and always-on neural network (NN) use cases. It incorporates an NN matrix engine to ensure efficient execution of various neural networks and their parameters.



The NPU may be used for typical imaging, video, audio, and data-based NN use cases and will typically be used in conjunction with the compute Hexagon DSP subsystem. | | ***Memory support*** | ***Memory support*** | | System memory via PoP and EBI | Four-channel PoP high-speed memory – LPDDR5 SDRAM (4 × 16-bit) designed for a 2750 MHz (LPDDR5) clock and system cache | | External memory via UFS | UFS 3.1 Gear 4 – for on-board memory | | External memory via SDC | SD v3.0 4-bit for SD card | | ***Multimedia*** | ***Multimedia*** | | Adreno display processing unit (DPU) | Adreno DPU 995, supports up to three 4K display (one internal display through DSI and two external displays through DisplayPort) | | Display interface | Two 4-lane DSI D-PHY 1.2 or two 3-trio C-PHY v1.1 with VESA DSC v1.1



DisplayPort v1.4 at 8.1 Gbps/lane over Type-C with support for MST and VESA DSC v1.1 and FEC (USB3 and USB2 concurrency supported)



Miracast – up to 4K60 | | Display performance | 5040 × 2160 at 60 Hz (or 120 Hz in VR mode), up to 30 bpp



Two 2560 × 2560 at 120 Hz for dual-panel VR displays, up to 30 bpp 4096 buffer width, and 16 hardware-layer composition | | Display processing | Qualcomm^®^ TruPalette Display Feature – HDR10+ and HDR10 tone mapping, color gamut mapping, six-zone, memory color, and picture adjust | | Pixel processing | Qualcomm^®^ Low-Power Picture Enhancement display compression [Qualcomm Universal Bandwidth Compression (UBWC 4.0, DSC v1.1)], CABL, FOSS, Qualcomm Local Tone Mapping, QSync, and destination scaler with DE | | Camera performance | Qualcomm Spectra 480 ISP to support up to 12 cameras by D-PHY and 18 cameras by C-PHY (seven concurrent)


| | Camera interface | MIPI CSI configurable in 4 + 4 + 4 + 4 + 4 + 4 configuration


| | Adreno video processing unit (VPU) | | | Adreno graphic processing unit (GPU) | | | Audio codec | Integrated within the WCD9380/WCD9385 high fidelity audio codec:


| | Speaker amplifier | Integrated within the WSA8810/WSA8815 class D/G, low noise smart amplifier:


| | Low-power audio subsystem (LPASS) | | | Audio interfaces | SLIMbus:





SWR:





Digital Mic:





MI^2^S:





TDM/PCM:


| | Digital mobile broadcast (DMB) | External IC required with SPI or SDIO interface | | ***Connectivity*** | ***Connectivity*** | | Qualcomm universal peripheral (QUP) ports | 20:7 bits each for four QUPs and 4-bit each for the other QUPs; multiplexed serial interface functions | | UART | UART interface available on all QUPs. HS-UART available on GPIO QUP6/QUP7/QUP12/QUP13/QUP18/QUP19/Qualcomm Sensing Hub | | I^2^C | I^2^C interface available on all QUPs up to 1 Mbps for touch, sensors, near field communicator (NFC), and so on; dedicated controller for each port | | I3C | I3C interface available on GPIO QUP0/QUP1/QUP8/QUP14 and Qualcomm Sensing Hub QUP0/QUP1/QUP2. I3C IBI (in-band interrupt) will not be supported. | | SPI | SPI interfaces available on all QUPs for cameras, sensors, and so on; dedicated controller for each port | | CCI I^2^C | Four dedicated I^2^C interfaces for camera | | USB | Two USB 3.1 ports, support Type-C with DisplayPort v1.4 in one port | | Secure digital interfaces | | | Wireless connectivity | QCA639x 802.11ax QCA643x/QCA642x 802.11ad at 60 GHz | | Touchscreen support | Capacitive panels via ext IC (I^2^C, I3C, SPI, and interrupts) | | Fingerprint support | Ultrasonic Qualcomm^®^ Fingerprint Sensors for under glass, under metal, or under OLED display. QFS2000/QFS2080/QFS2580/QFS2530 modules. | | ***Configurable GPIOs*** | ***Configurable GPIOs*** | | Number of GPIO ports | 180– GPIO\_0 to GPIO\_179 | | Input configurations | Pull-up, pull-down, keeper, or no pull | | Output configurations | Programmable drive current | | Top-level mode multiplexer | Provides a convenient way to program groups of GPIOs | | ***Internal functions*** | ***Internal functions*** | | **Security** | | | General hardware security features | SPU-240 with planned certification enabling Android Strongbox and iUICC, Secure Boot 3.0, Debug security, Key provisioning security, TrustZone, Qualcomm^®^ Trusted Execution Environment v5, hardware-backed keystore, combined image signing, image encryption, secure peripherals, Inline crypto engine (ICE), file-based encryption (FBE) | | Crypto engines | Crypto engine v5 (CE5), Qualcomm to submit for Federal Information Processing Standards (FIPS) certification to Certified for FIPS 140-2. | | TrustZone services | Secure file system, Fast Trusted Storage | | DRM support in hardware QFPROM | PlayReady SL2000/SL3000, Widevine level 1 and level 3, ISDB-T fuse bits available for OEM use | | Access control | Programmable security domain protection and sandboxing | | Boot sequence |

  1. Applications PBL


  2. XBL


  3. SHRM


  4. AOP


  5. HLOS


  6. Rest of subsystems




| | PLLs and clocks | | | Debug | JTAG, design for software debug (DFSD), embedded USB debug (EUD) | | ***Others*** | Thermal sensors; modes and resets; peripheral subsystem | | ***Chipset interface features*** | ***Chipset interface features*** | | Power management | 2-line SPMI; plus other lines, as needed, via GPIOs, I^2^C | | Wireless connectivity | Wireless connectivity | | WLAN



Bluetooth | PCIe interface



SLIMbus/UART interface | | ***Fabrication technology and package*** | ***Fabrication technology and package*** | | Digital die | 7 nm process | | PoP – small, thermally efficient package | MPSP1099 (QRB5165-LPDDR5): 14.0 × 12.4 × 0.56 mm max (without memory device on top) | | **QRB5165-LPDDR5** | **QRB5165-LPDDR5** | | Bottom pin array



Top pin array | Bottom: 1099-pin picoscale package (1099 PSP); 0.35 mm pitch



Top: 496-pin nanoscale package (496 NSP); 0.4 mm pitch | ^1^ Higher resolution and wider aspect ratio displays can be supported. Exact panel details and timings are required to determine if it can be supported. **Parent Topic:** [QRB5165 overview](https://docs.qualcomm.com/doc/80-PV086-5P/topic/qrb5165-overview.html) Last Published: Jul 07, 2023 [Previous Topic QRB5165 architecture overview](https://docs.qualcomm.com/bundle/publicresource/80-PV086-5P/topics/qrb5165-architecture-overview.md) [Next Topic Clock distribution](https://docs.qualcomm.com/bundle/publicresource/80-PV086-5P/topics/qrb5165-clock-distribution.md)